A fully gallium nitride integrated negative voltage generation circuit for negative voltage isolation

Abstract

The present invention belongs to the field of semiconductor power integration technology, and in particular relates to a full-gallium nitride integrated negative voltage generation circuit for negative voltage isolation. The present invention includes a DC voltage divider circuit, a pulse signal generation circuit, and first and second capacitor charge and discharge circuits. The DC voltage divider circuit is used to generate a voltage compatible with a wide power supply input from a DC voltage source according to the needs of negative voltage isolation; the pulse signal generation circuit is used to generate a negative voltage circuit switch control signal synchronized with the switching of a high-voltage gallium nitride device; and the first and second capacitor charge and discharge circuits are used to generate a stable negative voltage under the action of the control signal. The full-gallium nitride integrated negative voltage generation circuit for negative isolation of the present invention can achieve synchronous tracking of the negative voltage and the high-frequency switching of the high-voltage gallium nitride power device, and can flexibly generate the required stable negative voltage under different DC power supplies according to different isolation scenarios, and is fully compatible with the P‑GaN gate-enhanced gallium nitride power integration process platform.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor power integration, and in particular relates to a full gallium nitride integrated negative voltage generating circuit for negative voltage isolation. Background Art

[0002] Gallium nitride (GaN), a third-generation wide bandgap semiconductor material, has a bandgap of 3.4 eV, a thermal conductivity of 2.0 W / (cm·K), and a 2 / V·s electron mobility, 3.5×10 6 With a critical breakdown electric field of 10 V / cm, and an extremely high charge density in the two-dimensional electron gas (2DEG) generated at the junction surface due to polarization effects in the AlGaN / GaN heterojunction, gallium nitride high electron mobility transistors (GaN HEMTs) are capable of operating at higher frequencies, higher voltages, and higher temperatures than silicon devices. This significantly reduces the size of passive components such as capacitors, inductors, and transformers in power systems, lowering the need for heat dissipation and increasing the power density of power systems, thereby achieving miniaturization and low-carbonization of power equipment. They are now widely used in switching power supplies, new energy vehicles, photovoltaic inverters, and other fields.

[0003] Currently, the mainstream application of GaN HEMTs is still discrete power circuits, combining discrete enhancement-mode GaN devices with Si-based drivers and other peripheral circuit components soldered onto printed circuit boards (PCBs). Parasitic inductance in the signal loop, inevitably introduced by device packaging and PCB traces, causes gate signal oscillation when driving GaN devices, making them difficult to drive in high-frequency applications. Furthermore, during high-speed switching of GaN devices, parasitic parameters in the signal loop prevent the protection circuit from safely shutting down the GaN device in a timely manner. All of these factors hinder the full performance advantages of discrete GaN power circuits. However, full GaN integration, integrating GaN power devices with driver and protection circuits on the same substrate, can minimize parasitic parameters in the signal loop, even achieving zero parasitic inductance, thereby maximizing GaN performance and becoming the current trend in GaN applications.

[0004] In all-GaN power integrated circuits, high-voltage GaN power devices and low-voltage GaN logic devices are integrated on the same substrate. Due to parasitic capacitance between the high- and low-voltage devices and leakage current paths in the low-resistance P-type silicon substrate, high-frequency switching of the high-voltage GaN power devices inevitably generates crosstalk signals in the low-voltage logic devices. Crosstalk signals include both current and voltage. The current affects the drain current of the low-voltage device, while the voltage causes irregular potential fluctuations in the low-voltage device, manifesting as threshold voltage shifts and posing the risk of false turn-on. Common solutions for crosstalk include: 1) trench isolation by mesa etching in the active area. However, to achieve effective crosstalk isolation, the trench width is typically several hundred microns, significantly reducing the power density of the all-GaN IC. 2) ion implantation isolation. Similar to trench isolation, this can only be achieved by lateral expansion between devices, and ion implantation requires high process stability. 3) GaN-on-SOI isolation, but this isolation technology has high process requirements and poses thermal reliability issues because the oxide on the substrate semi-encapsulates the GaN device, and the thermal resistance of the oxide and substrate are different. 4) Reverse electric field coupling isolation structure applies a negative electric field within the trench to influence the electric field distribution between high- and low-voltage devices, suppressing crosstalk signals. It also allows for narrow trench widths, improving the power density of all-GaN ICs, making it a comprehensive crosstalk isolation solution for all-GaN ICs. Summary of the Invention

[0005] This invention addresses the problem of high-speed, stable generation of negative voltage under varying isolation requirements in the negative electric field coupling technology of monolithic GaN power integrated circuits. This invention proposes an all-GaN negative voltage generation circuit based on a P-GaN gate-enhancement-mode GaN power integrated process platform, constructed using a P-GaN gate-enhancement-mode HEMT (E-HEMT) and a MIS depletion-mode HEMT (D-HEMT). This circuit rapidly generates a negative voltage in the isolation trench when high-voltage GaN power devices are switched, modulating the electric field between high- and low-voltage devices and thus suppressing crosstalk noise. Furthermore, the voltage divider structure in the proposed circuit allows for flexible control of the generated negative voltage amplitude according to different crosstalk suppression scenarios. Furthermore, the generated negative voltage exhibits high stability for DC sources of varying amplitudes.

[0006] The present invention has the following characteristics:

[0007] 1) Fast response, capable of quickly generating negative voltage following the switching of high-voltage GaN power devices.

[0008] 2) The negative pressure is controllable and can be adjusted according to the needs of crosstalk isolation.

[0009] 3) High process compatibility. The devices used in this invention are all based on the more mature P-GaN gate-enhanced GaN power integration process platform.

[0010] The technical solution of the present invention is:

[0011] A full gallium nitride integrated negative voltage generating circuit for negative voltage isolation, comprising a voltage divider circuit, a pulse signal generating circuit, a first capacitor charging and discharging circuit, and a second capacitor charging and discharging circuit;

[0012] The voltage divider circuit includes a first D-HEMT tube and a first E-HEMT tube; the drain of the first D-HEMT tube is connected to the power supply, the gate and source of the first D-HEMT tube are short-circuited, the source of the first D-HEMT tube is connected to the gate and drain of the first E-HEMT tube, the source of the first E-HEMT tube is grounded, and the drain of the first E-HEMT tube is the output end of the voltage divider circuit;

[0013] The pulse signal generating circuit includes a second D-HEMT tube and a second E-HEMT tube; the drain of the second D-HEMT tube is connected to the output end of the voltage divider circuit, the gate and source of the second D-HEMT tube are short-circuited and then connected to the drain of the second E-HEMT tube, the gate of the second E-HEMT tube serves as the signal input end of the negative voltage generating circuit, the source of the second E-HEMT tube is grounded, and the drain of the second E-HEMT tube serves as the output end of the pulse signal generating circuit;

[0014] The first capacitor charging and discharging circuit includes a first diode D1 and a first capacitor C1; the anode of the first diode D1 is connected to the output end of the pulse signal generating circuit through the first capacitor C1, and the cathode of the first diode D1 is grounded;

[0015] The second capacitor charging and discharging circuit includes a second diode D2 and a second capacitor C2; the cathode of the second diode D2 is connected to the anode of the first diode D1, the anode of the second diode D2 is connected to one end of the second capacitor C2, and the other end of the second capacitor C2 is grounded; one end of the second capacitor C2 is the output end of the negative voltage generating circuit;

[0016] The pulse signal generating circuit is used to generate a negative voltage generating signal synchronously with the switch of the high-voltage GaN power device, and is used to control the first capacitor charging and discharging circuit and the second capacitor charging and discharging circuit to generate a stable negative voltage.

[0017] Furthermore, the devices used in the negative voltage generation circuit are all integrated on the same substrate based on the P-GaN gate enhancement-mode gallium nitride power integration process platform, and the D-HEMT tube, E-HEMT tube, diode, and capacitor are defined as an integrated device. The integrated device is composed of a Si substrate, a GaN buffer layer, a GaN channel layer, and an AlGaN barrier layer from bottom to top; along the lateral direction of the device, there are D-HEMT tubes, E-HEMT tubes, diodes, and capacitors, which are spaced apart from each other, wherein both ends of the D-HEMT tube portion have a first metal, the first metal penetrates the AlGaN barrier layer along the vertical direction of the device and contacts the GaN channel layer, a P-GaN layer is provided in the middle of the upper surface of the AlGaN barrier layer between the first metals, a dielectric layer is provided between the P-GaN layer and the first metals on both sides, and a second Metal; both ends of the E-HEMT tube portion have a first metal, the first metal penetrates the AlGaN barrier layer in the vertical direction of the device and contacts the GaN channel layer, the upper surface of the AlGaN barrier layer between the first metals has a dielectric layer, and the middle part of the upper surface of the dielectric layer has a second metal; the diode portion has a second metal at an end close to the E-HEMT tube, the second metal penetrates the AlGaN barrier layer in the vertical direction of the device and contacts the GaN channel layer, the diode portion has the first metal at an end away from the E-HEMT tube, the bottom of the first metal contacts the AlGaN barrier layer, and the upper surface of the AlGaN barrier layer between the second metal and the first metal has a dielectric layer; the upper surface of the capacitor portion has a dielectric layer, the upper surface of the dielectric layer at the end away from the diode has a second metal, a passivation layer is formed on the second metal, and a third metal is formed on the passivation layer.

[0018] The beneficial effects of the present invention are:

[0019] 1. It can rapidly generate negative voltage to modulate the electric field distribution between high- and low-voltage devices. Compared to traditional discrete negative voltage generation circuits, the devices used in the proposed all-GaN negative voltage generation circuit are fully compatible with the more mature P-GaN gate-enhanced GaN power integration process platform. This minimizes signal latency, enabling the generation of a negative voltage when high-voltage GaN power devices are turned on at high frequency. This prevents the negative voltage from causing threshold and leakage current drift in low-voltage GaN logic devices when the high-voltage GaN power devices are rapidly turned on.

[0020] 2. The negative voltage value generated can be adjusted according to different crosstalk scenarios and has high compatibility with different DC power supplies. Compared with the traditional resistor voltage divider method, by connecting the D-HEMT device with the gate and drain shorted in series with the E-HEMT with the gate and source shorted, the preset voltage divider can be flexibly adjusted by changing the gate width of the E-HEMT. In addition, the preset voltage divider under this structure will be less affected by different DC power supplies. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 This is a functional block diagram of a full gallium nitride integrated negative voltage generation circuit for negative voltage isolation proposed by the present invention;

[0022] Figure 2 This is a schematic diagram of the topological structure of a full gallium nitride integrated negative voltage generation circuit for negative voltage isolation proposed by the present invention;

[0023] Figure 3 This is a simulation diagram of a full gallium nitride integrated negative voltage generation circuit for negative voltage isolation proposed by the present invention based on ADS simulation software;

[0024] Figure 4 Schematic diagram of the P-GaN gate enhancement mode GaN power integration process platform compatible with the present invention;

[0025] Figure 5 Schematic diagram of the isolation application location in an all-GaN power IC according to an embodiment of the present invention. DETAILED DESCRIPTION

[0026] The technical solution of the present invention is described in detail below with reference to the accompanying drawings:

[0027] See also Figure 1 , a functional block diagram of a full gallium nitride integrated negative voltage generation circuit for negative voltage isolation proposed in the present invention.

[0028] Voltage divider circuit: used to meet the requirements of different negative voltage values in different crosstalk suppression scenarios, and can be compatible with different DC power inputs to produce relatively stable voltage divider.

[0029] Pulse signal generating circuit: used to generate a negative voltage generating signal synchronously with the switch of the high-voltage GaN power device, used to control the first capacitor charging and discharging circuit and the second capacitor charging and discharging circuit to generate a stable negative voltage.

[0030] The first and second capacitor charging and discharging circuits generate a stable negative voltage under the control of the pulse signal generating circuit.

[0031] Overall, the voltage divider output end of the voltage divider circuit is connected to the voltage input end of the pulse signal generating circuit; the signal output end of the pulse signal generating circuit is connected to the input end of the first capacitor charging and discharging circuit; the output end of the first capacitor charging and discharging circuit is connected to the input end of the second capacitor charging and discharging circuit.

[0032] Its function is described as follows: the voltage divider circuit divides the DC power supply voltage VDD to the set voltage divider value V in real time. divideWhen the high-voltage GaN power HEMT is turned off, the input signal at the input signal terminal of the negative voltage generating circuit remains at a low level, and the negative voltage generating circuit is disabled. When the high-voltage GaN power device switches at high frequency, during the period when the input signal is at a low level, the pulse signal generating circuit outputs V divide High level, charging the first capacitor charging and discharging circuit; in the period when the input signal is high level, the pulse signal generating circuit outputs 0V low level, and the first capacitor charging and discharging circuit charges the second capacitor charging and discharging circuit. Under the calibration of GND 0V, the voltage across capacitor C2 cannot jump, so the output amplitude is close to V divide negative voltage.

[0033] See also Figure 2 , is a schematic diagram of the topological structure of a full gallium nitride integrated negative voltage generation circuit for negative voltage isolation proposed by the present invention;

[0034] Its working principle is:

[0035] When the high-voltage GaN power HEMT is turned off, the input signal of the negative voltage generating circuit remains at a 0V level, and thus the second E-HEMT2 remains off. Therefore, the output of the pulse signal generating circuit maintains the divided voltage value Vdivide. At this time, neither the first capacitor charging and discharging circuit nor the second capacitor charging and discharging circuit performs any charging or discharging operations, and therefore the negative voltage generating circuit remains disabled, with the output remaining at 0V.

[0036] When the high-voltage GaN power device HEMT switches at high frequency, during the low-level period of the input signal, the first E-HEMT is cut off, and the voltage divider circuit charges the first charging capacitor circuit through the second D-HEMT. The voltage of the section connecting the capacitor C1 and the anode of the diode D1 is the forward conduction voltage of the diode, and the other section of the capacitor C1 is close to the divided voltage value V divide When the input signal is high level, the first E-HEMT is turned on, and the first capacitor charging and discharging circuit charges the second capacitor charging and discharging circuit through the first E-HEMT, and the voltage across the capacitor C2 is charged to V divide Since one end of capacitor C2 is grounded and the voltage across the capacitor cannot jump, the end of capacitor C2 connected to the anode of diode D2 has an amplitude close to V divide negative voltage.

[0037] Furthermore, in the voltage divider circuit, the voltage divider value V divide The expression is:

[0038]

[0039] Among them, N D 、N E are the gate widths of the first D-HEMT and the second E-HEMT, β D , βE are the current densities of the first D-HEMT and the second E-HEMT, respectively. V THE 、V THD The threshold voltages of the first D-HEMT and the first E-HEMT are

[0040] See also Figure 3 The proposed all-GaN integrated negative voltage generation circuit was simulated using the Advanced Design System (ADS). As can be seen from the output terminal VOUT, when the input signal VIIN remains low, the output VOUT remains in a disabled state of 0V. Under the conditions of an input signal frequency of 1MHz and a DC power supply VDD of 10V, the proposed negative voltage generation circuit simultaneously generates a negative voltage close to -7V through the voltage divider circuit. These simulation results demonstrate the high speed and adjustability of the negative voltage generated by the proposed circuit.

[0041] See also Figure 4 , the P-GaN gate enhancement GaN power integration process platform compatible with the embodiments of the present invention.

[0042] From bottom to top, they are Si substrate 01, GaN buffer layer 02, GaN channel layer 03, AlGaN barrier layer 04, P-GaN layer 05, first metal 06 on the surface of AlGaN barrier layer 04, dielectric layer 08, second metal 07 on the surface of P-GaN gate, passivation layer 09, and third metal 10 on the surface of passivation layer 09.

[0043] Furthermore, the GaN channel layer 03 and the AlGaN barrier layer 04 form a heterojunction structure, with a high-concentration 2DEG forming at the heterojunction interface due to polarization effects. The first metal 06 is a low-work-function metal used to form an ohmic contact with the channel layer 03, serving as the device's source, drain, or cathode. The second metal 07 is a high-work-function metal used to form a Schottky contact with the P-GaN layer 05, serving as the device's gate or anode. The third metal 10 is an interconnect metal used to connect various devices in the circuit.

[0044] The integrated circuit is composed of a first device 11, a second device 12, a third device 13, and a fourth device 14 integrated on the same substrate. The first device 11 is composed of a substrate layer 01, a buffer layer 02, a channel layer 03, a barrier layer 04, a P-GaN layer 05, a first metal 06, a second metal 07, and a dielectric layer 08; the second device 12 and the third device 13 are both composed of a substrate layer 01, a buffer layer 02, a channel layer 03, a barrier layer 04, a first metal 06, a second metal 07, and a dielectric layer 08; and the fourth device 14 is composed of a substrate layer 01, a buffer layer 02, a channel layer 03, a barrier layer 04, a first metal 06, a second metal 07, a dielectric layer 08, a second metal 07, a passivation layer 09, and a third metal 10.

[0045] Furthermore, the first device 11 is a P-GaN gate enhancement mode GaN HEMT, abbreviated as E-HEMT; the second device 12 is a MIS depletion mode GaN HEMT, abbreviated as D-HEMT; the third device 13 is a Schottky diode D; and the fourth device 14 is a capacitor C. All of the above devices are low-voltage devices.

[0046] See also Figure 5 , a schematic diagram of the application of negative voltage isolation in a full GaN power IC according to an embodiment of the present invention.

[0047] exist Figure 5 In the figure, the fifth device 15 is integrated with the first device 10 on the same substrate, wherein the fifth device 15 is composed of a substrate layer 01, a buffer layer 02, a channel layer 03, a barrier layer 04, a P-GaN layer 05, a first metal 06, a second metal 07, and a dielectric layer 08, and is a high-voltage P-GaN gate enhancement mode GaN power HEMT.

[0048] The output end of the circuit is a metal electrode 16, which covers the isolation trench 17 between the fifth device 15 and the first device 10. In the above application structure, when the fifth device 15 is turned on, the metal output electrode simultaneously generates a negative electric field to suppress crosstalk noise, thereby improving the stability and operational reliability of low-voltage logic devices represented by the first device 10.

Claims

1. A fully gallium nitride integrated negative voltage generation circuit for negative voltage isolation, used in high-voltage GaN power devices, characterized by: It includes a voltage divider circuit, a pulse signal generating circuit, a first capacitor charging and discharging circuit and a second capacitor charging and discharging circuit; The voltage divider circuit includes a first D-HEMT tube and a first E-HEMT tube; the drain of the first D-HEMT tube is connected to the power supply, the gate and source of the first D-HEMT tube are short-circuited, the source of the first D-HEMT tube is connected to the gate and drain of the first E-HEMT tube, the source of the first E-HEMT tube is grounded, and the drain of the first E-HEMT tube is the output end of the voltage divider circuit; The pulse signal generating circuit includes a second D-HEMT tube and a second E-HEMT tube; the drain of the second D-HEMT tube is connected to the output end of the voltage divider circuit, the gate and source of the second D-HEMT tube are short-circuited and then connected to the drain of the second E-HEMT tube, the gate of the second E-HEMT tube serves as the signal input end of the negative voltage generating circuit, the source of the second E-HEMT tube is grounded, and the drain of the second E-HEMT tube serves as the output end of the pulse signal generating circuit; The first capacitor charging and discharging circuit includes a first diode D1 and a first capacitor C1; the anode of the first diode D1 is connected to the output end of the pulse signal generating circuit through the first capacitor C1, and the cathode of the first diode D1 is grounded; The second capacitor charging and discharging circuit includes a second diode D2 and a second capacitor C2; the cathode of the second diode D2 is connected to the anode of the first diode D1, the anode of the second diode D2 is connected to one end of the second capacitor C2, and the other end of the second capacitor C2 is grounded; one end of the second capacitor C2 is the output end of the negative voltage generating circuit; The pulse signal generating circuit is used to generate a negative voltage generating signal synchronously with the switch of the high-voltage GaN power device, and is used to control the first capacitor charging and discharging circuit and the second capacitor charging and discharging circuit to generate a stable negative voltage.

2. The all-gallium nitride integrated negative voltage generating circuit for negative voltage isolation according to claim 1, characterized in that: The devices used in the negative voltage generation circuit are all integrated on the same substrate based on the P-GaN gate enhancement-mode gallium nitride power integration process platform. The D-HEMT tube, E-HEMT tube, diode, and capacitor are defined as the integrated device. The integrated device is composed of a Si substrate, a GaN buffer layer, a GaN channel layer, and an AlGaN barrier layer from bottom to top. Along the lateral direction of the device, there are D-HEMT tubes, E-HEMT tubes, diodes, and capacitors, which are spaced apart from each other. The two ends of the D-HEMT tube part have a first metal, which penetrates the AlGaN barrier layer in the vertical direction of the device and contacts the GaN channel layer. The middle of the upper surface of the AlGaN barrier layer between the first metals has a P-GaN layer, a dielectric layer is provided between the P-GaN layer and the first metals on both sides, and the upper surface of the P-GaN layer has a second metal The E-HEMT tube portion has a first metal at both ends, which penetrates the AlGaN barrier layer in the vertical direction of the device and contacts the GaN channel layer. A dielectric layer is provided on the upper surface of the AlGaN barrier layer between the first metals, and a second metal is provided in the middle of the upper surface of the dielectric layer. The diode portion has a second metal at the end close to the E-HEMT tube, which penetrates the AlGaN barrier layer in the vertical direction of the device and contacts the GaN channel layer. The diode portion has the first metal at the end away from the E-HEMT tube, the bottom of the first metal contacts the AlGaN barrier layer, and a dielectric layer is provided on the upper surface of the AlGaN barrier layer between the second metal and the first metal. The capacitor portion has a dielectric layer on its upper surface, a second metal is provided on the upper surface of the dielectric layer at the end away from the diode, a passivation layer is provided on the second metal, and a third metal is provided on the passivation layer.

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