Control circuit and method, switching power supply and electronic device

Abstract

The embodiments of the present disclosure disclose a control circuit and method, a switching power supply and an electronic device. The control circuit is applied to a Boost circuit including an inductor, a first power tube and a second power tube. The control circuit comprises: a detection circuit configured to detect the on-off state of the second power tube after the first power tube is turned off; generate a first detection signal in the case that the on-off state of the second power tube is switched to the off state, and generate a first clock signal based on a first voltage signal of the drain end of the first power tube; and a first control circuit configured to control the on-off state of the first power tube based on the first detection signal and the first clock signal after the second power tube is turned off.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, the field of electronic technology, and in particular to a control circuit and method, a switching power supply, and an electronic device. Background Technology

[0002] A boost converter is a switching DC-DC boost circuit that can make the output voltage higher than the input voltage. Based on whether the inductor current in the boost circuit is continuous, boost circuits can be divided into three different operating modes: Continuous Conduction Mode (CCM), Discontinuous Conduction Mode (DCM), and Boundary Conduction Mode (BCM).

[0003] In related technologies, for DCM mode, the peak value of the inductor current is unstable because the on-time of the main power transistor is fixed. Summary of the Invention

[0004] This disclosure provides at least one control circuit and method, a switching power supply, and an electronic device.

[0005] The technical solution of this disclosure embodiment is implemented as follows:

[0006] This disclosure provides a control circuit applied in a Boost circuit including an inductor, a first power transistor, and a second power transistor. The control circuit includes:

[0007] The detection circuit is used to detect the on / off state of the second power transistor after the first power transistor is turned off; when the on / off state of the second power transistor switches to the off state, it generates a first detection signal and generates a first clock signal based on a first voltage signal at the drain terminal of the first power transistor.

[0008] A first control circuit is configured to control the on / off state of the first power transistor based on the first detection signal and the first clock signal after the second power transistor is turned off.

[0009] This disclosure provides a control method applied to the above-described control circuit, the method comprising:

[0010] After the first power transistor is turned off, the on / off state of the second power transistor is detected to obtain the detection result;

[0011] When the detection result indicates that the on / off state of the second power transistor has switched to the off state, a first detection signal is generated, and a first clock signal is generated based on the first voltage signal at the drain terminal of the first power transistor.

[0012] After the second power transistor is turned off, the on / off state of the first power transistor is controlled based on the first detection signal and the first clock signal.

[0013] This disclosure provides a switching power supply, including the control circuit described above.

[0014] This disclosure provides an electronic device including the control circuit described above.

[0015] In this embodiment, the control circuit includes a detection circuit and a first control circuit. The detection circuit is used to detect the on / off state of the second power transistor after the first power transistor is turned off; when the on / off state of the second power transistor switches to the off state, it generates a first detection signal and generates a first clock signal based on a first voltage signal at the drain terminal of the first power transistor; the first control circuit is used to control the on / off state of the first power transistor based on the first detection signal and the first clock signal after the second power transistor is turned off. Thus, controlling the on / off state of the first power transistor using the first detection signal and the first clock signal can, on the one hand, improve the accuracy of the turn-on timing of the first power transistor, ensuring that the inductor current rises from the same initial value in each cycle, thereby reducing the possibility of unstable peak inductor current; on the other hand, it can reduce the influence of the Miller plateau of the power transistor, thereby reducing the power transistor's switching losses.

[0016] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0017] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the specification, serve to illustrate the technical solutions of this disclosure.

[0018] Figure 1A This is a schematic diagram of the composition structure of a Boost circuit in related technologies;

[0019] Figure 1B This is a schematic diagram of inductor current in DCM mode, as described in related technologies.

[0020] Figure 1C A schematic diagram of the composition structure of a control circuit provided in an embodiment of this disclosure;

[0021] Figure 1D A schematic diagram illustrating the generation of various signals based on inductor current, provided as an embodiment of this disclosure;

[0022] Figure 1EA schematic diagram of the composition structure of a detection sub-circuit provided in an embodiment of this disclosure;

[0023] Figure 1F A schematic diagram of the composition structure of a signal generation circuit provided in an embodiment of this disclosure;

[0024] Figure 1G A schematic diagram of the composition structure of a signal generation circuit provided in an embodiment of this disclosure;

[0025] Figure 1H A schematic diagram of the composition structure of a control circuit provided in an embodiment of this disclosure;

[0026] Figure 1I A schematic diagram of inductor current in DCM mode provided for an embodiment of this disclosure;

[0027] Figure 2 This is a schematic diagram illustrating the implementation process of a control method provided in an embodiment of this disclosure. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of this disclosure clearer, the disclosure will be further described in detail below with reference to the accompanying drawings. The described embodiments should not be regarded as limitations on this disclosure. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0029] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0030] In the following description, the terms “first, second, third” are used merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that “first, second, third” may be interchanged in a specific order or sequence where permitted, so that the embodiments of this disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0031] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of this disclosure only and is not intended to be limiting of this disclosure.

[0032] Figure 1A This is a schematic diagram of the composition structure of a Boost circuit in related technologies, such as... Figure 1A As shown, the Boost circuit includes a voltage source Vin, an inductor L, a first power transistor M1, a second power transistor M2, a capacitor C, and a load R.

[0033] It should be understood that this disclosure also applies to other Boost circuits with similar structures.

[0034] During implementation, under the influence of the clock signal CLK, a pulse width modulation (PWM) signal of a certain frequency is generated at the gate (G) of M1 through circuit loop control (i.e., returning a portion of the output to the input). This PWM signal can be used to control the on / off state of M1.

[0035] When the PWM signal is high, CLK is also high. Since the gate of M1 is high, then V... GS If the value is greater than the conduction threshold, then M1 can be turned on;

[0036] When the PWM signal is low, CLK can be high or low. Since M1 is turned off when the gate of M1 is low.

[0037] Ideally, if M1 is on, it can be considered a conductor; if M1 is off, it can be considered an open circuit. That is:

[0038] With M1 conducting, Vin supplies power to L, causing L to store energy, and C discharges to R. As time increases, the current i on L increases. L It will continue to increase.

[0039] With M1 off, L releases its stored electrical energy. Vin and L, connected in series, charge C and simultaneously supply power to R. At this time, the voltage Vout across R is greater than Vin. As time increases, the current i across L... L It will continue to decrease. After entering DCM mode, when i L When it approaches 0, M2 will turn off, at which point due to V LX The potential of i is not 0, making i L The parasitic capacitance Cds of M1 oscillates around 0 in the resonant circuit formed by L, thus causing V to... LX The potential will also oscillate at the same frequency as Vin. Then, in the next cycle of the PWM, M1 turns on. Since the on-time of M1 is fixed (i.e., the percentage of time the PWM signal is high), i... L The starting values ​​are different, causing i to... L The peak value is unstable.

[0040] Figure 1B This is a schematic diagram of inductor current in DCM mode in related technologies, such as... Figure 1B As shown, during the time t0 when the PWM1 signal is high, M1 is on and M2 is off, causing iL increases with time until it reaches the peak value; during the time t1 when the PWM1 signal is at the low level, M1 switches from conduction to cutoff and M2 switches from cutoff to conduction, causing i L to decrease with time. When i L is close to 0, M2 turns off. During the time t2 when the PWM1 signal is at the low level, M1 remains off and M2 switches from conduction to cutoff. Since the potential of V LX is not 0, it causes i L to oscillate around 0 in the resonant circuit composed of the parasitic capacitance Cds of M1 and L until the next cycle of the PWM1 signal arrives.

[0041] During the first cycle T1 of PWM1, the initial value of i L is Y11, and Y11 is approximately 0. The peak value of i L is Y12. During the time t0 of T1, M1 is on and M2 is off; during the time t1 of T1, M1 switches from conduction to cutoff and M2 switches from cutoff to conduction; during the time t2 of T1, M1 remains off and M2 switches from conduction to cutoff;

[0042] During the second cycle T2 of PWM1, the initial value of i L is Y21, and Y21 is less than 0. The peak value of i L is Y22. Since Y21 < Y11, Y22 < Y12. During the time t0 of T2, M1 is on and M2 is off; during the time t1 of T2, M1 switches from conduction to cutoff and M2 switches from cutoff to conduction; during the time t2 of T, M1 remains off and M2 switches from conduction to cutoff;

[0043] During the third cycle T3 of PWM1, the initial value of i L is Y31, and Y31 is greater than 0. The peak value of i L is Y32. Since Y31 > Y11, Y32 < Y12. During the time t0 of T3, M1 is on and M2 is off; during the time t1 of T3, M1 switches from conduction to cutoff and M2 switches from cutoff to conduction; during the time t2 of T3, M1 remains off and M2 switches from conduction to cutoff.

[0044] The embodiment of the present disclosure provides a control circuit that controls the on - off state of the first power transistor through the first detection signal and the first clock signal. On the one hand, it can improve the accuracy of the conduction moment of the first power transistor, so that the inductor current starts to rise from the same initial value in each cycle, thereby reducing the possibility of unstable peak value of the inductor current; on the other hand, it can reduce the influence of the Miller plateau of the power transistor, thereby reducing the on - off loss of the power transistor.

[0045] The technical solutions in the embodiments of this disclosure will now be clearly and completely described with reference to the accompanying drawings.

[0046] Figure 1C This is a schematic diagram of the composition structure of a control circuit provided in an embodiment of the present disclosure, such as... Figure 1C As shown, the control circuit is applied in a Boost circuit including an inductor L, a first power transistor M1, and a second power transistor M2. The control circuit 100 includes a detection circuit 111 and a first control circuit 112, wherein:

[0047] The detection circuit 111 is used to detect the on / off state of the second power transistor M2 after the first power transistor M1 is turned off; when the on / off state of the second power transistor M2 is switched to the off state, it generates a first detection signal and generates a first clock signal based on the first voltage signal at the drain terminal of the first power transistor M1.

[0048] The first control circuit 112 is used to control the on / off state of the first power transistor M1 based on the first detection signal and the first clock signal after the second power transistor M2 is turned off.

[0049] Here, the detection circuit 111 can be any circuit capable of performing the above-mentioned functions. For example, it can be a digital circuit, an analog circuit, etc. Examples include a detection chip, a flip-flop, a circuit with comparison functionality, a circuit with zero-crossing detection functionality, a circuit with signal phase-changing functionality, etc. In implementation, those skilled in the art can determine the implementation method of the detection circuit according to actual needs, and this disclosure does not limit this. In some embodiments, the detection circuit 111 operates during the period when the first power transistor M1 is off, and does not operate during the period when the first power transistor M1 is on.

[0050] The first power transistor M1 can be any suitable power transistor, such as a transistor, a field-effect transistor, or an NMOS (N-Metal-Oxide-Semiconductor). In practice, those skilled in the art can choose the first power transistor according to actual needs; this disclosure does not limit the choice.

[0051] The second power transistor M2 can be any suitable power transistor, such as a diode, transistor, or field-effect transistor. For example, a PMOS (P-Metal-Oxide-Semiconductor). In practice, those skilled in the art can choose the second power transistor according to actual needs, and the embodiments disclosed herein are not limited thereto.

[0052] The on / off state may include, but is not limited to, being on (closed) and off (open). In implementation, those skilled in the art can use any suitable method to represent the on / off state, and the embodiments disclosed herein are not limited thereto. For example, "1" represents being on and "0" represents being off.

[0053] In some implementations, the on / off state of the second power transistor can be detected using any suitable detection method. For example, detecting the voltage value, detecting the current inductance, etc. In practice, those skilled in the art can choose the detection method according to actual needs, and this disclosure does not limit the method. For example, real-time measurement of the current i across the inductor. L According to i L The on / off state of the second power transistor is obtained, that is: when i L When the value is not 0, the second power transistor is in the on state; when i L When the voltage is close to 0, the second power transistor is in the off state. For example, by measuring the source and drain voltages of the second power transistor in real time, when the drain voltage is greater than the source voltage, the second power transistor is in the on state; when the drain voltage is close to the source voltage, the second power transistor is in the off state.

[0054] The first detection signal represents the current i on the inductor L. L Enter DCM mode. At this time, due to the voltage V at the drain terminal of the first power transistor M1... LX It is not 0, so that i L The parasitic capacitance Cds of M1 oscillates around 0 in the resonant circuit formed by the inductance L, thus causing V to... LX It will also oscillate at the same frequency as the voltage source Vin to generate a first voltage signal. In implementation, those skilled in the art can represent the first detection signal in any suitable way, and this disclosure does not limit this. For example, a true first detection signal indicates entry into DCM mode. Or, for example, a 1 first detection signal indicates entry into DCM mode.

[0055] The first clock signal is a square wave signal with the same frequency as the first voltage signal. In implementation, the first voltage signal can be converted into the first clock signal using any suitable conversion method, such as zero-crossing detection. Those skilled in the art can choose the conversion method according to actual needs, and this disclosure does not limit the specific method used.

[0056] The first control circuit 112 can be any circuit capable of performing the above functions. For example, it can be a digital circuit, an analog circuit, or a trigger or control chip. In implementation, those skilled in the art can determine the implementation method of the first control circuit according to actual needs; this disclosure does not limit this. In some embodiments, the first control circuit 112 operates when M1 is off and M2 is also off, and does not operate when M1 is on or M2 is on.

[0057] Controlling the on / off state of the first power transistor M1 can include, but is not limited to, the first clock signal being a rising edge / high level and the first detection signal being true, the first detection signal being false, or the first clock signal being a falling edge / low level. In implementation, those skilled in the art can independently set the on / off state of the first power transistor M1 according to actual needs; this disclosure does not impose limitations. For example, when the first clock signal is a rising edge and the first detection signal is true, the on / off state of the first power transistor M1 is switched to the on state; when the first clock signal is a falling edge and / or the first detection signal is false, the on / off state of the first power transistor M1 is maintained in the off state.

[0058] In this embodiment, the control circuit includes a detection circuit and a first control circuit. The detection circuit is used to detect the on / off state of the second power transistor after the first power transistor is turned off; when the on / off state of the second power transistor switches to the off state, it generates a first detection signal and generates a first clock signal based on a first voltage signal at the drain terminal of the first power transistor; the first control circuit is used to control the on / off state of the first power transistor based on the first detection signal and the first clock signal after the second power transistor is turned off. Thus, controlling the on / off state of the first power transistor using the first detection signal and the first clock signal can, on the one hand, improve the accuracy of the turn-on timing of the first power transistor, ensuring that the inductor current rises from the same initial value in each cycle, thereby reducing the possibility of unstable peak inductor current; on the other hand, it can reduce the influence of the Miller plateau of the power transistor, thereby reducing the power transistor's switching losses.

[0059] In some embodiments, the detection circuit 111 includes an electrically connected differentiating circuit and a zero-crossing detection circuit; the differentiating circuit is used to adjust the phase of a first voltage signal at the drain terminal of the first power transistor to generate a second voltage signal when the second power transistor is in an off state; the zero-crossing detection circuit is used to perform zero-crossing detection on the second voltage signal to generate the first clock signal.

[0060] Here, the differentiating circuit can be any circuit capable of performing a differentiating function. For example, a differentiator, such as an RC differentiator. In implementation, those skilled in the art can determine the implementation method of the differentiating circuit according to actual needs, and the embodiments disclosed herein are not limited thereto.

[0061] The second voltage signal and the first voltage signal have the same frequency and amplitude, but different phases. The phase difference between the second voltage signal and the first voltage signal can be any suitable value, such as 45° or -90°.

[0062] The zero-crossing detection circuit can be any circuit capable of implementing zero-crossing detection. Examples include digital circuits and analog circuits. For instance, it could be a zero-crossing detection chip, a comparator, or a depletion-type NMOS transistor (with a threshold voltage of 0). In implementation, those skilled in the art can determine the implementation method of the zero-crossing detection circuit according to actual needs; this disclosure does not limit such implementation.

[0063] Figure 1D A schematic diagram illustrating the generation of various signals based on inductor current, as provided in this disclosure embodiment, is shown below. Figure 1D As shown, after the second power transistor M2 is turned off (i.e., i... L When V is close to 0, due to LX The potential of i is not 0, making i L The parasitic capacitance Cds of M1 oscillates around 0 in the resonant circuit formed by L, generating a current signal i. L Thus making V LX The potential will also oscillate at the same frequency with Vin as the center value, generating the first voltage signal LX. After the first voltage signal LX is processed by the differentiating circuit, it generates the second voltage signal Cout at the same frequency. After the second voltage signal is processed by the zero detection circuit, it generates the first clock signal Dout at the same frequency.

[0064] In this embodiment, when the second power transistor is in the off state, a differentiating circuit adjusts the phase of the first voltage signal at the drain terminal of the first power transistor to generate a second voltage signal. A zero-crossing detection circuit then detects the zero-crossing of this second voltage signal to generate the first clock signal. This method of generating the first clock signal using the differentiating circuit and the zero-crossing detection circuit improves the accuracy of the first clock signal, thereby enabling precise control of the first power transistor's off state. This ensures that the inductor current rises from the same initial value in each cycle, reducing the possibility of unstable peak values ​​in the inductor current.

[0065] In some embodiments, the detection circuit 111 includes a detection sub-circuit; the detection sub-circuit is used to detect a first voltage value at the drain terminal of the first power transistor and a second voltage value at the source terminal of the second power transistor, and when the first voltage value and the second voltage value meet a preset condition, to switch the on / off state of the second power transistor to the off state and generate the first detection signal.

[0066] Here, the detection sub-circuit can be any circuit capable of performing the above functions. For example, digital circuits, analog circuits, etc., such as flip-flops, comparators, etc. In implementation, those skilled in the art can determine the implementation method of the detection sub-circuit according to actual needs; this disclosure does not limit this approach.

[0067] The preset conditions may include, but are not limited to, approximate equality or approximate to a certain preset value. In implementation, those skilled in the art can independently set the preset conditions according to actual needs; this disclosure does not limit such settings. For example, when the first voltage value and the second voltage value are approximately equal, the second power transistor M2 is turned off.

[0068] In some embodiments, the detection subcircuit includes a comparator and a first flip-flop; the comparator includes a first input, a second input, and a first output; the first flip-flop includes a third input, a fourth input, a second output, and a third output.

[0069] Here, the first input of the comparator receives a first voltage value, the second input of the comparator receives a second voltage value, and the first output of the comparator is coupled to the third input of the first flip-flop.

[0070] The third input of the first flip-flop is coupled to the first output of the comparator. The fourth input of the first flip-flop receives an enable signal, and the second output of the first flip-flop provides a first detection signal and an inverted signal of the first detection signal. The enable signal is used to control the off state of the first power transistor M1. In implementation, the first flip-flop can be any suitable flip-flop, such as an RS flip-flop or a D flip-flop. Those skilled in the art can customize the first flip-flop according to actual needs; this disclosure does not limit the specific implementation.

[0071] In practice, when the third input of the first flip-flop receives a high level 1, the second output of the first flip-flop also provides a first detection signal of 1.

[0072] Figure 1E This is a schematic diagram of the composition structure of a detection sub-circuit provided in an embodiment of the present disclosure, such as... Figure 1E As shown, the detection sub-circuit includes a comparator Comp and a first flip-flop RS, wherein:

[0073] The first input (+) of comparator Comp receives the first voltage value V. LX The second input terminal (-) receives the second voltage value V. out The first output terminal Out1 is connected to the third input terminal S of the first flip-flop RS;

[0074] The third input S of the first flip-flop RS is coupled to the first output Out1 of the comparator Comp. The fourth input R receives the enable signal Nmos_on. The second output Q1 provides the first detection signal DCM. The third output... Provides the inverted signal of the first detection signal DCM In practice, if the signal Cmp_out output by the first output terminal Out1 of the comparator Comp is 1, then the first detection signal DCM output by the second output terminal Q of the first flip-flop RS is also 1.

[0075] In this embodiment, a detection sub-circuit detects a first voltage value at the drain terminal of the first power transistor and a second voltage value at the source terminal of the second power transistor. When the first and second voltage values ​​meet a preset condition, the on / off state of the second power transistor is switched to the off state, and the first detection signal is generated. This improves the accuracy of the second power transistor's turn-off timing by using the detection sub-circuit, preventing energy loss at the output terminal due to the inductor current dropping to a negative value. Furthermore, generating the first detection signal improves its accuracy, allowing for precise control of the first power transistor's off state. This ensures that the inductor current rises from the same initial value in each cycle, reducing the possibility of unstable peak inductor current.

[0076] In some embodiments, the first control circuit 112 includes a signal generation circuit and a second control circuit that are electrically connected; the signal generation circuit is used to generate a second detection signal based on a preset second clock signal and the first detection signal; and to generate an enable signal based on the second detection signal and the first clock signal; the second control circuit is used to control the on / off state of the first power transistor based on the enable signal.

[0077] Here, the signal generation circuit can be any suitable circuit capable of generating a detection signal. For example, digital circuits, analog circuits, etc., such as AND gates, signal generators, etc. In implementation, those skilled in the art can independently determine the implementation method of the signal generation circuit according to actual needs; this disclosure does not limit this approach.

[0078] The second clock signal can be a square wave signal of any suitable frequency. In implementation, those skilled in the art can set the frequency of the second clock signal according to actual needs, and the embodiments disclosed herein are not limited thereto.

[0079] The second detection signal may be the same as or different from the first detection signal. In implementation, those skilled in the art can represent the second detection signal in any suitable manner, and this disclosure does not limit this. For example, the second detection signal may be true or false. Another example is that the second detection signal is 1 or 0.

[0080] The method of generating the second detection signal may include, but is not limited to, the first detection signal, the second clock signal, the AND operation of the second clock signal and the first detection signal, or the OR operation of the second clock signal and the first detection signal. In implementation, those skilled in the art can choose the method of generating the second detection signal according to actual needs, and this disclosure does not limit this method. For example, the second detection signal can be obtained by ANDing the second clock signal and the first detection signal; that is, the second detection signal is true when the second clock signal is high and the first detection signal is true, and false when the second clock signal is low or the first detection signal is false.

[0081] The enable signal Nmos_on is used to control the off state of the first power transistor M1. In implementation, those skilled in the art can represent the enable signal in any suitable manner, and this disclosure does not limit the representation. For example, when the enable signal Nmos_on is true, the first power transistor M1 is turned on; when the enable signal Nmos_on is false, the first power transistor M1 is turned off. As another example, when the enable signal Nmos_on is 1, the first power transistor M1 is turned off; when the enable signal Nmos_on is 0, the first power transistor is turned on.

[0082] The enable signal Nmos_on can be generated in ways including, but not limited to, a previous enable signal, a second detection signal, a first clock signal, an AND operation between the first clock signal and the second detection signal, or an OR operation between the first clock signal and the second detection signal. In implementation, those skilled in the art can choose the method for generating the enable signal according to actual needs; this disclosure does not limit such methods.

[0083] For example, when the first clock signal is at a high level / rising edge, the second detection signal is used as the enable signal Nmos_on; when the first clock signal is at a low level / falling edge, the previous enable signal Nmos_on_pre is used as the enable signal Nmos_on.

[0084] In some embodiments, the signal generation circuit is further configured to: use the second detection signal as the enable signal during the rising edge of the first clock signal; and / or use the previous enable signal as the enable signal during the falling edge of the first clock signal.

[0085] Here, when the first clock signal is at its rising edge, if the second detection signal is true, then the enable signal Nmos_on is true, and the first power transistor M1 can be turned on or remain turned on. If the second detection signal is false, then the enable signal Nmos_on is also false, and the first power transistor M1 can be turned off or remain turned off. When the first clock signal is at its falling edge, if the previous enable signal Nmos_on_pre is true, then the enable signal Nmos_on continues to be true, and the first power transistor M1 remains on. If the previous enable signal Nmos_on_pre is false, then the enable signal Nmos_on continues to be false, and the first power transistor M1 remains off.

[0086] In some embodiments, the signal generation circuit includes a first AND gate and a second flip-flop that are electrically connected, wherein the first AND gate includes a fifth input, a sixth input, and a fourth output, and the second flip-flop includes a seventh input, an eighth input, and a fifth output.

[0087] Here, the fifth input of the first AND gate receives the second clock signal, the sixth input of the first AND gate receives the first detection signal, and the fourth output of the first AND gate is coupled to the seventh input of the second flip-flop.

[0088] The seventh input of the second flip-flop is coupled to the fourth output of the first AND gate, the eighth input of the second flip-flop receives the first clock signal, and the fifth output of the second flip-flop provides an enable signal. In implementation, the second flip-flop can be any suitable flip-flop, such as an RS flip-flop or a D flip-flop. Those skilled in the art can customize the second flip-flop according to actual needs; this disclosure does not impose any limitations.

[0089] Figure 1F This is a schematic diagram of the composition structure of a signal generation circuit provided in an embodiment of the present disclosure, as shown below. Figure 1F As shown, the signal generation circuit includes a first AND gate A1 and a second flip-flop DFF, wherein:

[0090] The fifth input terminal U5 of the first AND gate A1 receives the second clock signal CLK, the sixth input terminal U6 receives the first detection signal DCM, and the fourth output terminal Out4 is connected to the seventh input terminal D of the second flip-flop DFF;

[0091] The seventh input D of the second flip-flop DFF is coupled to the fourth output Out4 of the first AND gate A1; the eighth input C1 receives the first clock signal Dout; the fifth output Q2 provides the enable signal Nmos_on; and the sixth output... Provides the inverted signal of the enable signal Nmos_on

[0092] In some embodiments, the signal generation circuit further includes an OR gate and a second AND gate, wherein the second AND gate includes a ninth input terminal, a tenth input terminal, and a sixth output terminal, and the OR gate includes an eleventh input terminal, a twelfth input terminal, and a seventh output terminal.

[0093] Here, the ninth input of the second AND gate receives the second clock signal, the tenth input receives the inverted signal of the first detection signal, and the sixth output of the second AND gate is coupled to the eleventh input of the OR gate. In implementation, when the inductor current in the Boost circuit operates in CCM mode, the first detection signal DCM is 0. If the second clock signal is high, the enable signal Nmos_on is 1, and the first power transistor M1 will be normally turned on.

[0094] The eleventh input of the OR gate is coupled to the sixth output of the second AND gate, and the twelfth input of the OR gate is coupled to the fifth output of the second flip-flop. An enable signal is provided at the seventh output of the OR gate. In implementation, when the inductor current in the Boost circuit operates in DCM mode, the first detection signal DCM is 1. If the second clock signal CLK is high, the second detection signal is 1, but the first power transistor M1 will not be immediately turned on. Instead, it will wait until the first clock signal is at its rising edge, at which point the signal output from the fifth output of the second flip-flop will be consistent with the second detection signal, i.e., outputting a high level (1), making the enable signal Nmos_on 1. Only then will the first power transistor M1 be turned on. When the enable signal Nmos_on is 1, the first and second flip-flops are simultaneously reset, clearing the first detection signal DCM and the second flip-flop to zero.

[0095] Figure 1G This is a schematic diagram of the composition structure of a signal generation circuit provided in an embodiment of the present disclosure, as shown below. Figure 1G As shown, the signal generation circuit includes a first AND gate A1, a second AND gate A2, an OR gate A3, and a second flip-flop DFF, wherein:

[0096] The fifth input terminal U5 of the first AND gate A1 receives the second clock signal CLK, the sixth input terminal U6 receives the first detection signal DCM, and the fourth output terminal Out4 is connected to the seventh input terminal D2 of the second flip-flop DFF;

[0097] The ninth input U9 of the second AND gate A2 receives the second clock signal CLK, and the tenth input U10 receives the inverted signal of the first detection signal DCM. The sixth output terminal Out6 is coupled to the eleventh input terminal U11 of OR gate A3;

[0098] The eleventh input terminal U11 of OR gate A3 is coupled to the sixth output terminal Out6 of the second AND gate A2, and the twelfth input terminal U12 is coupled to the fifth output terminal Q2 of the second flip-flop DFF. The seventh output terminal Out7 provides the enable signal Nmos_on.

[0099] The seventh input terminal D of the second flip-flop DFF is coupled to the fourth output terminal Out4 of the first AND gate A1, the eighth input terminal C1 receives the first clock signal Dout, and the fifth output terminal Q2 is coupled to the twelfth input terminal U12 of the OR gate A3.

[0100] In implementation, when DCM is 1 and the second clock signal is high, DFF is enabled. When the rising edge of the first clock signal Dout is detected, DFF outputs Q2 as 1, which makes the enable signal also 1. At this time, the first power transistor is turned on. This ensures that the inductor current rises from the same initial value in each cycle of the second clock signal, thereby reducing the possibility of unstable peak inductor current caused by resonance.

[0101] The second control circuit can be any circuit capable of performing the above functions. For example, it can be a digital circuit, an analog circuit, or a trigger or control chip. In implementation, those skilled in the art can determine the implementation method of the second control circuit according to actual needs; this disclosure does not limit such implementation.

[0102] In some embodiments, the second control circuit is further configured to: switch the on / off state of the first power transistor to the on state when the enable signal is true; and / or, keep the on / off state of the first power transistor in the off state when the enable signal is false.

[0103] Here, if the enable signal Nmos_on is true, the first power transistor M1 is turned on; if the enable signal Nmos_on is false, the first power transistor M1 remains off.

[0104] In this embodiment, a signal generation circuit generates a second detection signal based on a preset second clock signal and a first detection signal; an enable signal is generated based on the second detection signal and the first clock signal; and a second control circuit controls the on / off state of the first power transistor based on the enable signal. Thus, by controlling the off state of the first power transistor using a simple circuit structure such as the signal generation circuit and the second control circuit, firstly, the accuracy of the first power transistor's turn-on timing can be improved, ensuring that the inductor current rises from the same initial value in each cycle, thereby reducing the possibility of unstable peak inductor current; secondly, the influence of the Miller plateau of the power transistor can be reduced, thereby reducing the switching losses of the power transistor; and finally, not only can the cost be reduced, but the applicability of the Boost circuit can also be expanded.

[0105] Figure 1H This is a schematic diagram of the composition structure of a control circuit provided in an embodiment of the present disclosure, such as... Figure 1H As shown, the control circuit includes a differentiator RC (corresponding to the aforementioned differentiator circuit), a zero-crossing detector Z (corresponding to the aforementioned zero-crossing detection circuit), a comparator Comp, a first flip-flop RS, a first AND gate A1, a second AND gate A2, an OR gate A3, and a second flip-flop DFF, wherein:

[0106] The differentiator RC receives the first voltage signal LX and adjusts the phase of the first voltage signal LX to obtain the second voltage signal Cout;

[0107] The zero-crossing detector Z receives the second voltage signal Cout and generates a first clock signal Dout based on the second voltage signal Cout. The first clock signal Dout is then sent to the eighth input terminal C1 of the second flip-flop DFF.

[0108] The first input (+) of comparator Comp receives the first voltage value V. LX The second input terminal (-) receives the second voltage value V. out The first output terminal Out1 is connected to the third input terminal S of the first flip-flop RS;

[0109] The third input S of the first flip-flop RS is coupled to the first output Out1 of the comparator Comp. The fourth input R receives the enable signal Nmos_on. The second output Q1 provides the first detection signal DCM. The third output... Provides the inverted signal of the first detection signal DCM

[0110] The fifth input terminal U5 of the first AND gate A1 receives the second clock signal CLK, the sixth input terminal U6 is coupled to the second output terminal Q1 of the first flip-flop RS, and is used to receive the first detection signal DCM. The fourth output terminal Out4 is connected to the seventh input terminal D2 of the second flip-flop DFF.

[0111] The ninth input U9 of the second AND gate A2 receives the second clock signal CLK, and the tenth input U10 is coupled to the third output of the first flip-flop RS. Inverted signal used to receive the first detection signal DCM The sixth output terminal Out6 is coupled to the eleventh input terminal U11 of OR gate A3;

[0112] The eleventh input terminal U11 of OR gate A3 is coupled to the sixth output terminal Out6 of the second AND gate A2, the twelfth input terminal U12 is coupled to the fifth output terminal Q2 of the second flip-flop DFF, and the seventh output terminal Out7 provides the enable signal Nmos_on to control the turn-off state of the first power transistor.

[0113] The seventh input terminal D of the second flip-flop DFF is coupled to the fourth output terminal Out4 of the first AND gate A1, the eighth input terminal C1 receives the first clock signal Dout generated by the zero-crossing detector Z, and the fifth output terminal Q2 is coupled to the twelfth input terminal U12 of the OR gate A3.

[0114] In implementation, when the inductor current i L When entering DCM mode, due to the voltage V at the drain terminal of the first power transistor M1 LX It is not 0, so that i L The parasitic capacitance Cds of M1 oscillates around 0 in the resonant circuit formed by the inductance L, thus causing V to... LX It will also oscillate at the same frequency with the voltage source Vin as the center value to generate the first voltage signal LX;

[0115] The first voltage signal LX is processed by the differentiator RC to generate a second voltage signal Cout of the same frequency. When LX resonates to the valley value, the corresponding Cout is the zero crossing point during the rise.

[0116] The second voltage signal Cout passes through the zero-crossing detector Z to generate the first clock signal Dout of the same frequency. When LX resonates to the valley value, Cout is the zero-crossing point when it rises. At this time, Dout generates a rising edge and sends the rising edge generated by Dout into the second flip-flop DFF.

[0117] When the signal Cmp_out output by the first output terminal Out1 of comparator Comp is 0, it indicates that the inductor current is in CCM mode. The first detection signal DCM can be obtained as 0 through the first flip-flop RS. Then, when the second clock signal CLK is high, the enable signal Nmos_on output by the seventh output terminal Out7 of OR gate A3 is 1. At this time, the first power transistor M1 is turned on.

[0118] When the signal Cmp_out output by the first output terminal Out1 of comparator Comp is 1, it indicates that the inductor current is in DCM mode. The first detection signal DCM is 1 can be obtained through the first flip-flop RS. Using the second flip-flop DFF, when the first clock signal Dout is rising, the output signal of the fifth output terminal Q2 of the second flip-flop is 1, and the enable signal Nmos_on output by the seventh output terminal Out7 of OR gate A3 is 1. At this time, the first power transistor M1 is turned on.

[0119] In implementation, when the second clock signal CLK is high, the first power transistor M1 is not immediately turned on. Instead, it waits until the first voltage signal LX resonates to its lowest point before turning on M1. This ensures that, firstly, the inductor current rises from the same initial value in each cycle of the second clock signal CLK, reducing the possibility of instability in the inductor current peak due to resonance; secondly, it reduces the Miller plateau effect of the first power transistor, thus reducing switching losses; and finally, by implementing power transistor turn-off control through a simple circuit structure, it not only reduces costs but also expands the applicability of the Boost circuit.

[0120] Figure 1I A schematic diagram of inductor current in DCM mode provided by an embodiment of this disclosure is shown below. Figure 1I As shown, when the clock signal CLK switches to a high level, the PWM2 signal does not immediately switch to a high level, but continues to remain at a low level, causing the first power transistor M1 to remain off until the inductor current i L When Nmos_on is 0 (i.e., Nmos_on is 1), the PWM2 signal switches to a high level, causing the first power transistor M1 to switch from off to on. During the time td when the PWM2 signal is low, both M1 and M2 are off; during the time t0 when the PWM2 signal is high, M1 switches from off to on, and M2 remains off, causing i L It will increase with time until it reaches its peak; during the time t1 when the PWM2 signal is low, M1 switches from on to off and M2 switches from off to on, causing i L It will decrease as time increases, when i LWhen the voltage approaches 0, M2 will turn off. During the time t2 when the PWM2 signal is low, M1 remains off, and M2 switches from on to off. This is because V... LX The potential of i is not 0, making i L The parasitic capacitance Cds of M1 and L form a resonant circuit that oscillates around 0 until the next cycle of the PWM2 signal arrives. That is:

[0121] During the first cycle T21 of PWM2, i L The initial value is Y11, which is approximately 0, i L The peak value is Y12. During time td of T21, both M1 and M2 are off; during time t0 of T21, M1 switches from off to on, while M2 remains off; during time t1 of T21, M1 switches from on to off, and M2 switches from off to on; during time t2 of T21, M1 remains off, and M2 switches from on to off.

[0122] During the second cycle T22 of PWM2, i L The initial value is Y21, i L The peak value is Y22, where Y21 is approximately Y11 and Y22 is approximately Y12. During time td of T22, M1 and M2 are both off; during time t0 of T22, M1 switches from off to on, while M2 remains off; during time t1 of T22, M1 switches from on to off, and M2 switches from off to on; during time t2 of T22, M1 remains off, and M2 switches from on to off.

[0123] During the third cycle T23 of PWM2, i L The initial value is Y31, i L The peak value is Y32, where Y31 is approximately Y11 and Y32 is approximately Y12. During time td of T23, M1 is turned off and M2 is turned off; during time t0 of T23, M1 switches from off to on and M2 remains off; during time t1 of T23, M1 switches from on to off and M2 switches from off to on; during time t2 of T23, M1 remains off and M2 switches from on to off.

[0124] In implementation, compared to Figure 1B In this case, the periods, high-level duration t0, and low-level duration (td+t1+t2) of the PWM1 and PWM2 signals are the same, but their phases are different. This ensures that the inductor current rises from the same initial value in each cycle of the PWM2 signal, thereby reducing the possibility of unstable peak inductor current due to resonance.

[0125] Based on the above embodiments, this disclosure provides a control method applicable to any of the above control circuits. Figure 2 This is a schematic diagram illustrating the implementation flow of a control method provided in an embodiment of this disclosure, as shown below. Figure 2 As shown, the method includes steps S21 to S23, wherein:

[0126] Step S21: After the first power transistor is turned off, the on / off state of the second power transistor is detected to obtain the detection result.

[0127] Here, the first power transistor M1 can be any suitable power transistor, such as an NMOS transistor or a field-effect transistor. The second power transistor M2 can also be any suitable power transistor, such as a diode or a PMOS transistor.

[0128] The detection result characterizes the on / off state of the second power transistor. The on / off state may include, but is not limited to, being on (closed) or off (open). In implementation, those skilled in the art can use any suitable method to represent the on / off state, and this disclosure does not impose any limitations. For example, "1" represents on, and "0" represents off.

[0129] In some implementations, the on / off state of the second power transistor can be detected using any suitable detection method. For example, detecting the voltage value, detecting the current or inductance, etc.

[0130] Step S22: When the detection result indicates that the on / off state of the second power transistor has switched to off, a first detection signal is generated, and a first clock signal is generated based on the first voltage signal at the drain terminal of the first power transistor.

[0131] Here, the first detection signal represents the inductor current i L Entering DCM mode. In implementation, those skilled in the art can represent the first detection signal in any suitable manner, and this disclosure does not limit the embodiments. For example, a true first detection signal indicates entering DCM mode. Or, for example, a 1 first detection signal indicates entering DCM mode.

[0132] Because the voltage V at the drain terminal of the first power transistor M1 LX It is not 0, so that i L The parasitic capacitance Cds of M1 oscillates around 0 in the resonant circuit formed by the inductance L, thus causing V to... LX It will also oscillate at the same frequency as the voltage source Vin to generate the first voltage signal.

[0133] The first clock signal is a square wave signal with the same frequency as the first voltage signal. In implementation, the first voltage signal can be converted into the first clock signal using any suitable conversion method, such as zero-crossing detection.

[0134] Step S23: After the second power transistor is turned off, the on / off state of the first power transistor is controlled based on the first detection signal and the first clock signal.

[0135] Here, controlling the on / off state of the first power transistor M1 can include, but is not limited to, the first clock signal being a rising edge / high level and the first detection signal being true, the first detection signal being false, or the first clock signal being a falling edge / low level. In implementation, those skilled in the art can independently set the on / off state of the first power transistor M1 according to actual needs; this disclosure does not impose limitations. For example, when the first clock signal is a rising edge and the first detection signal is true, the on / off state of the first power transistor M1 is switched to the on state; when the first clock signal is a falling edge and / or the first detection signal is false, the on / off state of the first power transistor M1 is maintained in the off state.

[0136] In this embodiment, the on / off state of the second power transistor is detected after the first power transistor is turned off, and a detection result is obtained. If the detection result indicates that the on / off state of the second power transistor has switched to off, a first detection signal is generated, and a first clock signal is generated based on a first voltage signal at the drain terminal of the first power transistor. After the second power transistor is turned off, the on / off state of the first power transistor is controlled based on the first detection signal and the first clock signal. Thus, controlling the on / off state of the first power transistor using the first detection signal and the first clock signal can, on the one hand, improve the accuracy of the turn-on timing of the first power transistor, ensuring that the inductor current rises from the same initial value in each cycle, thereby reducing the possibility of unstable peak inductor current. On the other hand, it can reduce the influence of the Miller plateau of the power transistor, thereby reducing the power transistor's switching losses.

[0137] In some embodiments, step S22, "generating a first detection signal when the detection result indicates that the on / off state of the second power transistor has switched to the off state," includes steps S221 to S222, wherein:

[0138] Step S221: Detect the first voltage value at the drain terminal of the first power transistor and the second voltage value at the source terminal of the second power transistor;

[0139] Step S222: When the first voltage value and the second voltage value meet the preset conditions, switch the on / off state of the second power transistor to the off state and generate the first detection signal.

[0140] In some embodiments, the step S22 of "generating a first clock signal based on the first voltage signal at the drain terminal of the first power transistor" includes steps S241 to S242, wherein:

[0141] Step S241: When the second power transistor is in the off state, adjust the phase of the first voltage signal at the drain terminal of the first power transistor to generate a second voltage signal.

[0142] Step S242: Perform zero-crossing detection on the second voltage signal to generate the first clock signal.

[0143] In some implementations, step S23, "controlling the on / off state of the first power transistor based on the first detection signal and the first clock signal," includes steps S231 to S233, wherein:

[0144] Step S231: Generate a second detection signal based on a preset second clock signal and the first detection signal.

[0145] Step S232: Generate an enable signal based on the second detection signal and the first clock signal.

[0146] Step S233: Based on the enable signal, control the on / off state of the first power transistor.

[0147] In some embodiments, step S232 includes step S2321 and / or step S2322, wherein:

[0148] Step S2321: During the rising edge of the first clock signal, the second detection signal is used as the enable signal.

[0149] Step S2322: During the falling edge of the first clock signal, the previous enable signal is used as the enable signal.

[0150] In some embodiments, step S233 includes step S2331 and / or step S2332, wherein:

[0151] Step S2331: When the enable signal is true, switch the on / off state of the first power transistor to the on state.

[0152] Step S2332: When the enable signal is false, keep the on / off state of the first power transistor in the off state.

[0153] The descriptions of the above method embodiments are similar to those of the above circuit embodiments, and have similar beneficial effects. For technical details not disclosed in the method embodiments of this disclosure, please refer to the descriptions of the circuit embodiments of this disclosure for understanding.

[0154] This disclosure provides a switching power supply, including any of the control circuits described above.

[0155] Here, a switching power supply, also known as a switching converter, is a high-frequency power conversion device and a type of power supply. Switching power supplies are widely used in industrial automation control, military equipment, scientific research equipment, LED lighting, industrial control equipment, communication equipment, power equipment, instrumentation, medical equipment, semiconductor refrigeration and heating, air purifiers, electronic refrigerators, LCD displays, LED lamps, communication equipment, audio-visual products, security monitoring, LED light strips, computer cases, digital products, and instruments. In implementation, those skilled in the art can independently design the implementation method of the switching power supply according to actual needs; this disclosure does not limit the scope of the embodiments.

[0156] This disclosure provides an electronic device including any of the control circuits described above.

[0157] Here, electronic devices can be various types of terminals such as laptops, tablets, desktop computers, set-top boxes, base stations, mobile stations, and mobile devices (e.g., mobile phones, portable music players, personal digital assistants, dedicated messaging devices, portable gaming devices).

[0158] In some embodiments, the electronic device further includes a processor. The processor may include, but is not limited to, an application processor (AP), a modem processor, a graphics processing unit (GPU), an image signal processor (ISP), a neural network processing unit (NPU), a controller, a video codec, a digital signal processor (DSP), a baseband, and / or a radio frequency integrated circuit (RFIC). The controller can generate operation control signals based on instruction opcodes and timing signals to control instruction fetching and execution. In some embodiments, the baseband and RF integrated circuits can be integrated into a single integrated circuit. In some embodiments, the baseband and RF circuits can be separate devices.

[0159] It should be noted that the descriptions of the switching power supply and electronic device embodiments above are similar to the descriptions of the control circuit embodiments above, and have similar beneficial effects. For technical details not disclosed in the switching power supply and electronic device embodiments of this disclosure, please refer to the descriptions of the control circuit embodiments of this disclosure for understanding.

[0160] It should be understood that the phrase "an embodiment" or "one embodiment" throughout the specification means that a particular feature, structure, or characteristic relating to an embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0161] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0162] In the several embodiments provided in this disclosure, it should be understood that the disclosed device can be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components may be combined, or integrated into another system, or some features may be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the various components shown or discussed may be through some interfaces, and the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0163] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units. They may be located in one place or distributed across multiple network units. Some or all of the units may be selected to achieve the purpose of this embodiment according to actual needs.

[0164] In addition, each functional unit in the embodiments of this disclosure can be integrated into one processing unit, or each unit can be a separate unit, or two or more units can be integrated into one unit; the integrated unit can be implemented in hardware or in the form of hardware plus software functional units.

[0165] The above description is merely an embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A control circuit, characterized in that, The control circuit, applied in a Boost circuit including an inductor, a first power transistor, and a second power transistor, comprises: The detection circuit is used to detect the on / off state of the second power transistor after the first power transistor is turned off; when the on / off state of the second power transistor switches to the off state, it generates a first detection signal and generates a first clock signal based on a first voltage signal at the drain terminal of the first power transistor. A first control circuit is used to control the on / off state of the first power transistor based on the first detection signal and the first clock signal after the second power transistor is turned off. The detection circuit includes an electrically connected differentiating circuit and a zero-crossing detection circuit. The differentiating circuit is used to adjust the phase of the first voltage signal at the drain terminal of the first power transistor to generate a second voltage signal when the second power transistor is in the off state. The zero-crossing detection circuit is used to perform zero-crossing detection on the second voltage signal to generate the first clock signal.

2. The control circuit according to claim 1, characterized in that, The detection circuit includes a detection sub-circuit; The detection sub-circuit is used to detect the first voltage value at the drain terminal of the first power transistor and the second voltage value at the source terminal of the second power transistor, and when the first voltage value and the second voltage value meet the preset conditions, to switch the on / off state of the second power transistor to the off state and generate the first detection signal.

3. The control circuit according to claim 2, characterized in that, The detection sub-circuit includes a comparator and a first flip-flop; The comparator includes: a first input terminal, a second input terminal, and a first output terminal, wherein the first input terminal receives the first voltage value, and the second input terminal receives the second voltage value; The first trigger includes a third input terminal, a fourth input terminal, a second output terminal, and a third output terminal, wherein the third input terminal is coupled to the first output terminal of the comparator, the fourth input terminal receives an enable signal, the second output terminal provides the first detection signal, and the second output terminal provides an inverted signal of the first detection signal.

4. The control circuit according to claim 1, characterized in that, The first control circuit includes a signal generation circuit and a second control circuit that are electrically connected. The signal generation circuit is used to generate a second detection signal based on a preset second clock signal and the first detection signal; An enable signal is generated based on the second detection signal and the first clock signal; The second control circuit is used to control the on / off state of the first power transistor based on the enable signal.

5. The control circuit according to claim 4, characterized in that, The signal generation circuit is also used for: During the rising edge of the first clock signal, the second detection signal is used as the enable signal; During the falling edge of the first clock signal, the previous enable signal is used as the enable signal.

6. The control circuit according to claim 4, characterized in that, The signal generation circuit includes a first AND gate and a second flip-flop that are electrically connected; The first AND gate includes a fifth input terminal, a sixth input terminal, and a fourth output terminal, wherein the fifth input terminal receives the second clock signal, and the sixth input terminal receives the first detection signal; The second flip-flop includes a seventh input, an eighth input, and a fifth output, wherein the seventh input is coupled to the fourth output of the first AND gate, the eighth input receives the first clock signal, and the fifth output provides the enable signal.

7. The control circuit according to claim 6, characterized in that, The signal generation circuit further includes an OR gate and a second AND gate; The second AND gate includes a ninth input terminal, a tenth input terminal, and a sixth output terminal, wherein the ninth input terminal receives the second clock signal, and the tenth input terminal receives the inverted signal of the first detection signal; The OR gate includes an eleventh input, a twelfth input, and a seventh output, wherein the eleventh input is coupled to the sixth output of the second AND gate, the twelfth input is coupled to the fifth output of the second flip-flop, and the seventh output provides the enable signal.

8. The control circuit according to any one of claims 4 to 7, characterized in that, The second control circuit is further configured to switch the on / off state of the first power transistor to the on state when the enable signal is true, and to keep the on / off state of the first power transistor in the off state when the enable signal is false.

9. A control method, characterized in that, The control method, applied in any one of claims 1 to 8, comprises: After the first power transistor is turned off, the on / off state of the second power transistor is detected to obtain the detection result; When the detection result indicates that the on / off state of the second power transistor has switched to the off state, a first detection signal is generated, and a first clock signal is generated based on the first voltage signal at the drain terminal of the first power transistor. After the second power transistor is turned off, the on / off state of the first power transistor is controlled based on the first detection signal and the first clock signal.

10. A switching power supply, characterized in that, The control circuit includes any one of claims 1 to 8.

11. An electronic device, characterized in that, The control circuit includes any one of claims 1 to 8.

Images