A low-power high-gain low-noise amplifier based on CMOS process

Abstract

The application discloses a low-power-consumption high-gain low-noise amplifier based on a CMOS process, comprising: an input stage circuit and an output stage circuit; the input stage circuit comprises: a first transformer, a second transformer, a feedback resistor Rf, a first transistor M1 and a first capacitor C1; and the output stage circuit comprises: a second transistor M2, a third transistor M3, a second capacitor C2, a third capacitor C3, a third transformer, a first inductor L1, a second inductor L2, a third inductor L3 and a first resistor R1. The LNA can realize good performance indexes such as low noise, high gain and low power consumption under the premise of guaranteeing to meet the requirement of realizing good input and output port impedance matching within a wide bandwidth.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of radio frequency integrated circuits, and particularly relates to a low-power high-gain low-noise amplifier based on a CMOS process. BACKGROUND

[0002] With the rapid development of wireless communication technology, as a key module in a wireless communication system, a radio frequency integrated circuit has become a current research hotspot. A low noise amplifier (LNA) is one of the most important parts in a wireless communication system, is located at the front end of a radio frequency receiver, and has a vital influence on the overall performance of the radio frequency receiver. According to a noise formula of a cascade circuit, the noise size of the LNA determines the overall noise of a receiving link. Secondly, the gain of the LNA must be large enough to reduce the influence of noise of a subsequent circuit on the overall noise performance of the system. In addition, as the most power-consuming module of the radio frequency receiving front end, designing a low-power LNA plays a vital role in reducing the power consumption of the entire radio frequency receiving front end.

[0003] The rapid development of wireless communication has brought many technical problems, such as serious signal interference and increasingly tight frequency resources. At present, domestic research on a wideband LNA working at a high frequency band is less, and the frequencies of various interference signals are also concentrated in a lower frequency band below 10 GHz. Meanwhile, the X-band application scenarios are wide, such as broadcast satellites, fixed communication service satellites, earth exploration satellites and weather satellites, and the like. How to design an X-band LNA with low noise, high gain, low power consumption and good input and output port impedance matching becomes a problem to be solved. SUMMARY

[0004] In order to solve the above problems in the prior art, the application provides a low-power high-gain low-noise amplifier based on a CMOS process. The technical problem to be solved by the application is solved through the following technical scheme.

[0005] The low-power high-gain low-noise amplifier based on the CMOS process comprises an input stage circuit and an output stage circuit.

[0006] The input stage circuit comprises a first transformer, a second transformer, a feedback resistor Rf, a first transistor M1 and a first capacitor C1.

[0007] The gate of the first transistor M1 is connected with the ground GNDA through the secondary winding T1-2 of the first transformer and the first capacitor C1; the source of the first transistor M1 is connected with the ground GNDA; the drain of the first transistor M1 is connected with the first power supply voltage VDD1 through the primary winding T2-1 of the second transformer, and the drain of the first transistor M1 is also connected with the gate of the first transistor M1 through the feedback resistor Rf, and the radio frequency signal input end RFin is connected with the ground GNDA through the primary winding T1-1 of the first transformer;

[0008] The output stage circuit comprises a second transistor M2, a third transistor M3, a second capacitor C2, a third capacitor C3, a third transformer, a first inductor L1, a second inductor L2, a third inductor L3 and a first resistor R1.

[0009] The gate of the second transistor M2 is connected with the first power supply voltage VDD1 through the secondary winding T2-2 of the second transformer, the source of the second transistor M2 is connected with the ground GNDA, and the drain of the second transistor M2 is connected with the second power supply voltage VDD2 through the first inductor L1, and the drain of the second transistor M2 is connected with the source of the third transistor M3 through the second capacitor C2.

[0010] The gate of the third transistor M3 is connected with the first power supply voltage VDD1 through the secondary winding T3-1 of the third transformer, the source of the third transistor M3 is connected with the ground GNDA through the primary winding T3-2 of the third transformer, the drain of the third transistor M3 is connected with the first power supply voltage VDD1 through the first resistor R1 and the second inductor L2, and the drain of the third transistor M3 is also connected with the third capacitor C3 and the third inductor L3 and the radio frequency signal output end RFout.

[0011] In an embodiment of the present application, the first capacitor C1 and the third capacitor C3 are both direct-current isolation capacitors.

[0012] In an embodiment of the present application, the transconductance g m1 The value range is [70m, 80m] Siemens.

[0013] In an embodiment of the present application, the transconductance g m2 The value range is [60m, 70m] Siemens, and the transconductance g m3 The value range is [40m, 50m] Siemens.

[0014] In an embodiment of the present application, the first transistor M1, the second transistor M2 and the third transistor M3 are all N-type metal-oxide-semiconductor field effect transistors.

[0015] In one embodiment of the present application, the first transistor M1, the second transistor M2 and the third transistor M3 all work in the saturation region.

[0016] In one embodiment of the present application, each device is implemented by using a CMOS process with a feature size of 40 nm.

[0017] Advantages of the present application:

[0018] The present application adopts a passive transformer for input impedance matching and inter-stage matching of an amplification circuit. Compared with an inductor, the transformer has more designable parameters and higher design freedom, and can better achieve wideband impedance matching. The DC shunt technology is adopted to solve the problem of high supply voltage caused by the stacking of transistors in a common-source common-gate structure. By supplying power to the common-source transistor and the common-gate transistor respectively, the two transistors have independent DC current paths while the RF signal path remains unchanged, thereby reducing the power consumption of the stage circuit under the premise of constant gain. The common-gate transistor transconductance enhancement technology based on transformer feedback is adopted. Without consuming extra power and providing almost no extra noise, the equivalent transconductance of the common-gate transistor is improved to increase the gain of the stage circuit. At the same time, a RF signal blocking inductor in the DC shunt structure is replaced by the transformer. Since the inductor area is similar to that of the transformer, the transconductance enhancement structure can increase the gain of the amplifier without consuming extra area.

[0019] The present application will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0020] Figure 1 A structure diagram of a low-power high-gain low-noise amplifier based on a CMOS process provided by an embodiment of the present application;

[0021] Figure 2 An input matching simulation diagram provided by an embodiment of the present application;

[0022] Figure 3 An output matching simulation diagram provided by an embodiment of the present application;

[0023] Figure 4 A gain simulation diagram provided by an embodiment of the present application;

[0024] Figure 5 A noise figure comparison simulation diagram provided by an embodiment of the present application;

[0025] Figure 6 A reverse isolation simulation diagram provided by an embodiment of the present application. DETAILED DESCRIPTION

[0026] The application will be described in further detail below with reference to specific embodiments, but the embodiments of the application are not limited thereto.

[0027] As shown in the figure, a low-power high-gain low-noise amplifier based on a CMOS process comprises an input stage circuit and an output stage circuit. Figure 1 The input stage circuit comprises an input impedance matching network based on a first transformer matching, a common-source amplification circuit based on a negative feedback structure of a parallel feedback resistor Rf, and an inter-stage impedance matching network based on a second transformer matching.

[0028] Compared with an inductor, a passive transformer has more designable parameters and higher design freedom, and the transformer used for the impedance matching circuit can better achieve wideband impedance matching. The parallel resistor negative feedback structure can provide a wideband real impedance, so that the input impedance of the amplifier remains constant in a quite wide frequency band range, thereby expanding the circuit bandwidth.

[0029] As shown in the figure, the input stage circuit comprises a first transformer, a second transformer, a feedback resistor Rf, a first transistor M1, and a first capacitor C1. Figure 1

[0030] The gate of the first transistor M1 is connected with the ground GNDA through the secondary winding T1-2 of the first transformer and the first capacitor C1; the source of the first transistor M1 is connected with the ground GNDA; the drain of the first transistor M1 is connected with the first power supply voltage VDD1 through the primary winding T2-1 of the second transformer, and the drain of the first transistor M1 is also connected with the gate of the first transistor M1 through the feedback resistor Rf, and the radio frequency signal input end RFin is connected with the ground GNDA through the primary winding T1-1 of the first transformer.

[0031] Specifically, one end of the primary winding T1-1 of the first transformer is connected with the radio frequency signal input end RFin, and the other end is connected with the ground GNDA. One end of the secondary winding T1-2 of the first transformer is connected with the ground GNDA, and the other end is connected with one end of the first capacitor C1. The gate of the first transistor M1 is connected with the other end of the first capacitor C1 and one end of the feedback resistor Rf. The other end of the feedback resistor Rf is connected with the drain of the first transistor M1. The drain of the first transistor M1 is connected with one end of the primary winding T2-1 of the second transformer, and the other end of the primary winding T2-1 of the second transformer is connected with the first power supply voltage VDD1. The source of the first transistor M1 is connected with the ground GNDA.

[0032] ​It should be noted that in the embodiment, the first transformer is used to realize good input port impedance matching, the first capacitor C1 is used to realize DC signal blocking while realizing input port impedance matching, and the second transformer is used to realize good inter-stage impedance matching of the amplification circuit.

[0033] Specifically, in the embodiment, the input stage circuit adopts passive transformer impedance matching technology and parallel resistance negative feedback technology, which can effectively solve the problem that a wideband circuit is difficult to realize good impedance matching.

[0034] The output stage circuit includes a common source and gate amplification circuit based on a transconductance enhancement structure of a third transformer feedback and a DC shunt structure of a primary winding of the third transformer, and an output impedance matching network.

[0035] The DC shunt structure reduces the supply voltage by supplying power to the common source transistor (second transistor M2) and the common gate transistor (third transistor M3) respectively, thereby reducing the power consumption of the stage circuit under the premise that the radio frequency signal path remains unchanged.

[0036] The transconductance enhancement structure based on transformer feedback improves the equivalent transconductance of the common gate transistor (third transistor M3) to improve the gain of the stage circuit without consuming additional power and providing additional noise. At the same time, the primary winding of the third transformer provides a radio frequency signal blocking inductor T3-2 for the DC shunt structure. Since the inductor area is similar to the transformer, the transconductance enhancement structure can improve the gain of the stage amplifier without consuming additional area.

[0037] As shown in Figure 1 The output stage circuit includes a second transistor M2, a third transistor M3, a second capacitor C2, a third capacitor C3, a third transformer, a first inductor L1, a second inductor L2, a third inductor L3, and a first resistor R1.

[0038] The gate of the second transistor M2 is connected to the first supply voltage VDD1 through the secondary winding T2-2 of the second transformer, the source of the second transistor M2 is connected to the ground GNDA, the drain of the second transistor M2 is connected to the second supply voltage VDD2 through the first inductor L1, and the drain of the second transistor M2 is connected to the source of the third transistor M3 through the second capacitor C2.

[0039] The gate of the third transistor M3 is connected with the first power voltage VDD1 through the secondary winding T3-1 of the third transformer, the source of the third transistor M3 is connected with the ground GNDA through the primary winding T3-2 of the third transformer, the drain of the third transistor M3 is connected with the first power voltage VDD1 through the first resistor R1 and the second inductor L2, and the drain of the third transistor M3 is also connected with the radio frequency signal output end RFout through the third capacitor C3 and the third inductor L3.

[0040] Specifically, one end of the secondary winding T2-2 of the second transformer is connected with the first power voltage VDD1, the other end of the secondary winding T2-2 of the second transformer is connected with the gate of the second transistor M2, the source of the second transistor M2 is connected with the ground GNDA, and the drain of the second transistor M2 is connected with one end of the first inductor L1 and one end of the second capacitor C2. The other end of the first inductor L1 is connected with the second power voltage VDD2. The other end of the second capacitor C2 is connected with the source of the third transistor M3 and one end of the primary winding T3-2 of the third transformer, the other end of the primary winding T3-2 of the third transformer is connected with the ground GNDA. The gate of the third transistor M3 is connected with one end of the secondary winding T3-1 of the third transformer, the other end of the secondary winding T3-1 of the third transformer is connected with the first power voltage VDD1. The drain of the third transistor M3 is connected with one end of the first resistor R1, the other end of the first resistor R1 is connected with one end of the second inductor L2, and the other end of the second inductor L2 is connected with the first power voltage VDD1. The drain of the third transistor M3 is connected with one end of the third capacitor C3, the other end of the third capacitor C3 is connected with one end of the third inductor L3, and the other end of the third inductor L3 is connected with the radio frequency signal output end RFout.

[0041] In the embodiment, the radio frequency signal is input by the radio frequency signal input end RFin, sequentially passes through the input stage circuit and the output stage circuit, is amplified under the premise of realizing low power consumption, low port reflection coefficient and low noise, and is output by the radio frequency signal output end RFout.

[0042] It should be noted that the first inductor L1 is used for blocking the radio frequency signal from entering VDD2, the second capacitor C2 is used for blocking the direct current signal between the source of the third transistor M3 and the drain of the second transistor M2, the primary winding T3-2 of the third transformer is used for blocking the radio frequency signal from entering GNDA, and simultaneously forms a transconductance enhancement structure with the secondary winding T3-1 thereof, which is used for enhancing the equivalent transconductance of the common-gate transistor (the third transistor M3), the first resistor R1 and the second inductor L2 provide a left half plane zero point for the stage amplification circuit, which is used for expanding the circuit bandwidth, and the third capacitor C3 is used for blocking the direct current signal at the output end, preventing the influence of the direct current signal at the output end on the circuit.

[0043] Specifically, in the embodiment, the common-source common-gate technology is adopted to reduce the gate-drain parasitic capacitance C of the common-source transistor (the second transistor M2) while providing sufficient gain gd The Miller effect is used to realize good isolation between the input and output terminals; the DC shunt technology is used to solve the problem of high supply voltage and large power consumption caused by the stacking of transistors in the common-source common-gate structure, and to reduce the power consumption of the stage circuit under the premise of constant gain; the transconductance enhancement technology based on the transformer is used to improve the equivalent transconductance of the common-gate transistor (the third transistor M3) and thus improve the gain of the stage amplification circuit, and the third transformer primary winding T3-2 is reused to realize the transconductance enhancement structure without increasing the additional area.

[0044] Further, the first capacitor C1 and the third capacitor C3 are DC blocking capacitors for blocking the influence of DC on the circuit at the input and output nodes, and the capacitance values of the first capacitor C1 and the third capacitor C3 are about 1 pF, preferably 1 pF.

[0045] Further, the transconductance g of the first transistor M1 is in the range of [60m, 70m] Siemens. m1 The parallel negative feedback resistor is used to provide a wideband real impedance to realize the impedance matching of the input port of the ultra-wideband circuit, and the resistance value of the feedback resistor Rf is about 1K ohm, preferably 1K ohm.

[0046] Further, to realize low power consumption of the output stage amplification circuit while compromising the gain performance of the stage amplification circuit, the transconductance g of the second transistor M2 is in the range of [60m, 70m] Siemens. m2 The transconductance g of the third transistor M3 is in the range of [40m, 50m] Siemens. m3 The transconductance g of the third transistor M3 is in the range of [40m, 50m] Siemens.

[0047] Further, the first transistor M1, the second transistor M2 and the third transistor M3 are all N-type metal-oxide-semiconductor field effect transistors.

[0048] Further, the first transistor M1, the second transistor M2 and the third transistor M3 all work in the saturation region.

[0049] Preferably, each component is realized by using a 40nm feature size CMOS process, the power supply voltage VDD1 is realized by using a 0.65V voltage, and the power supply voltage VDD2 is realized by using a 0.35V voltage.

[0050] The working principle of the present application is as follows:

[0051] In an alternative embodiment of the present application, the LNA in the present embodiment works in the frequency range of 8GHz-12GHz. In order to realize the input port impedance matching of the ultra-wideband circuit, the parallel resistance negative feedback structure can provide a wideband real impedance, so that the input impedance of the amplifier remains constant in a relatively wide frequency band, thereby expanding the circuit bandwidth. Only considering the influence of the output load impedance Z L , the feedback resistance Rf, the internal resistance R S of the signal source, and the gate-source parasitic capacitance of the MOS transistor, the gain and the dominant pole are obtained:

[0052] A V = g m1 Z L (Rf-1 / g m1 ) / (Rf+Z L ) (1)

[0053]

[0054] wherein g m1 is the transconductance of the common-source transistor (the first transistor) M1, C gs is the gate-source parasitic capacitance of the common-source transistor (the first transistor) M1. It can be concluded that the value of the feedback resistance Rf needs to be compromised between bandwidth expansion and gain. When Rf is infinite, the circuit is a common-source amplifier, the gain is equal to g m1 Z L , and the dominant pole is With the decrease of Rf, the gain decreases and the dominant pole moves to high frequency. This structure expands the bandwidth at the cost of gain. The transconductance g m1 of the common-source transistor M1 in the present embodiment is in the range of [70m, 80m] Siemens, and the value of the feedback resistance Rf is about 1K ohm.

[0055] Compared with the impedance matching by applying two independent inductors, the passive transformer impedance matching greatly reduces the layout area. Meanwhile, the transformer design parameters include the quality factor Q, the coupling coefficient k, the primary and secondary coil inductance values L1 and L2, the turn ratio N, and the mutual inductance M, etc. Compared with inductors, there are more designable parameters, higher design freedom, and better realization of wideband impedance matching. The secondary winding T2-2 of the second transformer is connected in series with the gate of the second transistor M2, which resonates with the parasitic capacitance of the gate of the second transistor M2, and can further compensate the gain of the amplification circuit. The inductance value of the secondary winding T2-2 of the transformer in the present embodiment is about 1.1nH, and the inductance value is preferably 1.1nH.

[0056] In an alternative embodiment of the present application, please continue to refer to Figure 1 , Figure 1The output stage circuit adopts DC shunt technology. The second capacitor C2 blocks the DC signal between the drain and source of the second transistor M2, and the first inductor L1 and the primary winding T3-2 of the third transformer block the radio frequency signal. At this time, the supply voltages of the second transistor M2 and the third transistor M3 are independent, and the common-source common-gate structure is no longer limited by the minimum supply voltage due to its stacked structure. In this embodiment, the first power supply voltage VDD1 is set to 0.65V, and the second power supply voltage VDD2 is set to 0.35V, realizing the low-voltage operation of the circuit. While realizing the low-voltage operation, the low operating current is also considered to achieve low power consumption. The common-source circuit gain of this stage circuit is shown in equation (3):

[0057] A V =g m2 sL1 (3)

[0058] Among them, g m2 Let s = jω be the transconductance of the second transistor M2.

[0059] If we only disregard the secondary winding T3-1 of the third transformer, the DC blocking capacitor (third capacitor) C3, and the impedance matching inductor (third inductor) L3, and perform small-signal analysis on the common-gate circuit of this stage, we can obtain its gain as shown in equation (4):

[0060]

[0061] Among them, g m3 For the transconductance of the third transistor M3, r o3 L is the channel resistance value of the third transistor M3. 3-2 Z represents the inductance value of the primary winding T3-2 of the third transformer. D Let be the load impedance, and its expression is shown in equation (5):

[0062] Z D =sL2+R1 (5)

[0063] L2 is the inductance value of the second inductor L2. From equations (3), (4), and (5) above, it can be seen that the gain performance of this stage of the circuit is less correlated with the transconductance of the common-gate transistor (third transistor) M3, meaning the size of the third transistor M3 has little impact on the gain performance of this stage of the circuit. The current formulas for the three MOS transistors operating in the saturation region are given by equation (6) below:

[0064]

[0065] Where, μ n C represents the carrier mobility. ox V is the capacitance per unit area of ​​the gate oxide layer, W is the gate width of the device, L is the gate length of the device, λ is the channel length modulation coefficient, and V is the capacitance per unit area of ​​the gate oxide layer. gsV ds is the source-drain voltage of the transistor, V th is the threshold voltage of the transistor. Therefore, without affecting the gain performance of the stage of the amplification circuit, the working current can be reduced by reducing the gate width of the third transistor M3, so as to reduce the power consumption of the stage of the amplification circuit. By selecting appropriate M3 size, the parasitic effect caused by the gate-drain parasitic capacitance C gd of the second transistor M2 can be reduced, and the influence of the Miller capacitance can be reduced. The transconductance g m3 of the common-gate transistor M3 ranges from 40 mS to 50 mS, and the transconductance g m2 of the common-source transistor M2 ranges from 60 mS to 70 mS.

[0066] In an alternative embodiment of the present application, please continue to refer to Figure 1 , in order to reduce the power consumption of the output stage circuit, the Π type DC shunt technology is adopted, and the inductor T3-2 is used to block the radio frequency signal. In order to increase the gain of the LNA, the third transformer is used to replace the inductor, and the equivalent transconductance of the common-gate transistor is improved by the transformer equivalent transconductance improvement technology, so as to improve the gain of the stage of the amplification circuit. The feedback coefficient of the structure is shown in formula (7):

[0067]

[0068] Wherein, L g is the gate equivalent inductance of the common-gate transistor M3, and C gs3 is the gate-source parasitic capacitance of the common-gate transistor M3. Under the premise that the denominator of formula (7) is positive, increasing the inductance value L g can increase the feedback coefficient A. At this time, the equivalent transconductance G m3 of the common-gate transistor M3 is shown in formula (8):

[0069] G m3 = g m3 (1+A) (8)

[0070] As can be seen from the above formula, the equivalent transconductance of the common-gate transistor M3 is improved by (1+A) times, the gain of the stage of the amplification circuit is improved, and the noise contributed by the common-gate transistor M3 becomes 1 / (1+A) 2 . The radio frequency signal blocking inductance is contributed by the primary winding T3-2 of the third transformer, which almost does not contribute additional noise, does not increase additional area and does not introduce additional power consumption, realizes the gain improvement of the stage of the amplification circuit, and makes a good trade-off between power consumption and gain performance index, which meets the low power consumption and high gain requirements of the LNA designed in the embodiment.

[0071] The technical effects of the application are further illustrated by simulation experiments as follows:

[0072] 1. Simulation conditions:

[0073] In the frequency band of 8-12GHz, the circuit of the application Figure 1 is simulated by using the SMIC 40nm CMOS process model under the conditions of a power supply voltage VDD1 of 0.65V and a power supply voltage VDD2 of 0.35V by using a Cadence simulation tool.

[0074] 2. Simulation contents:

[0075] Simulation 1: The input matching of the circuit of the application is simulated under the above conditions, and the result is shown in Table 1. The application achieves good input matching, and S11<-14.5dB in the simulation frequency band, wherein S11 is the reflection coefficient of port 1 when port 2 is matched. Figure 2

[0076] Simulation 2: The output matching of the circuit of the application is simulated under the above conditions, and the result is shown in Table 2. The application achieves good output matching, and S22<-14.2dB in the simulation frequency band, wherein S22 is the reflection coefficient of port 2 when port 1 is matched. Figure 3

[0077] Simulation 3: The gain of the circuit of the application is simulated under the above conditions, and the result is shown in Table 3. The application achieves high gain, and S21 is 21.9-24.4dB in the simulation frequency band. Figure 4

[0078] Simulation 4: The noise factor of the circuit of the application is simulated under the above conditions, and the result is shown in Table 4. The application achieves good noise performance, and the noise factor NF is 2.86-3.45dB in the simulation frequency band. Figure 5

[0079] Simulation 5: The isolation of the circuit of the application is simulated under the above conditions, and the result is shown in Table 5. The application achieves good reverse isolation, and S12<-57.4dB in the simulation frequency band, wherein S12 is the transmission coefficient of port 2 to port 1 when port 1 is matched. Figure 6

[0080] Simulation 6: The power consumption of the circuit of the application is simulated under the above conditions, and the power consumption is only 13.7mW.

[0081] ​​​​​In addition, the terms "first", "second", etc. are used only for descriptive purposes and do not connote or imply relative importance of or a number of indicated technical features. Thus, a feature defined with "first", "second" etc. can include one or more of the features implicitly or explicitly. In the description of the present application, the meaning of "a plurality" is two or more, unless otherwise expressly specified.

[0082] In the description of the present application, the description of the terms "one embodiment", "some embodiments", "an example", "a specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In the present application, the illustrative description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate different embodiments or examples described in the present application.

[0083] The above is a further detailed description of the present application in combination with specific preferred embodiments, and it cannot be considered that the specific implementation of the present application is limited to these descriptions. For those skilled in the art, without departing from the concept of the present application, a number of simple deductions or substitutions can be made, which should be considered as falling within the protection scope of the present application.

Claims

1. A low power consumption high gain low noise amplifier based on CMOS process, characterized in that, The application relates to a radio frequency (RF) signal input / output circuit. The input stage circuit and the output stage circuit are provided. The input stage circuit comprises a first transformer, a second transformer, a feedback resistor Rf, a first transistor M1 and a first capacitor C1. The gate of the first transistor M1 is connected with the ground GNDA through the secondary winding T1-2 of the first transformer and the first capacitor C1; the source of the first transistor M1 is connected with the ground GNDA; the drain of the first transistor M1 is connected with the first power supply voltage VDD1 through the primary winding T2-1 of the second transformer, and the drain of the first transistor M1 is also connected with the gate of the first transistor M1 through the feedback resistor Rf; and the radio frequency signal input end RFin is connected with the ground GNDA through the primary winding T1-1 of the first transformer. The output stage circuit comprises a second transistor M2, a third transistor M3, a second capacitor C2, a third capacitor C3, a third transformer, a first inductor L1, a second inductor L2, a third inductor L3 and a first resistor R1. The gate of the second transistor M2 is connected with the first power supply voltage VDD1 through the secondary winding T2-2 of the second transformer; the source of the second transistor M2 is connected with the ground GNDA; the drain of the second transistor M2 is connected with the second power supply voltage VDD2 through the first inductor L1; and the drain of the second transistor M2 is connected with the source of the third transistor M3 through the second capacitor C2. The gate of the third transistor M3 is connected with the first power supply voltage VDD1 through the secondary winding T3-1 of the third transformer; the source of the third transistor M3 is connected with the ground GNDA through the primary winding T3-2 of the third transformer; the drain of the third transistor M3 is connected with the first power supply voltage VDD1 through the first resistor R1 and the second inductor L2; and the drain of the third transistor M3 is also connected with the third inductor L3 and the radio frequency signal output end RFout through the third capacitor C3.

2. The low-power high-gain low-noise amplifier based on CMOS process according to claim 1, characterized in that, The first capacitor C1 and the third capacitor C3 are direct-current isolation capacitors.

3. The low-power high-gain low-noise amplifier based on CMOS process according to claim 1, characterized in that, The transconductance g of the first transistor M1 m1 The value range is [70m, 80m] Siemens.

4. The low-power high-gain low-noise amplifier based on CMOS process of claim 1, wherein, the transconductance g of the second transistor M2 m2 the transconductance g of the third transistor M3 in the range [40m, 50m] Siemens. m3 the transconductance g of the third transistor M3 in the range [40m, 50m] Siemens.

5. The low-power high-gain low-noise amplifier based on CMOS process according to claim 1, characterized in that, The first transistor M1, the second transistor M2 and the third transistor M3 are N-type metal-oxide-semiconductor field effect transistors.

6. The low-power high-gain low-noise amplifier based on CMOS process of claim 1, wherein, The first transistor M1, the second transistor M2 and the third transistor M3 all work in the saturation region.

7. The low-power high-gain low-noise amplifier based on CMOS process according to claim 1, characterized in that, Each device is realized by using a 40nm feature size CMOS process.

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