A method, apparatus and electronic device for time synchronization adjustment

Abstract

Embodiments of the present application disclose a time synchronization adjustment method, device and electronic equipment. Embodiments of the present application obtain at least two groups of initial path delay data, wherein the time length of each group of initial path delay data is the same; perform data filtering on each group of initial path delay data to generate candidate path delay data; generate a target path delay according to at least two groups of candidate path delay data; and adjust a slave clock time according to the target path delay, so that the slave clock time is synchronized with a master clock time. Through the above method, the accuracy of path delay can be improved, and the accuracy of time synchronization adjustment between the master clock and the slave clock can be improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of communication technology, in particular to a time synchronization adjustment method, device and electronic equipment. BACKGROUND

[0002] With the development of communication technology, the precision requirement of time synchronization between master clock and slave clock in communication service is higher and higher, but the implementation of high-precision time synchronization is difficult; the IEEE1588 Precision Time Protocol (PTP) standard provides a basic mechanism for time synchronization between master clock and slave clock, which needs to collect enough time stamp information back and forth between master clock and slave clock, determine the path delay according to the collected time stamp information, and then adjust the time synchronization between master clock and slave clock according to the path delay, so the precision of path delay greatly affects the precision of time synchronization adjustment between master clock and slave clock.

[0003] In the prior art, the path delay is mainly obtained by the following two methods, method one, median method; method two, average method; specifically, the median method needs to continuously calculate N path delay values, then sort the N path delay values in ascending or descending order, and take the path delay value in the middle position; the average method is to continuously calculate M path delay values, and then calculate the average of the M path delay values; due to the inconsistent forwarding time of devices in the network on the link, the inconsistent data processing time of the transceiver system, the sudden change of the network link, the packet loss caused by network interference, and the data delay caused by message blocking, queuing, etc. in the transceiver system, etc. Extreme path delay values are prone to occur, which leads to poor precision of path delay calculated by median method and average method.

[0004] In summary, how to improve the precision of path delay is a problem to be solved at present. SUMMARY

[0005] Therefore, the embodiments of the present application provide a time synchronization adjustment method, which can improve the precision of path delay, and further improve the precision of time synchronization adjustment between master clock and slave clock.

[0006] In a first aspect, the embodiments of the present application provide a time synchronization adjustment method, which comprises: obtaining at least two groups of initial path delay data, wherein the time length of each group of initial path delay data is the same;

[0007] Filtering each group of initial path delay data to generate candidate path delay data;

[0008] Generating a target path delay according to at least two groups of candidate path delay data;

[0009] adjusting the slave clock time according to the target path latency, so as to synchronize the slave clock time with the master clock time.

[0010] Optionally, the obtaining of the at least two groups of initial path latency data specifically comprises:

[0011] The at least two groups of initial path latency data are obtained in a time interval of a first set time length.

[0012] Optionally, the data filtering of each group of the initial path latency data to generate candidate path latency data specifically comprises:

[0013] The data filtering of each group of the initial path latency data to remove a peak value in each group of the initial path latency data.

[0014] The initial path latency data after the peak value is removed is determined as the candidate path latency data.

[0015] Optionally, the generating of the target path latency according to the at least two groups of the candidate path latency data specifically comprises:

[0016] calculating a first average value of all the candidate path latency data, and determining the first average value as the target path latency.

[0017] Optionally, the generating of the target path latency according to the at least two groups of the candidate path latency data specifically further comprises:

[0018] obtaining a plurality of candidate path latency data at any position in each group of the candidate path latency data;

[0019] calculating a second average value of all the plurality of candidate path latency data at the any position, and determining the second average value as the target path latency.

[0020] Optionally, the adjusting of the slave clock time according to the target path latency, so as to synchronize the slave clock time with the master clock time specifically comprises:

[0021] adjusting the slave clock time according to the target path latency and a preset algorithm, so as to synchronize the slave clock time with the master clock time.

[0022] Optionally, the preset algorithm is a PID algorithm.

[0023] In a second aspect, an embodiment of the present application provides a device for time synchronization adjustment, which comprises an obtaining unit configured to obtain at least two groups of initial path latency data, wherein a time length of each group of the initial path latency data is a first set time length.

[0024] The generating unit is configured to perform data filtering on each of the initial path delay data to generate candidate path delay data;

[0025] The generating unit is further configured to generate a target path delay according to at least two groups of the candidate path delay data.

[0026] The adjusting unit is configured to adjust a slave clock time according to the target path delay, so as to synchronize the slave clock time with a master clock time.

[0027] Optionally, the acquiring unit is specifically configured to:

[0028] Acquire at least two groups of initial path delay data with a first set time length.

[0029] Optionally, the generating unit is specifically configured to:

[0030] Perform data filtering on each of the initial path delay data to remove a peak value in each of the initial path delay data.

[0031] Determine the initial path delay data after the peak value is removed as candidate path delay data.

[0032] Optionally, the generating unit is further configured to:

[0033] Calculate a first average value of all the candidate path delay data, and determine the first average value as the target path delay.

[0034] Optionally, the generating unit is further configured to:

[0035] Acquire a plurality of candidate path delay data at any position in each of the candidate path delay data.

[0036] Calculate a second average value of all the plurality of candidate path delay data at the any position, and determine the second average value as the target path delay.

[0037] Optionally, the adjusting unit is specifically configured to:

[0038] Adjust the slave clock time according to the target path delay and a preset algorithm, so as to synchronize the slave clock time with the master clock time.

[0039] Optionally, the preset algorithm is a PID algorithm.

[0040] In a third aspect, an embodiment of the present application provides a computer readable storage medium, which stores computer program instructions, and the computer program instructions implement the method in the first aspect or any possible implementation of the first aspect when executed by a processor.

[0041] In a fourth aspect, an electronic device is provided, including a memory and a processor, the memory is configured to store one or more computer program instructions, wherein the one or more computer program instructions are executed by the processor to implement the method in the first aspect or any possible implementation of the first aspect.

[0042] The embodiments of the present application obtain at least two groups of initial path delay data, wherein the time length of each group of the initial path delay data is the same; perform data filtering on each group of the initial path delay data to generate candidate path delay data; generate target path delay according to at least two groups of the candidate path delay data; and adjust the slave clock time according to the target path delay to synchronize the slave clock time with the master clock time. Through the above method, the precision of the path delay can be improved, and the precision of the time synchronization adjustment between the master clock and the slave clock can be improved. BRIEF DESCRIPTION OF DRAWINGS

[0043] The above and other objects, features and advantages of the present application will become more apparent from the following description of embodiments of the present application taken in conjunction with the accompanying drawings, in which:

[0044] Figure 1 is a schematic diagram of a data transmission clock in the prior art;

[0045] Figure 2 is a flowchart of a time synchronization adjustment method according to an embodiment of the present application;

[0046] Figure 3 is a schematic diagram of initial path delay data according to an embodiment of the present application;

[0047] Figure 4 is a schematic diagram of candidate path delay data according to an embodiment of the present application;

[0048] Figure 5 is a schematic diagram of candidate path delay data selection according to an embodiment of the present application;

[0049] Figure 6 is a schematic diagram of a time synchronization adjustment device according to an embodiment of the present application;

[0050] Figure 7 is a schematic diagram of an electronic device according to an embodiment of the present application. DETAILED DESCRIPTION

[0051] The present invention is described below based on embodiments, but the invention is not limited to these embodiments. In the detailed description of the invention below, certain specific details are described in detail. Those skilled in the art will fully understand the invention even without these details. To avoid obscuring the essence of the invention, well-known methods, processes, flows, elements, and circuits are not described in detail.

[0052] Furthermore, those skilled in the art should understand that the accompanying drawings provided herein are for illustrative purposes only and are not necessarily drawn to scale.

[0053] Unless the context explicitly requires it, words such as "including" or "contains" throughout the application should be interpreted as including rather than exclusive or exhaustive; that is, meaning "including but not limited to".

[0054] In the description disclosed in this invention, it should be understood that the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance. Furthermore, in the description disclosed in this invention, unless otherwise stated, "a plurality of" means two or more.

[0055] In existing technologies, the IEEE 1588 Precision Time Protocol (PTP) specifies that PTP used for frequency and phase modulation is based on the premise of symmetrical transmit and receive channels. That is, the path for sending a message and the path for receiving a message are the same to ensure that the transmission and reception times are equal. Only under these conditions can the time for a message to propagate through the network be considered a constant, and half of the total round-trip delay be considered the one-way path delay. For example, as... Figure 1As shown, including device 1 and device 2, device 1 corresponds to the master clock, device 2 corresponds to the slave clock, the sync message is sent from the master clock to the slave clock, the time when the master clock sends the sync message is t1, the time when the slave clock receives the sync message is t2, and the sync message carries the t1 moment; the difference between t2-t1 includes the link delay, and also includes the first time difference between the master clock and the slave clock; the time when the slave clock sends the delay request (delay-req) is t3, the time when the master clock receives the delay-req is t4, the master clock sends the delay response (delay-resp), and the slave clock receives the delay-resp, and the delay-resp carries the t4 moment when the master clock receives the delay request; the difference between t4-t3 includes the link delay, and also includes the second time difference between the slave clock and the master clock; since the first time difference and the second time difference are just opposite, according to the PTP, half of the sum of the difference between t2-t1 and the difference between t4-t3 is the path delay.

[0056] After obtaining a plurality of path delays in the above manner, the target path delay is further obtained in the following two ways: way one, median method; specifically, the median method needs to continuously calculate N path delay values, then sort the N path delay values in ascending order or descending order, and take the path delay value at the middle position as the target path delay; for example, assuming that a plurality of path delay values are obtained, which are 2, 10, 1, 2, 1, 28, and 11, and are sorted in ascending order to obtain 1, 1, 2, 2, 10, 11, and 28, and the path delay value 2 at the middle position is determined as the target path delay; way two, average value method; specifically, the average value method is to continuously calculate M path delay values, and then calculate the average value of the M path delay values; for example, assuming that a plurality of path delay values are obtained, which are 2, 2, 2, 99, 2, 2, and 2, and the average value of the path delay values is 15.85; due to inconsistent device forwarding time in the network on the link, inconsistent data processing time of the transceiver system, sudden change of the network link, packet loss caused by network interference, and data delay caused by message blocking, queuing, etc. of the transceiver system, etc. Extreme path delay values may occur, for example, 99 in the above, and the precision of the path delay calculated by the median method and the average value method is poor.

[0057] Therefore, how to improve the precision of the path delay is a problem to be solved at present.

[0058] In the embodiment of the application, Figure 2 is a method flow chart of time synchronization adjustment. As shown in the figure, Figure 2 specifically includes the following steps:

[0059] In step S200, at least two groups of initial path delay data are acquired, wherein each group of initial path delay data has the same time length.

[0060] Specifically, at least two groups of initial path delay data with a first set time length are acquired.

[0061] In the embodiment of the present application, the first set time length can be any value, and in some specific cases, the first set time length can be the same as the time length of each group of initial path delay data. Assuming that two groups of initial path delay data are acquired, the first group of initial path delay data is acquired first, the time length of the first group of initial path delay data is 10 seconds, and the time interval is 10 seconds. After the 10s time interval, the second group of initial path delay data is continuously acquired, and the time length of the second group of initial path delay data is also 10 seconds.

[0062] In another aspect, a whole group of initial path delay data is acquired, and the whole group of initial path delay data is 30 seconds. The whole group of initial path delay data is evenly divided into three segments, each of which is 10 seconds. A group of initial path delay data corresponding to the first 10 seconds and a group of initial path delay data corresponding to the third 10 seconds are acquired, and a group of initial path delay data corresponding to the second 10 seconds is discarded. Since a single jitter needs to be adjusted several times to recover, the above-mentioned method can avoid using data in the same time period and reduce the influence of jitter on path delay.

[0063] The following will be described in detail through a specific embodiment, as shown in Figure 3 The initial path delay data included in T1 period is D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14 and D15, the initial path delay data included in T2 period is D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26, D27, D28, D29 and D30, and the initial path delay data included in T3 period is D31, D32, D33, D34, D35, D36, D37, D38, D39, D40, D41, D42, D43, D44 and D45. The initial path delay data included in the T1 period and the initial path delay data included in the T3 period are retained, and the initial path delay data included in the T2 period is discarded.

[0064] In the embodiment of the present application, the first set time length is assumed to be 0, that is, the time interval is 0, which means that the initial path delay data in a certain period does not need to be discarded.

[0065] Step S201: Filter the initial path delay data of each group to generate candidate path delay data.

[0066] Specifically, each set of initial path delay data is filtered to remove peak values; the initial path delay data after removing peak values ​​is determined as candidate path delay data.

[0067] In one possible implementation, the peak data can be either the highest peak or the lowest peak. The reason for the peak data may be due to a sudden and significant change in the network. Peak data can affect the overall performance, so it needs to be filtered out.

[0068] For example, such as Figure 4 As shown, assuming that the initial path delay data D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, and D15 included in time period T1, where D3, D8, and D13 are peak data, after removing the peak data D3, D8, and D13, candidate path delay data corresponding to time period T1 is generated, including D1, D2, D4, D5, D6, D7, D9, D10, D11, D12, D14, and D15; the path delay data included in time period T3... In the initial path delay data D31, D32, D33, D34, D35, D36, D37, D38, D39, D40, D41, D42, D43, D44, and D45, D33, D38, and D43 are peak data. After removing the peak data D33, D38, and D43, candidate path delay data corresponding to time period T3 is generated, including D31, D32, D34, D35, D36, D37, D39, D40, D41, D42, D44, and D45.

[0069] Step S202: Generate the target path delay based on at least two sets of candidate path delay data.

[0070] Specifically, generating the target path delay based on at least two sets of candidate path delay data includes the following two cases:

[0071] Case 1: Calculate the first average value of all the candidate path delay data, and determine the first average value as the target path delay.

[0072] For example, as described above Figure 4In the specific example, all of the candidate path delay data D1, D2, D4, D5, D6, D7, D9, D10, D11, D12, D14, D15, D31, D32, D34, D35, D36, D37, D39, D40, D41, D42, D44, and D45 are determined, a first sum value is determined by summing all of the data, a first average value equal to the first sum value / 24 is determined, and the first average value is determined as the target path delay.

[0073] In the embodiment of the present application, the candidate path delay data can be of any number, which is determined according to actual conditions, and the present application does not limit it.

[0074] In case two, a plurality of candidate path delay data at any position in each group of the candidate path delay data is obtained, a second average value of all of the plurality of candidate path delay data at the any position is calculated, and the second average value is determined as the target path delay.

[0075] Specifically, assuming that there are two groups of candidate path delay data, the second average value can be calculated by selecting the latter half of the candidate path delay data of the former group and the former half of the candidate path delay data of the latter group, or by selecting the former half of the candidate path delay data of the former group and the latter half of the candidate path delay data of the latter group, or by selecting the latter half of the candidate path delay data of the former group and the latter half of the candidate path delay data of the latter group, or by selecting the former half of the candidate path delay data of the former group and the former half of the candidate path delay data of the latter group, and the method for selecting data in each group of candidate path delay data is not limited by the present application according to actual conditions.

[0076] For example, the second average value is calculated by selecting the latter half of the candidate path delay data D1, D2, D4, D5, D6, D7, D9, D10, D11, D12, D14, and D15 corresponding to the T1 period and the former half of the candidate path delay data D31, D32, D34, D35, D36, D37, D39, D40, D41, D42, D44, and D45 corresponding to the T3 period, i.e., selecting D9, D10, D11, D12, D14, and D15 and selecting D31, D32, D34, D35, D36, and D37. Figure 5 As shown in FIG. 6, the latter half of the candidate path delay data D1, D2, D4, D5, D6, D7, D9, D10, D11, D12, D14, and D15 corresponding to the T1 period is selected, i.e., D9, D10, D11, D12, D14, and D15 are selected, the former half of the candidate path delay data D31, D32, D34, D35, D36, D37, D39, D40, D41, D42, D44, and D45 corresponding to the T3 period is selected, i.e., D31, D32, D34, D35, D36, and D37 are selected, a second sum value of D9, D10, D11, D12, D14, D15, D31, D32, D34, D35, D36, and D37 is calculated, a second average value equal to the second sum value / 12 is determined, and the second average value is determined as the target path delay.

[0077] Step S203, adjusting the slave clock time according to the target path delay, so as to synchronize the slave clock time with the master clock time.

[0078] Specifically, the slave clock time is adjusted according to the target path delay and a preset algorithm, and the preset algorithm is a PID algorithm.

[0079] In the embodiment of the application, the slave clock time is adjusted by the PID algorithm in the PTP each time the target path delay is obtained, and the adjustment is relatively small each time because the PID algorithm is used, so that large-range adjustment does not occur.

[0080] In a possible implementation, when the target path delay reaches a convergence state, that is, the difference (which can also be referred to as a time offset offset) between two consecutive target path delays is less than a set threshold, the following two processing modes can occur, and the details are as follows.

[0081] Mode one, the time offset offset is less than the set threshold value but greater than a set value, so that the slave clock time is not adjusted at this time.

[0082] For example, the set threshold value is 100 ns, the set value is 10 ns, and the time offset offset is 60 ns, so that the 60 ns is not used to adjust the slave clock time, and the next set of data is continuously obtained.

[0083] Mode two, the time offset offset is less than the set value, so that the slave clock time is adjusted at this time.

[0084] For example, the set value is 10 ns, and the time offset offset is 2 ns, so that the 2 ns is used to adjust the slave clock time.

[0085] In the embodiment of the application, the mode two can be referred to as slave clock time synchronization, that is, the time offset offset is used to perform small-range time adjustment.

[0086] In a possible implementation, if the time offset offset is greater than the set threshold value, the slave clock is calibrated, and the calibration is performed by adjusting the frequency by using the time offset offset value, so as to perform large-range time adjustment.

[0087] Figure 6 FIG. 1 is a schematic diagram of a time synchronization adjustment device according to an embodiment of the application. Figure 6 As shown in the figure, the device of the embodiment includes an acquisition unit 601, a generation unit 602, and an adjustment unit 603.

[0088] The acquisition unit 601 is configured to acquire at least two groups of initial path delay data, wherein the time length of each group of the initial path delay data is a first set time length.

[0089] Further, the acquisition unit is specifically configured to:

[0090] acquire at least two groups of initial path delay data with a time interval of a first set time length.

[0091] Further, the generation unit is specifically configured to:

[0092] perform data filtering on each group of the initial path delay data to remove the peak value in each group of the initial path delay data.

[0093] determine the initial path delay data after removing the peak value as candidate path delay data.

[0094] Further, the generation unit is specifically configured to:

[0095] calculate a first average value of all the candidate path delay data, and determine the first average value as the target path delay.

[0096] Further, the generation unit is specifically configured to:

[0097] acquire a plurality of candidate path delay data at any position in each group of the candidate path delay data.

[0098] calculate a second average value of all the plurality of candidate path delay data at the any position, and determine the second average value as the target path delay.

[0099] Further, the adjustment unit is specifically configured to:

[0100] adjust the slave clock time according to the target path delay and a preset algorithm, so as to synchronize the slave clock time with the master clock time.

[0101] Further, the preset algorithm is a PID algorithm.

[0102] Figure 7 is a schematic diagram of an electronic device of an embodiment of the present application. As shown in Figure 7 , Figure 7The electronic device shown is a time synchronization adjustment apparatus, which includes a general computer hardware structure, at least including a processor 701 and a memory 702. The processor 701 and the memory 702 are connected through a bus 703. The memory 702 is suitable for storing instructions or programs executable by the processor 701. The processor 701 can be a stand-alone microprocessor, or a set of one or more microprocessors. Thus, the processor 701 performs the processing of data and the control of other apparatuses by executing the instructions stored in the memory 702, thereby implementing the method flow of the embodiments of the present application as described above. The bus 703 connects the above-mentioned components together, and connects the above-mentioned components to a display controller 704 and a display apparatus, and an input / output (I / O) device 705. The input / output (I / O) device 705 can be a mouse, a keyboard, a modem, a network interface, a touch input device, a body sense input device, a printer, and other apparatuses known in the art. Typically, the input / output device 705 is connected to the system through an input / output (I / O) controller 706.

[0103] The instructions stored in the memory 702 are executed by the at least one processor 701 to implement: obtaining at least two groups of initial path delay data, wherein the time length of each group of the initial path delay data is the same; performing data filtering on each group of the initial path delay data to generate candidate path delay data; generating a target path delay according to at least two groups of the candidate path delay data; and adjusting a slave clock time according to the target path delay, so as to synchronize the slave clock time with a master clock time.

[0104] Specifically, the electronic device includes one or more processors 701 and a memory 702, Figure 7 Taking one processor 701 as an example. The processor 701 and the memory 702 can be connected through a bus or other means, Figure 7 For example, the memory 702 is connected through a bus. The memory 702 is a kind of non-volatile computer readable storage medium, which can be used to store non-volatile software programs, non-volatile computer executable programs and modules. The processor 701 performs various functional applications and data processing of the device by running the non-volatile software programs, instructions and modules stored in the memory 702, that is, implements the above-mentioned time synchronization adjustment method.

[0105] The memory 702 can include a program storage area and a data storage area, where the program storage area can store an operating system, at least one application required by the function, and the data storage area can store an option list, etc. In addition, the memory 702 can include a high-speed random access memory, and can also include a nonvolatile memory, such as at least one magnetic disk storage device, a flash memory device, or other nonvolatile solid-state memory device. In some embodiments, the memory 702 can optionally include a memory disposed remotely with respect to the processor 701, which can be connected to an external device through a network. Examples of the above network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and a combination thereof.

[0106] One or more modules are stored in the memory 702, and when executed by the one or more processors 701, perform the method of time synchronization adjustment in any of the above method embodiments.

[0107] The above products can perform the method provided by the embodiments of the present application, have the corresponding function modules and beneficial effects of performing the method, and the technical details not described in detail in the embodiments can be referred to the method provided by the embodiments of the present application.

[0108] Embodiments of the present application relate to a non-volatile storage medium for storing a computer-readable program for a computer to execute part or all of the above method embodiments.

[0109] That is, those skilled in the art can understand that all or part of the steps of the above-mentioned embodiment methods can be completed by programs instructing related hardware, the programs are stored in a storage medium, and include a plurality of instructions for causing a device (which can be a single-chip microcomputer, a chip, etc.) or a processor to execute all or part of the steps of the method described in the embodiments of the present application. The foregoing storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a magnetic disk or an optical disk, and various media that can store program codes.

[0110] Those skilled in the art can understand that the above embodiments are specific embodiments for implementing the present application, and in actual applications, various changes can be made in form and details without departing from the spirit and scope of the present application.

Claims

1. A method of time synchronization adjustment, characterized by, The method comprises: obtaining at least two groups of initial path delay data with a first set time interval, wherein the time interval of each group of initial path delay data is the same, and the at least two groups of initial path delay data refer to data obtained by selecting part of period data at intervals and removing intermediate period data between adjacent reserved period data from an entire section of continuously collected initial path delay data which is evenly divided into N periods with the same time interval; filtering each group of initial path delay data to generate candidate path delay data; generating a target path delay according to the at least two groups of candidate path delay data; adjusting the slave clock time according to the target path delay and a preset algorithm to synchronize the slave clock time with the master clock time; the filtering of each group of initial path delay data to generate candidate path delay data specifically comprises: filtering each group of initial path delay data to remove at least one highest peak value or at least one lowest peak value in each group of initial path delay data; determining the initial path delay data after the peak value is removed as candidate path delay data; the adjusting of the slave clock time according to the target path delay and a preset algorithm to synchronize the slave clock time with the master clock time specifically comprises: calculating the time offset of two continuous target path delays; if the time offset is less than a set value, adjusting the slave clock time; if the time offset is greater than a set threshold value, adjusting the slave clock time by adjusting the slave clock frequency; if the time offset is between the set value and the set threshold value, not adjusting the slave clock time.

2. The method of claim 1, wherein, the generating of a target path delay according to the at least two groups of candidate path delay data specifically comprises: calculating a first average value of all the candidate path delay data, and determining the first average value as the target path delay.

3. The method of claim 1, wherein, the generating of a target path delay according to the at least two groups of candidate path delay data specifically further comprises: obtaining multiple candidate path delay data at any position in each group of candidate path delay data; calculating a second average value of all the multiple candidate path delay data at any position, and determining the second average value as the target path delay.

4. The method of claim 1, wherein, The preset algorithm is a PID algorithm.

5. An apparatus for time synchronization adjustment, the apparatus comprising: The device comprises: an obtaining unit configured to obtain at least two groups of initial path delay data with a first set time interval, wherein the time interval of each group of initial path delay data is the first set time interval, and the at least two groups of initial path delay data refer to data obtained by selecting part of period data at intervals and removing intermediate period data between adjacent reserved period data from an entire section of continuously collected initial path delay data which is evenly divided into N periods with the same time interval; a generating unit configured to filter each group of initial path delay data to generate candidate path delay data; the generating unit is further configured to generate a target path delay according to the at least two groups of candidate path delay data; an adjusting unit configured to adjust the slave clock time according to the target path delay and a preset algorithm to synchronize the slave clock time with the master clock time; The generating unit is further configured to: perform data filtering on each set of the initial path latency data to remove at least one highest peak value or at least one lowest peak value in each set of the initial path latency data; determine the initial path latency data after removing the peak values as candidate path latency data; The adjusting unit is further configured to: calculate a time offset of two continuous target path latencies; if the time offset is less than a set value, adjust the slave clock time; if the time offset is greater than a set threshold value, adjust the slave clock frequency to adjust the time; if the time offset is between the set value and the set threshold value, do not adjust the slave clock time.

6. A computer readable storage medium having stored thereon computer program instructions, wherein, The computer program instructions, when executed by a processor, implement the method of any one of claims 1-4.

7. An electronic device comprising a memory and a processor, characterized in that The memory is configured to store one or more computer program instructions, wherein the one or more computer program instructions are executed by the processor to implement the method of any one of claims 1-4.

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