Vernier-multiphase clock time-to-digital conversion method

Abstract

The invention discloses a vernier-multiphase clock time-to-digital conversion method. The method comprises the following steps: generating two groups of multiphase clocks with different frequencies; when an initial signal edge arrives, starting a counter Cnt1 and latching the state of the first group of multi-phase clocks; when the stop signal edge arrives, starting a counter Cnt2 and latching the state of the second group of multi-phase clocks; monitoring the edges of the two counting clocks, and stopping counting when the two counting clocks are aligned for the first time; according to the latched phase state, fine counting correction values of the starting signal edge and the stopping signal edge in respective clock periods are calculated; and finally, the accurate time interval is calculated by integrating the rough counting value and the fine counting correction value. According to the invention, through combination of multi-phase clock interpolation and the vernier method, a nonlinear synchronization error in a traditional vernier method is converted into a deterministic system error, and the resolution, absolute precision and linearity of time measurement are significantly improved.

Description

Technical Field

[0001] This invention relates to the field of time measurement, to time-to-digital conversion, and specifically to a vernier-multiphase clock time-to-digital conversion method. Background Technology

[0002] A time-to-digital converter (TDC) is a key device or circuit that converts time intervals into digital quantities. It is the core of high-precision time measurement systems and is widely used in time-frequency measurement, laser ranging, high-energy physics, and biomedical imaging. Current research on TDC technology focuses on improving time resolution, without fully considering the impact of system nonlinear characteristics on its performance.

[0003] Current mainstream TDC implementation technologies include:

[0004] Direct counting method: This method uses a high-frequency reference clock to directly count time intervals. Its resolution is limited by the clock period, Tclk. To improve the resolution, the clock frequency must be increased, but this will drastically increase circuit power consumption, design complexity, and process requirements, making it difficult to achieve extremely high resolution (e.g., below 10ps) in practical systems.

[0005] Delay line interpolation: This method utilizes the inherent propagation delay of logic gates or dedicated delay cells to construct a delay chain. Time intervals shorter than a clock cycle are measured by detecting the signal's propagation position within the delay chain. While this method achieves high single-shot resolution, its accuracy is severely affected by process variations, power supply voltage fluctuations, and temperature variations (PVT), leading to unstable delay times. Furthermore, the delay line exhibits significant nonlinearity errors, requiring complex background calibration, which increases system complexity and power consumption.

[0006] Vernier Method: Vernier-type TDCs achieve high-resolution measurements by comparing the phase difference between two clocks—one fast and one slow—triggered by start and stop signals. However, path delays and clock jitter introduce a random synchronization error smaller than the clock period, causing the edges of the start / stop signals to be out of sync with the internal clock edges. This error is not a fixed value but fluctuates non-linearly with the actual time difference between the two signals. This error is difficult to calibrate using conventional methods and becomes a major factor limiting the absolute accuracy and linearity of the measurement.

[0007] Therefore, it is necessary to construct a method that can effectively suppress or transform the nonlinear error of the vernier method while retaining its high-resolution advantage, thereby achieving a balance between high precision and excellent linearity, and thus meeting the increasingly stringent performance requirements of modern precision measurement systems. Summary of the Invention

[0008] To address the problem in existing technologies, particularly traditional vernier-based time-to-digital converters (TDCs), where random and nonlinear synchronization errors caused by path delay and clock jitter are difficult to calibrate, thus limiting the absolute accuracy and linearity of measurements, this invention proposes a vernier-multi-phase clock time-to-digital converter method. The objective of this invention is to transform the nonlinear synchronization errors in the traditional vernier method into deterministic and calibrable system errors by organically combining the high-resolution characteristics of the vernier method with the precise measurement capabilities of multi-phase clock interpolation technology, without significantly increasing the system clock frequency and circuit complexity. This achieves high time resolution while significantly improving the absolute accuracy and linearity of time interval measurements.

[0009] The technical solution for achieving the objective of this invention is as follows:

[0010] A vernier-multiphase clock time-to-digital conversion method includes the following steps:

[0011] S1 generates the first set of multi-phase clocks:

[0012] Generate N independent and parallel phase-shifted clocks ( ), clock frequencies are all The phase difference between two adjacent clock paths is , ;

[0013] S2 generates the second set of multi-phase clocks:

[0014] Generate N independent and parallel phase-shifted clocks ( ), clock frequencies are all ,and The phase difference between two adjacent clock paths is , ;

[0015] S3, Configure the counter:

[0016] for Set the corresponding counter ,for Set the corresponding counter ;

[0017] S4, Start Signal Processing:

[0018] The counter is started when a valid start signal edge is detected. right Count the effective edges and record the current frequency of N channels. Phase offset clock state ;

[0019] S5, Stop signal processing:

[0020] The counter is started when a valid stop signal edge is detected. right Count the effective edges and record the current frequency of N channels. Phase offset clock state ;

[0021] S6, Cursor alignment detection and counting stop:

[0022] judge and Check if the valid edges of the two clock signals are aligned. Once aligned, both counters stop counting and save the corresponding count values. and ;get and Two rough counts;

[0023] S7, Fine-count calculation at the starting end:

[0024] According to the status Calculate the count value ,

[0025] like ,Right now latched ,but X represents the exception Other clock states are either 0 or 1;

[0026] like ,Right now latched ,but ;

[0027] S8, Stop End Fine Count Calculation:

[0028] According to the status Calculate the count value ,

[0029] like ,Right now latched ,but Y represents except Other clock states are either 0 or 1;

[0030] like ,Right now latched ,but ;

[0031] S9, Time interval calculation:

[0032] By combining the two coarse count values, as well as the fine count values ​​at the start and stop ends, the time interval between the start and stop signals is calculated, thus completing the measurement.

[0033] Preferably, the effective edge is a rising edge.

[0034] Furthermore, in S9, the formula for calculating the time interval between the start signal and the stop signal is:

[0035] .

[0036] This invention utilizes the high-resolution characteristics of multiphase clock interpolation and the vernier method to complete the time-to-digital conversion process based on the vernier-multiphase clock principle. It can accurately measure the time interval between the start and stop signals. Compared with existing technologies, this invention has the following significant advantages:

[0037] High resolution and high precision are combined: This invention inherits the advantage of the vernier method in achieving ultra-high theoretical resolution by utilizing minute differences in clock frequency. At the same time, by introducing a multi-phase clock to accurately interpolate and measure the position of the signal edge within a single clock cycle, it effectively obtains the accurate phase information lost by the traditional vernier method due to synchronization errors, thereby transforming the high resolution potential into actual, traceable high measurement accuracy.

[0038] Excellent linearity: This invention innovatively transforms the random and nonlinear synchronization errors that are difficult to predict and calibrate in the traditional vernier method into fixed-pattern, predictable systematic phase quantization errors through deterministic sampling of multi-phase clocks. These systematic errors can be effectively compensated through pre-calibration, for example, using lookup tables (LUTs) or polynomial fitting, thereby greatly improving the differential nonlinearity (DNL) and integral nonlinearity (INL) of the entire TDC, achieving excellent overall linearity.

[0039] Enhanced robustness and ease of calibration: Multi-phase clock groups are typically generated by the same phase-locked loop (PLL) or delay phase-locked loop (DLL), resulting in stable relative phase relationships and consistent overall drift effects from process, voltage, and temperature (PVT) variations. This reduces calibration complexity. Compared to delay line delays (TDCs) requiring unit-by-unit calibration, the calibration of this invention primarily targets the uniformity of multi-phase clocks and fixed system offsets, making it simpler and more efficient.

[0040] A reasonable balance between resources and power consumption: This invention maintains high precision without using extremely high-frequency clocks or extremely long, highly precise analog delay chains, reducing the extreme requirements on the manufacturing process and the overall power consumption and area of ​​the system. The improved precision is achieved through digital logic and phase information processing, making it more suitable for integration on modern digital processes (such as CMOS).

[0041] In summary, the vernier-multiphase clock time-to-digital conversion method provided by this invention cleverly integrates the advantages of two classic technologies, effectively resolving the contradiction between resolution, accuracy, and linearity in traditional methods, and providing a highly competitive solution for realizing the next generation of high-performance, highly integrated time measurement systems. Attached Figure Description

[0042] Figure 1 This is a block diagram of the time-to-digital converter used to implement the vernier-multiphase clock time-to-digital conversion method in an embodiment of the present invention;

[0043] Figure 2 This is a schematic diagram illustrating the workflow of a vernier-multiphase clock time-to-digital conversion method according to an embodiment of the present invention;

[0044] Figure 3 This is a schematic diagram of a phase-offset clock generated by a vernier-multiphase clock time-to-digital conversion method in an embodiment of the present invention;

[0045] Figure 4 This is a schematic diagram illustrating the calculation of the time interval between the start signal and the stop signal using a vernier-multiphase clock time digital conversion method according to an embodiment of the present invention. Detailed Implementation

[0046] The present invention will be further described below with reference to the embodiments and accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0047] Example:

[0048] like Figure 1 As shown, a vernier-multiphase clock-time-to-digital converter that implements the vernier-multiphase clock-time-to-digital converter method of the present invention includes a clock generation module, an edge detection module, an alignment detection module, a logic control module, a counter Cnt1, a counter Cnt2, a state latch 1, a state latch 2, and a data processing module.

[0049] The clock generation module is used to generate the first and second sets of multi-phase clock signals. In specific implementation, it can be based on phase-locked loop (PLL) or delay phase-locked loop (DLL) technology to generate two sets of clock signals with frequencies of f1 and f2 respectively from the same reference clock source.

[0050] The edge detection module is used to accurately detect the valid edges of the start and stop signals, which are usually rising edges. It filters, shapes, and synchronizes the input signal to ensure the accuracy of edge detection and anti-interference capability. After a valid edge is detected, a corresponding trigger pulse is generated to start the counter and latch.

[0051] The alignment detection module is used to monitor the rising edges of the reference clock in the first group of clocks and the reference clock in the second group of clocks in real time. When it is detected that the rising edges of the two clocks are aligned in time (i.e., they occur simultaneously or are within a very short time window), an alignment indication signal is generated.

[0052] The logic control module serves as the timing control core of the system, coordinating the working timing of each module. The logic control module receives the trigger signal from the edge detection module, generates a counter enable signal and a state latch sampling signal, and receives the alignment indication signal from the alignment detection module, generating a counter stop signal. This ensures the logical correctness and timing consistency of the entire measurement process.

[0053] The counter Cnt1 is used to count the rising edge of the reference clock in the first group of clocks; the counting is started by the logic control module when the rising edge of the start signal arrives; the counting stops when the alignment indication signal arrives and its count value is output.

[0054] The counter Cnt2 is used to count the rising edge of the reference clock in the second group of clocks; the counting is started by the logic control module when the rising edge of the stop signal arrives; the counting stops when the alignment indication signal arrives and its count value is output.

[0055] The state latch 1 is used to synchronously capture and latch the instantaneous logic level state of all N phase-offset clocks in the first group at the precise moment when the rising edge of the start signal arrives; the latched state vector records the phase information of the start signal edge relative to the first group of multi-phase clocks; this information is used to subsequently calculate the precise position of the start signal within a single clock cycle.

[0056] The state latch 2 is used to synchronously capture and latch the instantaneous logic level state of all N phase-offset clocks in the second group at the precise moment when the rising edge of the stop signal arrives; the latched state vector records the phase information of the stop signal edge relative to the second group of multi-phase clocks; this information is used to subsequently calculate the precise position of the stop signal within a single clock cycle;

[0057] The data processing module is the core of the system's computation, responsible for performing the final time interval calculation; receiving coarse count values ​​from counters Cnt1 and Cnt2, and phase state vectors from state latches 1 and 2; decoding the phase state vectors to calculate the fine count correction values ​​for the start signal and the stop signal; and performing comprehensive calculations according to a predetermined algorithm to obtain the precise time interval between the start signal and the stop signal.

[0058] The clock generation module is sequentially electrically connected to the alignment detection module, the logic control module, and the edge detection module; the clock generation module is electrically connected to the counters Cnt1, Cnt2, state latch 1, and state latch 2; the data processing module is electrically connected to the counters Cnt1, Cnt2, state latch 1, and state latch 2.

[0059] like Figure 2 As shown, a vernier-multiphase clock time-to-digital conversion method includes the following steps:

[0060] Step 1, as follows Figure 3 As shown, the clock generation module generates two independent and parallel phase-shifted clocks. ), clock frequency is The phase difference between two adjacent clock paths is , ;

[0061] Step 2, as follows Figure 3 As shown, the clock generation module generates two independent and parallel phase-shifted clocks. ), clock frequency is The phase difference between two adjacent clock paths is , ;

[0062] Step 3, for Set the corresponding counter ,for Set the corresponding counter ;

[0063] Step 4, as follows Figure 4 As shown, after the edge detection module detects the rising edge of the start signal, it starts the counter through the logic control module. right Counting is performed on the rising edge, and the current frequency of the two channels is recorded by state latch 1. Phase offset clock state ;

[0064] Step 5, as follows Figure 4As shown, after the edge detection module detects the rising edge of the stop signal, it starts the counter through the logic control module. right Counting is performed on the rising edge, and the current frequency of the two channels is recorded by state latch 2. Phase offset clock state ;

[0065] Step 6, as follows Figure 4 As shown, the alignment detection module determines... and Are the rising edges of the two clock signals aligned? Once aligned, the counter stops counting. The count value... , ;

[0066] Step 7, based on the status Calculate the count value , , latched ,but ;

[0067] Step 8, based on the status Calculate the count value , , latched ,but ;

[0068] Step 9: The data processing module calculates the time interval between the start signal and the stop signal. Measurement complete.

[0069] Thus, through the above steps and system, the time-to-digital conversion process based on the vernier-multiphase clock principle has been completed, realizing high-precision digital measurement of the time interval between the start signal and the stop signal.

[0070] The preferred embodiments of the present invention disclosed above are merely illustrative and do not limit the invention to the specific implementations described. Obviously, many modifications and variations can be made based on the content of this specification. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the present invention, thereby enabling those skilled in the art to better understand and utilize the present invention.

Claims

1. A vernier-multiphase clock time-to-digital conversion method, characterized in that, Includes the following steps: S1 generates the first set of multi-phase clocks: Generate N independent and parallel phase-shifted clocks ( ), clock frequencies are all The phase difference between two adjacent clock paths is , ; S2 generates the second set of multi-phase clocks: Generate N independent and parallel phase-shifted clocks ( ), clock frequencies are all ,and The phase difference between two adjacent clock paths is , ; S3, Configure the counter: for Set the corresponding counter ,for Set the corresponding counter ; S4, Start Signal Processing: The counter is started when a valid start signal edge is detected. right Count the effective edges and record the current frequency of N channels. Phase offset clock state ; S5, Stop signal processing: The counter is started when a valid stop signal edge is detected. right Count the effective edges and record the current frequency of N channels. Phase offset clock state ; S6, Cursor alignment detection and counting stop: judge and Check if the valid edges of the two clock signals are aligned. Once aligned, both counters stop counting and save the corresponding count values. and ;get and Two rough counts; S7, Fine-count calculation at the starting end: According to the status Calculate the count value , like ,Right now latched ,but X represents the exception. Other clock states are either 0 or 1; like ,Right now latched ,but ; S8, Stop End Fine Count Calculation: According to the status Calculate the count value , like ,Right now latched ,but Y represents except Other clock states are either 0 or 1; like ,Right now latched ,but ; S9, Time interval calculation: By combining the two coarse count values, as well as the fine count values ​​at the start and stop ends, the time interval between the start and stop signals is calculated, thus completing the measurement.

2. The vernier-multiphase clock time-to-digital conversion method according to claim 1, characterized in that, The effective edge is the rising edge.

3. The vernier-multiphase clock time-to-digital conversion method according to claim 1, characterized in that, In S9, the formula for calculating the time interval between the start signal and the stop signal is: 。 4. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the vernier-multiphase clock time-to-digital conversion method according to any one of claims 1 to 3.

5. A field-programmable gate array, characterized in that, The field-programmable gate array is configured with firmware for performing the vernier-multiphase clock time-to-digital conversion method according to any one of claims 1 to 3.

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