Semiconductor structure, method of fabricating the same, and memory system

Abstract

The embodiment of the present disclosure discloses a semiconductor structure, comprising: an active pillar array, comprising a first active pillar and a second active pillar arranged in an array, the first active pillar and the second active pillar each comprising a channel region and a first active region and a second active region respectively located at opposite ends of the channel region along a first direction, the first direction being a direction in which the channel region extends; a word line, surrounding the first active pillar and the second active pillar; a first storage structure, located at a first side of the active pillar array, electrically connected to the first active region of the first active pillar; a second storage structure, located at a second side of the active pillar array, electrically connected to the second active region of the second active pillar; the first side and the second side being opposite sides of the active pillar array along the first direction; a first bit line, located at the second side of the active pillar array, connected to the second active region of the first active pillar; and a second bit line, located at the first side of the active pillar array, connected to the first active region of the second active pillar.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, specifically to a semiconductor structure and its fabrication method, and a memory system. Background Technology

[0002] The memory array architecture of Dynamic Random Access Memory (DRAM) consists of an array of memory cells (i.e., 1T1C memory cells) each containing one transistor and one capacitor. The gate of the transistor is connected to the word line, the drain is connected to the bit line, and the source is connected to the capacitor.

[0003] As the size of dynamic random access memory (DRAM) continues to shrink, so too does the size of transistors. How to create DRAM with large storage capacity, small size, and high performance has become a pressing issue.

[0004] Public content

[0005] This disclosure presents a semiconductor structure, a method for fabricating the same, and a memory system.

[0006] According to one aspect of this disclosure, a semiconductor structure is provided, comprising:

[0007] An active column array includes a first active column and a second active column arranged in an array. The first active column and the second active column each include a channel region and a first active region and a second active region located at opposite ends of the channel region along a first direction. The first direction is the direction in which the channel region extends.

[0008] The character line surrounds the first active post and the second active post;

[0009] A first storage structure is located on the first side of the active pillar array and is electrically connected to the first active region of the first active pillar;

[0010] The second storage structure is located on the second side of the active pillar array and is electrically connected to the second active region of the second active pillar; the first side and the second side are two opposite sides of the active pillar array along the first direction;

[0011] The first line is located on the second side of the active column array and is connected to the second active region of the first active column;

[0012] The second bit line is located on the first side of the active column array and is connected to the first active region of the second active column.

[0013] In the above scheme, the first active column and the second active column constitute a plurality of columns of active columns arranged along the second direction and a plurality of rows of active columns arranged along the third direction. Each row of active columns includes alternating first active columns and second active columns, and each column of active columns includes a first active column or a second active column. The second direction intersects with the third direction and is perpendicular to the first direction.

[0014] In the above scheme, the word line extends along the second direction and surrounds the first active column and the second active column arranged in the same row along the second direction.

[0015] In the above scheme, the geometric center of the first active column projected onto the first plane is offset from the geometric center of the first storage structure projected onto the first plane along the second direction; and / or, the geometric center of the second active column projected onto the first plane is offset from the geometric center of the second storage structure projected onto the first plane along the second direction; the first plane is perpendicular to the first direction.

[0016] In the above scheme, the row active columns include a first row of active columns and a second row of active columns arranged alternately in the third direction; among the multiple first memory structures electrically connected to the first row of active columns, the geometric centers of two adjacent first memory structures projected onto the first plane are C1 and C2, respectively; among the multiple first memory structures electrically connected to the second row of active columns adjacent to the first row of active columns, the geometric center of the first memory structure with the smallest sum of distances to C1 and C2 projected onto the first plane is C3, and the line connecting C1, C2, and C3 forms an equilateral triangle;

[0017] And / or,

[0018] Among the multiple second memory structures electrically connected to the first row of active columns, the geometric centers of two adjacent second memory structures projected onto the first plane are C4 and C5, respectively; among the multiple second memory structures electrically connected to the second row of active columns adjacent to the first row of active columns, the geometric center of the second memory structure with the smallest sum of distances to C4 and C5 projected onto the first plane is C6, and the line connecting C4, C5, and C6 forms an equilateral triangle.

[0019] In the above scheme, both the first bit line and the second bit line extend along the third direction;

[0020] The first bit line is connected to the second active region of the first active column in the same column arranged along the third direction;

[0021] The second bit line is connected to the first active region of the second active column arranged in the same column along the third direction.

[0022] In the above scheme, the semiconductor structure further includes a gate oxide layer, the gate oxide layer surrounding the first active pillar and the second active pillar, and the word line surrounding the gate oxide layer.

[0023] In the above scheme, the first bit line is located between the active column array and the second memory structure, and the second bit line is located between the active column array and the first memory structure.

[0024] In the above scheme, the semiconductor structure further includes:

[0025] A first contact structure is located between the active pillar array and the first storage structure, and is used to electrically connect the first active area of ​​the first active pillar to the first storage structure.

[0026] The second contact structure is located between the active pillar array and the second memory structure, and is used to electrically connect the second active region of the second active pillar to the second memory structure.

[0027] In the above scheme, the semiconductor structure includes a dynamic random access memory, and both the first memory structure and the second memory structure include storage capacitors.

[0028] According to another aspect of this disclosure, a memory system is provided, comprising: one or more semiconductor structures as described in any of the above embodiments; and

[0029] A memory controller that is coupled to and controls the semiconductor structure.

[0030] According to another aspect of this disclosure, a method for fabricating a semiconductor structure is provided, comprising:

[0031] An active column array is formed, the active column array including a first active column and a second active column arranged in an array, the first active column and the second active column each include a channel region and a first active region and a second active region located at opposite ends of the channel region along a first direction, the first direction being the direction in which the channel region extends;

[0032] A word line is formed, the word line surrounding the first active post and the second active post;

[0033] A second bit line and a first memory structure are formed on the first side of the active pillar array; the second bit line is connected to the first active region of the second active pillar, and the first memory structure is electrically connected to the first active region of the first active pillar.

[0034] A first bit line and a second memory structure are formed on the second side of the active column array, respectively; the first bit line is connected to the second active region of the first active column, and the second memory structure is electrically connected to the second active region of the second active column; the first side and the second side are two opposite sides of the active column array along the first direction.

[0035] In the above scheme, the first active column and the second active column constitute a plurality of columns of active columns arranged along the second direction and a plurality of rows of active columns arranged along the third direction. Each row of active columns includes alternating first active columns and second active columns, and each column of active columns includes a first active column or a second active column. The second direction intersects with the third direction and is perpendicular to the first direction.

[0036] In the above scheme, the word line extends along the second direction and surrounds the first active column and the second active column arranged in the same row along the second direction.

[0037] In the above scheme, the geometric center of the first active column projected onto the first plane is offset from the geometric center of the first storage structure projected onto the first plane along the second direction; and / or, the geometric center of the second active column projected onto the first plane is offset from the geometric center of the second storage structure projected onto the first plane along the second direction; the first plane is perpendicular to the first direction.

[0038] In the above scheme, the row active columns include a first row of active columns and a second row of active columns arranged alternately in the third direction; among the multiple first memory structures electrically connected to the first row of active columns, the geometric centers of two adjacent first memory structures projected onto the first plane are C1 and C2, respectively; among the multiple first memory structures electrically connected to the second row of active columns adjacent to the first row of active columns, the geometric center of the first memory structure with the smallest sum of distances to C1 and C2 projected onto the first plane is C3, and the line connecting C1, C2, and C3 forms an equilateral triangle;

[0039] And / or,

[0040] Among the multiple second memory structures electrically connected to the first row of active columns, the geometric centers of two adjacent second memory structures projected onto the first plane are C4 and C5, respectively; among the multiple second memory structures electrically connected to the second row of active columns adjacent to the first row of active columns, the geometric center of the second memory structure with the smallest sum of distances to C4 and C5 projected onto the first plane is C6, and the line connecting C4, C5, and C6 forms an equilateral triangle.

[0041] In the above scheme, both the first bit line and the second bit line extend along the third direction;

[0042] The first bit line is connected to the second active region of the first active column in the same column arranged along the third direction;

[0043] The second bit line is connected to the first active region of the second active column arranged in the same column along the third direction.

[0044] In the above scheme, the method further includes: forming a gate oxide layer, the gate oxide layer surrounding the first active pillar and the second active pillar, and the word line surrounding the gate oxide layer.

[0045] The above scheme forms the second bit line and the first storage structure, including:

[0046] A second bit line is formed on the first side of the active column array;

[0047] A first storage structure is formed on the second bit line;

[0048] Forming the first line and the second storage structure, including:

[0049] A first line is formed on the second side of the active column array;

[0050] A second storage structure is formed on the first line.

[0051] The method in the above scheme further includes:

[0052] Before forming the first storage structure, a first contact structure is formed on a first side of the active pillar array; the first contact structure is used to electrically connect the first active region of the first active pillar to the first storage structure.

[0053] Before forming the second storage structure, a second contact structure is formed on the second side of the active pillar array; the second contact structure is used to electrically connect the second active region of the second active pillar to the second storage structure.

[0054] This disclosure provides a semiconductor structure and its fabrication method, as well as a memory system. The semiconductor structure fabrication method includes: forming an active pillar array, the active pillar array including a first active pillar and a second active pillar arranged in an array, the first active pillar and the second active pillar each including a channel region and a first active region and a second active region located at opposite ends of the channel region along a first direction, the first direction being the direction in which the channel region extends; forming word lines, the word lines surrounding the first active pillar and the second active pillar; forming a second bit line and a first memory structure on a first side of the active pillar array; the second bit line being connected to the first active region of the second active pillar, and the first memory structure being electrically connected to the first active region of the first active pillar; forming a first bit line and a second memory structure on a second side of the active pillar array; the first bit line being connected to the second active region of the first active pillar, and the second memory structure being electrically connected to the second active region of the second active pillar; the first side and the second side being opposite sides of the active pillar array along the first direction. In this embodiment, a first memory structure and a second memory structure are formed on opposite sides of an active pillar array along a first direction, and a first bit line and a second bit line are formed on opposite sides of the active pillar array along the first direction. Firstly, since the first bit line and the second bit line are respectively located on opposite sides of the active pillar array along the first direction, the number of bit lines on each side is reduced. This increases the distance between adjacent first bit lines and adjacent second bit lines, thereby reducing the parasitic capacitance between adjacent first bit lines and adjacent second bit lines, thus improving memory performance. Secondly, since the first memory structure and the second memory structure are respectively located on opposite sides along the first direction, the area available for setting the first memory structure and the second memory structure is increased, thus reducing the manufacturing difficulty when forming a memory structure with a large storage capacity. Furthermore, in this embodiment, the word line surrounds the first active pillar and the second active pillar, which better suppresses leakage current formation and increases drive current, facilitating an effective balance between performance and power consumption. Attached Figure Description

[0055] Figure 1a This is a schematic diagram of the structure of a DRAM memory cell formed using planar transistors in related technologies;

[0056] Figure 1b This is a schematic diagram of the structure of a DRAM memory cell formed using buried channel transistors in related technologies.

[0057] Figure 1c This is a three-dimensional structural diagram of a semiconductor structure provided in an embodiment of the present disclosure;

[0058] Figure 2aThis is a schematic diagram of the circuit connection of a DRAM transistor provided in an embodiment of this disclosure;

[0059] Figure 2b This is a schematic diagram of the circuit connection of a storage cell array provided in an embodiment of this disclosure;

[0060] Figure 3 A schematic flowchart illustrating a method for manufacturing a semiconductor structure according to an embodiment of this disclosure;

[0061] Figures 4-28 This is a cross-sectional schematic diagram of the manufacturing process of a semiconductor structure provided in an embodiment of the present disclosure. Detailed Implementation

[0062] To make the technical solutions and advantages of the embodiments of this disclosure clearer, the technical solutions of this disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. Although exemplary implementation methods of this disclosure are shown in the accompanying drawings, it should be understood that this disclosure can be implemented in various forms and should not be limited to the implementation methods set forth herein. Rather, these implementation methods are provided so that this disclosure will be thorough and complete, and will fully convey the scope of this disclosure to those skilled in the art.

[0063] The present disclosure is described in more detail below by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become clearer from the following description and claims. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present disclosure.

[0064] It is understood that the meanings of “on”, “above” and “above” in this disclosure should be interpreted in the broadest sense, such that “on” means not only that it is “on” something without any intervening feature or layer (i.e., directly on something), but also that it is “on” something with an intervening feature or layer.

[0065] Furthermore, for ease of description, spatial relative terms such as “on,” “above,” “above,” “upper,” “above,” “upper,” etc., may be used herein to describe the relationship between one element or feature and another element or feature as shown in the figures. In addition to the orientations depicted in the figures, the spatial relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations) and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0066] In embodiments of this disclosure, the term "substrate" refers to the material on which subsequent material layers are added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include various semiconductor materials, such as silicon, silicon germanium, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafer.

[0067] In embodiments of this disclosure, the term "layer" refers to a portion of material including a region having thickness. A layer may extend over the entirety of a lower or upper structure, or may have a range smaller than that of the lower or upper structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be located between any horizontal faces at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers. For example, an interconnect layer may include one or more conductor and contact sublayers (where interconnect lines and / or via contacts are formed), and one or more dielectric sublayers.

[0068] In the embodiments of this disclosure, the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0069] The semiconductor structure disclosed herein is at least a portion of the structure that will be used in subsequent processes to form the final device structure. Here, the final device may include a memory, including but not limited to dynamic random access memory (DRAM). The following description uses DRAM as an example only.

[0070] However, it should be noted that the following description of dynamic random access memory is only for illustrating this disclosure and is not intended to limit the scope of this disclosure.

[0071] In related technologies, the transistors of mainstream memory include planar transistors and buried channel array transistors (BCAT). However, regardless of whether it is a planar transistor or a buried channel array transistor, the source and drain are located on the horizontal sides of the gate in terms of their structure. Figure 1a A three-dimensional structural diagram of a semiconductor structure including planar transistors; Figure 1b This is a three-dimensional structural diagram of a semiconductor structure including a buried-channel transistor. (Example) Figure 1a and Figure 1b As shown, in the related technology, the source S and drain D of the transistor are located on opposite sides of the gate G. In this structure, the source and drain occupy different positions, resulting in a larger area for both planar transistors and buried channel transistors.

[0072] Furthermore, since transistors can be fabricated on silicon substrates, they can be used in various types of memory, such as DRAM. Typically, DRAM consists of multiple memory cells, each primarily composed of a transistor and a capacitor controlled by the transistor; that is, DRAM has a structure of one transistor (T) and one capacitor (C) (1T1C). Its main operating principle is to use the amount of charge stored in the capacitor to represent whether a binary bit is 1 or 0. Figure 1a and Figure 1b As shown, in a DRAM memory cell, the source (or drain) of the transistor is connected to the bit line, and the drain (or source) is connected to the capacitor. For chips formed using BCAT (Block Component Assembly), chip-on-board (COB) packaging is typically used to form the memory. Since the source and drain of planar transistors and buried channel transistors are located on opposite sides of the gate, the bit lines and capacitors in the DRAM memory cell are also located on the same side of the gate. Furthermore, subsequent processes require connections between the bit lines, transistors, and capacitors, as well as connections between word lines (WL) and transistors. This results in complex circuit routing and a high manufacturing difficulty in the DRAM memory array area.

[0073] Figure 1c This is a three-dimensional structural diagram of a semiconductor structure provided in an embodiment of the present disclosure; as shown below. Figure 1c As shown, the semiconductor structure includes a memory cell array 124, peripheral circuitry 125, and interconnects 126 connecting the memory cell array and the peripheral circuitry.

[0074] Figure 2a This is a circuit connection diagram of a 1T1C architecture provided in an embodiment of this disclosure; as shown... Figure 2a As shown, the drain of transistor T is electrically connected to the bit line (BL), and the source of transistor T is electrically connected to one of the electrode plates of capacitor C. The other electrode plate of capacitor C can be connected to a reference voltage, which can be ground or other voltages. The gate of transistor T is connected to the word line. The transistor T is turned on or off by applying a voltage through the word line WL. The bit line BL is used to perform read or write operations on transistor T when it is turned on. Figure 2b This is a circuit connection diagram of a memory cell array provided in an embodiment of the present disclosure, as shown below. Figure 2b As shown, DRAM is equipped with Row Access Strobe (RAS) line inputs and Column Access Strobe (CAS) line inputs, which use the row address and column address of the memory cell to address a specific memory cell in order to read and write the cell.

[0075] As memory technology advances, the size of dynamic random access memory (DRAM) continues to shrink, making it increasingly difficult to manufacture DRAM with both large storage capacity and high performance.

[0076] In view of this, in order to solve the above problems, the present disclosure provides a method for fabricating a semiconductor structure that can form a dynamic random access memory with a large storage capacity, small size and high performance, and with relatively low process difficulty.

[0077] This disclosure provides a method for fabricating a semiconductor structure. Figure 3 This is a schematic flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of this disclosure. Figure 3 As shown, the method for fabricating a semiconductor structure provided in this embodiment includes the following steps:

[0078] S100: Form an active column array, the active column array including a first active column and a second active column arranged in an array, the first active column and the second active column each include a channel region and a first active region and a second active region located at opposite ends of the channel region along a first direction, the first direction being the direction in which the channel region extends;

[0079] S200: Forming word lines, the word lines surrounding the first active post and the second active post;

[0080] S300: A second bit line and a first memory structure are formed on the first side of the active pillar array; the second bit line is connected to the first active region of the second active pillar, and the first memory structure is electrically connected to the first active region of the first active pillar;

[0081] S400: A first bit line and a second memory structure are formed on the second side of the active column array; the first bit line is connected to the second active region of the first active column, and the second memory structure is electrically connected to the second active region of the second active column; the first side and the second side are two opposite sides of the active column array along the first direction.

[0082] It should be understood that Figure 3 The steps shown are not exclusive; other steps may be performed before, after, or between any of the steps shown. Figure 3 The steps shown can be adjusted in order according to actual needs. Figures 4 to 28 This is a cross-sectional schematic diagram illustrating the fabrication process of a semiconductor structure according to an embodiment of this disclosure. It should be noted that... Figures 4 to 28 This is a schematic diagram illustrating the complete manufacturing process of a semiconductor structure. Unmarked parts in some of the accompanying drawings can be shared. The following section combines... Figure 3 , Figures 4 to 28 The method for fabricating the semiconductor structure provided in the embodiments of this disclosure will be described in detail.

[0083] In step S100, the main task is to form an active column array.

[0084] In some embodiments, the first active column and the second active column constitute a plurality of columns of active columns arranged along a second direction and a plurality of rows of active columns arranged along a third direction. Each row of active columns includes alternating first active columns and second active columns, and each column of active columns includes either a first active column or a second active column. The second direction intersects with the third direction and is perpendicular to the first direction.

[0085] In some specific examples, forming an active column array includes:

[0086] An initial active column array is formed, the initial active column array including an initial first active column and an initial second active column arranged in an array; the initial first active column and the initial second active column each include a bottom, a middle and a top arranged in sequence along a first direction.

[0087] In some specific examples, forming an active column array further includes:

[0088] Remove the top to form the first groove;

[0089] The first groove is enlarged along the second direction to form a second groove;

[0090] The first active region is formed in the second groove;

[0091] And / or,

[0092] Remove the bottom to form a third groove;

[0093] The third groove is enlarged along the second direction to form a fourth groove;

[0094] The second active region is formed in the fourth groove.

[0095] In step S200, the main task is to form word lines.

[0096] In some embodiments, the word lines extend along the second direction and surround the first active post and the second active post arranged in the same row along the second direction.

[0097] In some embodiments, the method further includes: forming a gate oxide layer surrounding the first active pillar and the second active pillar, and the word line surrounding the gate oxide layer.

[0098] The following is combined Figures 4 to 14 The process of forming an active column array and word lines is described in detail.

[0099] like Figure 4 as well as Figure 5 As shown, a semiconductor layer is provided, having a first surface and a second surface disposed opposite each other in the thickness direction of the semiconductor layer. A portion of the semiconductor layer material is removed from the first surface to form a plurality of fifth grooves 135 and a plurality of sixth grooves 136. The fifth grooves 135 extend along a second direction, and the sixth grooves 136 extend along a third direction. The fifth grooves 135 and sixth grooves 136 divide the semiconductor layer into a plurality of initial active pillars. The initial active pillars include an initial first active pillar 101 and an initial second active pillar 102. Both the initial first active pillar 101 and the initial second active pillar 102 include a bottom 129, a middle portion 130, and a top 131 sequentially stacked along the first direction, and the initial first active pillar 101 and the initial second active pillar 102 are arranged in an array to form an initial active pillar array. In the initial active column array, the initial first active column 101 and the initial second active column 102 constitute a plurality of initial column active columns arranged along the second direction and a plurality of initial row active columns arranged along the third direction. The initial first active column 101 and the initial second active column 102 in each initial row active column are arranged alternately, and each initial column active column includes either the initial first active column 101 or the initial second active column 102.

[0100] here, Figure 5 It shows in Figure 4 A cross-sectional view of position AA'.

[0101] In some specific examples, the first direction can be understood as in Figures 4-28 The Z-axis direction shown is not limited to the Z-axis direction. The second direction can be understood as... Figures 4-28 The X-axis direction shown in the diagram is not limited to the X-axis direction. The third direction can be understood as... Figures 4-28 The Y-axis direction shown in the figure can be understood to mean that the third direction is not limited to the Y-axis direction.

[0102] Here, the intersection of the second direction and the third direction can be understood as the angle between the second direction and the third direction being less than or equal to 90 degrees. In some specific examples, the angle between the second direction and the third direction is equal to 90 degrees.

[0103] In some specific examples, the semiconductor layer may include a substrate, which may include a substrate of elemental semiconductor material (e.g., a silicon (Si) substrate, a germanium (Ge) substrate, etc.), a composite semiconductor material substrate (e.g., a silicon-germanium (SiGe) substrate, a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, etc. Preferably, the substrate is a silicon substrate.

[0104] Next, as follows Figure 6 As shown, a first insulating layer 117 is formed in both the fifth groove 135 and the sixth groove 136. In some specific examples, the material of the first insulating layer 117 includes, but is not limited to, silicon oxide and silicon nitride.

[0105] In some specific examples, the methods for forming the first insulating layer 117 include, but are not limited to, physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), and other processes.

[0106] Next, as Figure 7 As shown, a portion of the first insulating layer 117 is removed, exposing the sidewalls of the top 131 and the middle 130 of the initial first active post 101, as well as the sidewalls of the top 131 and the middle 130 of the initial second active post 102, thus forming the first filling region 127.

[0107] In some specific examples, the methods for removing a portion of the first insulating layer 117 include, but are not limited to, etching processes.

[0108] Next, as Figure 8 As shown, the exposed sidewalls of the initial first active pillar 101 and the initial second active pillar 102 are oxidized to form an oxide layer 115; and a first conductive material 128 is formed in the first filling region 127.

[0109] Here, the first conductive material 128 includes, but is not limited to, polycrystalline silicon, conductive metal or conductive alloy, and the conductive metal may include titanium, titanium nitride, molybdenum, tungsten or copper, etc.

[0110] Next, as Figure 9 as well as Figure 10As shown, a second filling region 132 is formed by removing a portion of the first conductive material 128 between the top 131 of the initial first active pillar 101 and the top 131 of the initial second active pillar 102, as well as a portion of the first conductive material 128 between the middle portion 130 of the initial first active pillar 101 and the middle portion 130 of the initial second active pillar 102. Here, the remaining first conductive material 128 forms multiple word lines 114, which extend along a second direction and surround the initial first active pillar 101 and the initial second active pillar 102.

[0111] It is understood that in this embodiment of the present disclosure, the word line 114 surrounds the initial first active pillar 101 and the initial second active pillar 102, so that in the final semiconductor structure, the word line 114 surrounds the first active pillar 101 and the second active pillar 102. This can better suppress the formation of leakage current and increase the drive current, which is conducive to achieving an effective balance between performance and power consumption.

[0112] here, Figure 10 It shows in Figure 9 A cross-sectional view of position AA'.

[0113] Next, as Figure 11 As shown, a sixth insulating layer 122 is formed in the second filling region 132.

[0114] In some specific examples, the material of the sixth insulating layer 122 includes, but is not limited to, silicon oxide and silicon nitride.

[0115] In some specific examples, the methods for forming the sixth insulating layer 122 include, but are not limited to, PVD, CVD, and ALD.

[0116] Next, as Figure 12 As shown in Figure 14, the top 131 of the initial first active post 101 and the top 131 of the initial second active post 102 are removed to form a first groove 133. The first groove 133 is then enlarged along the second direction and / or the third direction to form a second groove 134, in which a first active region 103 is formed.

[0117] In some specific examples, the methods for forming the first groove 133 include, but are not limited to, etching processes.

[0118] Here, enlarging the first groove 133 along the second direction and / or the third direction means removing the oxide layer 115 and part of the sixth insulating layer 122 within the first groove 133 along the second direction and / or the third direction, so that the projected area of ​​the formed second groove 134 on the first plane is larger than the projected area of ​​the first groove 133 on the first plane, and the first plane is perpendicular to the first direction. Here, as... Figure 14As shown, the remaining oxide layer 115 constitutes the gate oxide layer 116, which surrounds the first active pillar 112 and the second active pillar 113, and the word line 114 surrounds the gate oxide layer 116.

[0119] Here, since the sidewalls of the bottom 129 of the initial first active pillar 101 and the bottom 129 of the initial second active pillar 102 are not oxidized, the projected area of ​​the bottom 129 of the initial first active pillar 101 on the first plane is larger than the projected area of ​​the middle part 130 of the initial first active pillar 101 on the first plane, and the projected area of ​​the bottom 129 of the initial second active pillar 102 on the first plane is larger than the projected area of ​​the middle part 130 of the initial second active pillar 102 on the first plane. In some specific examples, the bottom 129 of the initial first active pillar 101 and the bottom 129 of the initial second active pillar 102 may not be removed, so that the bottom 129 of the initial first active pillar 101 and the bottom 129 of the initial second active pillar 102 directly constitute the second active region 104, and the initial active pillars between the first active region 103 and the second active region 104 constitute the channel region 105. Here, the initial active column array corresponds to the formation of an active column array, the initial first active column 101 corresponds to the formation of a first active column 112, and the initial second active column 102 corresponds to the formation of a second active column 113. The first active regions 103 of the first active column 112 and the second active column 113 are both close to the first side, and the second active regions 104 of the first active column 112 and the second active column 113 are both close to the second side. The formed first active columns 112 and the second active columns 113 constitute several columns of active columns arranged along the second direction and several rows of active columns arranged along the third direction. The first active columns 112 and the second active columns 113 in each row of active columns are arranged alternately, and each column of active columns includes either the first active column 112 or the second active column 113.

[0120] It should be noted that, Figure 14 The first active column 112 and the second active column 113 shown are arranged alternately in the second direction, but Figure 14 This is merely an example of the arrangement of the first active column 112 and the second active column 113, and is not intended to limit the arrangement of the first active column 112 and the second active column 113 in the embodiments of this disclosure.

[0121] In some specific examples, semiconductor material can be formed in the second groove 134. The methods for forming semiconductor material include, but are not limited to, epitaxial growth process, deposition process, and then forming the first active region 103 by doping process or diffusion process on semiconductor material.

[0122] In some specific examples, the formed semiconductor structure can be an N-type transistor or a P-type transistor. In an N-type transistor, both the first active region 103 and the second active region 104 are doped with N-type doping; in a P-type transistor, both the first active region 103 and the second active region 104 are doped with P-type doping. For example, when the doping type is P-type doping, the P-type impurity source can be boron (B), aluminum (Al), etc., and the P-type impurity source is not limited to these; when the doping type is N-type doping, the N-type impurity source can be phosphorus (P), arsenic (As), etc., and the N-type impurity source is not limited to these.

[0123] It is understandable that, since the projected area of ​​the second groove 134 on the first plane is greater than the projected area of ​​the first groove 133 on the first plane, and the first active region 103 is formed in the second groove 134, the projected area of ​​the first active region 103 on the first plane is greater than the projected area of ​​the channel region 105 on the first plane.

[0124] Here, the first active region 103 can be the source or drain of a transistor, and the subsequently formed second active region 104 can also be the source or drain of a transistor. For example, the first active region 103 of the first active pillar 112 can be the source, and the second active region 104 of the first active pillar 112 can be the drain; the first active region 103 of the second active pillar 113 can be the drain, and the second active region 104 of the second active pillar 113 can be the source.

[0125] In other specific examples, the bottom 129 of the initial first active pillar 101 and the bottom 129 of the initial second active pillar 102 can be removed in subsequent processes to form a second active region 104 with a larger size along the second direction and / or the third direction. In practical applications, it can be selected whether to form a second active region 104 with a larger size along the second direction and / or the third direction according to specific requirements.

[0126] It is understood that in the embodiments of this disclosure, the projected area of ​​the first active region 103 and the second active region 104 on the first plane is greater than the projected area of ​​the channel region 105 on the first plane, thereby increasing the contact area between the first active region 103 and the second bit line 109 and the first memory structure 106, and increasing the contact area between the second active region 104 and the second memory structure 107 and the first bit line 108, thereby reducing the contact resistance.

[0127] It should be noted that, in the above embodiments, the top 131 and middle 130 sidewalls of the initial first active column 101 and the top 131 and middle 130 sidewalls of the initial second active column 102 are oxidized, thereby making the projected area of ​​the bottom 129 of the initial first active column 101 on the first plane larger than the projected area of ​​the middle 130 of the initial first active column 101 on the first plane, and the projected area of ​​the bottom 129 of the initial second active column 102 on the first plane larger than the projected area of ​​the middle 130 of the initial second active column 102 on the first plane. In other specific examples, the top 131 and middle 130 sidewalls of the initial first active pillar 101 and the top 131 and middle 130 sidewalls of the initial second active pillar 102 may not be oxidized. Instead, an oxide layer 115 may be directly formed on the top 131 and middle 130 sidewalls of the initial first active pillar 101 and the initial second active pillar 102 using a deposition process. In subsequent processes, the bottom 129 of the initial first active pillar 101 and the bottom 129 of the initial second active pillar 102 may be exposed by thinning the semiconductor layer from the second side of the semiconductor layer. Then, the bottom 129 of the initial first active pillar 101 and the bottom 129 of the initial second active pillar 102 may be removed to form a second active region 104 with a larger size along the second direction and / or the third direction.

[0128] In step S300, the main task is to form the first memory structure and the second bit line.

[0129] In some embodiments, the second bit line extends along the third direction;

[0130] The second bit line is connected to the first active region of the second active column arranged in the same column along the third direction.

[0131] In some embodiments, forming a second bit line and a first storage structure includes:

[0132] A second bit line is formed on the first side of the active column array;

[0133] The first storage structure is formed on the second bit line.

[0134] In some embodiments, the method further includes:

[0135] Before forming the first storage structure, a first contact structure is formed on a first side of the active pillar array; the first contact structure is used to electrically connect the first active region of the first active pillar to the first storage structure.

[0136] In some embodiments, the geometric center of the first active column projected onto the first plane is offset from the geometric center of the first storage structure projected onto the first plane along the second direction; the first plane is perpendicular to the first direction.

[0137] In some embodiments, the row active columns include a first row of active columns and a second row of active columns arranged alternately in the third direction; among the plurality of first memory structures electrically connected to the first row of active columns, the geometric centers of two adjacent first memory structures projected onto the first plane are C1 and C2, respectively; among the plurality of first memory structures electrically connected to the second row of active columns adjacent to the first row of active columns, the geometric center of the first memory structure with the smallest sum of distances to C1 and C2 projected onto the first plane is C3, and the line connecting C1, C2, and C3 forms an equilateral triangle.

[0138] The following is combined Figures 15 to 19 The specific process of forming the first memory structure and the second bit line is described in detail.

[0139] like Figure 15 as well as Figure 16 As shown, a second bit line 109 is formed on the first side of the active pillar array, i.e., on the first surface of the semiconductor layer. The second bit line 109 extends in a third direction and is connected to the first active region 103 of the second active pillar 113. In some specific examples, the bit line can be formed by forming a metal line at a predetermined bit line location. The metal line includes, but is not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polycrystalline silicon, doped silicon, silicide, or any combination thereof.

[0140] It is understood that the second active pillar 113 in the same column of active pillars shares the same second bit line 109, and the first active pillar 112 and the second active pillar 113 are arranged alternately in the second direction. The first bit line 108 connected to the first active pillar 112 will be set on the second side of the active pillar array in subsequent processes. The adjacent second bit lines 109 will form a first contact structure 110 in subsequent processes. The distance between adjacent second bit lines 109 is large, so the parasitic capacitance between adjacent second bit lines 109 is small. Similarly, the distance between adjacent first bit lines 108 formed in subsequent processes is large, so the parasitic capacitance between adjacent first bit lines 108 is small. This can improve the performance of the memory.

[0141] here, Figure 16 It shows in Figure 15 The cross-sectional view at position AA' is shown to more clearly illustrate the positional relationship between the first active column 112, the second active column 113, the word line 114, and the second position line 109. Figure 15 The top view shown is a perspective view.

[0142] Here, the first side of the active column array and the second side of the active column array mentioned below are the two sides of the active column array that are arranged opposite each other along the first direction.

[0143] Here, the bit line BL is used to perform read or write operations on the transistor and the connected memory structure when the transistor is turned on.

[0144] Next, as Figure 17 As shown, a second insulating layer 118 is formed on the active pillar array, the second bit line 109 is located in the second insulating layer 118, and a first contact structure 110 is formed in the second insulating layer 118. The first contact structure 110 is used to electrically connect the first active region 103 of the first active pillar 112 to the first memory structure formed in the subsequent process.

[0145] Here, connection and electrical connection can be understood as follows: connection refers to two parts being physically contacted and thus directly connected, while electrical connection refers to two parts being indirectly connected through other parts.

[0146] Here, the geometric center of the first contact structure 110 projected onto the first plane overlaps with the geometric center of the first active column 112 projected onto the first plane.

[0147] It should be noted that the overlap in the embodiments of this disclosure refers to the overlap that is designed in the design, and the deviation caused by the process is ignored in the embodiments of this disclosure.

[0148] In some specific examples, the specific process of forming the first contact structure 110 includes: forming a contact hole in the second insulating layer 118, and filling the contact hole with a conductive material to form the first contact structure 110.

[0149] In some specific examples, the material of the second insulating layer 118 includes, but is not limited to, silicon nitride and silicon oxide. Methods for forming the second insulating layer 118 include, but are not limited to, PVD, CVD, and ALD.

[0150] Next, as Figure 18 as well as Figure 19 As shown, a third insulating layer 119 is formed on the second insulating layer 118, and a first storage structure 106 is formed in the third insulating layer 119. The first storage structure 106 is electrically connected to the first active region 103 of the first active post 112 through the first contact structure 110.

[0151] here, Figure 19 It shows in Figure 18 The cross-sectional view at position AA' is shown to more clearly illustrate the positional relationship between the first active pillar 112, the second active pillar 113, the word line 114, the second bit line 109, and the first memory structure 106. Figure 18The top view shown is a perspective view, and some structures are omitted.

[0152] In some specific examples, the material of the third insulating layer 119 includes, but is not limited to, silicon nitride and silicon oxide. Methods for forming the third insulating layer 119 include, but are not limited to, PVD, CVD, and ALD.

[0153] like Figure 18 as well as Figure 19 As shown, the geometric center of the first active column 112 projected onto the first plane is offset from the geometric center of the first storage structure 106 projected onto the first plane along the second direction.

[0154] It should be noted that the offset in the embodiments of this disclosure refers to the offset designed during the design phase, while offsets caused by process factors are not within the scope of protection of the embodiments of this disclosure.

[0155] Here, since the geometric center of the first contact structure 110 projected onto the first plane overlaps with the geometric center of the first active column 112 projected onto the first plane, the geometric center of the first contact structure 110 projected onto the first plane and the geometric center of the first storage structure 106 projected onto the first plane are offset along the second direction.

[0156] Here, as Figure 18 As shown, the row active columns include first row active columns 137 and second row active columns 138 alternately arranged in the third direction; the first storage structure 106 electrically connected to two first active columns 112 belonging to the same column of adjacent first row active columns 137 and second row active columns 138 has an offset at the geometric center of its projection onto the second plane; the second plane is perpendicular to the third direction. That is, the offset directions of the first storage structure 106 electrically connected to the first row active column 137 and the first storage structure 106 electrically connected to the second row active column 138 are opposite. Figure 18 As shown, the two first storage structures 106 enclosed by the dashed box are active columns of the same column of active columns. The geometric centers of the first storage structures 106 electrically connected to the first row of active columns 137 are all offset along the negative X-axis direction of the geometric center of the first active column in the first plane projection. The geometric centers of the first storage structures 106 electrically connected to the second row of active columns 138 are all offset along the positive X-axis direction of the geometric center of the first active column in the first plane projection.

[0157] It is understandable that the offset directions of the first memory structure 106 electrically connected to the first row of active pillars 137 and the first memory structure 106 electrically connected to the second row of active pillars 138 are opposite. This results in a larger distance between the first memory structure 106 electrically connected to the first row of active pillars 137 and the first memory structure 106 electrically connected to the second row of active pillars 138. When forming a semiconductor structure with the same storage capacity, the size of the semiconductor structure in the third direction is reduced, thereby reducing the area of ​​the semiconductor structure and facilitating the miniaturization of devices.

[0158] like Figure 18 As shown, among the plurality of first storage structures 106 electrically connected to the first row of active columns 137, the geometric centers of two adjacent first storage structures 106 projected onto the first plane are C1 and C2, respectively; among the plurality of first storage structures 106 electrically connected to the second row of active columns 138 adjacent to the first row of active columns 137, the geometric center of the first storage structure 106 with the smallest sum of distances to C1 and C2 projected onto the first plane is C3, and the line connecting C1, C2, and C3 forms an equilateral triangle.

[0159] It is understandable that when the lines connecting C1, C2, and C3 form an equilateral triangle, the first memory structure is more evenly distributed, which results in a larger area utilization rate for the semiconductor structure.

[0160] In some specific examples, forming the first storage structure 106 may include the following steps: forming a storage structure hole on the first contact structure 110; forming the first storage structure 106 in the storage structure hole, for example, forming a storage capacitor.

[0161] In some specific examples, the storage capacitor can present various structures. For example, the storage capacitor may include a cup-shaped capacitor (CUP), a cylindrical capacitor (CYL), or a pillar-shaped capacitor (PIL). Each of these capacitors includes a bottom electrode, a top electrode, and a dielectric layer located between the bottom and top electrodes.

[0162] In some specific examples, the bottom electrode is electrically connected to the first active region 103 of the first active post 112, the top electrode of the cup-shaped capacitor CUP can be connected to 1 / 2 Vcc, and the bottom electrode of the cup-shaped capacitor CUP can be used to store the written data.

[0163] It should be noted that, when the bottom electrode areas of the cup-shaped capacitor (CUP), cylindrical capacitor (CYL), and pillar-shaped capacitor (PIL) are equal, the top electrode area of ​​the cylindrical capacitor (CYL) is the largest, followed by the cup-shaped capacitor (CUP) and the pillar-shaped capacitor (PIL). Therefore, in practical applications, the cylindrical capacitor (CYL) can be used as the storage unit of a memory, which is beneficial for improving the integration density of the memory.

[0164] It is understandable that a first memory structure 106 is formed on the first side of the active pillar array, and a second memory structure 107 is formed on the second side of the active pillar array in a subsequent process. The first memory structure 106 is connected to the first active region 103 of the first active pillar 112, and the second memory structure 107 is connected to the second active region 104 of the second active pillar 113. The first active pillar 112 and the second active pillar 113 are arranged alternately in the second direction, and the first active regions 103 of the first active pillar 112 and the second active regions 104 of the first active pillar 112 and the second active pillar 113 are all located on the same side. This allows the area occupied by the first memory structure 106 and the second memory structure 107 to increase while keeping the overall memory area unchanged. On the one hand, this reduces the process difficulty of forming the first memory structure 106 and the second memory structure 107 with larger storage capacity. On the other hand, it allows the formation of the first memory structure 106 and the second memory structure 107 with even larger storage capacity.

[0165] In step S400, the main task is to form the first bit line and the second storage structure.

[0166] In some embodiments, the first bit line extends along the third direction;

[0167] The first bit line is connected to the second active region of the first active column arranged in the same column along the third direction.

[0168] In some embodiments, forming a first line and a second storage structure includes:

[0169] A first line is formed on the second side of the active column array;

[0170] A second storage structure is formed on the first line.

[0171] In some embodiments, the method further includes:

[0172] Before forming the second storage structure, a second contact structure is formed on the second side of the active pillar array; the second contact structure is used to electrically connect the second active region of the second active pillar to the second storage structure.

[0173] In some embodiments, the geometric center of the second active column projected onto the first plane is offset from the geometric center of the second storage structure projected onto the first plane along the second direction.

[0174] In some embodiments, among the plurality of second memory structures electrically connected to the first row of active pillars, the geometric centers of two adjacent second memory structures projected onto the first plane are C4 and C5, respectively; among the plurality of second memory structures electrically connected to the second row of active pillars adjacent to the first row of active pillars, the geometric center of the second memory structure with the smallest sum of distances to C4 and C5 projected onto the first plane is C6, and the line connecting C4, C5, and C6 forms an equilateral triangle.

[0175] The following is combined Figures 20 to 28 The formation process of the first line and the second memory structure is described in detail.

[0176] In some specific examples, such as Figure 20 As shown, the method further includes: bonding a carrier layer 123 to a first side of the first storage structure 106, wherein the material of the carrier layer 123 includes, but is not limited to, silicon oxide.

[0177] It is understandable that in subsequent processes, process operations need to be performed on the second side of the active pillar array, that is, the second side of the semiconductor layer. The semiconductor layer needs to be flipped so that the first memory structure 106 is placed underneath. The carrier layer 123 can protect the first memory structure 106, the second bit line 109, and the first contact structure 110 to prevent them from being damaged in subsequent processes.

[0178] like Figure 21 As shown, the second side of the semiconductor layer is thinned to expose the second active region 104 of the first active pillar 112 and the second active pillar 113.

[0179] In some specific examples, the thinning process of the second side of the semiconductor layer includes, but is not limited to, chemical mechanical polishing (CMP) and etching processes.

[0180] In some specific examples, after exposing the second active region 104 of the first active pillar 112 and the second active pillar 113, the dimensions of the second active region 104 along the second direction and / or the third direction can be further enlarged. For example, the second active region 104 can be removed to form a third groove; the third groove can be enlarged along the second direction and / or the third direction to form a fourth groove; and semiconductor material can be filled into the fourth groove to form a second active region with a larger dimension along the second direction and / or the third direction.

[0181] Next, as Figure 22 as well as Figure 23As shown, a first line 108 is formed on the second surface. The first line 108 extends along the third direction and is connected to the second active region 104 of the first active column 112.

[0182] here, Figure 23 It shows in Figure 22 The cross-sectional view at position AA' is shown to more clearly illustrate the positional relationship between the first active pillar 112, the second active pillar 113, the word line 114, the second bit line 109, the first memory structure 106, and the first bit line 108. Figure 22 The top view shown is a perspective view, and some structures are omitted.

[0183] Next, as Figure 24 As shown, a fourth insulating layer 120 is formed on the second surface, the first line 108 is located in the fourth insulating layer 120, and a second contact structure 111 is formed in the fourth insulating layer 120. The second contact structure 111 is used to electrically connect the second active region 104 of the second active post 113 to the second memory structure formed in the subsequent process.

[0184] Here, the geometric center of the second contact structure 111 projected onto the first plane overlaps with the geometric center of the second active column 113 projected onto the first plane.

[0185] In some specific examples, the material of the fourth insulating layer 120 includes, but is not limited to, silicon nitride and silicon oxide. Methods for forming the fourth insulating layer 120 include, but are not limited to, PVD, CVD, and ALD.

[0186] Next, as Figure 25 as well as Figure 26 As shown, a fifth insulating layer 121 is formed on the fourth insulating layer 120, and a second storage structure 107 is formed in the fifth insulating layer 121. The second storage structure 107 is electrically connected to the second active region 104 of the second active post 113 through the second contact structure 111.

[0187] here, Figure 26 It shows in Figure 25 The cross-sectional view at position AA' is shown to more clearly illustrate the positional relationship between the first active pillar 112, the second active pillar 113, the word line 114, the second bit line 109, the first memory structure 106, the first bit line 108, and the second memory structure 107. Figure 25 The top view shown is a perspective view, and some structures are omitted.

[0188] In some specific examples, the material of the fifth insulating layer 121 includes, but is not limited to, silicon nitride and silicon oxide. Methods for forming the fifth insulating layer 121 include, but are not limited to, PVD, CVD, and ALD.

[0189] The second storage structure 107 is similar to the first storage structure 106 in structure and manufacturing method, and will not be described in detail here.

[0190] like Figure 25 as well as Figure 26 As shown, the geometric center of the second active column 113 projected onto the first plane is offset from the geometric center of the second storage structure 107 projected onto the first plane along the second direction.

[0191] Here, since the geometric center of the second contact structure 111 projected onto the first plane overlaps with the geometric center of the second active column 113 projected onto the first plane, the geometric center of the second contact structure 111 projected onto the first plane and the geometric center of the second storage structure 107 projected onto the first plane are offset along the second direction.

[0192] Here, the two second storage structures 107 electrically connected to two second active columns 113 belonging to the same column of the adjacent first row active columns 137 and second row active columns 138 are offset from the geometric center of the second plane projection. That is, the offset directions of the second storage structure 107 electrically connected to the first row active column 137 and the second storage structure 107 electrically connected to the second row active column 138 are opposite.

[0193] like Figure 25 As shown, the two second storage structures 107 enclosed by the dashed box are active columns of the same column of active columns. The geometric centers of the second storage structures 107 electrically connected to the first row of active columns 137 are all offset along the negative X-axis direction of the geometric center of the second active column in the first plane projection. The geometric centers of the second storage structures 107 electrically connected to the second row of active columns 138 are all offset along the positive X-axis direction of the geometric center of the second active column in the first plane projection.

[0194] It is understandable that the offset directions of the second memory structure electrically connected to the first row of active pillars and the second memory structure electrically connected to the second row of active pillars are different. This results in a larger distance between the two memory structures. When forming a semiconductor structure with the same storage capacity, the size of the semiconductor structure in the third direction is reduced, thereby reducing the area of ​​the semiconductor structure and facilitating the miniaturization of devices.

[0195] In some specific examples, the projection portions of the first storage structure 106 and the second storage structure 107 onto the first plane overlap. For example... Figure 25 as well as Figure 26As shown, the first and second memory structures, which are electrically connected to the active columns in the same row, are offset in the same direction, for example, as shown in the figure. Figure 25 as well as Figure 26 As shown, the first storage structure 106 and the second storage structure 107, which are electrically connected to the first row of active columns 137, are both offset along the negative X-axis direction, so that the projection portions of the first storage structure 106 and the second storage structure 107 on the first plane overlap.

[0196] In other specific examples, the projections of the first storage structure 106 and the second storage structure 107 onto the first plane overlap. For example... Figure 27 as well as Figure 28 As shown, the first memory structure 106 and the second memory structure 107, which are electrically connected to the active columns in the same row, are offset in opposite directions, as exemplarily as... Figure 27 as well as Figure 28 As shown, the first storage structure 106, which is electrically connected to the first row of active pillars 137, is offset along the negative X-axis direction, and the second storage structure 107, which is electrically connected to the first row of active pillars 137, is offset along the positive X-axis direction, so that the projections of the first storage structure 106 and the second storage structure 107 on the first plane overlap.

[0197] like Figure 25 As shown, among the multiple second storage structures 107 electrically connected to the first row of active columns, the geometric centers of two adjacent second storage structures 107 projected onto the first plane are C4 and C5, respectively; among the multiple second storage structures 107 electrically connected to the second row of active columns adjacent to the first row of active columns, the geometric center of the second storage structure 107 with the smallest sum of distances to C4 and C5 projected onto the first plane is C6, and the line connecting C4, C5, and C6 forms an equilateral triangle.

[0198] It is understandable that when the lines connecting C4, C5, and C6 form an equilateral triangle, the second memory structure is more evenly distributed, which results in a larger area utilization rate for the semiconductor structure.

[0199] In some specific examples, the ratio of (pitch of active pin)2:(pitch of word line)2:(pitch of bit line)2 is 1:3:4.

[0200] Here, the pitch of an active column can be understood as the distance between the geometric centers of the first and second adjacent active columns in the same row. The pitch of a word line can be understood as the distance between the geometric centers of two adjacent word lines. The pitch of a bit line can be understood as the distance between the geometric centers of adjacent first bit lines or adjacent second bit lines.

[0201] It should be noted that the values ​​of (active column pitch)2: (word line pitch)2: (bit line pitch)2 given in the above embodiments are merely exemplary demonstrations and are not intended to limit the values ​​of (active column pitch)2: (word line pitch)2: (bit line pitch)2 in this disclosure.

[0202] In some specific examples, the semiconductor structure includes a dynamic random access memory, and both the first memory structure 106 and the second memory structure 107 include storage capacitors.

[0203] This disclosure provides a method for fabricating a semiconductor structure, comprising: forming an active pillar array, the active pillar array including a first active pillar 112 and a second active pillar 113 arranged in an array, the first active pillar 112 and the second active pillar 113 each including a channel region 105 and a first active region 103 and a second active region 104 respectively located at opposite ends of the channel region 105 along a first direction, the first direction being the direction in which the channel region 105 extends; forming word lines 114, the word lines 114 surrounding the first active pillar 112 and the second active pillar 113; and forming second bits on a first side of the active pillar array. The active column array includes a bit line 109 and a first storage structure 106; the second bit line 109 is connected to the first active region 103 of the second active column 113, and the first storage structure 106 is electrically connected to the first active region 103 of the first active column 112; a first bit line 108 and a second storage structure 107 are formed on the second side of the active column array; the first bit line 108 is connected to the second active region 104 of the first active column 112, and the second storage structure 107 is electrically connected to the second active region 104 of the second active column 113; the first side and the second side are two opposite sides of the active column array along the first direction. In this embodiment, a first memory structure 106 and a second memory structure 107 are formed on opposite sides of an active column array along a first direction, and a first bit line 108 and a second bit line 109 are formed on opposite sides of the active column array along the first direction. Firstly, since the first bit line 108 and the second bit line 109 are respectively located on opposite sides of the active column array along the first direction, the number of bit lines on each side is reduced. This increases the distance between adjacent first bit lines 108 and adjacent second bit lines 109, thereby reducing the parasitic capacitance between adjacent first bit lines 108 and adjacent second bit lines 109, thus improving memory performance. Secondly, since the first memory structure 106 and the second memory structure 107 are respectively located on opposite sides along the first direction, the area available for setting the first memory structure 106 and the second memory structure 107 is increased, thereby reducing the process difficulty when forming a memory structure with a large storage capacity. In addition, in this embodiment of the present disclosure, the word line 114 surrounds the first active post 112 and the second active post 113, which can better suppress the formation of leakage current and increase the drive current, thus helping to achieve an effective balance between performance and power consumption.

[0204] According to another aspect of this disclosure, embodiments of this disclosure also provide a semiconductor structure, including: an active pillar array, including a first active pillar and a second active pillar arranged in an array, the first active pillar and the second active pillar each including a channel region and a first active region and a second active region respectively located at opposite ends of the channel region along a first direction, the first direction being the direction in which the channel region extends; word lines surrounding the first active pillar and the second active pillar; a first memory structure located on a first side of the active pillar array and electrically connected to a first active region of the first active pillar; a second memory structure located on a second side of the active pillar array and electrically connected to a second active region of the second active pillar; the first side and the second side being two opposite sides of the active pillar array along the first direction; a first bit line located on the second side of the active pillar array and connected to the second active region of the first active pillar; and a second bit line located on the first side of the active pillar array and connected to the first active region of the second active pillar.

[0205] The semiconductor structures provided in this disclosure include various types of memory, such as NAND flash memory, Nor flash memory, DRAM, static random access memory (SRAM), and phase-change memory (PCM).

[0206] In some embodiments, the semiconductor structure includes a dynamic random access memory, and both the first and second memory structures include storage capacitors.

[0207] The embodiments disclosed herein merely exemplify some common memories, and the scope of protection of this disclosure is not limited thereto. Any memory containing the semiconductor structure provided in the embodiments of this disclosure falls within the scope of protection of this invention.

[0208] In some embodiments, the first active column and the second active column constitute a plurality of columns of active columns arranged along a second direction and a plurality of rows of active columns arranged along a third direction. Each row of active columns includes alternating first active columns and second active columns, and each column of active columns includes either a first active column or a second active column. The second direction intersects with the third direction and is perpendicular to the first direction.

[0209] In some embodiments, the word lines extend along the second direction and surround the first active post and the second active post arranged in the same row along the second direction.

[0210] In some embodiments, the geometric center of the first active post projected onto the first plane is offset from the geometric center of the first storage structure projected onto the first plane along the second direction; and / or, the geometric center of the second active post projected onto the first plane is offset from the geometric center of the second storage structure projected onto the first plane along the second direction; the first plane is perpendicular to the first direction.

[0211] In some embodiments, the row active columns include a first row of active columns and a second row of active columns arranged alternately in the third direction;

[0212] The two first memory structures that are electrically connected to two first active columns belonging to the same column in the adjacent first row and second row of active columns have an offset from the geometric center of the projection on the second plane;

[0213] And / or,

[0214] The two second storage structures, which are electrically connected to two second active columns belonging to the same column in the adjacent first row and second row of active columns, are offset from the geometric center of the projection on the second plane; the second plane is perpendicular to the third direction.

[0215] In some embodiments, the row active columns include a first row of active columns and a second row of active columns arranged alternately in the third direction; among the plurality of first memory structures electrically connected to the first row of active columns, the geometric centers of two adjacent first memory structures projected onto the first plane are C1 and C2, respectively; among the plurality of first memory structures electrically connected to the second row of active columns adjacent to the first row of active columns, the geometric center of the first memory structure with the smallest sum of distances to C1 and C2 projected onto the first plane is C3, and the line connecting C1, C2, and C3 forms an equilateral triangle;

[0216] And / or,

[0217] Among the multiple second memory structures electrically connected to the first row of active columns, the geometric centers of two adjacent second memory structures projected onto the first plane are C4 and C5, respectively; among the multiple second memory structures electrically connected to the second row of active columns adjacent to the first row of active columns, the geometric center of the second memory structure with the smallest sum of distances to C4 and C5 projected onto the first plane is C6, and the line connecting C4, C5, and C6 forms an equilateral triangle.

[0218] In some embodiments, both the first bit line and the second bit line extend along the third direction;

[0219] The first bit line is connected to the second active region of the first active column in the same column arranged along the third direction;

[0220] The second bit line is connected to the first active region of the second active column arranged in the same column along the third direction.

[0221] In some embodiments, the semiconductor structure further includes a gate oxide layer surrounding the first active pillar and the second active pillar, and the word line surrounding the gate oxide layer.

[0222] In some embodiments, the first bit line is located between the active pillar array and the second memory structure, and the second bit line is located between the active pillar array and the first memory structure.

[0223] In some embodiments, the semiconductor structure further includes:

[0224] A first contact structure is located between the active pillar array and the first storage structure, and is used to electrically connect the first active area of ​​the first active pillar to the first storage structure.

[0225] The second contact structure is located between the active pillar array and the second memory structure, and is used to electrically connect the second active region of the second active pillar to the second memory structure.

[0226] In some embodiments, the projection of the first storage structure onto the first plane overlaps with the projection of the second storage structure onto the first plane.

[0227] In some embodiments, the projection of the first storage structure onto the first plane partially overlaps with the projection of the second storage structure onto the first plane.

[0228] In some embodiments, the geometric center of the first contact structure projected onto the first plane overlaps with the geometric center of the first active post projected onto the first plane; the geometric center of the second contact structure projected onto the first plane overlaps with the geometric center of the second active post projected onto the first plane.

[0229] The semiconductor structure provided in the above embodiments has been described in detail in the method section and will not be repeated here.

[0230] According to another aspect of this disclosure, embodiments of this disclosure also provide a memory system, including:

[0231] One or more semiconductor structures as described in the above embodiments; and

[0232] A memory controller that is coupled to and controls the semiconductor structure.

[0233] The semiconductor structure disclosed herein is at least a portion of the structure that will be used in subsequent processes to form a final device structure. Here, the final device may include a memory.

[0234] In the several embodiments provided in this disclosure, it should be understood that the disclosed devices and methods can be implemented in a non-target manner. The device embodiments described above are merely illustrative; for example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components may be combined, or integrated into another system, or some features may be ignored or not executed. Furthermore, the various components shown or discussed may be coupled or directly coupled to each other.

[0235] The features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method or device embodiments.

[0236] This disclosure provides specific embodiments, but its scope of protection is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed herein should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A semiconductor structure, characterized in that, include: An active column array includes a first active column and a second active column arranged in an array. The first active column and the second active column each include a channel region and a first active region and a second active region located at opposite ends of the channel region along a first direction. The first direction is the direction in which the channel region extends. The first active column and the second active column constitute a plurality of columns of active columns arranged along the second direction and a plurality of rows of active columns arranged along the third direction. Each row of active columns includes alternating first active columns and second active columns, and each column of active columns includes either a first active column or a second active column. The second direction intersects with the third direction and is perpendicular to the first direction. The character line surrounds the first active post and the second active post; A first storage structure is located on the first side of the active pillar array and is electrically connected to the first active region of the first active pillar; The second storage structure is located on the second side of the active pillar array and is electrically connected to the second active region of the second active pillar; the first side and the second side are two opposite sides of the active pillar array along the first direction; The first line is located on the second side of the active column array and is connected to the second active region of the first active column; The second bit line is located on the first side of the active column array and is connected to the first active region of the second active column.

2. The semiconductor structure according to claim 1, characterized in that, The word line extends along the second direction and surrounds the first active post and the second active post arranged in the same row along the second direction.

3. The semiconductor structure according to claim 1, characterized in that, The geometric center of the first active column projected onto the first plane is offset from the geometric center of the first storage structure projected onto the first plane along the second direction; And / or, the geometric center of the second active column projected onto the first plane is offset from the geometric center of the second storage structure projected onto the first plane along the second direction; The first plane is perpendicular to the first direction.

4. The semiconductor structure according to claim 3, characterized in that, The row active columns include a first row of active columns and a second row of active columns arranged alternately in the third direction; among the multiple first memory structures electrically connected to the first row of active columns, the geometric centers of two adjacent first memory structures projected onto the first plane are C1 and C2, respectively; Among the multiple first memory structures that are electrically connected to the second row of active columns adjacent to the first row of active columns, the first memory structure with the smallest sum of distances to C1 and C2 has C3 as its geometric center in the projection of the first plane, and the line connecting C1, C2, and C3 forms an equilateral triangle. And / or, Among the multiple second memory structures electrically connected to the first row of active columns, the geometric centers of two adjacent second memory structures projected onto the first plane are C4 and C5, respectively. Among the multiple second memory structures that are electrically connected to the second row of active columns adjacent to the first row of active columns, the second memory structure with the smallest sum of distances to C4 and C5 has C6 as its geometric center when projected onto the first plane, and the line connecting C4, C5, and C6 forms an equilateral triangle.

5. The semiconductor structure according to claim 1, characterized in that, Both the first bit line and the second bit line extend along the third direction; The first bit line is connected to the second active region of the first active column in the same column arranged along the third direction; The second bit line is connected to the first active region of the second active column arranged in the same column along the third direction.

6. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure further includes a gate oxide layer surrounding the first active pillar and the second active pillar, and the word line surrounding the gate oxide layer.

7. The semiconductor structure according to claim 1, characterized in that, The first bit line is located between the active pillar array and the second memory structure, and the second bit line is located between the active pillar array and the first memory structure.

8. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure also includes: A first contact structure is located between the active pillar array and the first storage structure, and is used to electrically connect the first active area of ​​the first active pillar to the first storage structure. The second contact structure is located between the active pillar array and the second memory structure, and is used to electrically connect the second active region of the second active pillar to the second memory structure.

9. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure includes a dynamic random access memory, and both the first and second memory structures include storage capacitors.

10. A memory system, characterized in that, include: One or more semiconductor structures as described in any one of claims 1-9; as well as A memory controller that is coupled to and controls the semiconductor structure.

11. A method for fabricating a semiconductor structure, characterized in that, The method includes: An active column array is formed, comprising a first active column and a second active column arranged in an array. Each of the first and second active columns includes a channel region and a first active region and a second active region located at opposite ends of the channel region along a first direction. The first direction is the direction in which the channel region extends. The first and second active columns constitute a plurality of columns of active columns arranged along a second direction and a plurality of rows of active columns arranged along a third direction. Each row of active columns includes alternating first and second active columns, and each column of active columns includes either a first active column or a second active column. The second direction intersects the third direction and is perpendicular to the first direction. A word line is formed, the word line surrounding the first active post and the second active post; A second bit line and a first memory structure are formed on the first side of the active pillar array; the second bit line is connected to the first active region of the second active pillar, and the first memory structure is electrically connected to the first active region of the first active pillar. A first bit line and a second memory structure are formed on the second side of the active column array, respectively; the first bit line is connected to the second active region of the first active column, and the second memory structure is electrically connected to the second active region of the second active column; the first side and the second side are two opposite sides of the active column array along the first direction.

12. The manufacturing method according to claim 11, characterized in that, The word line extends along the second direction and surrounds the first active post and the second active post arranged in the same row along the second direction.

13. The manufacturing method according to claim 11, characterized in that, The geometric center of the first active column projected onto the first plane is offset from the geometric center of the first storage structure projected onto the first plane along the second direction; And / or, the geometric center of the second active column projected onto the first plane is offset from the geometric center of the second storage structure projected onto the first plane along the second direction; The first plane is perpendicular to the first direction.

14. The manufacturing method according to claim 13, characterized in that, The row active columns include a first row of active columns and a second row of active columns arranged alternately in the third direction; among the multiple first memory structures electrically connected to the first row of active columns, the geometric centers of two adjacent first memory structures projected onto the first plane are C1 and C2, respectively; Among the multiple first memory structures that are electrically connected to the second row of active columns adjacent to the first row of active columns, the first memory structure with the smallest sum of distances to C1 and C2 has C3 as its geometric center in the projection of the first plane, and the line connecting C1, C2, and C3 forms an equilateral triangle. And / or, Among the multiple second memory structures electrically connected to the first row of active columns, the geometric centers of two adjacent second memory structures projected onto the first plane are C4 and C5, respectively. Among the multiple second memory structures that are electrically connected to the second row of active columns adjacent to the first row of active columns, the second memory structure with the smallest sum of distances to C4 and C5 has C6 as its geometric center when projected onto the first plane, and the line connecting C4, C5, and C6 forms an equilateral triangle.

15. The manufacturing method according to claim 11, characterized in that, Both the first bit line and the second bit line extend along the third direction; The first bit line is connected to the second active region of the first active column in the same column arranged along the third direction; The second bit line is connected to the first active region of the second active column arranged in the same column along the third direction.

16. The manufacturing method according to claim 11, characterized in that, The method further includes: forming a gate oxide layer, the gate oxide layer surrounding the first active pillar and the second active pillar, and the word line surrounding the gate oxide layer.

17. The manufacturing method according to claim 11, characterized in that, Forming the second bit line and the first storage structure includes: A second bit line is formed on the first side of the active column array; A first storage structure is formed on the second bit line; Forming the first line and the second storage structure, including: A first line is formed on the second side of the active column array; A second storage structure is formed on the first line.

18. The manufacturing method according to claim 11, characterized in that, The method further includes: Before forming the first storage structure, a first contact structure is formed on a first side of the active pillar array; the first contact structure is used to electrically connect the first active region of the first active pillar to the first storage structure. Before forming the second storage structure, a second contact structure is formed on the second side of the active pillar array; the second contact structure is used to electrically connect the second active region of the second active pillar to the second storage structure.

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