Display substrate and display device

Abstract

A display substrate and a display device, comprising a display area and a peripheral area, the display area has a plurality of sub-pixels, each column of sub-pixels is connected with a data line; part of the data lines are directly connected with connection pads, and the other part of the data lines are connected with the connection pads through data connection lines; the plurality of sub-pixels comprise first color sub-pixels and second color sub-pixels, the connection pads comprise first connection pads and second connection pads, the first connection pads and the second connection pads are respectively electrically connected with the first color sub-pixels and the second color sub-pixels; the first signal transmission lines are in a first metal layer, and the second signal transmission lines are in a second metal layer; the first signal transmission lines and the second signal transmission lines are respectively electrically connected with the first connection pads and the second connection pads; the data line connected with the second connection pad and the first signal transmission line connected with the first connection pad have an overlap, or the data connection line is electrically connected with the first connection pad or the second connection pad through a connection electrode, and the connection electrode and the adjacent data line have an overlap.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to a display substrate and a display device. BACKGROUND

[0002] With the continuous development of display technology, consumers have increasingly high demand for narrow frame design of display devices. Therefore, how to further reduce the frame width of display devices has become the focus of researchers in the display field. Compared with traditional liquid crystal display devices, organic light-emitting diode (OLED) display products commonly used in narrow frame design have the advantages of self-luminous, wide color gamut, high contrast, thinness, etc., and are widely used in electronic devices such as mobile phones and tablet computers.

[0003] Generally, the display area of a display substrate includes a plurality of signal lines for driving the pixel structure in the display substrate to emit light for display. These signal lines need to be driven by a driving circuit or a driving chip electrically connected thereto. The driving circuit or the driving chip is usually arranged in the peripheral area of the display substrate. Therefore, the plurality of signal lines in the display area, such as data lines, need to be led out to the fanout area and then connected to the peripheral area that does not perform a display function but has an integrated circuit, including a lead area and a bonding area. The lead area includes a plurality of leads, and the bonding area is used for bonding with an external driving circuit or a driving chip. At this time, the plurality of leads can be electrically connected to the plurality of signal lines and extended to the bonding area, so that the pixel structure is bonded with the external driving circuit or the driving chip. SUMMARY

[0004] At least one embodiment of the present disclosure provides a display substrate and a display device. The display substrate is designed by jumpering data lines at a connection area of a fanout region adjacent to a display area (AA). The arrangement order of sub-pixels connected to data lines and data connection lines at a position close to the fanout region of the display area is different from the arrangement order of sub-pixels connected to a plurality of first signal transmission lines and a plurality of second signal transmission lines at a position away from the display area of the fanout region. The plurality of first signal transmission lines or the plurality of second signal transmission lines connected to sub-pixels of the same color are adjusted to be located in the same film layer to avoid different parasitic capacitances caused by the plurality of first signal transmission lines or the plurality of second signal transmission lines connected to sub-pixels of the same color in different film layers, and to avoid the problem of different data signal write amounts caused by different loads of the plurality of first signal transmission lines or the plurality of second signal transmission lines connected to sub-pixels of the same color.

[0005] The display substrate comprises a substrate, a display area and a peripheral area surrounding the display area, the peripheral area comprises a fan-out area adjacent to the display area and a pad area on a side of the fan-out area away from the display area; a plurality of sub-pixels arranged in a matrix in the display area, each column of the sub-pixels is connected with a data line; the fan-out area comprises a connection area adjacent to the display area, part of the data lines are directly connected with connection pads in the connection area, and another part of the data lines are connected with the connection pads in the connection area through data connection lines; the plurality of sub-pixels comprises a plurality of first color sub-pixels and a plurality of second color sub-pixels, the connection pads comprise a plurality of first connection pads and a plurality of second connection pads, the plurality of first connection pads are electrically connected with the plurality of first color sub-pixels, and the plurality of second connection pads are electrically connected with the plurality of second color sub-pixels; a plurality of first signal transmission lines and a plurality of second signal transmission lines are arranged at intervals at a position of the fan-out area close to the pad area, the plurality of first signal transmission lines are arranged in a first metal layer, and the plurality of second signal transmission lines are arranged in a second metal layer different from the first metal layer; the plurality of first signal transmission lines and the plurality of first connection pads are electrically connected one by one, and the plurality of second signal transmission lines and the plurality of second connection pads are electrically connected one by one; wherein two adjacent data connection lines and at least two data lines between the two adjacent data connection lines form a data line group, the connection pads connected with the at least two data lines in the data line group comprise at least one first connection pad and one second connection pad, and in at least one data line group, the data line connected with the second connection pad and the first signal transmission line connected with the first connection pad have an overlapping part in the substrate in orthographic projection; or the connection pads connected with the data lines and the data connection lines in the data line group comprise one first connection pad and one second connection pad, and in at least one data line group, the data connection line is electrically connected with the first connection pad or the second connection pad through a connection electrode, and the connection electrode and the data line adjacent to the data connection line have an overlapping part in the substrate in orthographic projection.

[0006] For example, in the display substrate provided by at least one of the embodiments of the present disclosure, the data lines and the data connection lines are arranged in the third conductive layer, the connection pads connected to two adjacent data lines in the one data line group are respectively the first connection pad and one second connection pad, the first data line in the odd column among the two adjacent data lines in the one data line group is connected to the first signal transmission line adjacent to the second data line in the even column, and the second data line in the even column extends to the side close to the first data line adjacent thereto at the position of the display area and the fan-out area to be electrically connected to the first signal transmission line corresponding thereto.

[0007] For example, in the display substrate provided by at least one of the embodiments of the present disclosure, the first data line in the odd column extends to the side close to the pad area first and then extends to the second data line in the even column adjacent thereto to form an "L" type structure or an inverted "L" type structure in the fan-out area, and the second data line in the even column extends to the side close to the first data line first and then extends to the side close to the pad area to form an unsealed quadrilateral with the first data line.

[0008] For example, in the display substrate provided by at least one of the embodiments of the present disclosure, the first data line and the first signal transmission line connected to the second data line intersect on a plane parallel to the main surface of the substrate.

[0009] For example, in the display substrate provided by at least one of the embodiments of the present disclosure, the plurality of first signal transmission lines and the plurality of second signal transmission lines are arranged alternately.

[0010] For example, in the display substrate provided by at least one of the embodiments of the present disclosure, a plurality of third signal transmission lines and a plurality of fourth signal transmission lines are arranged in the pad area in the second direction, the arrangement order of the sub-pixels connected to the plurality of third signal transmission lines and the plurality of fourth signal transmission lines is consistent with the arrangement order of the sub-pixels connected to the plurality of data lines and the plurality of data connection lines, a part of the plurality of third signal transmission lines is in the odd column, another part of the plurality of third signal transmission lines is in the even column, a part of the plurality of fourth signal transmission lines is in the odd column, another part of the plurality of fourth signal transmission lines is in the even column, at least one third signal transmission line and the second data line correspond to sub-pixels of the same color, and at least one fourth signal transmission line and the first data line correspond to sub-pixels of the same color.

[0011] For example, in the display substrate provided by at least one of the embodiments of the present disclosure, the third signal transmission lines arranged in even-numbered columns and the corresponding first signal transmission lines are electrically connected by first switching lines, the fourth signal transmission lines arranged in odd-numbered columns and the corresponding second signal transmission lines are electrically connected by second switching lines, the first switching lines and the second switching lines are located in different layers, the first switching lines are in a first conductive layer, the second switching lines are in a second conductive layer, and the first conductive layer and the second conductive layer are different layers.

[0012] For example, in the display substrate provided by at least one of the embodiments of the present disclosure, the fourth signal transmission lines arranged in even-numbered columns and the corresponding second signal transmission lines are electrically connected by fourth switching lines, the third signal transmission lines arranged in odd-numbered columns and the corresponding first signal transmission lines are electrically connected by third switching lines, and the third switching lines and the fourth switching lines are both arranged in the second conductive layer.

[0013] For example, in the display substrate provided by at least one of the embodiments of the present disclosure, at least one third signal transmission line arranged in an even-numbered column and one fourth signal transmission line arranged in an odd-numbered column are arranged adjacent to each other, and the first switching line connected to the at least one third signal transmission line arranged in the even-numbered column and the second switching line connected to the one fourth signal transmission line arranged in the odd-numbered column intersect in a plane parallel to a main surface of the substrate.

[0014] For example, in the display substrate provided by at least one of the embodiments of the present disclosure, the data lines and the data connection lines are arranged in a third conductive layer, at least one data connection line arranged in an odd-numbered column and one data line arranged in an even-numbered column are arranged adjacent to each other, the at least one data connection line arranged in the odd-numbered column is connected to the one data line arranged in the even-numbered column by a first connection electrode to be electrically connected to the first signal transmission line corresponding to the at least one data connection line arranged in the odd-numbered column, the first connection electrode is located in a second conductive layer, the second conductive layer and the third conductive layer are different layers, and the one data line arranged in the even-numbered column is electrically connected to the second signal transmission line corresponding thereto.

[0015] For example, in the display substrate provided by at least one of the embodiments of the present disclosure, the first connection electrode extends along a direction from the at least one data connection line arranged in the odd-numbered column to the one data line arranged in the even-numbered column at a position where the display area and the fan-out area meet.

[0016] For example, in the display substrate provided by at least one of the embodiments of the present disclosure, the data lines and the data connection lines are arranged on a third conductive layer, at least one of the data lines arranged on an odd column and one of the data connection lines arranged on an even column are arranged adjacently, the one of the data connection lines arranged on the even column is connected to the second signal transmission line corresponding to the one of the data connection lines arranged on the even column by a second connection electrode, the second connection electrode is arranged on a second conductive layer, and the second conductive layer and the third conductive layer are different layers, and the at least one of the data lines arranged on the odd column is electrically connected to the first signal transmission line corresponding to the at least one of the data lines arranged on the odd column.

[0017] For example, in the display substrate provided by at least one of the embodiments of the present disclosure, the second connection electrode extends along a direction from the one of the data connection lines arranged on the even column to the at least one of the data lines arranged on the odd column at a position where the display area and the fan-out area meet.

[0018] For example, in the display substrate provided by at least one of the embodiments of the present disclosure, the plurality of first signal transmission lines are arranged on even columns, and the plurality of second signal transmission lines are arranged on odd columns.

[0019] For example, in the display substrate provided by at least one of the embodiments of the present disclosure, a plurality of third signal transmission lines and a plurality of fourth signal transmission lines are arranged in the second direction at a position where the fan-out area and the pad area meet, the arrangement sequence of the sub-pixels connected to the plurality of third signal transmission lines and the plurality of fourth signal transmission lines is consistent with the arrangement sequence of the sub-pixels connected to the plurality of data lines and the plurality of data connection lines, a part of the plurality of third signal transmission lines is arranged on odd columns, another part of the plurality of third signal transmission lines is arranged on even columns, a part of the plurality of fourth signal transmission lines is arranged on odd columns, another part of the plurality of fourth signal transmission lines is arranged on even columns, and the plurality of third signal transmission lines and the first connection pads one-to-one correspond to sub-pixels of the same color, and the plurality of fourth signal transmission lines and the plurality of second connection pads one-to-one correspond to sub-pixels of the same color.

[0020] For example, in the display substrate provided by at least one of the embodiments of the present disclosure, the third signal transmission lines arranged on odd columns and the corresponding first signal transmission lines are electrically connected by first switching lines, the fourth signal transmission lines arranged on even columns and the corresponding second signal transmission lines are electrically connected by second switching lines, the first switching lines are arranged on a second conductive layer, the second switching lines are arranged on a first conductive layer, and the first conductive layer and the second conductive layer are different layers.

[0021] For example, in the display substrate provided by at least one of the embodiments of the present disclosure, the third signal transmission lines arranged in even-numbered columns and the corresponding first signal transmission lines are electrically connected by third transfer lines, and the fourth signal transmission lines arranged in odd-numbered columns and the corresponding second signal transmission lines are electrically connected by fourth transfer lines, and the third transfer lines and the fourth transfer lines are arranged on the second conductive layer.

[0022] For example, in the display substrate provided by at least one of the embodiments of the present disclosure, at least one of the third signal transmission lines arranged in odd-numbered columns and one of the fourth signal transmission lines arranged in even-numbered columns are arranged adjacent to each other, and the first transfer line connected to the at least one of the third signal transmission lines arranged in odd-numbered columns and the second transfer line connected to the one of the fourth signal transmission lines arranged in even-numbered columns intersect on a plane parallel to the main surface of the substrate.

[0023] For example, in the display substrate provided by at least one of the embodiments of the present disclosure, the fan-out area further comprises a semiconductor layer, a first gate layer, a second gate layer, an interlayer insulating layer, a first conductive layer, a planarization layer and a second conductive layer arranged in sequence; the first color sub-pixel comprises a green sub-pixel, and the second color sub-pixel comprises a red sub-pixel and a blue sub-pixel; a test unit is arranged in the fan-out area, the test unit comprises a first test switch transistor connected to the red sub-pixel and a second test switch transistor connected to the blue sub-pixel; a source electrode of the first test switch transistor is connected to a first test signal input end, a part of the second signal transmission lines are electrically connected to a drain electrode of the first test switch transistor, and a gate electrode of the first test switch transistor is electrically connected to a first part of the first conductive layer; a source electrode of the second test switch transistor is connected to a second test signal input end, another part of the second signal transmission lines are electrically connected to a drain electrode of the second test switch transistor, and a gate electrode of the second test switch transistor is electrically connected to a second part of the first conductive layer; and the first part and the second part of the first conductive layer are spaced apart from each other.

[0024] At least one of the embodiments of the present disclosure further provides a display device comprising the display substrate described in any one of the above. BRIEF DESCRIPTION OF DRAWINGS

[0025] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings described below only relate to some of the embodiments of the present disclosure, and are not a limitation on the present disclosure.

[0026] Figure 1 FIG. 1 is a schematic diagram of the arrangement of data signal lines in a display area and a fan-out area of a display substrate;

[0027] Figure 2 A schematic diagram of a planar structure of a display substrate provided for at least one embodiment of the present disclosure;

[0028] Figure 3 A schematic diagram of arrangement of data lines, data connection lines and signal transmission lines in a display area and a fan-out area of a display substrate provided for at least one embodiment of the present disclosure;

[0029] Figure 4 A layout of a display area and a fan-out area of a display substrate provided for at least one embodiment of the present disclosure;

[0030] Figure 5 A schematic diagram of a planar structure corresponding to a first metal layer in Figure 4 ;

[0031] Figure 6 A schematic diagram of a planar structure corresponding to a second metal layer in Figure 4 ;

[0032] Figure 7 A schematic diagram of a planar structure corresponding to an interlayer insulating layer disposed on a side of the second metal layer away from the substrate in Figure 4 ;

[0033] Figure 8 A schematic diagram of a planar structure corresponding to a first conductive layer in Figure 4 ;

[0034] Figure 9 A schematic diagram of a planar structure corresponding to a first planarization layer on a side of the first conductive layer away from the substrate in Figure 4 ;

[0035] Figure 10 A schematic diagram of a planar structure corresponding to a second conductive layer in Figure 4 ;

[0036] Figure 11 A schematic diagram of a planar structure corresponding to a second planarization layer on a side of the second conductive layer away from the substrate in Figure 4 ;

[0037] Figure 12 A schematic diagram of a planar structure corresponding to a third conductive layer in Figure 4 ;

[0038] Figure 13 A schematic diagram of a planar structure of a test unit in a display substrate provided for at least one embodiment of the present disclosure;

[0039] Figure 14 A schematic diagram of a planar structure of an active layer in Figure 13 ;

[0040] Figure 15 for Figure 13 A schematic diagram of the planar structure of the first metal layer in the middle;

[0041] Figure 16 for Figure 13 A schematic diagram of the planar structure of the second metal layer in the middle;

[0042] Figure 17 for Figure 13 The circuit diagram corresponding to the first test switch transistor of the red sub-pixel when it is turned on;

[0043] Figure 18 for Figure 13 The circuit diagram corresponding to the second test switch transistor of the blue sub-pixel when it is turned on;

[0044] Figure 19 for Figure 13 A schematic diagram showing the location of the third via structure in the interlayer insulating layer on the side of the second metal layer away from the active layer;

[0045] Figure 20 for Figure 13 A schematic diagram of the planar structure of the first conductive layer in the middle;

[0046] Figure 21 for Figure 13 Schematic diagram of the planar structure of the third planarization layer;

[0047] Figure 22 for Figure 13 Schematic diagram of the planar structure of the second conductive layer;

[0048] Figure 23 A schematic diagram of a planar structure at the junction of a pad area and a test unit in a display substrate, provided for at least one embodiment of the present disclosure;

[0049] Figure 24 for Figure 23 A schematic diagram of the planar structure of the first metal layer in the middle;

[0050] Figure 25 for Figure 23 A schematic diagram of the planar structure of the second metal layer in the middle;

[0051] Figure 26 for Figure 23 A schematic diagram showing the location of the fourth via structure in the interlayer insulating layer on the side of the second metal layer away from the active layer;

[0052] Figure 27 for Figure 23 A schematic diagram of the planar structure of the first conductive layer in the middle;

[0053] Figure 28 forFigure 23 A schematic view of a planar structure of a fourth planarization layer in the display substrate;

[0054] Figure 29 A schematic view of a planar structure of a second conductive layer in the display substrate; Figure 23

[0055] Figure 30 A schematic view of a planar structure of a test unit in the display substrate according to at least one of the embodiments of the present disclosure;

[0056] Figure 31 A layout of a display area and a fan-out area of a display substrate according to at least one of the embodiments of the present disclosure;

[0057] Figure 32 A schematic view of a planar structure of a first metal layer in the display substrate; Figure 31

[0058] Figure 33 A schematic view of a planar structure of a second metal layer in the display substrate according to at least one of the embodiments of the present disclosure; Figure 31

[0059] Figure 34 A schematic view of a planar structure of an interlayer insulating layer disposed on a side of the second metal layer away from the substrate in the display substrate; Figure 31

[0060] Figure 35 A schematic view of a planar structure of a first conductive layer in the display substrate; Figure 31

[0061] Figure 36 A schematic view of a planar structure of a first planarization layer on a side of the first conductive layer away from the substrate in the display substrate; Figure 31

[0062] Figure 37 A schematic view of a planar structure of a second conductive layer in the display substrate; Figure 31

[0063] Figure 38 A schematic view of a planar structure of a second planarization layer on a side of the second conductive layer away from the substrate in the display substrate; Figure 31

[0064] Figure 39 A schematic view of a planar structure of a third conductive layer in the display substrate; Figure 31

[0065] Figure 40 A schematic view of a planar structure of a test unit in the display substrate according to at least one of the embodiments of the present disclosure;

[0066] ​​​​​​​​​Figure 41 for Figure 40 A schematic diagram of the planar structure of the active layer;

[0067] Figure 42 for Figure 40 A schematic diagram of the planar structure of the first metal layer in the middle;

[0068] Figure 43 for Figure 40 A schematic diagram of the planar structure of the second metal layer in the middle;

[0069] Figure 44 for Figure 40 The circuit diagram corresponding to the first test switch transistor of the red sub-pixel when it is turned on;

[0070] Figure 45 for Figure 40 The circuit diagram corresponding to the second test switch transistor of the blue sub-pixel when it is turned on;

[0071] Figure 46 for Figure 31 An interlayer insulating layer is disposed in the second metal layer on the side away from the active layer;

[0072] Figure 47 for Figure 31 A schematic diagram of the planar structure of the first conductive layer in the middle;

[0073] Figure 48 for Figure 31 A schematic diagram of the planar structure of the third planarization layer;

[0074] Figure 49 for Figure 31 Schematic diagram of the planar structure of the second conductive layer;

[0075] Figure 50 A schematic diagram of a planar structure at the junction of a pad area and a test unit in a display substrate, provided for at least one embodiment of the present disclosure;

[0076] Figure 51 for Figure 50 A schematic diagram of the planar structure of the first metal layer in the middle;

[0077] Figure 52 for Figure 50 A schematic diagram of the planar structure of the second metal layer in the middle;

[0078] Figure 53 for Figure 50 A schematic diagram showing the location of the fourth via structure in the interlayer insulating layer on the side of the second metal layer away from the active layer;

[0079] Figure 54 for Figure 50 A schematic diagram of the planar structure of the first conductive layer in the middle;

[0080] Figure 55 For Figure 50 a schematic view of a planar structure of a fourth planarization layer in the embodiment;

[0081] Figure 56 For Figure 50 a schematic view of a planar structure of a second conductive layer in the embodiment; and

[0082] Figure 57 a schematic view of a display device provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0083] In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are some but not all of the embodiments of the present disclosure. Based on the described embodiments of the present disclosure, all other embodiments obtained by those of ordinary skill in the art without creative effort belong to the scope of the present disclosure.

[0084] Unless otherwise defined, technical or scientific terms used in the present disclosure should have the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. The terms “first”, “second”, and similar terms used in the present disclosure do not necessarily denote any ordinal, quantity, or importance, but are used to distinguish different components. The terms “include”, “contain”, and similar terms mean that the elements or objects before the terms encompass the elements or objects listed after the terms and equivalents thereof, and do not exclude other elements or objects. The terms “connected” or “coupled” and similar terms are not limited to physical or mechanical connections or couplings, but can include electrical connections or couplings, whether direct or indirect. The terms “upper”, “lower”, “left”, “right”, and the like are used only to indicate relative positions, and when the absolute positions of the described objects are changed, the relative positions may also be changed accordingly.

[0085] With the development of Active Matrix Organic Light Emitting Diode (AMOLED) display technology, consumers have increasingly higher demands for the display performance of OLED displays. Adopting a narrow bezel design is a crucial measure to improve the display performance of OLED devices, and a key technology for achieving narrow bezels is FIP (Fanout In Pixel) technology. In the structure of OLED displays using FIP technology to achieve narrow bezels, the arrangement order of the data signal lines connecting each sub-pixel is staggered. This arrangement can cause the data signal lines connecting the fan-out areas of sub-pixels of the same color to be located in different film layers. Due to the different parasitic capacitances between different film layers, the load on the data signal lines connecting the same color sub-pixels will also be different, resulting in different signal write amounts on the data signal lines connecting the same color sub-pixels. Ultimately, this leads to different display brightness in the OLED display, thus affecting the overall display quality of the OLED display.

[0086] For example, Figure 1 This is a schematic diagram showing the arrangement of data signal lines in the display area and fan-out area of ​​a display substrate, as shown below. Figure 1 As shown, the thinner traces within the display area (AA) are conventional first data signal lines, while the thicker traces are second data signal lines inserted using the FIP method. Solid lines in the fanout region represent third data signal lines disposed on the first gate metal layer, and dashed lines represent fourth data signal lines disposed on the second gate metal layer. The first and second gate metal layers are different metal layers. In the display area (AA), from left to right, the sub-pixels connected to the first data signal lines are red sub-pixel (R), green sub-pixel (G), blue sub-pixel (B), green sub-pixel (G), red sub-pixel (R), green sub-pixel (G), blue sub-pixel (B), green sub-pixel (G), red sub-pixel (R), green sub-pixel (G), blue sub-pixel (B), and green sub-pixel (G), i.e., 12 sub-pixels arranged in the order RGBGRGBGRGBG to form a cycle. The arrangement of the third data signal lines connected to each sub-pixel is also represented by symbols such as R, G, and B, referring to the actual arrangement of the data signal lines connected to the aforementioned sub-pixels of different colors. Figure 1In the display region (AA), two adjacent first data signal lines form a first group of first data signal line groups, two adjacent first data signal lines adjacent to the first group of first data signal line groups form a second group of first data signal line groups, one second data signal line is inserted between the first group of first data signal line groups and the second group of first data signal line groups, and at the position of the edge, no second data signal line is inserted between two adjacent groups of first data signal line groups. By inserting the second data signal line between the first group of first data signal line groups and the second group of first data signal line groups, the arrangement order of the data signal lines (including the third data signal lines and the fourth data signal lines) in the fanout region is changed, that is, in the display region (AA), the arrangement order of the first data signal lines is different from the arrangement order of the third data signal lines and the fourth data signal lines in the fanout region. For example, in the fanout region of FIG. 10, the third data signal lines arranged at odd positions are located on the first gate metal layer, and the fourth data signal lines arranged at even positions are located on the second gate metal layer, that is, from left to right, the first third data signal line connected with the green sub-pixel G, the third third data signal line connected with the green sub-pixel G, the fifth third data signal line connected with the blue sub-pixel B, the seventh third data signal line connected with the green sub-pixel G, the ninth third data signal line connected with the green sub-pixel G, and the eleventh third data signal line connected with the blue sub-pixel B are located on the first gate metal layer, the second fourth data signal line connected with the red sub-pixel R, the fourth fourth data signal line connected with the blue sub-pixel B, the sixth fourth data signal line connected with the green sub-pixel G, the eighth fourth data signal line connected with the red sub-pixel R, the tenth fourth data signal line connected with the red sub-pixel R, and the twelfth fourth data signal line connected with the green sub-pixel G are located on the second gate metal layer, and each 12 data signal lines are a period. That is, in the fanout region, the arrangement order of the 12 data signal lines is GRGBBGGRGRBG, the sixth fourth data signal line connected with the green sub-pixel G and the twelfth fourth data signal line connected with the green sub-pixel G are both located on the second gate metal layer, and the remaining third data signal lines connected with the green sub-pixel G are all located on the first gate metal layer. In this way, the data signal lines connected with the sub-pixels of the same color are located on different layers, so that the parasitic capacitances between different film layers are different, the loads of different film layers are different, the signal write amounts of the data signal lines connected with the sub-pixels of the same color are different, and finally the display brightness of the OLED display device is different, thereby affecting the display quality of the entire OLED display device. Figure 1

[0087] ​The inventors of the present disclosure notice that when the parasitic capacitances of the first gate metal layer and the second gate metal layer are different, the resistances of the third data signal line and the fourth data signal line respectively connected with the green sub-pixel G will be different, thereby causing the problem that the display brightness of the display device has differences, and therefore, it can be considered to design the data signal line jumper at the position close to the display area (AA) of the fanout region, that is, to change the arrangement order of the data signal line in the fanout region to adjust the data signal line connected with the sub-pixel of the same color to be located in the same film layer, so as to avoid the problem that the parasitic capacitances of the data signal lines connected with the sub-pixels of the same color are different when the data signal lines are in different film layers, thereby avoiding the problem that the loads of the data signal lines connected with the sub-pixels of the same color are different, that is, the data signal write amount is different, that is, the influence caused by the different parasitic capacitances can be avoided, and moreover, the subsequent connection order of the data signal line in the driving circuit will not be affected.

[0088] The display substrate includes a substrate, which is divided into a display area and a peripheral area surrounding the display area. The peripheral area includes a fan-out area adjacent to the display area and a pad area on a side of the fan-out area away from the display area. A plurality of sub-pixels arranged in a matrix are arranged in the display area. Each column of sub-pixels is connected to a data line. The fan-out area includes a connection area adjacent to the display area. Some data lines are directly connected to connection pads in the connection area, and the other data lines are connected to the connection pads in the connection area through data connection lines. The plurality of sub-pixels include a plurality of columns of first color sub-pixels and a plurality of columns of second color sub-pixels. The connection pads include a plurality of first connection pads and a plurality of second connection pads. The plurality of first connection pads are electrically connected to the plurality of columns of first color sub-pixels, and the plurality of second connection pads are electrically connected to the plurality of columns of second color sub-pixels. A plurality of first signal transmission lines and a plurality of second signal transmission lines are arranged at intervals in a position of the fan-out area close to the pad area. The plurality of first signal transmission lines are arranged in a first metal layer, and the plurality of second signal transmission lines are arranged in a second metal layer different from the first metal layer. The plurality of first signal transmission lines are electrically connected to the plurality of first connection pads one by one, and the plurality of second signal transmission lines are electrically connected to the plurality of second connection pads one by one. Two adjacent data connection lines and at least two data lines between the two adjacent data connection lines form a data line group. The connection pads connected to the at least two data lines in the data line group include at least one first connection pad and one second connection pad. In at least one data line group, the data lines connected to the second connection pads and the first signal transmission lines connected to the first connection pads have overlapping portions in the fan-out area in the orthographic projection on the substrate. Alternatively, the connection pads connected to the data lines and the data connection lines in the data line group include one first connection pad and one second connection pad. In at least one data line group, the data connection lines are electrically connected to the first connection pads or the second connection pads through connection electrodes. The connection electrodes and the data lines adjacent to the data connection lines have overlapping portions in the fan-out area in the orthographic projection on the substrate.

[0089] For example, by designing data line jumpers or data line and data connection line jumpers in the connection area adjacent to the display area (AA) in the fanout region, the display substrate can make the arrangement order of sub-pixels connected to data lines and data connection lines in the display area near the fanout region different from the arrangement order of sub-pixels connected to the first and second connection pads in the fanout region far from the display area. This allows the signal transmission lines (including the first and second signal transmission lines) connected to sub-pixels of the same color in the fanout region to be located in the same film layer, thereby avoiding different parasitic capacitances caused by the signal transmission lines connected to sub-pixels of the same color being in different film layers. This also avoids the problem of different data signal write amounts caused by different loads on the signal transmission lines connected to sub-pixels of the same color.

[0090] For example, Figure 2 This is a schematic diagram of a planar structure of a display substrate provided in at least one embodiment of the present disclosure, such as... Figure 2 As shown, the display substrate 100 includes a display area 101 and a peripheral area 110. The peripheral area 110 includes a fan-out area 104 adjacent to the display area 101 and a pad area 105 on the side of the fan-out area 104 away from the display area 101. The fan-out area 104 can be used as a test area, and a driving circuit is disposed in the pad area 105. The location where the fan-out area 104 and the display area 101 meet is the location shown in the connection area 102. The inventors of this disclosure have noted that at least at the location where the fan-out area 104 and the display area 101 meet, i.e., at the connection area 102, it is necessary to design data line jumpers or data line connection jumpers.

[0091] For example, the planar shape of the display area 101 can be rectangular, and the edges of the display area 101 can be rounded. Figure 2 In the plan view shown, the display area 101 has a rectangular shape with rounded corners, but the embodiments of this disclosure are not limited to this, and the display area can also be a rectangle or other irregular structure.

[0092] For example, this display area 101 is used to display images, although Figure 2The display region 101 is provided with a plurality of data lines, a plurality of scan lines, a plurality of horizontal transfer lines, a plurality of vertical transfer lines and a light-emitting control signal line. The vertical transfer lines can be arranged between two data lines adjacent to each other, and the vertical transfer lines can be arranged parallel to the data lines. A cathode power voltage for driving the light-emitting structure of the display substrate can be applied to the vertical transfer lines, and the vertical transfer lines are connected to the access end connecting the cathode power voltage to the display region to transmit the cathode power voltage to the corresponding sub-pixels. The plurality of horizontal transfer lines are connected to the data lines to transmit the data voltage to the data lines, and each data line is connected to a plurality of sub-pixels in the same column to provide the data signal or the data voltage to the corresponding sub-pixels in the display region. The data lines and the vertical transfer lines are located in the same film layer, the horizontal transfer lines and the vertical transfer lines are located in different film layers, and the horizontal transfer lines are electrically connected to the data lines through the first via structure to transmit the data voltage to the data lines. The scan lines can be arranged parallel to the light-emitting control signal lines and the horizontal transfer lines, and the scan lines, the data lines and the light-emitting control lines can be electrically connected to each sub-pixel. Each sub-pixel includes an organic light-emitting diode, a first transistor to an nth transistor and a storage capacitor.

[0093] For example, the peripheral region 110 can include a left peripheral region adjacent to the left side of the display region 101, a right peripheral region adjacent to the right side of the display region 101, an upper peripheral region adjacent to the upper side of the display region 101, and a lower peripheral region adjacent to the lower side of the display region 101. Since the data pads and the gate pads for connecting the driving components are arranged in the lower peripheral region, the lower peripheral region can have a larger area. For example, the lower peripheral region has a width greater than the widths of the upper peripheral region, the left peripheral region and the right peripheral region. It should be noted that the widths of the upper peripheral region, the lower peripheral region, the left peripheral region and the right peripheral region respectively refer to the minimum distances between the edges adjacent to the display region and the edges farthest away from the display region of the upper peripheral region, the lower peripheral region, the left peripheral region and the right peripheral region. Hereinafter, the peripheral region refers to the lower peripheral region arranged with the data pads and the gate pads unless otherwise specified.

[0094] For example, Figure 2 The lower peripheral region is mainly shown in FIG. 1, and the lower peripheral region includes a fan-out area 104 adjacent to the display region 101 and a pad area 105 on the side of the fan-out area 104 away from the display region 101, and the data pads and the gate pads are arranged in the pad area 105. The peripheral lines for transmitting the OLED cathode power voltage (for example, a low power voltage) are arranged in the lower peripheral region, and the peripheral lines can be connected to each of the vertical transfer lines. The chip of the data driving component can be connected to the data pads, for example, the driving substrate including the timing control component can be connected to the gate pads.

[0095] For example, Figure 3A schematic diagram of arrangement of data lines, data connection lines and signal transmission lines in a display area and a fan-out area of a display substrate is provided for at least one embodiment of the present disclosure, Figure 4 A layout of a display area and a fan-out area of a display substrate is provided for at least one embodiment of the present disclosure, for example, as shown in Figure 2 、 Figure 3 and Figure 4 , the display substrate 100 comprises a substrate 111, the substrate 111 comprises a display area 101 and a peripheral area 110 surrounding the display area 101, the peripheral area 110 comprises a fan-out area 104 adjacent to the display area 101 and a pad area 105 on a side of the fan-out area 104 away from the display area 101; a plurality of sub-pixels 112 arranged in a matrix are arranged in the display area 101, the plurality of sub-pixels 112 are arranged to form a plurality of columns of sub-pixels, and each column of sub-pixels 112 is electrically connected to one data line 113; the fan-out area 104 comprises a connection area 114 adjacent to the display area 101, part of the data lines 113 are directly connected to connection pads 127 in the connection area 114, and the other part of the data lines 113 are connected to the connection pads 127 in the connection area 114 through data connection lines 128; the plurality of sub-pixels 112 comprise a plurality of columns of first color sub-pixels 112A and a plurality of columns of second color sub-pixels 112B, the connection pads 127 comprise a plurality of first connection pads 127A and a plurality of second connection pads 127B, the plurality of first connection pads 127A are electrically connected to the plurality of columns of first color sub-pixels 112A, and the plurality of second connection pads 127B are electrically connected to the plurality of columns of second color sub-pixels 112B; a plurality of first signal transmission lines 129 and a plurality of second signal transmission lines 130 are arranged at intervals in a position of the fan-out area 104 close to the pad area 105, the plurality of first signal transmission lines 129 are arranged in a first metal layer 115, and the plurality of second signal transmission lines 130 are arranged in a second metal layer 116 different from the first metal layer 115; the plurality of first signal transmission lines 129 are electrically connected to the plurality of first connection pads 127A one by one, and the plurality of second signal transmission lines 130 are electrically connected to the plurality of second connection pads 127B one by one, at least two data lines 113 between two adjacent data connection lines 128 form a data line group 13, the connection pads 127 connected to the at least two data lines 113 in the data line group 13 comprise at least one first connection pad 127A and one second connection pad 127B, and in at least one data line group 13, the data line 113 connected to the second connection pad 127B and the first signal transmission line 129 connected to the first connection pad 127A have overlapping parts in the orthographic projection on the substrate 111.

[0096] For example, in combination with Figure 2 ,Figure 3 and Figure 4 As shown in FIG. 1, the plurality of data lines 113 and the plurality of data connection lines 128 are arranged on the substrate 111, extend in the first direction X in the display area 101 and are arranged in the second direction Y which is perpendicular to the first direction X, the plurality of data lines 113 and the plurality of data connection lines 128 extend from the display area 101 to the fan-out area 104, and at the position of the display area 101 close to the fan-out area 104, part of the plurality of data lines 113 are arranged in the odd-numbered columns, and the other part are arranged in the even-numbered columns, part of the plurality of data connection lines 128 are arranged in the even-numbered columns, and the other part are arranged in the odd-numbered columns; the fan-out area 104 includes a connection area 114 which is adjacent to the display area 101, and in the other areas of the fan-out area 104 except the connection area 114, the plurality of first signal transmission lines 129 and the plurality of second signal transmission lines 130 are arranged in the second direction Y, and one of the plurality of first signal transmission lines 129 and the plurality of second signal transmission lines 130 are arranged in the odd-numbered columns, and the other of the plurality of first signal transmission lines 129 and the plurality of second signal transmission lines 130 are arranged in the even-numbered columns, the plurality of first signal transmission lines 129 are arranged in the first metal layer 115, and the plurality of second signal transmission lines 130 are arranged in the second metal layer 116 which is in a different layer from the first metal layer 115. This design can make the arrangement order of the sub-pixels connected with the data lines 113 and the data connection lines 128 at the position of the display area 101 close to the fan-out area 104 different from the arrangement order of the sub-pixels connected with the plurality of first signal transmission lines 129 and the plurality of second signal transmission lines 130 at the position of the fan-out area 104 away from the display area 101, so as to adjust the plurality of first signal transmission lines 129 or the plurality of second signal transmission lines 130 connected with the sub-pixels of the same color to be in the same film layer, to avoid the problem of different loads of the plurality of first signal transmission lines 129 or the plurality of second signal transmission lines 130 connected with the sub-pixels of the same color caused by different parasitic capacitances of the plurality of first signal transmission lines 129 or the plurality of second signal transmission lines 130 connected with the sub-pixels of the same color in different film layers.

[0097] For example, as shown in FIG. 1, Figure 3As shown, the data lines 113 and the data connection lines 128 are arranged in the third conductive layer, and the connection pads 127 connected to two adjacent data lines 113 in one data line group 13 are respectively a first connection pad 127A and a second connection pad 127B; the first data line 113A (for example, the third data line connected to the red sub-pixel) in the two adjacent data lines 113 in one data line group 13 located in the odd column crosses and connects with the first signal transmission line 129 connected to the second data line 113B (for example, the fourth data line connected to the green sub-pixel) located in the even column adjacent to the first data line 113A. For example, the second data line 113B located in the even column extends to the side close to the first data line 113A adjacent to it at the position of the display area 101 and the fan-out area 104 to be electrically connected to the corresponding first signal transmission line 129.

[0098] For example, in one example, the first color sub-pixel 112A is a green sub-pixel G, and the second color sub-pixel 112B is a red sub-pixel R or a blue sub-pixel B. For example, as shown in FIG. 1, the data line 113 connected to the green sub-pixel G is the third data line, and the data line 113 connected to the red sub-pixel R is the fourth data line. Figure 3 As shown, along the first direction X at the position close to the fan-out area 104 of the display area 101, the data lines 113 and the data connection lines 128 are sequentially arranged as a whole along the second direction Y, and the data connection lines 128 connected to the green sub-pixel G (the first data connection line), the data lines 113 connected to the red sub-pixel R (the first data line), the data lines 113 connected to the green sub-pixel G (the second data line), the data connection lines 128 connected to the blue sub-pixel B (the second data connection line), the data lines 113 connected to the blue sub-pixel B (the third data line), the data lines 113 connected to the green sub-pixel G (the fourth data line), the data connection lines 128 connected to the green sub-pixel G (the third data connection line), the data lines 113 connected to the red sub-pixel R (the fifth data line), the data lines 113 connected to the green sub-pixel G (the sixth data line), the data connection lines 128 connected to the red sub-pixel R (the fourth data connection line), the data lines 113 connected to the blue sub-pixel B (the seventh data line), and the data lines 128 connected to the green sub-pixel G (the eighth data line) are sequentially arranged. That is, in this example, the first data connection line, the second data line, the third data line, the third data connection line, the sixth data line, and the seventh data line are arranged in the odd column, and the first data line, the second data connection line, the fourth data line, the fifth data line, the fourth data connection line, and the eighth data line are arranged in the even column.

[0099] It should be noted that the data connection line is inserted in the FIP mode, so that the data line connected to the data connection line is connected to the corresponding connection pad through the data connection line.

[0100] For example, in one example, the first color sub-pixel 112A is a green sub-pixel G, and the second color sub-pixel 112B is a red sub-pixel R or a blue sub-pixel B. For example, as shown in FIG. 1, the data line 113 connected to the green sub-pixel G is the third data line, and the data line 113 connected to the red sub-pixel R is the fourth data line.Figure 3 In the fanout region 104, except for the connection region 114, the first signal transmission lines 129 are arranged in odd columns, and the second signal transmission lines 130 are arranged in even columns, the plurality of first signal transmission lines 129 and the plurality of first connection pads 127A are electrically connected one by one, and are electrically connected to the plurality of first color sub-pixels 112A one by one; the plurality of second signal transmission lines 130 and the plurality of second connection pads 127B are electrically connected one by one, and are electrically connected to the plurality of second color sub-pixels 112B one by one, and the plurality of first signal transmission lines 129 are arranged in the first metal layer 115, and the plurality of second signal transmission lines 130 are arranged in the second metal layer 116 which is different from the first metal layer 115. That is, the display substrate is designed by arranging the data lines and the data connection lines in the connection region of the fanout region adjacent to the display region (AA), so that the arrangement order of the sub-pixels connected to the data lines and the data connection lines at the position close to the fanout region of the display region is different from the arrangement order of the sub-pixels connected to the plurality of first signal transmission lines and the plurality of second signal transmission lines at the position away from the display region of the fanout region, so as to adjust the plurality of first signal transmission lines or the plurality of second signal transmission lines connected to the sub-pixels of the same color to the same film layer, to avoid the problem that the plurality of first signal transmission lines or the plurality of second signal transmission lines connected to the sub-pixels of the same color have different parasitic capacitances when they are in different film layers, and further avoid the problem that the plurality of first signal transmission lines or the plurality of second signal transmission lines connected to the sub-pixels of the same color have different loads, resulting in different data signal write amounts.

[0101] It should be noted that the first data line to the eighth data line refers to the order of the data lines in the same row as the data connection lines, and the first data connection line to the fourth data connection line refers to the order of the data connection lines inserted in the FIP mode. The first data line to the eighth data line and the first data connection line to the fourth data connection line are respectively taken from the data lines and the data connection lines, only for ordering to facilitate description, and are not other data lines in addition to the data lines and the data connection lines.

[0102] It should be further noted that the data line jumper refers to exchanging the positions of two adjacent data lines, exchanging the data line in the odd column to the position in the even column, exchanging the data line in the even column to the position in the odd column, and still maintaining the adjacent position relationship, which can be achieved by crossing the data lines in different layers at the corresponding position of the connection region in the plane.

[0103] For example, as shown in FIG. 1, the data line jumper is arranged in the connection region 114 of the fanout region 104, and the data line jumper is arranged in the connection region 114 of the fanout region 104. Figure 4As shown, in the fan-out region 104, excluding the connection region 114, the region is described in terms of 12 signal transmission lines arranged sequentially along the second direction Y as one cycle. These 12 signal transmission lines in one cycle include multiple first signal transmission lines 129 and multiple second signal transmission lines 130. Figure 4 In this configuration, the multiple first signal transmission lines 129 are all arranged in odd-numbered columns, and the multiple second signal transmission lines 130 are all arranged in even-numbered columns.

[0104] For example, such as Figure 4 As shown, in the fan-out region 104, along the second direction Y, the following are arranged sequentially: a first connecting pad 127A connected to the green sub-pixel G, a second connecting pad 127B connected to the red sub-pixel R, a first connecting pad 127A connected to the green sub-pixel G, a second connecting pad 127B connected to the blue sub-pixel B, a first connecting pad 127A connected to the green sub-pixel G, a second connecting pad 127B connected to the blue sub-pixel B, a first connecting pad 127A connected to the green sub-pixel G, a second connecting pad 127B connected to the red sub-pixel R, and a first connecting pad 127B connected to the green sub-pixel G. 27A, a second connecting pad 127B connected to the red sub-pixel R, a first connecting pad 127A connected to the green sub-pixel G, and a second connecting pad 127B connected to the blue sub-pixel B. Multiple first connecting pads 127A are electrically connected to multiple first signal transmission lines 129 in a one-to-one correspondence. Multiple second connecting pads 127B are electrically connected to multiple second signal transmission lines 130 in a one-to-one correspondence. This allows multiple first signal transmission lines 129 to be placed in the first metal layer 115, and multiple second signal transmission lines 130 to be placed in a second metal layer 116 located on a different layer than the first metal layer 115. This allows the signal transmission lines connected to sub-pixels of the same color to be located in the same film layer, avoiding different parasitic capacitances caused by signal transmission lines connected to sub-pixels of the same color being in different film layers. This also avoids the problem of different data signal write amounts due to different loads on the signal transmission lines connected to sub-pixels of the same color.

[0105] For example, combining Figure 2 and Figure 4 The display area 101 may include a plurality of thin-film transistors, at least one of which may be a dual-gate structure. For example, the first thin-film transistor includes a first gate and a second gate, while the other thin-film transistors each have only one gate. The first metal layer 115 may be formed in the same layer as the first gate of the first thin-film transistor, and the second metal layer 116 may be formed in the same layer as the second gate of the first thin-film transistor. In the direction perpendicular to the main surface of the substrate 111, although in Figure 4Not shown, an insulating layer is also provided between the first metal layer 115 and the second metal layer 116, which can prevent electrical communication between data lines 113 that have overlapping portions in the connection area 114 and in a plane parallel to the main surface of the substrate 111.

[0106] For example, such as Figure 4 As shown, when the parasitic capacitance of the first metal layer 115 and the second metal layer 116 changes, the resistance of the first signal transmission line 129 connected to the green sub-pixel G will differ, resulting in a difference in the display brightness of the display device. Therefore, in the embodiments of this disclosure, the third data line 113 connected to the blue sub-pixel B and the fourth data line 113 connected to the green sub-pixel G are connected by jumpers in the connection area 114, and the seventh data line 113 connected to the blue sub-pixel B and the eighth data line 113 connected to the green sub-pixel G are connected by jumpers, so that the green sub-pixel G is still connected to the first signal transmission line 129 located in the first metal layer 115, and the blue sub-pixel B is still connected to the second signal transmission line 130 located in the second metal layer 116. After connection, in the fan-out area 104 other than the connection area 114, the arrangement order of the sub-pixels connected to multiple signal transmission lines is GRGBGB GRGRGB, so that the first signal transmission lines 129 connected to the green sub-pixel G are all arranged in odd-numbered columns (i.e., Figure 4 The first signal transmission line 129 and the second signal transmission line 130 connected to the sub-pixel are arranged as a whole and located in the first metal layer 115. The second signal transmission line 130 connected to the blue sub-pixel B or the red sub-pixel R are all arranged in even-numbered columns. Figure 4 The first signal transmission line 129 and the second signal transmission line 130 connected to the sub-pixel are arranged as a whole and located in the second metal layer 116, thereby avoiding the influence of parasitic capacitance.

[0107] For example, Figure 5 For corresponding Figure 4 A schematic diagram of the planar structure of the first metal layer in the middle, combined with Figure 4 and Figure 5 As shown, in the areas of the fan-out region 104 other than the connection region 114, the multiple first signal transmission lines 129 in the first metal layer 115 all have a zigzag shape. Each of the multiple first signal transmission lines 129 includes a vertical portion extending along the first direction X, and then a diagonal portion extending along a direction at an obtuse angle to the first direction X. This diagonal portion causes the final first signal transmission line 129 to shrink towards the middle region. The vertical portions of the multiple first signal transmission lines 129 are evenly distributed in the second direction Y, so that the signal transmitted to the first signal transmission lines 129 is more uniform.

[0108] For example,Figure 6 The at least one embodiment of this disclosure provides a corresponding Figure 4 A schematic diagram of the planar structure of the second metal layer in the middle, combined with Figure 4 and Figure 6 In the fan-out region 104, excluding the areas involving jumper locations, multiple second signal transmission lines 130 in the second metal layer 116 all have a zigzag shape. Each of these multiple second signal transmission lines 130 includes a vertical portion extending along the first direction X, followed by a diagonal portion extending at an obtuse angle to the first direction X. This diagonal portion causes the final second signal transmission line 130 to contract towards the central region. The vertical portions of these multiple second signal transmission lines 130 are evenly distributed in the second direction Y to ensure more uniform signal transmission to the second signal transmission lines 130. (Ignore) Figure 6 The leftmost second signal transmission line that is not connected to a sub-pixel, along the second direction Y, the vertical length of the third second signal transmission line 130 and the sixth second signal transmission line 130 is greater than the vertical length of the other second signal transmission lines 130. This design is to realize the above-mentioned jumper design of adjacent first signal transmission lines 129 and second signal transmission lines 130, and this design does not increase the process steps.

[0109] For example, Figure 7 For corresponding Figure 4 A schematic diagram of the planar structure of the interlayer insulating layer disposed on the side of the second metal layer away from the substrate, as shown in the figure. Figure 7 As shown, the interlayer insulating layer 117 is provided with a plurality of first hole structures 117A, which can realize the electrical connection between the structure disposed on the side of the interlayer insulating layer 117 away from the substrate 111 and the structure disposed on the side of the interlayer insulating layer 117 close to the substrate 111.

[0110] For example, Figure 8 For corresponding Figure 4 A schematic diagram of the planar structure of the first conductive layer in the image, as shown below. Figure 8 As shown, the connection pad 127 includes a double-layer structure. The first conductive layer 118 includes a plurality of first connectors 118A, which can serve as the layer structure of the connection pad 127 near the substrate 111. Together with the second connectors mentioned later, they work to electrically connect the plurality of data lines 113 or data connection lines 128 located in the display area 101 to the corresponding plurality of first signal transmission lines 129 or second signal transmission lines 130 located in the fan-out area 104. The material of the first conductive layer 118 can be a conductive metal or a conductive metal oxide, as long as a stable connection relationship can be achieved. The embodiments disclosed herein do not limit this.

[0111] For example, Figure 9For corresponding to the planar structure schematic diagram of the first planarization layer on the side of the first conductive layer away from the substrate in Figure 4 , as shown in Figure 9 , a plurality of second hole structures 119A are arranged in the first planarization layer 119, and the plurality of second hole structures 119A are used to connect the first conductive layer 118 and the second conductive layer located on the side of the first planarization layer 119 away from the substrate 111.

[0112] For example, Figure 10 For corresponding to the planar structure schematic diagram of the second conductive layer in Figure 4 , as shown in Figure 10 , the plurality of second connecting pieces 120G on the second conductive layer 120 can be used as the layer structure of the connecting pad 127 away from the substrate 111, and the plurality of second connecting pieces 120G and the first connecting piece 118A are used to connect the data line 113 or the plurality of data connecting lines 128 and the corresponding plurality of first signal transmission lines 129 or the plurality of second signal transmission lines 130.

[0113] For example, Figure 11 For corresponding to the planar structure schematic diagram of the second planarization layer on the side of the second conductive layer away from the substrate in Figure 4 , as shown in Figure 11 , a plurality of third hole structures 121A are arranged in the second planarization layer 121, and the plurality of third hole structures 121A are used to connect the second conductive layer 120 and the third conductive layer located on the side of the second planarization layer 121 away from the substrate 111.

[0114] For example, Figure 12 For corresponding to the planar structure schematic diagram of the third conductive layer in Figure 4 , as shown in Figure 12 , the third conductive layer 122 has a plurality of data lines 113 and a plurality of data connecting lines 128. As can be seen from Figure 12 , along the second direction Y, the plurality of data lines 113 and the plurality of data connecting lines 128 are sorted respectively, and in order, they are the first data connecting line, the first data line, the second data line, the second data connecting line, the third data line, the fourth data line, the third data connecting line, the fifth data line, the sixth data line, the fourth data connecting line, the seventh data line and the eighth data line, that is, the first data connecting line 128 refers to the data connecting line arranged in the first position among the 4 data connecting lines, that is, the first data connecting line 128, and the second data connecting line 128 to the fourth data connecting line 128 have similar definitions; the first data line 113 refers to the data line arranged in the first position among the 8 data lines, that is, the first data line 113, and the second data line 113 to the eighth data line 113 have similar definitions.

[0115] For example, as shown in Figure 12 the first data connection line 128 extends along the first direction X; the first data line 113 extends along the first direction X first, and then extends obliquely to the lower right corner; the second data line 113 extends along the first direction X first, and then extends obliquely to the lower left corner; the second data connection line 128 extends along the first direction X; the third data line 113 extends along the first direction X first, and then extends along the second direction Y to form a hook-shaped or non-closed quadrilateral; the fourth data line 113 extends along the first direction X first, and then extends along the direction opposite to the second direction; the third data connection line 128, the fifth data line 113, the sixth data line 113, the fourth data connection line 128, the seventh data line 113 and the eighth data line 113 repeat the shapes of the first data connection line 128, the first data line 113, the second data line 113, the second data connection line 128, the third data line 113 and the fourth data line 113 in sequence, and details are not described herein.

[0116] For example, in one example, as shown in Figure 2 , Figure 4 and Figure 12 , the third data line 113 and the seventh data line 113 extend to the side close to the pad area 105 first in the fan-out area 104, and then extend to the directions of the fourth data line 113 and the eighth data line 113 adjacent thereto respectively to form an “L”-shaped structure or an inverted “L”-shaped structure; the fourth data line 113 extends to the direction close to the third data line 113 first, and then extends to the side close to the pad area 105 to form a non-closed quadrilateral with the third data line 113, i.e., the right side is not closed to have an opening; the eighth data line 113 extends to the direction close to the seventh data line 113 first, and then extends to the side close to the pad area 105 to form a non-closed quadrilateral with the seventh data line 113, i.e., the right side is not closed to have an opening.

[0117] For example, as shown in Figure 4 , the first data line 113A (for example, the third data line connected with the red sub-pixel) in the odd column extends to the side close to the pad area 105 first in the fan-out area 104, and then extends to the direction of the second data line 113B (for example, the fourth data line connected with the green sub-pixel) in the even column adjacent thereto to form an “L”-shaped structure or an inverted “L”-shaped structure; the second data line 113B in the even column extends to the direction close to the first data line 113A first in the fan-out area 104, and then extends to the side close to the pad area 105 to form a non-closed quadrilateral with the first data line 113A.

[0118] For example, as shown in Figure 2 ,Figure 4 and Figure 12 As shown, the third data line 113 and the seventh data line 113 connected to the blue sub-pixel B extend first along the second direction Y, and then along the first direction X, thus forming an L-shape. Correspondingly, the fourth data line 113 and the eighth data line 113 connected to the green sub-pixel G extend in the opposite direction to the second direction Y. Alternatively, the third data line 13 and the seventh data line 113 connected to the blue sub-pixel B can extend first in the opposite direction to the second direction Y, and then along the first direction X to form an inverted L-shape. Correspondingly, the fourth data line 113 and the eighth data line 113 connected to the green sub-pixel G extend in the second direction Y.

[0119] For example, combining Figure 4 and Figure 12 As shown, the third data line 113 connected to the blue sub-pixel B crosses the first signal transmission line 129 connected to the adjacent fourth data line 113, and is electrically connected to the second signal transmission line 130 corresponding to the third data line 113. The fourth data line 113 extends to one side of the adjacent third data line 113 at the junction of the display area 101 and the fan-out area 104 to be electrically connected to the corresponding first signal transmission line 129. That is, the third data line 113 intersects with the first signal transmission line 129 connected to the adjacent fourth data line 113, but the fourth data line 113 does not intersect with the first signal transmission line 129 electrically connected to the adjacent third data line 113. For example, the third data line 113 crosses and connects to the first signal transmission line 129 connected to the fourth data line 113, so that the third data line 113 connected to the blue sub-pixel B is electrically connected to the corresponding second signal transmission line 130, and the fourth data line 113 extends in the direction opposite to the second direction Y to be electrically connected to the corresponding first signal transmission line 129, that is, the first signal transmission line 129 is also connected to the green sub-pixel G. For example, in Figure 4In the third embodiment, the third data line 113 is routed from a position close to the wiring area of the display area to the connection pad through the third conductive layer, and the fourth data line 113 is connected to the connection pad from a position away from the wiring area of the display area through the third conductive layer, that is, the third data line 113 and the first signal transmission line 129 connected to the fourth data line 113 cross each other, but the fourth data line 113 and the second signal transmission line 130 connected to the third data line 113 do not cross each other. Since only the third data line 113 located in the third conductive layer and connected to the blue sub-pixel B overlaps with the first signal transmission line 129 connected to the green sub-pixel G, but the fourth data line 113 connected to the green sub-pixel G does not overlap with the second signal transmission line 130 connected to the blue sub-pixel B, the parasitic capacitance can be reduced, and the capacitance difference between different signal film layers caused by the jumper can be minimized.

[0120] For example, as shown in FIG. 13A, in the plane parallel to the main surface of the substrate 111, the first data line 113A (for example, the third data line connected to the red sub-pixel) and the first signal transmission line 129 connected to the second data line 113B (for example, the fourth data line connected to the green sub-pixel) cross each other; the second data line 113B and the second signal transmission line 130 connected to the first data line 113A do not cross each other. Figure 4

[0121] It should be noted that the above-mentioned crossing of the third data line across the first signal transmission line connected to the fourth data line refers to the overlapping part of the third data line and the first signal transmission line connected to the fourth data line in the plane parallel to the main surface of the substrate 111, that is, the orthographic projection of the third data line on the substrate and the orthographic projection of the first signal transmission line connected to the fourth data line on the substrate have overlapping parts.

[0122] The design of the seventh data line 113 connected to the blue sub-pixel B and the eighth data line 113 connected to the green sub-pixel G can refer to the related design of the third data line 113 and the fourth data line 113 described above, and will not be repeated here.

[0123] For example, Figure 13 A planar structure schematic diagram of a test unit in a display substrate provided by at least one embodiment of the present disclosure is shown in FIG. 13B. Figure 13 ​As shown, in the second direction Y, in the test unit, a plurality of first signal transmission lines 129 connected with the first color sub-pixels 112A and a plurality of second signal transmission lines 130 connected with the second color sub-pixels 112B are arranged alternately in sequence, the first color sub-pixels are green sub-pixels G, and the second color sub-pixels 112B include blue sub-pixels B or red sub-pixels R. There are a plurality of thin film transistors in the test unit, each thin film transistor includes an active layer, a gate, a source and a drain, and the thin film transistor is a test switch transistor.

[0124] For example, Figure 14 For example, Figure 13 The planar structure of the active layer in the first metal layer is shown in FIG. 12B, and the active layer is described in combination with Figure 14 As shown, the material of the active layer 123 is polysilicon, and the active layer 123 is arranged in a plurality of rows and a plurality of columns. Figure 14 The structure of 12 complete active layers is shown in FIG. 12A, and one complete active layer 123 is shown in each rectangular dashed frame, that is, the 12 complete active layers 123 correspond to two repeating units, and the six active layers 123 arranged in the first row are the active layers of the test switch transistors arranged in the first row corresponding to three blue sub-pixels B and three red sub-pixels R, and the six active layers 123 arranged in the second row are the active layers of the test switch transistors arranged in the second row corresponding to three blue sub-pixels B and three red sub-pixels R. Hereinafter, only the six active layers 123 arranged in the first row are described as one repeating unit.

[0125] For example, Figure 15 For example, Figure 13 The planar structure of the first metal layer in the first metal layer is shown in FIG. 12B, and the active layer is described in combination with Figure 13 , Figure 15 and Figure 3 As shown, the first metal layer 115 includes a first part 115A connected with the first color sub-pixels and a second part 115B serving as the gate of the test switch transistor. The first color sub-pixels 112A and the second color sub-pixels 112B, although not shown in Figure 13 and Figure 15 , can be referred to as 112A and 112B in Figure 3 The second color sub-pixels 112B include blue sub-pixels B and red sub-pixels R, and in the test phase, the test switch transistor is mainly used to control the blue sub-pixels B and the red sub-pixels R not to be turned on at the same time, that is, to make only one of the blue sub-pixels B and the red sub-pixels R in the on state and the other in the off state at different times, so as to avoid the problem of color mixing when the light is emitted, so that the purity of the emitted light is not high and the color deviation phenomenon occurs.

[0126] It should be noted that the first part 115A in Figure 15 is also Figure 13The first signal transmission line 129 in the middle.

[0127] For example, combining Figure 13 and Figure 15 The second portion 115B of the first metal layer 115 includes a main body portion 115B1 and a branch portion 115B2. The main body portion 115B1 is used to connect to the first sub-part 118C of the first conductive layer 118, and the branch portion 115B2 serves as the gate of a test switching transistor. The first sub-part 118C of the first conductive layer provides a gate signal voltage for the test switching transistor. The structure of the first conductive layer 118 will be described in detail when describing the first conductive layer 118.

[0128] For example, combining Figure 13 and Figure 15 The arrangement order of the sub-pixels connected to the first signal transmission line 129 and the second signal transmission line 130 in the first row is: green sub-pixel G, red sub-pixel R, green sub-pixel G, blue sub-pixel B, green sub-pixel G, blue sub-pixel B, green sub-pixel G, red sub-pixel R, green sub-pixel G, red sub-pixel R, green sub-pixel G, and blue sub-pixel B. This arrangement order of the sub-pixels connected to the first signal transmission line 129 and the second signal transmission line 130 in the first row... Figure 3 In the fan-out area 104, except for the connection area 114, the sub-pixels connected to the first signal transmission line 129 and the second signal transmission line 130 are arranged in the same order.

[0129] For example, Figure 16 for Figure 13 A schematic diagram of the planar structure of the second metal layer, combined with Figure 13 and Figure 16 As shown, the open transistor ultimately transmits the test signal to the second metal layer 116. Since the first signal transmission line 129 connected to the first color sub-pixel 112A and the second signal transmission line 130 connected to the second color sub-pixel 112B are located in different metal layers, the open transistor can control the lighting status of the first color sub-pixel 112A and the second color sub-pixel 112B respectively.

[0130] It should be noted that, Figure 13 The second signal transmission line 130 is located in Figure 16 On the second metal layer 116 shown, Figure 16 The long strip shown corresponds to Figure 13 The second signal transmission line 130 in the middle.

[0131] It should be noted that although the blue sub-pixel B in the first row and the red sub-pixel R in the second row are connected to the same second signal transmission line, or although the red sub-pixel B in the first row and the blue sub-pixel B in the second row are connected to the same second signal transmission line, there will be no signal crosstalk problem due to the control of the test switch transistor.

[0132] For example, Figure 17 for Figure 13 The circuit diagram corresponding to the first test switch transistor of the red sub-pixel when it is turned on. Figure 18 This is a circuit diagram showing the second test switch transistor corresponding to the blue sub-pixel when it is turned on. (Example:) Figure 17 and 18 As shown, when testing a red monochrome image, the red subpixel needs to be lit, and the blue subpixel needs to be off; similarly, when testing a blue monochrome image, the blue subpixel needs to be lit, and the red subpixel needs to be off. For example, in one example, the input signal voltages are as follows: red subpixel switch signal (SWR): -7V, blue subpixel switch signal (SWB): +7V, red subpixel source signal (DR): 3V, blue subpixel source signal (DB): 7V. For the first test switch transistor corresponding to the red subpixel, applying a -7V SWR signal turns it on, inputting a 3V DR signal into the second signal transmission line. At this time, when the applied SWB voltage is +7V, the second test switch transistor corresponding to the blue subpixel is off, and the DB signal cannot be input to the second signal transmission line. Therefore, the voltage on the second signal transmission line is 3V, and the red subpixel is lit. For example, in another example, for the blue sub-pixel, when a -7V SWB signal is applied to the second test switching transistor corresponding to the blue sub-pixel, the second test switching transistor of the blue sub-pixel is turned on, and at this time, a 7V DB signal is input to the second signal transmission line; at this time, when the applied SWR voltage is +7V, the first test switching transistor corresponding to the red sub-pixel is turned off, the DR signal cannot be input to the second signal transmission line, therefore, the voltage on the second signal transmission line is 7V, and the corresponding blue sub-pixel is lit.

[0133] For example, Figure 19 for Figure 13 A schematic diagram showing the location of the third via structure in the interlayer insulating layer on the side of the second metal layer away from the active layer, as shown below. Figure 19 As shown, the interlayer insulating layer 124 is provided with a plurality of third via structures 124A. Through the third via structures 124A, the first conductive layer and other structures disposed on the side of the second metal layer 116 away from the active layer can be electrically connected to the first metal layer 115, the second metal layer 116 and the active layer.

[0134] For example, Figure 20 For example, Figure 13 For example, Figure 13 For example, Figure 15 For example, Figure 20 For example, For example,

[0135] For example, Figure 13 For example, Figure 15 For example, Figure 20 For example, For example,

[0136] For example, Figure 13 For example, Figure 15 For example, Figure 20In one repeat unit, the first conductive layer 118 includes two parallel first conductive layer first subparts 118C. For example, the first conductive layer first subparts 118C on the upper side are each connected to the gate of the first test switch transistor that controls the red subpixel to be lit, and the first conductive layer first subparts 118C on the lower side are each connected to the gate of the second test switch transistor that controls the blue subpixel to be lit, so that the gate driving voltage can be applied to the first test switch transistor that controls the red subpixel to be lit and the second test switch transistor that controls the blue subpixel to be lit, respectively, so that the blue subpixel and the red subpixel are lit in different stages, so as not to cause the color mixing of red light and blue light.

[0137] For example, Figure 21 For example, Figure 13 For example, Figure 13 , Figure 15 and Figure 21 The third planarization layer 125 is provided with a plurality of grooves, which can realize the electrical connection between the first conductive layer 118 and the second conductive layer 120 above the first conductive layer 118.

[0138] For example, Figure 22 For example, Figure 13 For example, Figure 13 and Figure 22 The second conductive layer 120 has the same planar shape as the first conductive layer second subpart 118D of the first conductive layer 118, and the orthographic projection of the second conductive layer 120 on the substrate substrate 111 overlaps the orthographic projection of the first conductive layer second subpart 118D of the first conductive layer 118 on the substrate substrate 111.

[0139] For example, Figure 23 For example, Figure 23As shown, in the second direction Y, in the pad area 105, multiple third signal transmission lines 132 connected to a first color sub-pixel and multiple fourth signal transmission lines 133 connected to a second color sub-pixel are sequentially arranged. The first color sub-pixel is a green sub-pixel G, and the second color sub-pixel includes a blue sub-pixel B or a red sub-pixel R. Multiple third signal transmission lines 132 and multiple fourth signal transmission lines 133 are arranged in the pad area 105 in the second direction Y. The arrangement order of the sub-pixels connected to the multiple third signal transmission lines 132 and multiple fourth signal transmission lines 133 is consistent with the arrangement order of the sub-pixels connected to the multiple data lines 113 and multiple data connection lines 128. A portion of the multiple third signal transmission lines 132 is in an odd-numbered column, and another portion is in an even-numbered column. A portion of the multiple fourth signal transmission lines 133 is in an odd-numbered column, and another portion is in an even-numbered column.

[0140] For example, combining Figure 4 and Figure 23 At least one third signal transmission line 132 and the second data line 113B correspond to sub-pixels of the same color, for example, both corresponding to green sub-pixels. At least one fourth signal transmission line 133 and the first data line 113A correspond to sub-pixels of the same color, for example, both corresponding to red sub-pixels.

[0141] For example, in Figure 23 In the diagram, the sub-pixels connected to multiple third signal transmission lines 132 and multiple fourth signal transmission lines 133 are, in sequence, green sub-pixel G, red sub-pixel R, green sub-pixel G, blue sub-pixel B, blue sub-pixel B, green sub-pixel G, green sub-pixel G, red sub-pixel R, green sub-pixel G, red sub-pixel R, blue sub-pixel B, and green sub-pixel G, thus connecting with... Figure 3 The data lines 113 and 128 at the junction of the display area 101 and the fan-out area 104 are arranged in the same order.

[0142] For example, Figure 24 for Figure 23 A schematic diagram of the planar structure of the first metal layer is shown below. Figure 24 As shown, the first metal layer 115 includes multiple spaced portions in a first row. These portions correspond to the first signal transmission line 129 connected to the first color sub-pixel in the test unit. The multiple portions in the second row correspond to the third signal transmission line 132 connected to the first color sub-pixel and the fourth signal transmission line 133 connected to the second color sub-pixel in the pad area 105. That is, the third signal transmission line 132 connected to the first color sub-pixel and the fourth signal transmission line 133 connected to the second color sub-pixel in the pad area 105 are disposed on the same layer. Figure 24In the middle, the third signal transmission line 132 and the fourth signal transmission line 133, from left to right, receive the driving signals of green sub-pixel G, red sub-pixel R, green sub-pixel G, blue sub-pixel B, blue sub-pixel B, green sub-pixel G, green sub-pixel G, red sub-pixel R, green sub-pixel G, red sub-pixel R, blue sub-pixel B and green sub-pixel G in sequence, so as to drive the sub-pixels of the corresponding colors to be lit.

[0143] For example, Figure 25 for Figure 23 A schematic diagram of the planar structure of the second metal layer, combined with Figure 23 and Figure 25 As shown, the second metal layer 116 includes a plurality of mutually spaced portions, which are respectively inserted into... Figure 24 The first metal layer 115 includes the spaced positions of a plurality of mutually spaced portions located in the first row.

[0144] For example, Figure 26 for Figure 23 A schematic diagram showing the location of the fourth via structure in the interlayer insulating layer on the side of the second metal layer away from the active layer, as shown below. Figure 26 As shown, the interlayer insulating layer 124 is provided with a plurality of fourth via structures 124B, through which the first conductive layer or other layer structure disposed on the second metal layer 116 can be electrically connected to the first metal layer 115 and the second metal layer 116.

[0145] For example, Figure 27 for Figure 23 A schematic diagram of the planar structure of the first conductive layer, as shown below. Figure 27 As shown, the first conductive layer 118 includes a first adapter line 118B, which extends from the upper left corner to the lower right corner. The third signal transmission line 132, arranged in an even-numbered column, and the corresponding first signal transmission line 129 are electrically connected through the first adapter line 118B.

[0146] For example, Figure 28 for Figure 23 A schematic diagram of the planar structure of the fourth planarization layer is shown below. Figure 28 As shown, the fourth planarization layer 126 is provided with a plurality of fifth via structures 126A, which are used to connect the first conductive layer 118 and other conductive layer structures thereon.

[0147] For example, Figure 29 for Figure 23 A schematic diagram of the planar structure of the second conductive layer is shown below. Figure 29As shown, the second conductive layer 120 includes a second jumper line 120A extending from the upper right corner to the lower left corner. The fourth signal transmission line 133 arranged in the odd-numbered column and the corresponding second signal transmission line 130 are electrically connected through the second jumper line 120A, the first jumper line 118B is in the first conductive layer 118, the second jumper line 120A is in the second conductive layer 120, and the first jumper line 118B and the second jumper line 120A are located in different layers. The fourth signal transmission line 133 arranged in the even-numbered column and the corresponding second signal transmission line are electrically connected through the fourth jumper line 120C, the third signal transmission line arranged in the odd-numbered column and the corresponding first signal transmission line are electrically connected through the third jumper line 120B, and the third jumper line 120B and the fourth jumper line 120C are both disposed in the second conductive layer 120.

[0148] For example, in combination with Figure 23 , 27 and 29, the third signal transmission line 132 arranged in the odd-numbered column and the fourth signal transmission line 133 arranged in the even-numbered column are adjacently disposed, and in a plane parallel to the main surface of the substrate 111, the first jumper line 118B connected to the third signal transmission line 132 arranged in the odd-numbered column and the second jumper line 120A connected to the fourth signal transmission line 133 arranged in the even-numbered column intersect. The third signal transmission line 132 arranged in the odd-numbered column and the first signal transmission line 129 are electrically connected through the first jumper line 118B, the fourth signal transmission line 133 arranged in the even-numbered column and the second signal transmission line 130 are electrically connected through the second jumper line 120A, the first jumper line 118B and the second jumper line 120A are located in different layers, the first jumper line 118B is in the first conductive layer, and the second jumper line 120A is in the second conductive layer.

[0149] For example, in combination with Figure 23 , 27 and 29, the third signal transmission line 132 arranged in the odd-numbered column and the corresponding first signal transmission line 129 are electrically connected through the third jumper line 120B, the fourth signal transmission line 133 arranged in the even-numbered column and the corresponding second signal transmission line 130 are electrically connected through the fourth jumper line 120C, and the third jumper line 120B and the fourth jumper line 120C are both disposed in the second conductive layer 120.

[0150] For example, in other examples, it can also be that the third signal transmission line 132 arranged in the odd-numbered column and the fourth signal transmission line 133 arranged in the even-numbered column are adjacently disposed, and in a plane parallel to the main surface of the substrate, the third jumper line 120B connected to the third signal transmission line 132 arranged in the odd-numbered column and the fourth jumper line 120C connected to the fourth signal transmission line 133 arranged in the even-numbered column intersect.

[0151] For example, Figure 30 FIG. 6 is a schematic diagram of the arrangement of data lines, data connection lines and signal transmission lines in a display area and a fan-out area of a display substrate according to another embodiment of the present disclosure, Figure 31 FIG. 7 is a layout of a display area and a fan-out area of a display substrate according to another embodiment of the present disclosure, for example, in combination with Figure 2 、 Figure 30 and Figure 31 , the display substrate 100 includes a substrate 111, the substrate 111 includes a display area 101 and a peripheral area 110 surrounding the display area 101, the peripheral area 110 includes a fan-out area 104 adjacent to the display area 101 and a pad area 105 on a side of the fan-out area 104 away from the display area 101; a plurality of sub-pixels 112 arranged in a matrix are disposed in the display area 101, the plurality of sub-pixels 112 are arranged to form a plurality of columns of sub-pixels, and each column of sub-pixels 112 is electrically connected to one data line 113, i.e., each column of sub-pixels 112 is connected to one data line 113. The fan-out area 104 includes a connection area 114 adjacent to the display area 101, part of the data lines 113 are directly connected to connection pads 127 in the connection area 114, and the other part of the data lines 113 are connected to the connection pads 127 in the connection area 114 through data connection lines 128; the plurality of sub-pixels 112 include a plurality of columns of first color sub-pixels 112A and a plurality of columns of second color sub-pixels 112B, the connection pads 127 include a plurality of first connection pads 127A and a plurality of second connection pads 127B, the plurality of first connection pads 127A are electrically connected to the plurality of columns of first color sub-pixels 112A, and the plurality of second connection pads 127B are electrically connected to the plurality of columns of second color sub-pixels 112B; the fan-out area 104 has a plurality of first signal transmission lines 129 and a plurality of second signal transmission lines 130 arranged at intervals at a position close to the pad area 105, the plurality of first signal transmission lines 129 are arranged in a first metal layer 115, and the plurality of second signal transmission lines 130 are arranged in a second metal layer 116 different from the first metal layer 115; the plurality of first signal transmission lines 129 are electrically connected to the plurality of first connection pads 127A one by one, and the plurality of second signal transmission lines 130 are electrically connected to the plurality of second connection pads 127B one by one, two adjacent data connection lines 128 and at least two data lines 113 located between the two adjacent data connection lines 128 form a data line group 13, the connection pads 127 connected to the data lines 113 and the data connection lines 128 in the data line group 13 include one first connection pad 127A and one second connection pad 127B, and in at least one data line group 13, the data connection line 128 is electrically connected to the first connection pad 127A or the second connection pad 127B through a connection electrode 131, and the connection electrode 131 and one data line 113 adjacent to the data connection line 128 connected to the connection electrode 131 have an overlapping portion in the orthogonal projection of the substrate 111 on the fan-out area 104.

[0152] For example, combining Figure 2 , Figure 30 and Figure 31 As shown, multiple data lines 113 and multiple data connection lines 128 are disposed on a substrate 111, extending in a first direction X in the display area 101 and arranged in a second direction Y intersecting the first direction X. The multiple data lines 113 and multiple data connection lines 128 extend from the display area 101 to the fan-out area 104. At a position near the fan-out area 104 in the display area 101, a portion of the multiple data lines 113 are disposed in odd-numbered columns and another portion in even-numbered columns, and a portion of the multiple data connection lines 128 are disposed in even-numbered columns and another portion in odd-numbered columns. Fan-out area 104 includes connection area 114 adjacent to display area 101. In the other areas of fan-out area 104 excluding connection area 114, multiple first signal transmission lines 129 and multiple second signal transmission lines 130 are arranged in the second direction Y. One of the multiple first signal transmission lines 129 and multiple second signal transmission lines 130 is arranged in an odd-numbered column, and the other of the multiple first signal transmission lines 129 and multiple second signal transmission lines 130 is arranged in an even-numbered column. Multiple first signal transmission lines 129 are arranged in a first metal layer 115, and multiple second signal transmission lines 130 are arranged in a second metal layer 116 located on a different layer from the first metal layer 115. This design allows the arrangement order of sub-pixels connected to the data lines 113 and 128 near the fan-out area 104 of the display area 101 to differ from the arrangement order of sub-pixels connected to the multiple first signal transmission lines 129 and 130 far from the display area 101 of the fan-out area 104. This ensures that sub-pixels connected to the multiple first signal transmission lines 129 or 130 of the same color are positioned on the same film layer, avoiding different parasitic capacitances caused by the multiple first signal transmission lines 129 or 130 of the same color being on different film layers. This also avoids the problem of different data signal write amounts caused by different loads on the multiple first signal transmission lines 129 or 130 of the same color.

[0153] For example, in one example, the first color sub-pixel 112A is the green sub-pixel G, and the second color sub-pixel 112B includes the red sub-pixel R and the blue sub-pixel B. For example, as Figure 30As shown, along the first direction X, at a position of the display region 101 close to the fan-out region 104, the data lines 113 and the data connection lines 128 are sequentially arranged as a whole along the second direction Y, in the order of the data connection line 128 connected to the green sub-pixel G (first data connection line), the data line 113 connected to the red sub-pixel R (first data line), the data line 113 connected to the green sub-pixel G (second data line), the data connection line 128 connected to the blue sub-pixel B (second data connection line), the data line 113 connected to the blue sub-pixel B (third data line), the data line 113 connected to the green sub-pixel G (fourth data line), the data connection line 128 connected to the green sub-pixel G (third data connection line), the data line 113 connected to the red sub-pixel R (fifth data line), the data line 113 connected to the green sub-pixel G (sixth data line), the data connection line 128 connected to the red sub-pixel R (fourth data connection line), the data line 113 connected to the blue sub-pixel B (seventh data line), and the data line 128 connected to the green sub-pixel G (eighth data line). That is, in this example, the first data connection line, the second data line, the third data line, the third data connection line, the sixth data line, and the seventh data line are provided in odd-numbered columns, and the first data line, the second data connection line, the fourth data line, the fifth data line, the fourth data connection line, and the eighth data line are provided in even-numbered columns.

[0154] For example, in the case where the data connection line 128 is provided in the fan-out region 104, the data connection line 128 is provided in the connection region 114 and in the region other than the connection region 114 in the fan-out region 104. Figure 30 For example, in the case where the data connection line 128 is provided in the fan-out region 104, the data connection line 128 is provided in the connection region 114 and in the region other than the connection region 114 in the fan-out region 104. Figure 30In the plurality of first signal transmission lines 129 and plurality of second signal transmission lines 130 connected to the sub-pixels, the first signal transmission lines 129 are arranged in even-numbered columns, and the second signal transmission lines 130 are arranged in odd-numbered columns. The plurality of first signal transmission lines 129 are electrically connected to the plurality of first connecting pads 127A in a one-to-one correspondence, and are also electrically connected to the plurality of first color sub-pixels 112A in a one-to-one correspondence; the plurality of second signal transmission lines 130 are electrically connected to the plurality of second connecting pads 127B in a one-to-one correspondence, and are also electrically connected to the plurality of second color sub-pixels 112B in a one-to-one correspondence, thereby such that the plurality of first signal transmission lines 129 are arranged in the first metal layer, and the plurality of second signal transmission lines 130 are arranged in the second metal layer, which is located in a different layer from the first metal layer. In other words, the display substrate designs jumpers for data lines and data connection lines in the connection area adjacent to the display area (AA) in the fanout region. The arrangement order of sub-pixels connected to the data lines and data connection lines near the fanout region of the display area is different from the arrangement order of sub-pixels connected to multiple first signal transmission lines and multiple second signal transmission lines far from the display area in the fanout region. This is to adjust multiple first signal transmission lines or multiple second signal transmission lines connected to sub-pixels of the same color to be located in the same film layer, so as to avoid different parasitic capacitances caused by multiple first signal transmission lines or multiple second signal transmission lines connected to sub-pixels of the same color being in different film layers, thereby avoiding multiple first signal transmission lines or multiple second signal transmission lines connected to sub-pixels of the same color.

[0155] It should be noted that the first to eighth data lines mentioned above refer to the sorting of data lines located in the same row as the data connection lines, while the first to fourth data connection lines refer to the sequential sorting of data connection lines inserted in FIP mode. The first to eighth data lines and the first to fourth data connection lines are taken from the data lines and data connection lines respectively, and are used merely for ease of description and do not refer to any other data lines besides the data lines and data connection lines.

[0156] It should also be noted that the aforementioned data lines and data connection jumpers refer to swapping the positions of adjacent data lines and data connection lines while maintaining their adjacent positional relationship. Specifically, this can be achieved by intersecting data lines and data connection lines located on different layers at positions corresponding to the connection areas on the plane.

[0157] For example, such as Figure 31 As shown, in the fan-out region 104, excluding the connection region 114, the region is described in terms of 12 signal transmission lines arranged sequentially along the second direction Y as one cycle. These 12 signal transmission lines in one cycle include multiple first signal transmission lines 129 and multiple second signal transmission lines 130. Figure 31In this configuration, the multiple first signal transmission lines 129 are all arranged in even-numbered columns, and the multiple second signal transmission lines 130 are all arranged in odd-numbered columns.

[0158] For example, such as Figure 31 As shown, in the fan-out region 104, along the second direction Y, the following are arranged sequentially: a second connecting pad 127B connected to the red sub-pixel R, a first connecting pad 127A connected to the green sub-pixel G, a second connecting pad 127B connected to the blue sub-pixel B, a first connecting pad 127A connected to the green sub-pixel G, a second connecting pad 127B connected to the blue sub-pixel B, a first connecting pad 127A connected to the green sub-pixel G, a second connecting pad 127B connected to the red sub-pixel R, a first connecting pad 127A connected to the green sub-pixel G, and a second connecting pad 127B connected to the red sub-pixel R. 27B, a first connecting pad 127A connected to the green sub-pixel G, a second connecting pad 127B connected to the blue sub-pixel B, and a first connecting pad 127A connected to the green sub-pixel G. Multiple first connecting pads 127A are electrically connected to multiple first signal transmission lines 129 in a one-to-one correspondence. Multiple second connecting pads 127B are electrically connected to multiple second signal transmission lines 130 in a one-to-one correspondence. This allows multiple first signal transmission lines 129 to be placed in the first metal layer 115, and multiple second signal transmission lines 130 to be placed in a second metal layer 116 located on a different layer than the first metal layer 115. This allows the signal transmission lines connected to sub-pixels of the same color to be located in the same film layer, avoiding different parasitic capacitances caused by signal transmission lines connected to sub-pixels of the same color being in different film layers. This also avoids the problem of different data signal write amounts due to different loads on the signal transmission lines connected to sub-pixels of the same color.

[0159] For example, combining Figure 2 and Figure 31 The display area 101 may include multiple thin-film transistors (TFTs), which are test switch transistors. At least one of the TFTs may be a dual-gate structure. For example, the first TFT includes a first gate and a second gate, while the other TFTs each have only one gate. The first metal layer 115 may be formed on the same layer as the first gate of the first TFT, and the second metal layer 116 may be formed on the same layer as the second gate of the first TFT. In the direction perpendicular to the main surface of the substrate 111, although... Figure 31 Not shown, an insulating layer is also provided between the first metal layer 115 and the second metal layer 116, which prevents electrical connection between the first signal transmission line 129 and the second signal transmission line 130 in the connection area 114 and on a plane parallel to the main surface of the substrate 111.

[0160] For example, when the parasitic capacitance of the first metal layer 115 and the second metal layer 116 changes, the resistance of the first signal transmission line 129 connected with the green sub-pixel G will be different, which will cause the difference in display brightness. Therefore, in the embodiment of the present disclosure, in the connecting area 114, the first data connection line 128 connected with the green sub-pixel G and the first data line 113 connected with the red sub-pixel R are designed by jumper, the second data line 113 connected with the green sub-pixel G and the second data connection line 128 connected with the blue sub-pixel B are designed by jumper, the third data connection line 128 connected with the green sub-pixel G and the fifth data line 113 connected with the red sub-pixel R are designed by jumper, and the sixth data line 113 connected with the green sub-pixel G and the fourth data connection line 128 connected with the red sub-pixel R are designed by jumper, so that the green sub-pixel G is still connected to the first metal layer 115, the blue sub-pixel B and the red sub-pixel R are still connected to the second metal layer 116, and after connection, in the other areas of the fan-out area 104 except the connecting area 114, the arrangement order of the sub-pixels connected with the first signal transmission line 129 and the second signal transmission line 130 is RGBGBGRGRGBG, so that the first signal transmission line 129 connected with the green sub-pixel G is arranged in the even position (the first signal transmission line 129 and the second signal transmission line 130 connected with the sub-pixel are arranged as a whole in Figure 31 the middle), and is located in the first metal layer 115, and the second signal transmission line 130 connected with the blue sub-pixel B or the red sub-pixel R is arranged in the odd position (the first signal transmission line 129 and the second signal transmission line 130 connected with the sub-pixel are arranged as a whole in Figure 31 the middle), and is located in the second metal layer 116, so that the influence of the parasitic capacitance can be avoided.

[0161] For example, Figure 32 the first metal layer in Figure 31 , a planar structure schematic diagram is provided, in combination with Figure 31 and Figure 32 , in the other areas of the fan-out area 104 except the connecting area 114, the plurality of first signal transmission lines 129 in the first metal layer 115 all have the shape of a broken line, and the plurality of first signal transmission lines 129 all include a vertical part extending along the first direction X, and a slanted part extending along the direction which is an obtuse angle with the first direction X, and the slanted part makes the final first signal transmission line 129 inwardly retract into the middle area. The vertical parts of the plurality of first signal transmission lines 129 are uniformly distributed in the second direction Y, so that the signals transmitted to the first signal transmission line 129 are more uniform.

[0162] For example, Figure 33 a planar structure schematic diagram corresponding to Figure 31a schematic diagram of a planar structure of the second metal layer in the display panel 100, in combination with Figure 31 and Figure 33 In the fan-out area 104, except for the area involving the jumper position, each of the plurality of second signal transmission lines 130 in the second metal layer 116 has a shape of a broken line, and each of the plurality of second signal transmission lines 130 includes a vertical portion extending along the first direction X and a slanted line portion extending along a direction that is obtuse to the first direction X, so that the final second signal transmission line 130 is inwardly retracted into the middle area. The vertical portions of the plurality of second signal transmission lines 130 are uniformly distributed in the second direction Y, so that the signals transmitted to the second signal transmission lines 130 are more uniform.

[0163] For example, Figure 34 corresponding to Figure 31 a schematic diagram of a planar structure of the interlayer insulating layer disposed on the side of the second metal layer away from the substrate in the display panel 100, as shown in Figure 34 The interlayer insulating layer 117 is provided with a plurality of first hole structures 117A, which can realize electrical connection between the structure disposed on the side of the interlayer insulating layer 117 away from the substrate 111 and the structure on the side of the interlayer insulating layer 117 close to the substrate 111.

[0164] For example, Figure 35 corresponding to Figure 31 a schematic diagram of a planar structure of the first conductive layer in the display panel 100, as shown in Figure 35 The first conductive layer 118 includes a plurality of first connecting pieces 118A, which can be used as the layer structure of the connecting pad 127 close to the substrate 111, and the second connecting pieces mentioned later to realize one-to-one electrical connection between the plurality of data lines 113 or the plurality of data connecting lines 128 in the display area 101 and the corresponding plurality of first signal transmission lines 129 or the plurality of second signal transmission lines 130 in the fan-out area 104. The material of the first conductive layer 118 can be a conductive metal or a conductive metal oxide, as long as it can meet the stable connection relationship, and the embodiments of the present disclosure do not limit it.

[0165] For example, Figure 36 corresponding to Figure 31 a schematic diagram of a planar structure of the first planarization layer on the side of the first conductive layer away from the substrate in the display panel 100, as shown in Figure 36 The first planarization layer 119 is provided with a plurality of second hole structures 119A, and the plurality of second hole structures 119A are used to connect the first conductive layer 118 and the second conductive layer on the side of the first planarization layer 119 away from the substrate 111.

[0166] For example, Figure 37 corresponding toFigure 31 a plan view of the second conductive layer in FIG. 12B, as shown in FIG. 12C. Figure 37 As shown in FIG. 12C, the second conductive layer 120 has a plurality of connection electrodes 131, including a plurality of first connection electrodes 131E and a plurality of second connection electrodes 131F, each of which is in a bent shape. The plurality of first connection electrodes 131E are used to connect the data connection lines 128 on the third conductive layer mentioned later and the corresponding first signal transmission lines 129, and the plurality of second connection electrodes 131F are used to connect the data connection lines 128 on the third conductive layer and the corresponding second signal transmission lines 130. As shown in FIG. 12C, the bent shape of the first connection electrodes 131E and the second connection electrodes 131F can realize the jumpering of the first data connection line 128 connected with the green sub-pixel G and the first data line 113 connected with the red sub-pixel R, the jumpering of the second data line 113 connected with the green sub-pixel G and the second data connection line 128 connected with the blue sub-pixel B, the jumpering of the third data connection line 128 connected with the green sub-pixel G and the fifth data line 113 connected with the red sub-pixel R, and the jumpering of the fourth data connection line 128 connected with the red sub-pixel R and the sixth data line 113 connected with the green sub-pixel G. It should be noted that the above-mentioned jumpering is to exchange the arrangement positions of the first signal transmission lines connected with the above-mentioned data connection lines after jumpering and the second signal transmission lines connected with the above-mentioned data lines after jumpering in the second direction Y. Figure 37

[0167] For example, Figure 38 As shown in FIG. 12D, the second planarization layer 121 has a plurality of third hole structures 121A for connecting the second conductive layer 120 and the third conductive layer on the side of the second planarization layer 121 away from the substrate 111. Figure 31 a plan view of the second conductive layer in FIG. 12B, as shown in FIG. 12C. Figure 38 As shown in FIG. 12C, the second conductive layer 120 has a plurality of connection electrodes 131, including a plurality of first connection electrodes 131E and a plurality of second connection electrodes 131F, each of which is in a bent shape. The plurality of first connection electrodes 131E are used to connect the data connection lines 128 on the third conductive layer mentioned later and the corresponding first signal transmission lines 129, and the plurality of second connection electrodes 131F are used to connect the data connection lines 128 on the third conductive layer and the corresponding second signal transmission lines 130. As shown in FIG. 12C, the bent shape of the first connection electrodes 131E and the second connection electrodes 131F can realize the jumpering of the first data connection line 128 connected with the green sub-pixel G and the first data line 113 connected with the red sub-pixel R, the jumpering of the second data line 113 connected with the green sub-pixel G and the second data connection line 128 connected with the blue sub-pixel B, the jumpering of the third data connection line 128 connected with the green sub-pixel G and the fifth data line 113 connected with the red sub-pixel R, and the jumpering of the fourth data connection line 128 connected with the red sub-pixel R and the sixth data line 113 connected with the green sub-pixel G. It should be noted that the above-mentioned jumpering is to exchange the arrangement positions of the first signal transmission lines connected with the above-mentioned data connection lines after jumpering and the second signal transmission lines connected with the above-mentioned data lines after jumpering in the second direction Y.

[0168] For example, Figure 39 As shown in FIG. 12D, the second planarization layer 121 has a plurality of third hole structures 121A for connecting the second conductive layer 120 and the third conductive layer on the side of the second planarization layer 121 away from the substrate 111. Figure 31 a plan view of the second conductive layer in FIG. 12B, as shown in FIG. 12C. Figure 39 As shown in FIG. 12C, the second conductive layer 120 has a plurality of connection electrodes 131, including a plurality of first connection electrodes 131E and a plurality of second connection electrodes 131F, each of which is in a bent shape. The plurality of first connection electrodes 131E are used to connect the data connection lines 128 on the third conductive layer mentioned later and the corresponding first signal transmission lines 129, and the plurality of second connection electrodes 131F are used to connect the data connection lines 128 on the third conductive layer and the corresponding second signal transmission lines 130. As shown in FIG. 12C, the bent shape of the first connection electrodes 131E and the second connection electrodes 131F can realize the jumpering of the first data connection line 128 connected with the green sub-pixel G and the first data line 113 connected with the red sub-pixel R, the jumpering of the second data line 113 connected with the green sub-pixel G and the second data connection line 128 connected with the blue sub-pixel B, the jumpering of the third data connection line 128 connected with the green sub-pixel G and the fifth data line 113 connected with the red sub-pixel R, and the jumpering of the fourth data connection line 128 connected with the red sub-pixel R and the sixth data line 113 connected with the green sub-pixel G. It should be noted that the above-mentioned jumpering is to exchange the arrangement positions of the first signal transmission lines connected with the above-mentioned data connection lines after jumpering and the second signal transmission lines connected with the above-mentioned data lines after jumpering in the second direction Y. Figure 39 ​As can be seen, along the second direction Y, the multiple data lines 113 and multiple data connection lines 128 are sorted as follows: first data connection line, first data line, second data line, second data connection line, third data line, fourth data line, third data connection line, fifth data line, sixth data line, fourth data connection line, seventh data line, and eighth data line. That is, the first data connection line 128 refers to the data connection line that is arranged in the first position among the four data connection lines, that is, the first data connection line 128. The second to fourth data connection lines 128 have similar definitions. The first data line 113 refers to the data line that is arranged in the first position among the eight data lines, that is, the first data line 113. The second to eighth data lines 113 have similar definitions.

[0169] For example, such as Figure 31 and Figure 39 As shown, the first data connection line 128 extends in a straight line along the first direction X; the first data line 113 extends in a bent direction along the first direction X, with its connection end facing the opposite direction to the second direction Y; the second data line 113 extends in a bent direction along the first direction X, with its connection end facing the second direction Y; the second data connection line 128 extends in a straight line along the first direction X; the third data line 113 extends in a bent direction along the first direction X, with its connection end facing the second direction Y; the fourth data line 113 extends in a bent direction along the first direction X, with its connection end facing the opposite direction to the second direction Y; the third data connection line 128, the fifth data line 113, the sixth data line 113, the fourth data connection line 128, the seventh data line 113, and the eighth data line 113 sequentially repeat the shapes of the first data connection line 128, the first data line 113, the second data line 113, the second data connection line 128, the third data line 113, and the fourth data line 113, respectively, and will not be described in detail here.

[0170] For example, in one example, combining Figure 2 , Figure 31 and Figure 39 As shown, at least one data connection line 128 located in an odd-numbered column extends in the fan-out area 104 towards the side near the pad area 105, and is then electrically connected via a first connection electrode 131E disposed on the second conductive layer 120 and a corresponding first signal transmission line 129. An adjacent first data line 113 crosses the first connection electrode 131E to be electrically connected to the corresponding second signal transmission line 130. Figure 31In the diagram, the first data line 113 connected to the red sub-pixel B crosses and connects the first connection electrode 131E of the first data connection line 128 connected to the green sub-pixel G and the first signal transmission line 129. The second data line 113 connected to the green sub-pixel G crosses and connects the second connection electrode 131F of the second data connection line 128 connected to the blue sub-pixel B and the second signal transmission line 130. The fifth data line 113 connected to the red sub-pixel R crosses and connects the first connection electrode 131E of the third data connection line 128 connected to the green sub-pixel G and the first signal transmission line 129. The sixth data line 113 connected to the green sub-pixel G crosses and connects the second connection electrode 131F of the fourth data connection line 128 connected to the red sub-pixel R and the second signal transmission line 130.

[0171] It should be noted that the crossing of the data line across the first connection electrode and the crossing of the data line across the second connection electrode refer to the overlapping portions of the data line and the corresponding first connection electrode on a plane parallel to the main surface of the substrate, and the overlapping portions of the data line and the corresponding second connection electrode. That is, the orthographic projection of the data line on the substrate and the orthographic projection of the corresponding first connection electrode on the substrate overlap, and the orthographic projection of the data line on the substrate and the orthographic projection of the corresponding second connection electrode on the substrate overlap.

[0172] For example, Figure 40 This is a schematic diagram of the planar structure of a test unit in a display substrate provided in at least one embodiment of the present disclosure, as shown below. Figure 40 As shown, in the second direction Y, in this test unit, multiple first signal transmission lines 129 connected to the first color sub-pixel 112A and multiple second signal transmission lines 130 connected to the second color sub-pixel 112B are alternately arranged in sequence. The first color sub-pixel is a green sub-pixel G, and the second color sub-pixel 112B includes a blue sub-pixel B or a red sub-pixel R. The test unit contains multiple thin-film transistors, each including an active layer, a gate, a source, and a drain. These multiple thin-film transistors serve as test switching transistors.

[0173] For example, Figure 41 for Figure 40 A schematic diagram of the planar structure of the active layer, as shown below. Figure 41 As shown, the active layer 123 is made of polycrystalline silicon. Figure 41The diagram shows the structure of 12 complete active layers. Each rectangular dashed box indicates a complete active layer 123, meaning that the 12 complete active layers 123 correspond to two repeating units. The 6 active layers 123 in the first row are active layers for test switch transistors corresponding to 3 blue sub-pixels and 3 red sub-pixels, respectively. The 6 active layers in the second row are active layers for test switch transistors corresponding to 3 blue sub-pixels and 3 red sub-pixels, respectively. The following description only considers the 6 active layers 123 in the first row as one repeating unit.

[0174] For example, Figure 42 for Figure 40 A schematic diagram of the planar structure of the first metal layer is shown below. Figure 42 As shown, the first metal layer 115 includes a first portion 115A connected to the first color sub-pixel, and a second portion 115B serving as the gate of a test switching transistor. The first color sub-pixel 112A and the second color sub-pixel 112B, although... Figure 40 and Figure 42 Not shown in the image, but it can be found in [reference]. Figure 40 The second color sub-pixel 112A and 112B are shown in the figure. The second color sub-pixel 112B includes a blue sub-pixel B and a red sub-pixel R. During the testing phase, the test switch transistor is mainly used to control the blue sub-pixel B and the red sub-pixel R to not be turned on at the same time. That is, at different times, only one of the blue sub-pixel B and the red sub-pixel R is in the on state, while the other is in the off state, so as to avoid the phenomenon of color shift caused by low purity of emitted light.

[0175] It should be noted that, Figure 42 The first part, 115A, is... Figure 40 The first signal transmission line 129 in the middle.

[0176] For example, combining Figure 40 and Figure 42 The second portion 115B of the first metal layer 115 includes a main body portion 115B1 and a branch portion 115B2. The main body portion 115B1 is used to connect to the first sub-part 118C of the first conductive layer 118, and the branch portion 115B2 serves as the gate of a test switching transistor. The first sub-part 118C of the first conductive layer provides a gate signal voltage for the test switching transistor. The structure of the first conductive layer 118 will be described in detail when describing the first conductive layer 118.

[0177] For example, combining Figure 40 and Figure 42The arrangement order of the sub-pixels connected to the first signal transmission line 129 and the second signal transmission line 130 in the first row is: red sub-pixel R, green sub-pixel G, blue sub-pixel B, green sub-pixel G, blue sub-pixel B, green sub-pixel G, red sub-pixel R, green sub-pixel G, red sub-pixel R, green sub-pixel G, blue sub-pixel B, green sub-pixel G. This arrangement order of the sub-pixels connected to the first signal transmission line 129 and the second signal transmission line 130 in the first row... Figure 30 In the fan-out area 104, except for the connection area 114, the sub-pixels connected to the first signal transmission line 129 and the second signal transmission line 130 are arranged in the same order.

[0178] For example, Figure 43 for Figure 40 A schematic diagram of the planar structure of the second metal layer, combined with Figure 40 and Figure 43 As shown, the open transistor ultimately transmits the signal to the second metal layer 116, so that the first signal transmission line 129 connected to the first color sub-pixel 112A and the second signal transmission line 130 connected to the second color sub-pixel 112B are located in different metal layers, thereby controlling the lighting status of the first color sub-pixel 112A and the second color sub-pixel 112B respectively.

[0179] It should be noted that, Figure 40 The second signal transmission line 130 is located in Figure 43 On the second metal layer 116 shown, Figure 43 The long strip shown corresponds to Figure 40 The second signal transmission line 130 in the middle.

[0180] It should be noted that although the blue sub-pixel B in the first row and the red sub-pixel R in the second row are connected to the same second signal transmission line 130, or although the red sub-pixel B in the first row and the blue sub-pixel B in the second row are connected to the same second signal transmission line 130, there will be no signal crosstalk problem due to the control of the test switch transistor.

[0181] For example, Figure 44 for Figure 40 The circuit diagram corresponding to the first test switch transistor of the red sub-pixel when it is turned on. Figure 45 for Figure 40 The circuit diagram corresponding to the second test switch transistor of the blue sub-pixel is shown when it is turned on. Figure 44 and 45As shown, when testing a red monochrome image, the red subpixel needs to be lit, and the blue subpixel needs to be off; similarly, when testing a blue monochrome image, the blue subpixel needs to be lit, and the red subpixel needs to be off. For example, in one example, the input signal voltages are as follows: red subpixel switch signal (SWR): -7V, blue subpixel switch signal (SWB): +7V, red subpixel source signal (DR): 3V, blue subpixel source signal (DB): 7V. For the first test switch transistor corresponding to the red subpixel, applying a -7V SWR signal turns it on, inputting a 3V DR signal into the second signal transmission line. At this time, when the applied SWB voltage is +7V, the second test switch transistor corresponding to the blue subpixel is off, and the DB signal cannot be input to the second signal transmission line. Therefore, the voltage on the second signal transmission line is 3V, and the red subpixel is lit. For example, in another example, for the blue sub-pixel, when a -7V SWB signal is applied to the second test switching transistor corresponding to the blue sub-pixel, the second test switching transistor of the blue sub-pixel is turned on, and at this time, a 7V DB signal is input to the second signal transmission line; at this time, when the applied SWR voltage is +7V, the first test switching transistor corresponding to the red sub-pixel is turned off, the DR signal cannot be input to the second signal transmission line, therefore, the voltage on the second signal transmission line is 7V, and the corresponding blue sub-pixel is lit.

[0182] For example, Figure 46 for Figure 31 An interlayer insulating layer disposed on the side of the second metal layer away from the active layer, such as Figure 46 As shown, the interlayer insulating layer 124 is provided with a plurality of third via structures 124A. Through the third via structures 124A, the first conductive layer and other structures disposed on the side of the second metal layer 116 away from the active layer can be electrically connected to the first metal layer 115, the second metal layer 116 and the active layer.

[0183] For example, Figure 47 for Figure 31 A schematic diagram of the planar structure of the first conductive layer in the middle, combined with Figure 31 , Figure 42 and Figure 47As shown, the first conductive layer 118 includes a first conductive layer first sub-portion 118C1, a first conductive layer second sub-portion 118D1, and a first conductive layer third sub-portion 118E. The first conductive layer first sub-portion 118C1 is electrically connected with the main portion 115B1 included in the second portion 115B of the first metal layer 115 to provide a gate driving signal for the test switch transistor. The source S1 of the first test switch transistor for controlling the red sub-pixel R is electrically connected with the first conductive layer second sub-portion 118D1 to provide a monochromatic power voltage test signal for the red sub-pixel. The drain D1 of the first test switch transistor for controlling the red sub-pixel R is electrically connected with the second signal transmission line 130, the source S1 and the drain D1 are overlapped on both sides of the active layer of the first test switch transistor corresponding to the red sub-pixel R, and the branch portion 115B2 included in the second portion 115B of the first metal layer 115 is used as the gate of the first test switch transistor for controlling the red sub-pixel R. The first conductive layer third sub-portion 118E is configured to be electrically connected with the second signal transmission line 130.

[0184] For example, as shown in conjunction with Figure 31 , Figure 42 and Figure 47 , the first conductive layer 118 further includes a first conductive layer first sub-portion 118C2 and a first conductive layer second sub-portion 118D2. The first conductive layer first sub-portion 118C2 is electrically connected with the main portion 115B1 included in the second portion 115B of the first metal layer 115 to provide a gate driving signal for the test switch transistor. The source S1 of the second test switch transistor for controlling the blue sub-pixel B is electrically connected with the first conductive layer second sub-portion 118D2 to provide a monochromatic power voltage test signal for the blue sub-pixel B. The drain D1 of the second test switch transistor for controlling the blue sub-pixel B is electrically connected with the second signal transmission line 130, the source S1 and the drain D1 are overlapped on both sides of the active layer of the second test switch transistor corresponding to the blue sub-pixel B, and the branch portion 115B2 included in the second portion 115B of the first metal layer 115 is used as the gate of the second test switch transistor for controlling the blue sub-pixel B.

[0185] For example, as shown in conjunction with Figure 31 , Figure 42 and Figure 47In one repeat unit, the first conductive layer 118 includes two parallel first conductive layer first subparts 118C. For example, the first conductive layer first subparts 118C on the upper side are each connected to the gate of the first test switch transistor for controlling the red subpixel to be lit, and the first conductive layer first subparts 118C on the lower side are each connected to the gate of the second test switch transistor for controlling the blue subpixel to be lit, so as to respectively apply a gate driving voltage to the first test switch transistor for controlling the red subpixel to be lit and the second test switch transistor for controlling the blue subpixel to be lit, so that the blue subpixel and the red subpixel are lit in different stages, so as not to cause color mixing of red light and blue light.

[0186] For example, Figure 48 For example, Figure 31 For example, Figure 31 For example, Figure 42 For example, Figure 48 The third planarization layer 125 is provided with a plurality of grooves, which can realize electrical connection between the first conductive layer 118 and the second conductive layer 120 above the first conductive layer 118.

[0187] For example, Figure 49 For example, Figure 31 For example, Figure 31 For example, Figure 49 The second conductive layer 120 has the same planar shape as the first conductive layer second subpart 118D of the first conductive layer 118, and the orthographic projection of the second conductive layer 120 on the substrate substrate 111 overlaps the orthographic projection of the first conductive layer second subpart 118D of the first conductive layer 118 on the substrate substrate 111.

[0188] For example, Figure 50 For example, Figure 50As shown, in the second direction Y, in the pad area 105, multiple third signal transmission lines 132 connected to a first color sub-pixel and multiple fourth signal transmission lines 133 connected to a second color sub-pixel are sequentially arranged. The first color sub-pixel is a green sub-pixel G, and the second color sub-pixel includes a blue sub-pixel B or a red sub-pixel R. Multiple third signal transmission lines 132 and multiple fourth signal transmission lines 133 are arranged in the pad area 105 in the second direction Y. The arrangement order of the sub-pixels connected to the multiple third signal transmission lines 132 and multiple fourth signal transmission lines 133 is consistent with the arrangement order of the sub-pixels connected to the multiple data lines 113 and multiple data connection lines 128. A portion of the multiple third signal transmission lines 132 is in an odd-numbered column, and another portion is in an even-numbered column. A portion of the multiple fourth signal transmission lines 133 is in an odd-numbered column, and another portion is in an even-numbered column.

[0189] For example, in Figure 50 In the diagram, the sub-pixels connected to multiple third signal transmission lines 132 and multiple fourth signal transmission lines 133 are, in sequence, green sub-pixel G, red sub-pixel R, green sub-pixel G, blue sub-pixel B, blue sub-pixel B, green sub-pixel G, green sub-pixel G, red sub-pixel R, green sub-pixel G, red sub-pixel R, blue sub-pixel B, and green sub-pixel G, thus connecting with... Figure 30 The data lines 113 and 128 at the junction of the display area 101 and the fan-out area 104 are arranged in the same order.

[0190] For example, Figure 51 for Figure 50 A schematic diagram of the planar structure of the first metal layer is shown below. Figure 51 As shown, the first metal layer 115 includes multiple spaced portions in a first row. These portions correspond to the first signal transmission line 129 connected to the first color sub-pixel in the test unit. The multiple portions in the second row correspond to the third signal transmission line 132 connected to the first color sub-pixel and the fourth signal transmission line 133 connected to the second color sub-pixel in the pad area 105. That is, the third signal transmission line 132 connected to the first color sub-pixel and the fourth signal transmission line 133 connected to the second color sub-pixel in the pad area 105 are disposed on the same layer. Figure 51 In the middle, the third signal transmission line 132 and the fourth signal transmission line 133, from left to right, receive the driving signals of green sub-pixel G, red sub-pixel R, green sub-pixel G, blue sub-pixel B, blue sub-pixel B, green sub-pixel G, green sub-pixel G, red sub-pixel R, green sub-pixel G, red sub-pixel R, blue sub-pixel B and green sub-pixel G in sequence, so as to drive the sub-pixels of the corresponding colors to be lit.

[0191] For example, Figure 52 For example, Figure 50 For example, Figure 50 For example, Figure 52 As shown in FIG. 11B, the second metal layer 116 includes a plurality of spaced-apart portions, and the plurality of spaced-apart portions of the second metal layer 116 are respectively inserted between the spaced-apart portions of the first metal layer 115 in the first row. Figure 51 For example, For example,

[0192] For example, Figure 53 For example, Figure 50 For example, Figure 53 As shown in FIG. 12B, the interlayer insulating layer 124 includes a plurality of fourth hole structures 124B, and the first conductive layer or other layer structure disposed on the second metal layer 116 can be electrically connected to the first metal layer 115 and the second metal layer 116 through the fourth hole structure 124B. For example,

[0193] For example, Figure 54 For example, Figure 50 As shown in FIG. 13B, the first conductive layer 118 includes a first jumper line 118B extending from the upper left corner to the lower right corner. Figure 54 For example, For example,

[0194] For example, Figure 55 For example, Figure 50 As shown in FIG. 14B, the fourth planarization layer 126 includes a plurality of fifth hole structures 126A for connecting the first conductive layer 118 and other conductive layer structures thereon. Figure 55 For example, For example,

[0195] For example, Figure 56 For example, Figure 50 As shown in FIG. 15B, the second conductive layer 120 includes a second jumper line 120A extending from the upper right corner to the lower left corner. Figure 56 For example, For example,

[0196] For example, Figure 50 , 54And 56, the at least one third signal transmission line 132 arranged in the odd-numbered column and one fourth signal transmission line 133 arranged in the even-numbered column are adjacently arranged, and in a plane parallel to the main surface of the substrate 111, the second transition line 120A connected with the at least one third signal transmission line 132 arranged in the odd-numbered column and the first transition line 118B connected with the one fourth signal transmission line 133 arranged in the even-numbered column intersect. The third signal transmission line 132 arranged in the odd-numbered column and the corresponding first signal transmission line 129 are electrically connected through the second transition line 120A, the fourth signal transmission line 133 arranged in the even-numbered column and the corresponding second signal transmission line 130 are electrically connected through the first transition line 118B, the first transition line 118B and the second transition line 120A are located in different layers, the first transition line 118B is in the first conductive layer 118, and the second transition line 120A is in the second conductive layer 120.

[0197] For example, in combination with Figure 50 , Figure 54 and Figure 56 , the third signal transmission line 132 arranged in the even-numbered column and the first signal transmission line 129 are electrically connected through the third transition line 120B, and the fourth signal transmission line 133 arranged in the odd-numbered column and the second signal transmission line 130 are electrically connected through the fourth transition line 120C, and the third transition line 120B and the fourth transition line 120C are both arranged in the second conductive layer 120.

[0198] For example, in combination with Figure 50 , Figure 54 and Figure 56 , the at least one third signal transmission line 132 arranged in the even-numbered column and the one fourth signal transmission line 133 arranged in the odd-numbered column are adjacently arranged, and in a plane parallel to the main surface of the substrate 111, the third transition line 120B connected with the at least one third signal transmission line 132 arranged in the even-numbered column and the fourth transition line 120C connected with the one fourth signal transmission line 133 arranged in the odd-numbered column do not intersect.

[0199] For example, as shown in Figure 31 , the connection electrode 131E extends along the direction from the at least one data connection line to the one adjacent data line at the position where the display area and the fan-out area meet.

[0200] For example, the above can also take 16 sub-pixels arranged in the second direction Y as one period, or take 16 sub-pixels arranged in the second direction Y as one period, and the embodiments of the present disclosure do not limit this.

[0201] The display device provided by at least one embodiment of the present disclosure also provides a display device. Figure 57 A schematic diagram of a display device according to an embodiment of the present disclosure is shown in FIG. 1. As shown in Figure 57As shown, the display device 300 includes the display substrate 100 described above. Thus, the display device 300 can avoid the phenomenon that the parasitic capacitances of the data signal lines connected to the sub-pixels of the same color are different when the data signal lines are in different film layers, and further can avoid the problem that the loads of the data signal lines connected to the sub-pixels of the same color are different, resulting in different data signal write amounts, that is, the influence caused by the different parasitic capacitances, and also does not affect the connection order of the data signal lines in the subsequent driving circuit.

[0202] For example, in some examples, the display device can further include a functional component located on the side of the substrate away from the light-emitting element. For example, the functional component includes at least one of a camera module (for example, a front camera module), a 3D structured light module (for example, a 3D structured light sensor), a time-of-flight 3D imaging module (for example, a time-of-flight sensor), an infrared sensing module (for example, an infrared sensing sensor), and the like. The display device can also be a smart phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, or any product or component having a display function.

[0203] The display substrate and the display device provided by at least one embodiment of the present disclosure have at least one of the following beneficial technical effects:

[0204] (1) The display substrate provided by at least one embodiment of the present disclosure adjusts the plurality of first signal transmission lines or the plurality of second signal transmission lines connected to the sub-pixels of the same color to be located in the same film layer by designing the data lines and the data line jumpers or the data lines and the data connection line jumpers at the connection area of the fan-out area adjacent to the display area (AA), so as to make the arrangement order of the sub-pixels connected to the data lines and the data connection lines at the position of the fan-out area close to the wiring area of the display area different from the arrangement order of the sub-pixel data lines connected to the plurality of first signal transmission lines and the plurality of second signal transmission lines at the position of the wiring area and the fan-out area away from the display area, so as to adjust the plurality of first signal transmission lines or the plurality of second signal transmission lines connected to the sub-pixels of the same color to be located in the same film layer, to avoid the phenomenon that the parasitic capacitances of the plurality of first signal transmission lines or the plurality of second signal transmission lines connected to the sub-pixels of the same color are different when the plurality of first signal transmission lines or the plurality of second signal transmission lines are in different film layers, and further to avoid the problem that the loads of the plurality of first signal transmission lines or the plurality of second signal transmission lines connected to the sub-pixels of the same color are different, resulting in different data signal write amounts.

[0205] (2) The display substrate provided by at least one of the embodiments of the present disclosure, the third data line is connected to the connection pad from the position close to the wiring area of the display area through the third conductive layer, the fourth data line is connected to the connection pad from the position away from the wiring area of the display area through the third conductive layer, that is, the third data line and the first signal transmission line connected with the fourth data line cross, but the fourth data line and the second signal transmission line connected with the third data line do not cross. Since only the third data line located in the third conductive layer and connected with the blue sub-pixel overlaps with the first signal transmission line connected with the green sub-pixel, but there is no overlap between the fourth data line connected with the green sub-pixel and the second signal transmission line connected with the blue sub-pixel, so that the parasitic capacitance can be reduced, and thus the capacitance difference between different signal film layers caused by the jumper can be minimized.

[0206] (3) The display substrate provided by at least one of the embodiments of the present disclosure, in one repeating unit, the first conductive layer includes two parallel first conductive layer first sub-parts, the first conductive layer first sub-part on the upper side is connected with the gate of the first test switch transistor for controlling the red sub-pixel to be lighted, and the first conductive layer first sub-part on the lower side is connected with the gate of the second test switch transistor for controlling the blue sub-pixel to be lighted, so that the gate driving voltage can be applied to the first test switch transistor for controlling the red sub-pixel to be lighted and the second test switch transistor for controlling the blue sub-pixel to be lighted respectively, so that the blue sub-pixel and the red sub-pixel are lighted in different stages, so that the color mixing of red light and blue light will not be caused.

[0207] The following points need to be explained:

[0208] (1) The drawings of the embodiments of the present disclosure only involve the structures involved in the embodiments of the present disclosure, and other structures can be referred to the general design.

[0209] (2) For the sake of clarity, the thickness of the layer or region is magnified or reduced in the drawings used to describe the embodiments of the present disclosure, that is, the drawings are not drawn according to the actual proportion.

[0210] (3) In the case of no conflict, the embodiments of the present disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0211] The above is only a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A display substrate, comprising: The substrate includes a display area and a peripheral area surrounding the display area, the peripheral area including a fan-out area adjacent to the display area and a pad area on the side of the fan-out area away from the display area; The display area is provided with a plurality of sub-pixels arranged in a matrix, and each column of the sub-pixels is connected to a data line; the fan-out area includes a connection area adjacent to the display area, some of the data lines are directly connected to the connection pads located in the connection area, and other data lines are connected to the connection pads located in the connection area through data connection lines; The plurality of sub-pixels includes a plurality of columns of first color sub-pixels and a plurality of columns of second color sub-pixels, the connecting pads include a plurality of first connecting pads and a plurality of second connecting pads, the plurality of first connecting pads are electrically connected to the plurality of columns of first color sub-pixels, and the plurality of second connecting pads are electrically connected to the plurality of columns of second color sub-pixels; The fan-out area has multiple first signal transmission lines and multiple second signal transmission lines spaced apart near the pad area. The multiple first signal transmission lines are disposed on a first metal layer, and the multiple second signal transmission lines are disposed on a second metal layer located on a different layer than the first metal layer. The plurality of first signal transmission lines and the plurality of first connection pads are electrically connected to each other in a one-to-one correspondence; the plurality of second signal transmission lines and the plurality of second connection pads are electrically connected to each other in a one-to-one correspondence. Specifically, a data line group is defined as two adjacent data connection lines and at least two data lines located between the two adjacent data connection lines. The connection pads connected to at least two data lines in a data line group include at least one first connection pad and one second connection pad. In at least one data line group, the orthographic projections of the data line connected to the second connection pad and the first signal transmission line connected to the first connection pad on the substrate overlap in the fan-out region. Alternatively, the connection pads connected to the data lines and data connection lines in a data line group include one first connection pad and one second connection pad. In at least one data line group, the data connection line is electrically connected to the first connection pad or the second connection pad via a connection electrode. The orthographic projections of the connection electrode and an adjacent data line connected to it on the substrate overlap in the fan-out region. The data line and the data connection line are disposed in the third conductive layer, and the connection pads connected to two adjacent data lines in the data line group are respectively the first connection pad and the second connection pad. In the data line group, the first data line located in the odd-numbered column of two adjacent data lines crosses over and connects to the second data line located in the even-numbered column adjacent to it, which is the first signal transmission line. The second data line located in the even-numbered column extends towards the side of the first data line adjacent to it at the boundary between the display area and the fan-out area to be electrically connected to the corresponding first signal transmission line.

2. The display substrate according to claim 1, wherein, The first data line located in the odd-numbered column extends first towards the side closer to the pad area in the fan-out area, and then extends towards the adjacent second data line located in the even-numbered column to form an "L"-shaped structure or an inverted "L"-shaped structure. The second data line located in the even-numbered column extends first towards the side closer to the first data line in the fan-out area, and then extends towards the side closer to the pad area, so as to form an open quadrilateral with the first data line.

3. The display substrate according to claim 1, wherein, On a plane parallel to the main surface of the substrate, the first data line and the first signal transmission line connected to the second data line intersect; the second data line and the second signal transmission line electrically connected to the first data line do not intersect.

4. The display substrate according to any one of claims 1 to 3, wherein, The plurality of first signal transmission lines and the plurality of second signal transmission lines are arranged alternately in sequence.

5. The display substrate according to claim 4, wherein, In the pad area and in the second direction, there are multiple third signal transmission lines and multiple fourth signal transmission lines. The arrangement order of the sub-pixels connected to the multiple third signal transmission lines and the multiple fourth signal transmission lines is consistent with the arrangement order of the sub-pixels connected to the multiple data lines and the multiple data connection lines. A portion of the multiple third signal transmission lines is in an odd-numbered column, and another portion of the multiple third signal transmission lines is in an even-numbered column. A portion of the multiple fourth signal transmission lines is in an odd-numbered column, and another portion of the multiple fourth signal transmission lines is in an even-numbered column. At least one of the third signal transmission lines and the second data line corresponds to a sub-pixel of the same color, and at least one of the fourth signal transmission lines and the first data line corresponds to a sub-pixel of the same color.

6. The display substrate according to claim 5, wherein, The third signal transmission line arranged in an even-numbered column and the corresponding first signal transmission line are electrically connected through a first adapter wire, and the fourth signal transmission line arranged in an odd-numbered column and the corresponding second signal transmission line are electrically connected through a second adapter wire. The first adapter wire and the second adapter wire are located on different layers. The first adapter wire is on a first conductive layer, and the second adapter wire is on a second conductive layer. The first conductive layer and the second conductive layer are different layers.

7. The display substrate according to claim 6, wherein, The fourth signal transmission line arranged in an even-numbered column and the corresponding second signal transmission line are electrically connected through a fourth adapter wire, and the third signal transmission line arranged in an odd-numbered column and the corresponding first signal transmission line are electrically connected through a third adapter wire. Both the third adapter wire and the fourth adapter wire are disposed in the second conductive layer.

8. The display substrate according to claim 6 or 7, wherein, At least one third signal transmission line arranged in an even-numbered column and one fourth signal transmission line arranged in an odd-numbered column are arranged adjacent to each other, and on a plane parallel to the main surface of the substrate, the first adapter line connected to the at least one third signal transmission line arranged in an even-numbered column and the second adapter line connected to the fourth signal transmission line arranged in an odd-numbered column intersect.

9. The display substrate according to claim 1, wherein, The data line and the data connection line are disposed in the third conductive layer. At least one data connection line located in an odd-numbered column and one data line located in an even-numbered column are arranged adjacent to each other; The at least one data connection line located in an odd-numbered column crosses the adjacent data line located in an even-numbered column via a first connection electrode to be electrically connected to the first signal transmission line corresponding to the at least one data connection line located in an odd-numbered column. The first connection electrode is located in a second conductive layer, and the second conductive layer and the third conductive layer are different layers. The data line located in the even-numbered column is electrically connected to the corresponding second signal transmission line.

10. The display substrate according to claim 9, wherein, The first connection electrode extends at the location where the display area and the fan-out area meet, along a direction from the at least one data connection line located in an odd-numbered column to the one data line located in an even-numbered column.

11. The display substrate according to claim 1, wherein, The data line and the data connection line are disposed in the third conductive layer. At least one data line located in an odd-numbered column and one data connection line located in an even-numbered column are arranged adjacent to each other; The data connection line located in an even-numbered column crosses the adjacent at least one data line located in an odd-numbered column via a second connection electrode to be electrically connected to the second signal transmission line corresponding to the data connection line located in an even-numbered column. The second connection electrode is located in a second conductive layer, and the second conductive layer and the third conductive layer are different layers. The at least one data line located in an odd-numbered column is electrically connected to the corresponding first signal transmission line.

12. The display substrate according to claim 11, wherein, The second connection electrode extends at the location where the display area and the fan-out area meet, along a direction from one of the data connection lines located in an even-numbered column to the at least one of the data lines located in an odd-numbered column.

13. The display substrate according to any one of claims 9 to 12, wherein, The plurality of first signal transmission lines are located in even-numbered columns, and the plurality of second signal transmission lines are located in odd-numbered columns.

14. The display substrate according to any one of claims 9 to 12, wherein, At the junction of the fan-out area and the pad area, and in a second direction, multiple third signal transmission lines and multiple fourth signal transmission lines are arranged. The arrangement order of the sub-pixels connected to the multiple third signal transmission lines and the multiple fourth signal transmission lines is consistent with the arrangement order of the sub-pixels connected to the multiple data lines and the multiple data connection lines. A portion of the multiple third signal transmission lines is in odd-numbered columns, and another portion of the multiple third signal transmission lines is in even-numbered columns. A portion of the multiple fourth signal transmission lines is in odd-numbered columns, and another portion of the multiple fourth signal transmission lines is in even-numbered columns. Furthermore, each of the multiple third signal transmission lines and the first connection pad corresponds to a sub-pixel of the same color, and each of the multiple fourth signal transmission lines and the multiple second connection pads corresponds to a sub-pixel of the same color.

15. The display substrate according to claim 14, wherein, The third signal transmission line arranged in an odd-numbered column and the corresponding first signal transmission line are electrically connected through a first adapter wire, and the fourth signal transmission line arranged in an even-numbered column and the corresponding second signal transmission line are electrically connected through a second adapter wire. The first adapter wire is on a second conductive layer, and the second adapter wire is on a first conductive layer. The first conductive layer and the second conductive layer are different layers.

16. The display substrate according to claim 15, wherein, The third signal transmission line arranged in an even-numbered column and the corresponding first signal transmission line are electrically connected through a third adapter wire, and the fourth signal transmission line arranged in an odd-numbered column and the corresponding second signal transmission line are electrically connected through a fourth adapter wire. Both the third adapter wire and the fourth adapter wire are disposed in the second conductive layer.

17. The display substrate according to claim 16, wherein, At least one third signal transmission line arranged in an odd-numbered column and one fourth signal transmission line arranged in an even-numbered column are arranged adjacent to each other, and on a plane parallel to the main surface of the substrate, the first adapter line connected to the at least one third signal transmission line arranged in an odd-numbered column and the second adapter line connected to the fourth signal transmission line arranged in an even-numbered column intersect.

18. The display substrate according to claim 1, wherein, The fan-out region also includes a semiconductor layer, a first gate layer, a second gate layer, an interlayer insulating layer, a first conductive layer, a planarization layer, and a second conductive layer stacked sequentially. The first color sub-pixel includes a green sub-pixel, and the second color sub-pixel includes a red sub-pixel and a blue sub-pixel; A test unit is provided in the fan-out area. The test unit includes a first test switch transistor connected to the red sub-pixel and a second test switch transistor connected to the blue sub-pixel. The source of the first test switch transistor is connected to the first test signal input terminal, a portion of the second signal transmission line is electrically connected to the drain of the first test switch transistor, and the gate of the first test switch transistor is electrically connected to a first portion of the first conductive layer. The source of the second test switch transistor is connected to the second test signal input terminal, another part of the second signal transmission line is electrically connected to the drain of the second test switch transistor, and the gate of the second test switch transistor is electrically connected to the second part of the first conductive layer. The first portion and the second portion of the first conductive layer are spaced apart from each other.

19. A display device comprising a display substrate according to any one of claims 1 to 18.

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