Organic light emitting display device

Abstract

Disclosed is an organic light emitting display device including a substrate, a first signal line, a second signal line, a compensation line, and a bridge pattern, wherein the substrate defines a display area and a non-display area surrounding the display area, the display area includes a main area and at least one protruding area, and a plurality of pixels are located in the display area, the first signal line is located on the substrate in the main area to provide a signal to the plurality of pixels, the second signal line is located on the substrate in the at least one protruding area to provide a signal to the plurality of pixels, the compensation line is located on the substrate in the non-display area and is electrically connected to the second signal line, the bridge pattern is located over the second signal line and the compensation line in the non-display area and electrically connects the second signal line with the compensation line, and the bridge pattern includes a double bridge structure.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2017-0114511, filed on September 7, 2017, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. TECHNICAL FIELD

[0003] Aspects of embodiments of the present disclosure relate to an organic light emitting display device. BACKGROUND

[0004] With the development of multimedia technology, display devices are becoming increasingly important. Accordingly, various types of display devices are being used these days, such as liquid crystal display (LCD) devices and organic light emitting display (OLED) devices.

[0005] Among them, an organic light emitting display device displays an image by using an organic light emitting element that emits light when an electron and a hole are combined. Such an organic light emitting display device has advantages in that it has a fast response speed, high brightness, and a large viewing angle, and low power consumption.

[0006] In addition, since the organic light emitting display device is self-emissive, in which each pixel can generate light by itself, it has an advantage in that it allows a display area of a display image of various shapes, compared to other types of display devices.

[0007] An organic light emitting display device generally includes a plurality of pixels each displaying one of three colors of red, green, and blue. Each of the pixels can be individually driven by a driver arranged with a plurality of thin film transistors and various metal lines.

[0008] During a process of manufacturing an organic light emitting display device, a plurality of insulating layers and a plurality of metal layers are stacked with each other. In this way, an undesirable high static electricity can be generated during a process of stacking the insulating layers. If such static electricity is introduced into a driver of the organic light emitting display device, characteristics of the pixels can become different from each other, so that display quality can be deteriorated. SUMMARY

[0009] According to an aspect of embodiments of the present disclosure, there is provided an organic light emitting display device capable of preventing or substantially preventing display quality from being deteriorated due to static electricity.

[0010] These and other aspects, embodiments and advantages of the present disclosure will become apparent to those of ordinary skill in the art from the following description and the attached claims.

[0011] According to an exemplary embodiment of the present disclosure, an organic light emitting display device is capable of preventing or substantially preventing display quality from being deteriorated due to static electricity.

[0012] It should be noted that the effects of the present disclosure are not limited to the above-mentioned effects, and other effects of the present disclosure will be apparent to those skilled in the art from the following description. BRIEF DESCRIPTION OF DRAWINGS

[0013] The above and other aspects and features of the present disclosure will become more apparent from the following detailed description, taken in conjunction with the accompanying drawings, which illustrate several exemplary embodiments of the present disclosure, by the way of example, in which:

[0014] Figure 1 is a block diagram of an organic light emitting display apparatus according to an exemplary embodiment of the present disclosure;

[0015] Figure 2 is a circuit diagram of a pixel according to an exemplary embodiment of the present disclosure;

[0016] Figure 3 is a layout diagram of an organic light emitting display apparatus according to an exemplary embodiment of the present disclosure;

[0017] Figure 4 is Figure 3 an enlarged layout diagram of a region "A" of

[0018] Figure 5 is Figure 4 an enlarged layout diagram of a region "B" of

[0019] Figure 6 is a cross-sectional view taken along a line I-I' and a line II-II' of Figure 5

[0020] Figure 7 is a cross-sectional view taken along a line corresponding to a line I-I' and a line II-II' of Figure 5

[0021] Figure 8 is a cross-sectional view taken along a line corresponding to a line I-I' and a line II-II' of Figure 5

[0022] Figure 9 is a cross-sectional view taken along a line corresponding to a line I-I' and a line II-II' of Figure 5

[0023] Figure 10 is an enlarged layout diagram of a region "A" of Figure 3 DETAILED DESCRIPTION​​​​​

[0024] The present application will now be described in greater detail with reference to the accompanying drawings, which illustrate some exemplary embodiments of the application. This application may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the application to those skilled in the art. Like reference numerals refer to like elements throughout the specification. In the drawings, the thickness of layers and regions can be exaggerated for clarity.

[0025] It should be understood that, although the terms “first,” “second,” “third,” etc. can be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Thus, a first element discussed below could be termed a second element without departing from the teachings of the present application.

[0026] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular articles “a,” “an,” and “the” are intended to include the plural forms as well, including “at least one,” unless the content clearly indicates otherwise. “Or” means “and / or.” As used herein, the phrase “and / or” includes any and all combinations of one or more of the associated listed items. It will be understood that the terms “comprises” and / or “comprising,” or “includes” and / or “including” when used in this specification, specify the presence of stated features, regions, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components, and / or groups thereof.

[0027] For the purposes of this description, spatially relative terms such as “beneath,” “below,” “lower,” “above,” “upper,” and the like can be used to describe one element’s or feature’s relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. For example, if a device in the figures is inverted, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the exemplary term “below” can encompass both an orientation of above and below. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0028] Hereinafter, some exemplary embodiments of the present disclosure will be described in further detail with reference to the accompanying drawings.

[0029] Figure 1 is a block diagram of an organic light emitting display apparatus according to an exemplary embodiment of the present disclosure.

[0030] Referring to Figure 1 , the organic light emitting display apparatus 10 includes a display area DA, a signal controller 11, a data driver 12, a scan driver 13, a gate driver (not shown), and a power supply 14.

[0031] The display area DA can be an area in which an image is displayed. The display area DA according to an exemplary embodiment of the present disclosure is shown in Figure 1 as having a rectangular shape for illustrating circuit connections. However, the actual shape of the display area DA will be described in more detail later. The display area DA can include a plurality of gate lines, a plurality of data lines crossing the plurality of gate lines, and a plurality of pixels PX each connected to a corresponding gate line and data line. The plurality of data lines can extend in a column direction (e.g., a direction in which the number of rows increases). The plurality of gate lines can extend in a row direction (e.g., a direction in which the number of columns increases). A plurality of power supply lines can also be disposed in the display area DA. Each of the plurality of power supply lines can be connected to a corresponding pixel PX.

[0032] The signal controller 11 can receive a control signal CS and image signals R, G, and B from an external device. The image signals R, G, and B contain luminance information of a plurality of pixels PX. In an embodiment, the control signal CS can include a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, and a clock signal. The signal controller 11 can generate first to third drive control signals CONT1 to CONT3 and image data DATA according to the image signals R, G, and B and the control signal CS.

[0033] The gate driver can be connected to the plurality of gate lines in the display area DA and can generate a plurality of gate signals G1 to Gn according to the second drive control signal CONT2. The gate driver can sequentially apply the plurality of gate signals G1 to Gn at a gate-on voltage level to the plurality of gate lines.

[0034] The data driver 12 can be connected to a plurality of data lines in the display area DA, and can sample and hold image data DATA input in response to a first driving control signal CONT1 and convert it into an analog voltage, thereby generating a plurality of data signals D1 to Dm. The data driver 12 can transmit the plurality of data signals D1 to Dm to the corresponding data lines. The pixels PX in the display area DA can be individually turned on when receiving the gate signals G1 to Gn at the gate-on voltage level, and can receive the data signals D1 to Dm.

[0035] The scan driver 13 can be connected to a plurality of gate lines in the display area DA, and can generate and provide a plurality of scan signals G1 to Gn to the gate lines in response to a second driving control signal CONT2.

[0036] The power supply 14 can supply a first power voltage ELVDD and a second power voltage ELVSS to a plurality of power supply lines connected to the plurality of pixels PX. The first power voltage ELVDD and the second power voltage ELVSS can generate a driving current for each of the pixels PX.

[0037] Although not shown in the drawing, the gate signals G1 to Gn, the data signals D1 to Dm, the first power voltage ELVDD, the second power voltage ELVSS, and other signals can be provided to each of the pixels PX via additional lines. In an embodiment, these signals can be used to initialize certain nodes, thereby compensating for a threshold voltage and detecting and compensating for degradation, thereby improving the display quality of the organic light emitting display device 10.

[0038] Figure 2 is a circuit diagram of a pixel according to an exemplary embodiment of the disclosure.

[0039] Referring to Figure 2 The pixel PX includes a first transistor T1, a second transistor T2, a first capacitor C1, and an organic light emitting element EL.

[0040] The first transistor T1 can include a control electrode connected to a gate line GL, an input electrode connected to a data line DL, and an output electrode connected to a first node N1. The first transistor T1 can be turned on when receiving a gate signal having a voltage level of an on level applied to the gate line GL, and can transmit a data signal to the first node N1.

[0041] The second transistor T2 can include a control electrode connected to the first node N1, an input electrode connected to a second node N2, and an output electrode connected to an anode of the organic light emitting element EL. The second node N2 can receive a first power voltage ELVDD.

[0042] A first capacitor C1 can be disposed between the first node N1 and the second node N2. A data signal provided from the first transistor T1 can charge the first capacitor C1 with a corresponding voltage. The first capacitor C1 can maintain a voltage at a control electrode of the second transistor T2 at a predetermined level. The second transistor T2 can control a driving current supplied to the organic light emitting element EL from the first power voltage ELVDD based on the voltage maintained at the first node N1.

[0043] The organic light emitting element EL can include an anode connected to a third node (not shown), a cathode connected to a second power voltage ELVSS, and an organic light emitting layer (not shown). The organic light emitting layer can emit light of one of primary colors. In an embodiment, the primary colors can be three colors of red, green, and blue. A desired color can be displayed by combining the three primary colors in the same space or at the same time. The organic light emitting layer (not shown) can include small molecule organic materials or polymer organic materials corresponding to each color. The organic materials corresponding to each color can emit light according to an amount of current flowing through the organic light emitting layer (not shown).

[0044] Figure 3 is a layout diagram of an organic light emitting display apparatus according to an exemplary embodiment of the present disclosure.

[0045] Referring to Figure 3 , an organic light emitting display apparatus 10 according to an exemplary embodiment of the present disclosure includes a display area DA in which a plurality of pixels PX are disposed to display an image, and a non-display area BA different from the display area DA.

[0046] The display area DA displays an image as described above, and includes a plurality of pixels PX.

[0047] According to an exemplary embodiment of the present disclosure, the display area DA can include a main area MA, a first protruding area TA1, and a second protruding area TA2. The main area MA occupies a majority of the display area DA and can have a substantially rectangular shape. The first protruding area TA1 and the second protruding area TA2 can be formed in contact with the main area MA, and can be areas for displaying an image having a shape protruding from the main area MA in a particular direction. According to an exemplary embodiment, as depicted in Figure 3 , the first protruding area TA1 can be disposed at an upper left end of the main area MA, and the second protruding area TA2 can be disposed at an upper right end of the main area MA.

[0048] When the display area DA has such a shape, the length of the gate lines GL, the length of the data lines DL, and the length of the power supply lines can be different in the main area MA, in the first protruding area TA1, and in the second protruding area TA2 depending on the direction in which they extend. In particular, the difference in length between the lines can be sharp at the boundary between the main area MA and the first protruding area TA1 and at the boundary between the main area MA and the second protruding area TA2.

[0049] In this case, the resistance of each of the lines and the capacitance with respect to the other lines can also vary sharply, so that mura can be observed at the boundary between the main area MA and the first protruding area TA1 and at the boundary between the main area MA and the second protruding area TA2, thereby degrading the display quality.

[0050] Therefore, an additional compensation wiring structure is used to prevent or substantially prevent this case, as will be described in further detail later.

[0051] The non-display area BA does not display an image, but includes elements for displaying an image on the display area DA. In an embodiment, the non-display area BA can be arranged so that it surrounds the display area DA.

[0052] Circuit elements, driving chips, and electronic components for performing the functions of the signal controller 11, the data driver 12, the gate driver, and the power supply 14 can be arranged in the non-display area BA. In addition, a compensation wiring structure can be arranged to prevent or substantially prevent mura at the boundary between the main area MA and the first protruding area TA1 and at the boundary between the main area MA and the second protruding area TA2.

[0053] Figure 4 is Figure 3 An enlarged layout view of the area "A".

[0054] Referring to Figure 4 , the organic light emitting display device 10 includes a display area DA and a non-display area BA, wherein the display area DA includes a main area MA, a first protruding area TA1, and a second protruding area TA2, and the non-display area BA surrounds the display area DA.

[0055] A plurality of gate lines GL1_MA to GLn_MA, GL1_TA1 to GLx_TA1, and GL1_TA2 to GLx_TA2 extending in a first direction dr1 and a plurality of data lines DL1 to DLm extending in a second direction dr2 can be arranged in the display area DA.

[0056] In observing the entire display area DA (i.e., from Figure 3When the data lines DL1 to DLm are arranged in the display area DA without a sharp difference in length (in the case of the viewpoint of the data lines DL1 to DLm), the data lines DL1 to DLm can be arranged in the display area DA without a sharp difference in length. Accordingly, the difference in length of the data lines DL1 to DLm can not significantly degrade the display quality.

[0057] On the other hand, since the gate lines GL1_MA to GLn_MA, GL1_TA1 to GLx_TA1, and GL1_TA2 to GLx_TA2 extend in the first direction dr1, they cannot pass through the first protruding area TA1 and the second protruding area TA2 together. Accordingly, the lengths of the gate lines GL1_MA to GLn_MA arranged in the main area MA, the lengths of the gate lines GL1_TA1 to GLx_TA1 arranged in the first protruding area TA1, and the lengths of the gate lines GL1_TA2 to GLx_TA2 arranged in the second protruding area TA2 can be significantly different from each other.

[0058] In particular, the two gate lines GL1_MA and GLx_TA1 arranged at the boundary between the main area MA and the first protruding area TA1 can have a relatively large difference in length compared to other lines. Likewise, the two gate lines GL1_MA and GLx_TA2 arranged at the boundary between the main area MA and the second protruding area TA2 can have a relatively large difference in length compared to other lines.

[0059] In view of the above, according to an exemplary embodiment, the organic light emitting display device 10 can further include compensation lines CL1_TA1 to CLx_TA1 and CL1_TA2 to CLx_TA2 arranged in the non-display area BA, wherein the compensation lines CL1_TA1 to CLx_TA1 and CL1_TA2 to CLx_TA2 are electrically connected to the gate lines GL1_TA1 to GLx_TA1 arranged in the first protruding area TA1 and the gate lines GL1_TA2 to GLx_TA2 arranged in the second protruding area TA2, respectively.

[0060] The gate lines GL1_TA1 to GLx_TA1 arranged in the first protruding area TA1 and the gate lines GL1_TA2 to GLx_TA2 arranged in the second protruding area TA2 are connected to the compensation lines CL1_TA1 to CLx_TA1 and CL1_TA2 to CLx_TA2, respectively, such that their lengths are increased. That is, the gate lines GL1_TA1 to GLx_TA1 arranged in the first protruding area TA1 and the gate lines GL1_TA2 to GLx_TA2 arranged in the second protruding area TA2 are connected to the compensation lines CL1_TA1 to CLx_TA1 and CL1_TA2 to CLx_TA2, respectively, such that they can have resistance values similar to those of the gate lines GL1_MA to GLn_MA arranged in the main area MA. As a result, degradation of the display quality can be reduced.

[0061] Further, a compensation metal pattern CMP_TA1 and CMP_TA2 can be arranged in the non-display area BA, the compensation metal pattern CMP_TA1 and CMP_TA2 being arranged to overlap a portion of each of the compensation lines CL1_TA1 to CLx_TA1 and CL1_TA2 to CLx_TA2 and having a plate shape covering a certain area. The compensation metal pattern CMP_TA1 and CMP_TA2 can be controlled so that the gate lines GL1_TA1 to GLx_TA1 arranged in the first protruding area TA1 and the gate lines GL1_TA2 to GLx_TA2 arranged in the second protruding area TA2 have a similar capacitance value to that of the gate lines GL1_MA to GLn_MA arranged in the main area MA.

[0062] In particular, in a cross section, the power supply lines for supplying the first power supply voltage ELVDD to each of the pixels PX are arranged closer to the gate lines GL1_MA to GLn_MA, GL1_TA1 to GLx_TA1 and GL1_TA2 to GLx_TA2 than the power supply lines for supplying the second power supply voltage ELVSS to each of the pixels PX, and thus, they can form a stronger capacitance with the gate lines GL1_MA to GLn_MA, GL1_TA1 to GLx_TA1 and GL1_TA2 to GLx_TA2 than other lines. Further, since the power supply lines for supplying the first power supply voltage ELVDD to each of the pixels PX continuously provide a constant voltage level or a signal having a relatively small amount of voltage variation, they can form a stronger capacitance with the gate lines GL1_MA to GLn_MA, GL1_TA1 to GLx_TA1 and GL1_TA2 to GLx_TA2 than other lines. Accordingly, the compensation metal patterns CMP_TA1 and CMP_TA2 can be formed by using metal made of the same material as the power supply lines providing the first power supply voltage ELVDD on the same layer. Further, the first power supply voltage ELVDD can be applied to the compensation metal patterns CMP_TA1 and CMP_TA2.

[0063] The gate lines GL1_TA1 to GLx_TA1 arranged in the first protruding area TA1 and the gate lines GL1_TA2 to GLx_TA2 arranged in the second protruding area TA2 are connected to the respective compensation lines CL1_TA1 to CLx_TA1 and CL1_TA2 to CLx_TA2 via a plurality of bridge patterns BP1_TA1 to BPx_TA1 and BP1_TA2 to BPx_TA2, respectively.

[0064] In the cross-section of the organic light emitting display device 10, each of the bridge patterns BP1_TA1 to BPx_TA1 and BP1_TA2 to BPx_TA2 can be mechanically connected to lines on both sides thereof via at least two metal wiring layers to electrically connect the lines. Due to the structure of the bridge patterns BP1_TA1 to BPx_TA1 and BP1_TA2 to BPx_TA2, unintended high voltage static that can occur in the non-display area BA during the process of manufacturing the organic light emitting display device 10 can be prevented or substantially prevented from adversely affecting the drivers of the pixels PX arranged in the display area DA. Accordingly, degradation of the display quality of the organic light emitting display device 10 can be reduced.

[0065] Although the structure has been described as being for compensating characteristics of resistance and capacitance of the gate lines GL1_MA to GLn_MA, GL1_TA1 to GLx_TA1, and GL1_TA2 to GLx_TA2, it should be noted that this is merely illustrative. For example, depending on the direction in which the first and second protruding areas TA1 and TA2 protrude or the direction in which the data lines DL1 to DLm extend, the structure can be for compensating characteristics of resistance and capacitance of the data lines DL1 to DLm. Furthermore, in addition to being for compensating characteristics of the gate lines GL1_MA to GLn_MA, GL1_TA1 to GLx_TA1, and GL1_TA2 to GLx_TA2 or the data lines DL1 to DLm, the structure can also be for compensating resistance and capacitance of various lines for initializing certain nodes of the pixels PX, compensating threshold voltage of the second transistor T2, sensing the organic light emitting element EL, and compensating degradation caused by use thereof.

[0066] In addition, although the display area DA is described and illustrated as having a shape including the main area MA and two protruding areas TA1 and TA2 in the above-described exemplary embodiments, it should be understood that a compensation structure for a display area DA having a different shape is also possible. Furthermore, it should be understood that in various embodiments, the display area DA can include more or less than two protruding areas, and the display area DA can have a shape other than a rectangle without protruding areas.

[0067] The structure of the compensation lines CL1_TA1 to CLx_TA1 and CL1_TA2 to CLx_TA2 and the bridge patterns BP1_TA1 to BPx_TA1 and BP1_TA2 to BPx_TA2 will be described in more detail below.

[0068] Figure 5 is an enlarged layout view of the area "B" of Figure 4 is a cross-sectional view taken along the line I-I' and the line II-II' of Figure 6 Figure 5 ​​

[0069] Figure 5 and Figure 6 further illustrates a portion of the compensation lines CL1_TA1 to CLx_TA1 and a portion of the bridge patterns BP1_TA1 to BPx_TA1 arranged in a first protruding area TA1 of the gate lines GL1_TA1, GL2_TA1 and GL3_TA1. Figure 4

[0070] Referring to Figure 5 and Figure 6 , the organic light emitting display device 10 according to an exemplary embodiment of the disclosure includes a lower substrate 110, a buffer layer 120, a first insulating layer 130, gate lines GL1_TA1, GL2_TA1 and GL3_TA1, compensation lines CL1_TA1, CL2_TA1 and CL3_TA1, a second insulating layer 140, bridge patterns BP1_TA1, BP2_TA1 and BP3_TA1, and a planarization layer PL.

[0071] In an exemplary embodiment, the lower substrate 110 can be an insulating substrate. In an embodiment, the lower substrate 110 can include a glass substrate, a quartz substrate, a ceramic substrate, or a plastic substrate. In another exemplary embodiment, the lower substrate 110 can be a flexible substrate capable of being bent, folded, or rolled. Such a lower substrate 110 can include, but is not limited to, polyimide.

[0072] The buffer layer 120 can be arranged on the lower substrate 110. The buffer layer 120 can prevent or substantially prevent penetration of impurity elements, and can provide a flat surface. In an exemplary embodiment, the buffer layer 120 can include a silicon nitride (SiN x ) layer, a silicon oxide (SiO2) layer, or a silicon oxynitride (SiO x N y ) layer. In an embodiment, the buffer layer 120 can be omitted depending on the type of the lower substrate 110, process conditions, etc.

[0073] Although not shown in the drawings, in an embodiment, a semiconductor layer can be arranged on the buffer layer 120. The semiconductor layer (not shown) can be an element for driving a switching transistor of each of the pixels PX. In an embodiment, the semiconductor layer (not shown) can be made of amorphous silicon, polysilicon, single crystal silicon, low temperature polysilicon, and oxide semiconductor, or a mixture thereof.

[0074] The buffer layer 120 and the semiconductor layer (not shown) have the first insulating layer 130 arranged thereon. In an exemplary embodiment, the first insulating layer 130 can be a gate insulating layer. The first insulating layer 130 can be made of a material selected from the group consisting of, for example, silicon oxide (SiO x ) and silicon nitride (SiN x ​It is made of at least one or a mixture thereof, consisting of inorganic insulating materials, benzocyclobutene (BCB), acrylic materials and organic insulating materials such as polyimide.

[0075] Gate lines GL1_TA1, GL2_TA1, and GL3_TA1 are arranged on the first insulating layer 130. Additionally, compensation lines CL1_TA1, CL2_TA1, and CL3_TA1 are also arranged on the first insulating layer 130, electrically connected to the gate lines GL1_TA1, GL2_TA1, and GL3_TA1 via bridging patterns BP1_TA1, BP2_TA1, and BP3_TA1, respectively.

[0076] Gate lines GL1_TA1, GL2_TA1 and GL3_TA1 may extend from each pixel row toward the non-display area BA in the first direction dr1 and are respectively connected to the bridging patterns BP1_TA1, BP2_TA1 and BP3_TA1 on one side.

[0077] Compensation lines CL1_TA1, CL2_TA1, and CL3_TA1 can be connected to bridging patterns BP1_TA1, BP2_TA1, and BP3_TA1 on opposite sides that are not connected to gate lines GL1_TA1, GL2_TA1, and GL3_TA1, respectively. Furthermore, compensation lines CL1_TA1, CL2_TA1, and CL3_TA1 can be arranged in the non-display area BA such that they surround the first protruding area TA1.

[0078] For example, the compensation lines CL1_TA1, CL2_TA1, and CL3_TA1, as well as the gate lines GL1_TA1, GL2_TA1, and GL3_TA1, may include at least one of aluminum (Al)-based metals containing aluminum alloys, silver (Ag)-based metals containing silver alloys, copper (Cu)-based metals containing copper alloys, molybdenum (Mo)-based metals containing molybdenum alloys, chromium (Cr), titanium (Ti), and tantalum (Ta).

[0079] A second insulating layer 140 is disposed on the compensation lines CL1_TA1, CL2_TA1, and CL3_TA1, and the gate lines GL1_TA1, GL2_TA1, and GL3_TA1. In an embodiment, the second insulating layer 140 may be made of a material selected from silicon oxide (SiO2). x ) and silicon nitride (SiN) x It is made of at least one or a mixture thereof, consisting of inorganic insulating materials, benzocyclobutene (BCB), acrylic materials and organic insulating materials such as polyimide.

[0080] The first bridge metal patterns BM11_TA1, BM12_TA1, and BM13_TA1 and the second bridge metal patterns BM21_TA1, BM22_TA1, and BM23_TA1 are disposed on the second insulating layer 140. In addition, the compensation metal pattern CMP_TA1 is disposed on the second insulating layer 140.

[0081] The first bridge metal patterns BM11_TA1, BM12_TA1, and BM13_TA1 and the second bridge metal patterns BM21_TA1, BM22_TA1, and BM23_TA1 can be some of elements of the bridge patterns BP1_TA1, BP2_TA1, and BP3_TA1. The first bridge metal patterns BM11_TA1, BM12_TA1, and BM13_TA1 and the second bridge metal patterns BM21_TA1, BM22_TA1, and BM23_TA1 can form third bridge metal patterns BM31_TA1, BM32_TA1, and BM33_TA1.

[0082] The first bridge metal patterns BM11_TA1, BM12_TA1, and BM13_TA1 can be mechanically and electrically connected to the gate lines GL1_TA1, GL2_TA1, and GL3_TA1, respectively, via contact holes that penetrate the second insulating layer 140. In addition, the second bridge metal patterns BM21_TA1, BM22_TA1, and BM23_TA1 can be mechanically and electrically connected to the compensation lines CL1_TA1, CL2_TA1, and CL3_TA1, respectively, via contact holes that penetrate the second insulating layer 140.

[0083] As such, instead of directly connecting the gate lines GL1_TA1, GL2_TA1, and GL3_TA1 and the compensation lines CL1_TA1, CL2_TA1, and CL3_TA1, by electrically connecting them via the first bridge metal patterns BM11_TA1, BM12_TA1, and BM13_TA1 and the second bridge metal patterns BM21_TA1, BM22_TA1, and BM23_TA1, it is possible to reduce static electricity that can occur due to the formation of the second insulating layer 140 and elements on the second insulating layer 140, thereby preventing or substantially preventing degradation of display quality. More specifically, it is possible to prevent or substantially prevent static electricity that can occur in the compensation lines CL1_TA1, CL2_TA1, and CL3_TA1 in the non-display area BA as the second insulating layer 140 and elements on the second insulating layer 140 are formed from being introduced into each of the pixels PX via the gate lines GL1_TA1, GL2_TA1, and GL3_TA1, thereby reducing degradation of display quality. In other words, the bridge patterns BP1_TA1, BP2_TA1, and BP3_TA1 can be a double bridge structure.

[0084] The compensation metal pattern CMP_TA1 can be arranged as a planar electrode in a portion of the non-display area BA. As Figure 6 As shown in FIG. 2, the compensation metal pattern CMP_TA1 can be arranged such that it faces the compensation lines CL1_TA1, CL2_TA1, and CL3_TA1, with the second insulating layer 140 therebetween. As a result, each of the compensation lines CL1_TA1, CL2_TA1, and CL3_TA1 forms a compensation capacitance Ccp with the compensation metal pattern CMP_TA1. With this structure, the gate lines GL1_TA1, GL2_TA1, and GL3_TA1 arranged in the first protruding area TA1 can have a similar capacitance value to that of the gate lines GL1_MA to GLn_MA arranged in the main area MA.

[0085] According to an exemplary embodiment, the width in the first direction dr1 of the first protruding area TA1 decreases toward the top of the first protruding area TA1. Accordingly, in the viewpoint of the first gate line GL1_TA1 at the top, the first gate line GL1_TA1 can form the smallest capacitance with the adjacent lines. Therefore, the area in which the compensation metal pattern CMP_TA1 overlaps the gate line GL1_TA1 at the top can be the largest. Accordingly, as shown in FIG. 2, the width of the compensation metal pattern CMP_TA1 in the first direction dr1 can vary depending on the location. Figure 5 Figure 5 According to an exemplary embodiment, the width in the first direction dr1 of the first protruding area TA1 decreases toward the top of the first protruding area TA1. Accordingly, in the viewpoint of the first gate line GL1_TA1 at the top, the first gate line GL1_TA1 can form the smallest capacitance with the adjacent lines. Therefore, the area in which the compensation metal pattern CMP_TA1 overlaps the gate line GL1_TA1 at the top can be the largest. Accordingly, as shown in FIG. 2, the width of the compensation metal pattern CMP_TA1 in the first direction dr1 can vary depending on the location. Figure 4

[0086] As described above, the first power voltage ELVDD can be applied to the compensation metal pattern CMP_TA1. However, the voltage applied to the compensation metal pattern CMP_TA1 can not be limited thereto.

[0087] The first bridge metal patterns BM11_TA1, BM12_TA1, and BM13_TA1, the second bridge metal patterns BM21_TA1, BM22_TA1, and BM23_TA1, and the compensation metal pattern CMP_TA1 can include at least one selected from the group consisting of a metal, an alloy, a metal nitride, a conductive metal oxide, and a transparent conductive material. In an exemplary embodiment, they can have a single-layer structure or a multi-layer structure made of (Ni), cobalt (Co), titanium (Ti), silver (Ag), copper (Cu), molybdenum (Mo), aluminum (Al), beryllium (Be), niobium (Nb), gold (Au), iron (Fe), selenium (Se), tantalum (Ta), etc. In addition, they can be made of an alloy formed by adding at least one element selected from the group consisting of titanium (Ti), zirconium (Zr), tungsten (W), tantalum (Ta), niobium (Nb), platinum (Pt), hafnium (Hf), oxygen (O), and nitrogen (N) to any of the above-described metals.

[0088] ​​The first bridge metal patterns BM11_TA1, BM12_TA1, and BM13_TA1, the second bridge metal patterns BM21_TA1, BM22_TA1, and BM23_TA1, and the compensation metal pattern CMP_TA1 are disposed with a planarization layer PL.

[0089] A top surface of the planarization layer PL can be substantially flat. Accordingly, a light emitting efficiency of an organic light emitting element EL, which is described later, can be increased. In an exemplary embodiment, the planarization layer PL can include an organic material. For example, the planarization layer PL can include at least one selected from the group consisting of polyimide, polyacrylic acid, and polysiloxane.

[0090] The third bridge metal patterns BM31_TA1, BM32_TA1, and BM33_TA1 are disposed on the planarization layer PL. The third bridge metal patterns BM31_TA1, BM32_TA1, and BM33_TA1 can be elements of the bridge patterns BP1_TA1, BP2_TA1, and BP3_TA1, respectively.

[0091] The third bridge metal patterns BM31_TA1, BM32_TA1, and BM33_TA1 on one side can be mechanically and electrically connected to the first bridge metal patterns BM11_TA1, BM12_TA1, and BM13_TA1, respectively, via contact holes that penetrate the planarization layer PL. The third bridge metal patterns BM31_TA1, BM32_TA1, and BM33_TA1 on the other side can be mechanically and electrically connected to the second bridge metal patterns BM21_TA1, BM22_TA1, and BM23_TA1, respectively, via contact holes that penetrate the planarization layer PL. Accordingly, the third bridge metal patterns BM31_TA1, BM32_TA1, and BM33_TA1 can electrically connect the first bridge metal patterns BM11_TA1, BM12_TA1, and BM13_TA1 with the second bridge metal patterns BM21_TA1, BM22_TA1, and BM23_TA1, respectively.

[0092] Thus, instead of directly connecting the first bridge metal patterns BM11_TA1, BM12_TA1, and BM13_TA1 with the second bridge metal patterns BM21_TA1, BM22_TA1, and BM23_TA1, by electrically connecting them via the third bridge metal patterns BM31_TA1, BM32_TA1, and BM33_TA1, it is possible to reduce static electricity that can occur due to the formation of the planarization layer PL and the elements on the planarization layer PL, thereby preventing or substantially preventing deterioration of display quality. More specifically, it is possible to prevent or substantially prevent static electricity that can occur in the compensation metal patterns CMP_TA1 in the non-display area BA as the planarization layer PL and the elements on the planarization layer PL are formed from being introduced into each of the pixels PX via the compensation lines CL1_TA1, CL2_TA1, and CL3_TA1, the second bridge metal patterns BM21_TA1, BM22_TA1, and BM23_TA1, and the first bridge metal patterns BM11_TA1, BM12_TA1, and BM13_TA1 due to the compensation capacitance Ccp, thereby reducing deterioration of display quality.

[0093] In an embodiment, the third bridge metal patterns BM31_TA1, BM32_TA1, and BM33_TA1 can be made of a reflective metal such as aluminum, silver, chromium, or an alloy thereof. However, it should be understood that this is merely illustrative. In an embodiment, the third bridge metal patterns BM31_TA1, BM32_TA1, and BM33_TA1 can be made of the same material as the material of the electrodes of the organic light emitting elements EL.

[0094] In the present embodiment, some of the gate lines GL1_TA1, GL2_TA1, and GL3_TA1, some of the compensation lines CL1_TA1, CL2_TA1, and CL3_TA1, and some of the bridge patterns BP1_TA1, BP2_TA1, and BP3_TA1 have been described as examples. However, it should be understood that the exemplary embodiments of the present disclosure are not limited thereto. That is, although not shown in Figure 5 and Figure 6 , the above description can equally apply to other gate lines, other compensation lines, and other bridge patterns arranged in the first protruding area TA1. It should be understood that the description can equally apply to the second protruding area TA2 as well.

[0095] Figure 7 is a cross-sectional view taken along a line corresponding to the line I-I' and the line II-II' of Figure 5 the organic light emitting display device according to another exemplary embodiment of the present disclosure.

[0096] The elements and reference numerals described above with respect to Figures 1 to 6 will not be described again.

[0097] Referring to Figure 7 , the organic light emitting display device 10 according to another exemplary embodiment of the present disclosure includes a lower substrate 110, a buffer layer 120, a compensation semiconductor pattern CAP_TA1, a first insulating layer 130, gate lines GL1_TA1, GL2_TA1, and GL3_TA1, compensation lines CL1_TA1, CL2_TA1, and CL3_TA1, a second insulating layer 140, bridge patterns BP1_TA1, BP2_TA1, and BP3_TA1, and a planarization layer PL.

[0098] That is, unlike the organic light emitting display device 10 shown in Figures 1 to 6 , the organic light emitting display device 10 according to the present exemplary embodiment further includes a compensation semiconductor pattern CAP_TA1.

[0099] The compensation semiconductor pattern CAP_TA1 is disposed on the buffer layer 120. The compensation semiconductor pattern CAP_TA1 can form a capacitance with the compensation line CL1_TA1. That is, in addition to the compensation metal pattern CMP_TA1 for forming a first compensation capacitance Ccp1 with the compensation line CL1_TA1 to prevent or substantially prevent degradation of display quality, the compensation semiconductor pattern CAP_TA1 is additionally disposed to form a second compensation capacitance Ccp2 with the compensation line CL1_TA1. As a result, degradation of display quality can be more effectively prevented.

[0100] The compensation semiconductor pattern CAP_TA1 can be disposed so as to overlap the compensation metal pattern CMP_TA1. Although not shown in the drawings, the compensation semiconductor pattern CAP_TA1 can have the same shape as the compensation metal pattern CMP_TA1. However, it should be understood that this is merely illustrative. In an embodiment, the compensation semiconductor pattern CAP_TA1 can be formed as a continuous pad overlapping the compensation metal pattern CMP_TA1. In addition, the compensation semiconductor pattern CAP_TA1 can be formed in various shapes capable of forming a capacitance with the compensation line CL1_TA1.

[0101] In an embodiment, the compensation semiconductor pattern CAP_TA1 can be formed of the same material as a semiconductor layer (not shown) on the same layer.

[0102] Figure 8 is a cross-sectional view of an organic light emitting display device according to another exemplary embodiment of the present disclosure taken along a line corresponding to line I-I' and line II-II' of Figure 5 .

[0103] The elements and reference numerals already described above with respect to Figures 1 to 6 will not be described again.

[0104] Referring to Figure 8According to another exemplary embodiment of the present disclosure, an organic light emitting display device 10 includes a lower substrate 110, a buffer layer 120, a first insulating layer 130, gate lines GL1_TA1, GL2_TA1, and GL3_TA1, a second insulating layer 140, compensation lines CL1_TA1, CL2_TA1, and CL3_TA1, a third insulating layer 150, bridge patterns BP1_TA1, BP2_TA1, and BP3_TA1, and a planarization layer PL.

[0105] That is, unlike the organic light emitting display device 10 shown in FIG. 1A, the organic light emitting display device 10 according to the present exemplary embodiment further includes the third insulating layer 150. Accordingly, the positions of the lines can be adjusted. In an embodiment, the third insulating layer 150 can be made of the same material as the first insulating layer 130 and the second insulating layer 140 described above. Figures 1 to 6 The buffer layer 120 is disposed on the lower substrate 110.

[0106] The first insulating layer 130 is disposed on the buffer layer 120.

[0107] The gate lines GL1_TA1, GL2_TA1, and GL3_TA1 are disposed on the first insulating layer 130.

[0108] The second insulating layer 140 is disposed on the gate lines GL1_TA1, GL2_TA1, and GL3_TA1.

[0109] The compensation line CL1_TA1 is disposed on the second insulating layer 140.

[0110] The third insulating layer 150 is disposed on the compensation line CL1_TA1.

[0111] The first bridge metal pattern BM11_TA1, the second bridge metal pattern BM21_TA1, and the compensation metal pattern CMP_TA1 are disposed on the third insulating layer 150. The first bridge metal pattern BM11_TA1 can be mechanically and electrically connected to the gate line GL1_TA1 via a contact hole that penetrates the second insulating layer 140 and the third insulating layer 150. In addition, the second bridge metal pattern BM21_TA1 can be mechanically and electrically connected to the compensation line CL1_TA1 via a contact hole that penetrates the third insulating layer 150.

[0112] The planarization layer PL is disposed on the first bridge metal pattern BM11_TA1, the second bridge metal pattern BM21_TA1, and the compensation metal pattern CMP_TA1.

[0113] The third bridge metal pattern BM31_TA1 is disposed on the planarization layer PL.

[0114]

[0115] ​That is, the organic light emitting display device 10 according to the present exemplary embodiment uses more layers than the organic light emitting display device 10 shown in Figures 1 to 6 to prevent or substantially prevent display quality deterioration.

[0116] Figure 9 is a cross-sectional view taken along a line corresponding to the line I-I' and the line II-II' of the organic light emitting display device according to another exemplary embodiment of the present disclosure. Figure 5

[0117] The elements described above with respect to Figure 8 will not be described again.

[0118] Referring to Figure 9 , the organic light emitting display device 10 according to another exemplary embodiment of the present disclosure includes a lower substrate 110, a buffer layer 120, a first insulating layer 130, gate lines GL1_TA1, GL2_TA1, and GL3_TA1, a second insulating layer 140, compensation lines CL1_TA1, CL2_TA1, and CL3_TA1, a third insulating layer 150, a fourth insulating layer 160, bridge patterns BP1_TA1, BP2_TA1, and BP3_TA1, and a planarization layer PL.

[0119] That is, unlike the organic light emitting display device 10 shown in Figure 8 , the organic light emitting display device 10 according to the present exemplary embodiment further includes the fourth insulating layer 160. Unlike the embodiment shown in Figure 8 in which the third bridge metal pattern BM31_TA1 can be made of a material of an electrode of the organic light emitting element EL, the third bridge metal pattern BM31_TA1 can be formed by using another metal layer made of the same material as the first bridge metal pattern BM11_TA1 and the second bridge metal pattern BM21_TA1.

[0120] The buffer layer 120 is disposed on the lower substrate 110. The first insulating layer 130 is disposed on the buffer layer 120. The gate lines GL1_TA1, GL2_TA1, and GL3_TA1 are disposed on the first insulating layer 130. The second insulating layer 140 is disposed on the gate lines GL1_TA1, GL2_TA1, and GL3_TA1. The compensation line CL1_TA1 is disposed on the second insulating layer 140. The third insulating layer 150 is disposed on the compensation line CL1_TA1. The first bridge metal pattern BM11_TA1, the second bridge metal pattern BM21_TA1, and the compensation metal pattern CMP_TA1 are disposed on the third insulating layer 150.

[0121] ​A fourth insulating layer 160 is disposed on the first bridge metal pattern BM11_TA1, the second bridge metal pattern BM21_TA1, and the compensation metal pattern CMP_TA1. In an embodiment, the fourth insulating layer 160 can be made of at least one selected from the group consisting of inorganic insulating materials such as silicon oxide (SiO x ) and silicon nitride (SiN x ), benzocyclobutene (BCB), an acrylic material, and an organic insulating material such as polyimide, or a mixture thereof.

[0122] A third bridge metal pattern BM31_TA1 is disposed on the fourth insulating layer 160. The third bridge metal pattern BM31_TA1 can be mechanically and electrically connected to the first bridge metal pattern BM11_TA1 and the second bridge metal pattern BM21_TA1 through a contact hole that penetrates the fourth insulating layer 160.

[0123] A planarization layer PL is disposed on the fourth insulating layer 160. An organic light emitting element EL is disposed on the planarization layer PL.

[0124] That is, the organic light emitting display device 10 according to the present exemplary embodiment can form the third bridge metal pattern BM31_TA1 by using another metal layer made of the same material as the first bridge metal pattern BM11_TA1 and the second bridge metal pattern BM21_TA1. Although not shown in the drawings, in the embodiment shown in FIG. 1, the third bridge metal pattern BM31_TA1 can be formed by using a metal layer made of the same material as the first bridge metal pattern BM11_TA1 and the second bridge metal pattern BM21_TA1. Figures 6 to 9 In the embodiment shown in FIG. 1, the gate lines in the main area MA and the gate lines in the protruding areas A1 and A2 can be disposed on the same layer, and the present disclosure is not limited thereto.

[0125] Figure 10 is an enlarged layout view corresponding to the area "A" of Figure 3 according to another exemplary embodiment of the present disclosure.

[0126] The elements and reference numerals described above with respect to Figures 1 to 4 will not be described again.

[0127] Referring to Figure 10 , the organic light emitting display device 10 according to the present exemplary embodiment includes a display area DA and a non-display area BA, wherein the display area DA includes a main area MA, a first protruding area TA1, and a second protruding area TA2, and the non-display area BA surrounds the display area DA.

[0128] In the display area DA, a plurality of gate lines GL1_MA to GLn_MA, GL1_TA1 to GLk_TA1, GL1_TA2 to GLk_TA2, and GL(k+1)_TA12 to GLx_TA12, which extend along the first direction dr1, can be arranged, where k is a positive integer greater than 1 and less than x. According to the present exemplary embodiment, the organic light emitting display apparatus 10 can further include compensation lines CL1_TA1 to CLk_TA1 and CL1_TA2 to CLk_TA2, and bridge patterns BP1_TA1 to BPk_TA1 and BP1_TA2 to BPk_TA2, which are arranged in the non-display area BA.

[0129] Unlike the organic light emitting display apparatus 10 according to the embodiment shown in Figure 4 , the organic light emitting display apparatus 10 according to the present exemplary embodiment can further include gate lines GL(k+1)_TA12 to GLx_TA12, which are arranged in the first protruding area TA1 and the second protruding area TA2 and further extend through a portion of the non-display area BA.

[0130] In the organic light emitting display apparatus 10 according to the exemplary embodiment shown in Figure 4 , none of the gate lines GL1_TA1 to GLx_TA1 and GL1_TA2 to GLx_TA2 arranged in the first protruding area TA1 and the second protruding area TA2 are electrically connected to each other. In contrast, in the organic light emitting display apparatus 10 according to the exemplary embodiment shown in Figure 10 , some of the gate lines GL(k+1)_TA12 to GLx_TA12 arranged in the first protruding area TA1 and the second protruding area TA2 are electrically connected to each other through the non-display area BA. As a result, a difference in length between the gate lines GL(k+1)_TA12 to GLx_TA12 and the gate lines GL1_MA to GLn_MA can be reduced.

[0131] The gate lines GL(k+1)_TA12 to GLx_TA12 arranged in the non-display area BA can have a curved portion such that they are as close as possible to the main area MA. Accordingly, a spacing between the gate lines GL(k+1)_TA12 to GLx_TA12 measured in the second direction dr2 in the non-display area BA can be smaller than a spacing measured in the first protruding area TA1 and the second protruding area TA2.

[0132] While some exemplary embodiments of the present application have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the application disclosed in the accompanying claims.

Claims

1. A light-emitting display device, comprising: A substrate having a display area and a non-display area defined thereon, wherein the display area includes a first area and a second area, and a plurality of pixels are located in the display area; A first signal line is located on the substrate in the first region; A second signal line is located on the substrate in the second region; A compensation line is located on the substrate in the non-display area and is electrically connected to the second signal line; A bridging pattern is placed above the second signal line and the compensation line in the non-display area, and electrically connects the second signal line to the compensation line. A first insulating layer is disposed between the bridging pattern and the compensation line, the first insulating layer comprising a first surface facing the substrate and a second surface opposite to the first surface; and A compensation metal pattern is located above and overlaps the compensation line in the non-display area. The first signal line and the second signal line are configured to provide signals to the plurality of pixels. The bridging pattern includes a first bridging metal pattern, a second bridging metal pattern, and a third bridging metal pattern. The first bridging metal pattern is located above the second signal line and the compensation line, and is electrically connected to the second signal line. The second bridging metal pattern is located above the second signal line and the compensation line, and is electrically connected to the compensation line. The third bridging metal pattern is located above the first and second bridging metal patterns, and electrically connects the first and second bridging metal patterns. The first bridging metal pattern, the second bridging metal pattern, and the compensation metal pattern are in direct contact with the second surface of the first insulating layer.

2. The light-emitting display device as claimed in claim 1, further comprising: A second insulating layer is disposed on the first bridging metal pattern and the second bridging metal pattern. The third bridging metal pattern is disposed on the second insulating layer, and The second insulating layer is disposed between the third bridging metal pattern and the first bridging metal pattern.

3. The light-emitting display device as described in claim 1, further comprising: A third insulating layer is disposed on the first signal line and the second signal line. The compensation line is disposed on the third insulating layer, and The third insulating layer is disposed between the compensation line and the first signal line.

4. The light-emitting display device as claimed in claim 1, wherein, Each of the pixels includes a light-emitting element. The third bridging metal pattern is made of the same material as the electrodes of the light-emitting element.

5. The light-emitting display device as claimed in claim 1, wherein, Each of the pixels includes a light-emitting element. The light-emitting display device further includes a planarization layer disposed between the light-emitting element and the third bridging metal pattern.

6. The light-emitting display device as claimed in claim 1, further comprising: A compensation semiconductor pattern is disposed in the non-display area between the substrate and the compensation line, and overlaps with the compensation line.

7. The light-emitting display device as claimed in claim 1, wherein, Each of the pixels includes a light-emitting element. The voltage applied to the compensation metal pattern is equal to the power supply voltage applied to the light-emitting element.

8. The light-emitting display device as claimed in claim 1, wherein, The signal is a gate signal.

9. The light-emitting display device as claimed in claim 1, wherein, The second region extends from the first region.

10. A light-emitting display device, comprising: A substrate having a display area and a non-display area defined thereon, wherein the display area includes a first area and a second area, and a plurality of pixels are located in the display area; A first signal line is located on the substrate in the first region; A second signal line is located on the substrate in the second region; A compensation line is located on the substrate in the non-display area and is electrically connected to the second signal line; A first insulating layer is located above the first signal line, the second signal line, and the compensation line. The first insulating layer includes a first surface facing the substrate and a second surface opposite to the first surface. A first bridging metal pattern is located directly on the second surface of the first insulating layer in the non-display area and is electrically connected to the second signal line; The second bridging metal pattern is located directly on the second surface of the first insulating layer in the non-display area and is electrically connected to the compensation line. A compensation metal pattern is placed directly on the second surface of the first insulating layer in the non-display area and overlaps with the compensation line; A second insulating layer is formed on the first bridging metal pattern and the second bridging metal pattern; and A third bridging metal pattern is located on the second insulating layer in the non-display area and is electrically connected to the first bridging metal pattern and the second bridging metal pattern. The first signal line and the second signal line are configured to provide signals to the plurality of pixels.

11. The light-emitting display device as claimed in claim 10, wherein, The compensation line is arranged on a different layer than the layer on which the first signal line and the second signal line are arranged.

12. The light-emitting display device as claimed in claim 10, wherein, The compensation metal pattern overlaps with the compensation line in the non-display area.

13. The light-emitting display device as claimed in claim 12, further comprising: A compensation semiconductor pattern is located in the non-display area on a layer between the substrate and the compensation line, and overlaps with the compensation line.

14. The light-emitting display device as claimed in claim 12, wherein, Each of the pixels includes a light-emitting element. The voltage applied to the compensation metal pattern is equal to the power supply voltage applied to the light-emitting element.

15. The light-emitting display device as claimed in claim 10, wherein, The signal is a gate signal.

16. The light-emitting display device as claimed in claim 10, wherein, The second region extends from the first region.

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