Mram devices and methods of forming the same
By employing multiple filling steps and a single planarization step in the construction of MRAM devices, the damage to the MTJ layer caused by traditional etching steps is avoided, the problem of device performance degradation is solved, and higher performance and lower leakage current are achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
- Filing Date
- 2017-03-20
- Publication Date
- 2026-07-24
AI Technical Summary
In the fabrication process of existing MRAM devices, multiple etching steps can damage the MTJ layer, affecting device performance and increasing leakage current.
The variable resistance memory cell is formed by using multiple filling steps and a single planarization step, avoiding traditional etching steps and ensuring the integrity of the MTJ layer.
This reduces damage to the MTJ layer, lowers leakage current, and improves the performance of MRAM devices.
Smart Images
Figure CN116322275B_ABST
Abstract
Description
[0001] Divisional application
[0002] This application is a divisional application of the patent application filed on March 20, 2017, entitled "MRAM Device and Method of Forming Thereof", with patent application number 201710167690.3. Technical Field
[0003] The embodiments of the present invention relate to MRAM devices and methods for forming the same. Background Technology
[0004] Semiconductor memory is used in integrated circuits for electronic applications, such as radios, televisions, mobile phones, and personal computing devices. One type of semiconductor memory device includes spintronics, which combine semiconductor technology with magnetic materials and devices. Electrons spin through their magnetic moment rather than their electric charge; spintronics are used to represent bits.
[0005] Such spintronic devices are magnetoresistive random access memory (MRAM) arrays, which include conductive lines (word lines and bit lines) positioned in different directions (e.g., perpendicular to each other in different metal layers). Magnetic tunnel junctions (MTJs) are sandwiched between the conductors, serving as magnetic storage cells. Various techniques for the construction and materials of MRAM have been implemented to attempt and further improve device performance. Summary of the Invention
[0006] According to some embodiments of the present invention, a magnetoresistive random access memory (MRAM) device is provided, comprising: a dielectric layer located above a substrate and having an opening; a variable resistance memory cell located in the opening and including a first electrode, a second electrode, and a magnetic tunnel junction layer located between the first electrode and the second electrode; and a conductive layer filling the remaining portion of the opening and electrically connected to one of the first electrode and the second electrode of the variable resistance memory cell.
[0007] According to other embodiments of the present invention, a magnetoresistive random access memory (MRAM) device is also provided, comprising: a conductive structure located above a substrate and embedded in a first dielectric layer; a second dielectric layer located above the substrate and having an opening exposing the conductive structure; a conductive layer located in the opening; and a variable resistance memory cell located between the conductive layer and the conductive structure and between the conductive layer and the second dielectric layer, wherein the variable resistance memory cell includes a bottom electrode, a top electrode, and a magnetic tunnel junction layer located between the bottom electrode and the top electrode.
[0008] According to further embodiments of the present invention, a method for forming a resistive random access memory (RRAM) device is also provided, comprising: providing a substrate having a conductive structure formed on the substrate and a first dielectric layer formed around the conductive structure; forming a second dielectric layer over the first dielectric layer; forming an opening in the second dielectric layer, wherein the opening exposes the conductive structure; forming a bottom electrode over the second dielectric layer, wherein the bottom electrode fills the opening; forming a magnetic tunnel junction layer over the bottom electrode, wherein the magnetic tunnel junction layer fills the opening; forming a top electrode over the magnetic tunnel junction layer, wherein the top electrode fills the opening; forming a conductive layer over the top electrode, wherein the conductive layer fills the opening; and performing a planarization step until the surface of the second dielectric layer is exposed. Attached Figure Description
[0009] The various aspects of the invention can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial practice, the components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the components may be arbitrarily increased or decreased.
[0010] Figures 1A to 1E This is a schematic cross-sectional view of a method for forming an MRAM device according to some embodiments.
[0011] Figure 2 This is a flowchart of a method for forming an MRAM device according to some embodiments.
[0012] Figures 3 to 4 This is a schematic cross-sectional view of an MRAM device according to an optional embodiment.
[0013] Figures 5A to 5E This is a schematic cross-sectional view of an MRAM device according to some alternative embodiments.
[0014] Figure 6 This is a flowchart of a method for forming an MRAM device according to some alternative embodiments.
[0015] Figures 7 to 8 This is a schematic cross-sectional view of an MRAM device according to another alternative embodiment. Detailed Implementation
[0016] The following disclosure provides numerous different embodiments or instances for implementing the various features offered by the subject matter. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component on or above a second component can include embodiments where the first and second components are in direct contact, and can also include instances where an additional component can be formed between the first and second components, thereby allowing the first and second components to not be in direct contact. Furthermore, reference numerals and / or characters may be repeated in various instances of the invention. Such repetition is for simplification and clarity and does not in itself indicate a relationship between the discussed embodiments and / or configurations.
[0017] Furthermore, for ease of description, spatial relative terms such as "below," "under," "lower part," "above," "over," "covering above," and "upper part" may be used herein to describe the relationship between one element or component and another (or other) element or component as shown in the figure. In addition to the orientation shown in the figure, spatial relationship terms are intended to include different orientations of the device during use or operation. The device may be positioned in other ways (rotated 90 degrees or in other orientations), and the spatial relationship descriptors used herein can be interpreted accordingly.
[0018] Figures 1A to 1E This is a schematic cross-sectional view of a method for forming an MRAM device according to some embodiments. Figure 2 This is a flowchart of a method for forming an MRAM device according to some embodiments. It should be noted that... Figure 2 Additional steps are provided before, during, and / or after the steps described herein. Various figures have been simplified to better understand the inventive concept of the invention.
[0019] refer to Figure 1A and Figure 2 In step 200, a substrate 100 is provided, a conductive structure 104 is formed on the substrate 100, and a first dielectric layer 102 is formed around the conductive structure 104.
[0020] In some embodiments, substrate 100 comprises elemental semiconductors and / or compound semiconductors, such as silicon or germanium, and compound semiconductors such as silicon germanium, silicon carbide, gallium arsenide, indium arsenide, gallium nitride, or indium phosphide. In some embodiments, substrate 100 is a semiconductor-on-insulator (SOI) substrate. In various embodiments, substrate 100 may take the form of a planar substrate, a substrate with multiple fins, nanowires, or other forms known to those skilled in the art. In some embodiments, various layers and / or device structures are formed over or within substrate 100. These layers include dielectric layers, doped layers, polysilicon layers, metal layers, or combinations thereof. These device structures include transistors, resistors, and / or capacitors, which may be interconnected to additional integrated circuits via interconnect layers.
[0021] In some embodiments, the conductive structure 104 is a metal wire embedded in the first dielectric layer 102. In an alternative embodiment, the conductive structure 104 is a metal plug (or "metal via") formed through the first dielectric layer 102. In another alternative embodiment, the conductive structure 104 is a metal gate or a polysilicon gate surrounded by the first dielectric layer 102. In yet another alternative embodiment, the conductive structure 104 includes at least one of a metal wire, a metal plug, a metal gate, a polysilicon gate, a silicide layer, and a doped layer.
[0022] In some embodiments, the conductive structure 104 comprises Al, Cu, Mo, Ti, TiN, Ta, TaN, W, WN, NiSi, CoSi, or combinations thereof. In some embodiments, the first dielectric layer 102 comprises silicon oxide, fluorinated silica glass (FSG), carbon-doped silicon oxide, silicon nitride, silicon oxynitride, tetraethyl orthosilicate (TEOS) oxide, phosphosilicate glass (PSG), borosilicate glass (BPSG), or black silicate glass. (Applied Materials, Santa Clara, California), amorphous fluorinated carbon, low-k dielectric materials with a dielectric constant of less than about 4, or combinations thereof.
[0023] In some embodiments, the conductive structure 104 is formed after the formation of the first dielectric layer 102. In alternative embodiments, the conductive structure 104 is formed before the formation of the first dielectric layer 102. Methods for forming the conductive structure 104 and the first dielectric layer 102 include performing suitable process steps, including deposition, photolithographic patterning, doping, ion implantation, and / or etching.
[0024] Continue to refer to Figure 1A and Figure 2In step 202, a second dielectric layer 112 is formed over the first dielectric layer 102. In some embodiments, the second dielectric layer 112 has the same material as the first dielectric layer 102. In alternative embodiments, the second dielectric layer 112 has a different material than the first dielectric layer 102. In some embodiments, the second dielectric layer 112 includes, from bottom to top, an optional etch stop layer 106, an intermediate layer 108, and an optional polishing stop layer 110.
[0025] An etch stop layer 106 is optionally formed over the conductive structure 104 and the first dielectric layer 102. During subsequent etch steps that define the opening, the etch stop layer 106 is configured to protect adjacent components (e.g., the conductive structure 104) from damage. In some embodiments, the etch stop layer 106 comprises a dielectric material, such as SiN, SiC, SiCN, SiON, SiCON, or combinations thereof, and the method of forming the etch stop layer 106 includes performing a suitable deposition process, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), plasma-enhanced CVD (PECVD), etc.
[0026] Intermediate layer 108 is formed above etch stop layer 106. Intermediate layer 108 includes silicon oxide, FSG, carbon-doped silicon oxide, silicon nitride, silicon oxynitride, TEOS oxide, PSG, BPSG, and black oxide. (Applied Materials, Santa Clara, California), amorphous fluorinated carbon, low-k dielectric materials having a dielectric constant of less than about 4, or combinations thereof, and the intermediate layer 108 formation method includes performing suitable techniques such as CVD, ALD, high-density plasma CVD (HDPCVD), spin coating, etc.
[0027] A polishing stop layer 110 is optionally formed over the intermediate layer 108. During subsequent polishing steps, the polishing stop layer 110 is configured to protect adjacent components (e.g., the intermediate layer 108) from damage. In some embodiments, the polishing stop layer 110 comprises a dielectric material such as SiN, SiC, SiCN, SiON, SiCON, or combinations thereof, and the method of forming the polishing stop layer 110 includes performing a suitable deposition process such as CVD, ALD, PECVD, etc.
[0028] refer to Figure 1B and Figure 2In step 204, an opening 114 is formed in the second dielectric layer 112. In some embodiments, the opening 114 penetrates the second dielectric layer 112 and exposes at least a portion of the conductive structure 104. During the formation of the opening 114, the etch stop layer 106 has a higher etch resistance than the intermediate layer 108 or the polishing stop layer 110, so the etch stop layer 116 prevents the etching process from penetrating down into the dielectric layer 102 and the conductive structure 104. In the step of forming the opening 114, the second dielectric layer 112 is partially removed to form a second dielectric layer 112a, which includes, from bottom to top, an optional etch stop layer 106a, an intermediate layer 108a, and an optional polishing stop layer 110a. In some embodiments, the width of the opening 114 is smaller than the width of the conductive structure 104. In some embodiments, the opening 114 is a contact opening, a via opening, a conductive trench, or an inlay opening. In some embodiments, the opening 114 is formed by a suitable process such as photolithography etching.
[0029] refer to Figure 1C and Figure 2 In step 206, a bottom electrode 113 is formed over the second dielectric layer 112a and fills the opening 114. In some embodiments, the bottom electrode 113 is conformally formed on the top surface of the second dielectric layer 112a and on the sidewalls and bottom of the opening 114. In some embodiments, the bottom electrode is in physical contact with the conductive structure 104. In alternative embodiments, the bottom electrode is electrically connected to the conductive structure 104 via one or more conductive elements. In some embodiments, the bottom electrode 113 comprises Pt, Al, Cu, AlCu, Au, Ti, TiN, Ta, TaN, W, WN, or combinations thereof, and the bottom electrode 113 is formed by a suitable technique such as electroless plating, sputtering, electroplating, PVD, CVD, ALD, etc. In some embodiments, when the conductive structure 104 and the bottom electrode 113 are made of different materials, an optional barrier layer is formed between the conductive structure 104 and the bottom electrode 113. The barrier layer prevents diffusion and / or any junction spikes between the conductive structure 104 and the bottom electrode 113. In some embodiments, the barrier layer includes at least one of Ti, TiN, Ta, TaN, W, and WN, and the barrier layer is formed by a suitable technique, such as electroless plating, sputtering, electroplating, PVD, CVD, ALD, etc.
[0030] Continue to refer to Figure 1C and Figure 2In step 208, a magnetic tunnel junction (MTJ) layer 122 is formed above the bottom electrode 113 and fills the opening 114. In some embodiments, the MTJ layer 122 is uniformly formed on the surface of the top electrode 113 on the outer and inner sides of the opening 114. In some embodiments, by applying a voltage, the MTJ layer 122 has a resistance that can switch between a high-resistance state and a low-resistance state (or conductor state).
[0031] In some embodiments, the MTJ layer 122 comprises a high-k dielectric material having a dielectric constant greater than about 8, a binary metal oxide, a transition metal oxide, or a combination thereof. In some embodiments, the MTJ layer 122 comprises a fixed layer 116, a free layer 120, and a tunnel layer 118 located between the fixed layer 116 and the free layer 120. In some embodiments, the fixed layer 116 is in physical contact with the bottom electrode 113.
[0032] Fixed layer 116 and free layer 120 form two ferromagnetic plates, each capable of maintaining a magnetic field. Fixed layer 116 and free layer 120 are separated by a tunnel layer 118. Fixed layer 116 has a fixed magnetic polarity, while free layer 120 has a variable magnetic polarity to match an external field for data storage. Due to the magnetic tunneling effect, the resistance of MTJ layer 122 varies based on the direction of the magnetic field in the two plates (e.g., fixed layer 116 and free layer 120). In some embodiments, MTJ layer 122 has a lower resistance if the two plates have the same polarity, and a higher resistance if the two plates have opposite polarities.
[0033] In some embodiments, the anchoring layer 116 comprises a synthetic antiferromagnetic (SAF) structure. In some embodiments, the anchoring layer 116 comprises a top anchoring layer, a bottom anchoring layer, and a metal layer, the top anchoring layer being in physical contact with the tunnel layer 118, and the metal layer being located between the top and bottom anchoring layers. For example, each top and bottom anchoring layer comprises CoFeB, NiFe, CoFe, Fe, or a suitable material, and the metal layer comprises Ru, Cu, Ta, or a suitable material. In some embodiments, the tunnel layer 118 comprises MgO, Al2O3, or a suitable material. In some embodiments, the free layer 120 comprises a magnetic material such as CoFeB, NiFe, CoFe, Fe, or a suitable material. In some embodiments, the MTJ layer 122 can be fabricated using suitable techniques such as magnetron sputtering deposition, molecular beam epitaxy, pulsed laser deposition, electron beam physical vapor deposition, CVD, ALD, or suitable methods.
[0034] Continue to refer to Figure 1C and Figure 2In step 210, a top electrode 123 is formed over the MTJ layer 112 and fills the opening 114. In some embodiments, the top electrode 123 is conformally formed on the surfaces of the MTJ layer 122 on the outer and inner sides of the opening 114. In some embodiments, the material of the top electrode 123 is the same as the material of the bottom electrode 113. In optional embodiments, the material of the top electrode 123 is different from the material of the bottom electrode 113. In some embodiments, the top electrode 123 comprises Pt, Al, Cu, AlCu, Au, Ti, TiN, Ta, TaN, W, WN, or combinations thereof, and the bottom electrode 113 is formed by a suitable technique, such as electroless plating, sputtering, electroplating, PVD, CVD, ALD, etc.
[0035] Continue to refer to Figure 1C and Figure 2 In step 212, a conductive layer 124 is formed over the top electrode 123 and fills the opening 114. In some embodiments, the conductive layer 124 is formed on the surface of the top electrode 123 and fills the opening 114. In some embodiments, the conductive layer 124 comprises Al, Cu, Mo, Ti, TiN, Ta, TaN, W, WN, or combinations thereof, and the conductive layer 124 is formed by a suitable technique, such as electroless plating, sputtering, electroplating, PVD, CVD, ALD, etc. In some embodiments, the conductive layer 124 has the same material as the conductive structure 104. In optional embodiments, the conductive layer 124 has a different material than the conductive structure 104.
[0036] In some embodiments, when the conductive layer 124 and the top electrode 123 are made of different materials, an optional barrier layer is formed between the conductive layer 124 and the top electrode 123. The barrier layer prevents diffusion and / or any junction spikes between the conductive layer 124 and the top electrode 123. In some embodiments, the barrier layer comprises at least one of TiN, Ti, Ta, TaN, W, and WN, and the barrier layer is formed by a suitable technique, such as electroless plating, sputtering, electroplating, PVD, CVD, ALD, etc.
[0037] refer to Figure 1D , Figure 1E as well as Figure 2In step 214, a planarization step is performed until the surface of the second dielectric layer 112a / 112b is exposed. In some embodiments, the conductive layer 124, top gate 123, MTJ layer 122, and bottom electrode 113 outside the opening 114 are removed. More specifically, the conductive layer 124, top gate 123, MTJ layer 122, and bottom electrode 113 are partially removed to form the conductive layer 124a, top gate 123a, MTJ layer 122a (including a fixed layer 116a, a free layer 120a, and a tunnel layer 118a located between the fixed layer 116a and the free layer 120a), and bottom gate 113a inside the opening 114. In some embodiments, the planarization step includes performing a chemical mechanical polishing (CMP) process using a polishing stop layer 110a as a stop layer. During the planarization step, the polishing stop layer 110a has a polishing resistance higher than that of the conductive layer 124, top electrode 123, MTJ layer 122, or bottom electrode 113. The polishing stop layer 110a prevents the planarization step from entering the film stack inside the opening 114.
[0038] In some embodiments, such as Figure 1D As shown, the planarization step stops on the surface of the polishing stop layer 110a. This completes the MRAM device 10 of this disclosure. In some embodiments, the MRAM device 10 has a variable resistance storage cell 105, which is composed of a bottom electrode 113a, an MTJ layer 122a, and a top electrode 123a and is embedded in a second dielectric layer 112a.
[0039] In optional embodiments, such as Figure 1E As shown, according to process requirements, the planarization step removes the polishing stop layer 110a and stops on the surface of the intermediate layer 108a. This completes the MRAM device 20 of this disclosure. In some embodiments, the MRAM device 20 has a variable resistance storage cell 105, which is composed of a bottom electrode 113a, an MTJ layer 122a, and a top electrode 123a and is embedded in a second dielectric layer 112b.
[0040] In the above embodiments, the width of the opening 114 is smaller than the width of the conductive structure 104, but this disclosure is not limited thereto. In optional embodiments, such as Figure 3 As shown, the width of the opening 114 is substantially equal to the width of the conductive structure 104. This completes the MRAM device 30 of this disclosure. In some cases, the sidewalls of the conductive structure 104 are aligned with the sidewalls of the opening 114.
[0041] In another alternative embodiment, the width of the opening 114 is greater than the width of the conductive structure 104, thereby completing the MRAM device 40 of this disclosure.
[0042] The various MRAM devices disclosed herein offer improved performance. More specifically, in conventional methods, multiple etching steps are required for patterning the bottom electrode, MTJ layer, and top electrode, and these etching steps result in prolonged exposure to a plasma environment, thus degrading device performance. However, the variable resistance memory cells of this disclosure, formed through multiple filling steps (e.g., steps 206 to 210) and a subsequent single planarization step (e.g., step 214), do not involve any conventional etching steps. This disclosure eliminates the drawbacks of conventional methods, such as damaging etching of the MTJ layer. The absence of etching damage in the MTJ layer reduces potential leakage current in the MRAM device and thus improves device performance.
[0043] The following is for reference. Figure 1D , Figure 1E , Figure 3 and Figure 4 The structure of the MRAM device disclosed herein is described.
[0044] In some embodiments, this disclosure provides an MRAM device 10 / 20 / 30 / 40, which includes a substrate 100, a first dielectric layer 102, a conductive structure 104, a variable resistance memory cell 105, a second dielectric layer 112a / 112b, and a conductive layer 124a. The conductive structure 104 is located above the substrate 100 and embedded in the first dielectric layer 102. In some embodiments, the conductive structure 104 includes at least one of a metal line, a metal plug, a metal gate, a polysilicon gate, a silicide layer, and a doped layer.
[0045] The second dielectric layer 112a / 112b is located above the substrate 100 and has an opening 114 that exposes the conductive structure 104. In some embodiments, such as Figure 1D and Figure 1E As shown, the width of opening 114 is smaller than the width of conductive structure 104. In alternative embodiments, such as... Figure 3 As shown, the width of opening 114 is substantially equal to the width of conductive structure 104. In another alternative embodiment, such as... Figure 4 As shown, the width of the opening 114 is greater than the width of the conductive structure 104.
[0046] In some embodiments, such as Figure 1D As shown, the second dielectric layer 112a includes an etch stop layer 106a, an intermediate layer 108 above the etch stop layer 106a, and a polishing stop layer 110 above the intermediate layer 108. In optional embodiments, such as Figure 1E , Figure 3 as well as Figure 4As shown, the second dielectric layer 112b includes an etch stop layer 106a and an intermediate layer 108a located above the etch stop layer 106a.
[0047] The conductive layer 124a is in the opening 114. In some embodiments, the top surface of the conductive layer 124a is substantially coplanar with the top surface of the second dielectric layers 112a / 112b.
[0048] A variable resistance storage cell 105 is located between the conductive layer 124a and the conductive structure 104, and also between the conductive layer 124a and the second dielectric layers 112a / 112b. In some embodiments, the variable resistance storage cell 105 is in physical contact with each conductive structure 104 and the conductive layer 124a. In some embodiments, the variable resistance storage cell 105 includes a bottom electrode 113a, a top electrode 123a, and an MTJ layer 122a located between the bottom electrode 113a and the top electrode 123a. In some embodiments, the MTJ layer 122a includes a fixed layer 116a, a free layer 120a, and a tunnel layer 118a located between the fixed layer 116a and the free layer 120a, wherein the fixed layer 116a has fixed magnetic poles, and the free layer 120a has variable magnetic poles.
[0049] In some embodiments, in the variable resistance memory cell 105, the bottom electrode 113a is on the sidewall and bottom of the opening 114, and the top electrode 123a is on the same sidewall and bottom of the opening 114, while the MTJ layer 122a is located between the bottom electrode 113a and the top electrode 123a. More specifically, each bottom electrode 113a, MTJ layer 122a, and top electrode 123a is formed in a U-shape.
[0050] This disclosure further provides an MRAM device 10 / 20 / 30 / 40, which includes a substrate 100, a dielectric layer (e.g., a second dielectric layer 112a / 112b), a variable-resistance memory cell 105, and a conductive layer 124a. The dielectric layer (e.g., the second dielectric layer 112a / 112b) is located above the substrate 100 and has an opening 114 therein. The variable-resistance memory cell 105 is in the opening 114 and includes a first electrode (e.g., a bottom electrode 113a), a second electrode (e.g., a top electrode 123a), and an MTJ layer 122a located between the first and second electrodes. The conductive layer 124a fills the remaining portion of the opening 114 and is electrically connected to one of the first electrode (e.g., the bottom electrode 113a) and the second electrode (e.g., the top electrode 123a) of the variable-resistance memory cell 105. Furthermore, another electrical connection is made between the first electrode (e.g., bottom electrode 113a) and the second electrode (e.g., top electrode 123a) of the variable resistance storage cell 105 and the conductive structure 104 located below the dielectric layer (e.g., second dielectric layer 112a / 112b). In some embodiments, the second electrode (e.g., top electrode 123a) of the variable resistance storage cell 105 is electrically connected to the conductive layer 124a located within the opening 114, and the first electrode (e.g., bottom electrode 113a) of the variable resistance storage cell 105 is electrically connected to the conductive structure 104 located below the opening 114.
[0051] In the above embodiments, each bottom electrode 113a, MTJ layer 122a, and top electrode 123a is formed in a U-shape and is formed in the same opening 114. This description is provided for illustrative purposes and is not intended to limit the scope of this disclosure. That is, each bottom electrode, MTJ layer, and top electrode does not necessarily have to be U-shaped, and their shapes can be adjusted as needed. More specifically, depending on process requirements, each bottom electrode, MTJ layer, and top electrode can be formed with a suitable shape, such as an I-shape, L-shape, V-shape, stepped shape, etc. For example, the bottom electrode can be formed in a horizontal I-shape and disposed only at the bottom of the opening, while the MTJ layer and top electrode can be formed in a U-shape and disposed on the sidewalls and bottom of the opening.
[0052] Those skilled in the art will recognize that a variable resistance memory cell is considered to fall within the spirit and scope of this disclosure as long as it is formed within an opening and one of its electrodes is electrically connected to or physically in contact with a conductive line in the same opening. In some embodiments, these variable resistance memory cells can be subsequently formed through multiple filling steps followed by a single planarization step, without any conventional etching steps that could damage the device. Therefore, the performance of the MRAM device can be correspondingly improved.
[0053] In the above embodiments, the bottom electrode, MTJ layer, and top electrode of the variable resistance memory cell are formed in the same opening without any additional patterning steps. Therefore, the variable resistance memory cell of this disclosure is considered a self-aligned memory cell. This simplifies the process and thus saves costs.
[0054] In some embodiments, for Figures 1A to 1E The steps of forming the bottom electrode and the top electrode in the method can be omitted. In these cases, the conductive structure 104 can serve as the bottom electrode while the conductive layer 124a can serve as the top electrode. Figures 5A to 5E The method is similar to Figures 1A to 1E The differences between these methods will be explained in detail below and will not be repeated here.
[0055] Figures 5A to 5E This is a schematic cross-sectional view of an MRAM device according to an optional embodiment. Figure 6 This is a flowchart of a method for forming an MRAM device according to some alternative embodiments. Figures 7 to 8 This is a schematic cross-sectional view of an MRAM device according to another alternative embodiment. It should be noted that... Figure 6 Additional steps are provided before, during, and / or after the steps described herein. Various figures have been simplified to better understand the inventive concept of the invention.
[0056] refer to Figure 5A and Figure 6 In step 300, a substrate 100 is provided, a bottom electrode (e.g., conductive structure 104) is formed on the substrate 100, and a first dielectric layer 102 is formed around the bottom electrode.
[0057] Continue to refer to Figure 5A and Figure 6 In step 302, a second dielectric layer 112 is formed over the first dielectric layer 102. In some embodiments, the second dielectric layer 112 includes, from bottom to top, an optional etch stop layer 106, an intermediate layer 108, and an optional polishing stop layer 110.
[0058] refer to Figure 5B and Figure 6In step 304, an opening 114 is formed in the second dielectric layer 112, thus exposing the bottom electrode (e.g., conductive structure 104). In some embodiments, the opening 114 penetrates the second dielectric layer 112 and exposes at least a portion of the bottom electrode (e.g., conductive structure 104). More specifically, partial removal of the second dielectric layer 112 is performed to form a second dielectric layer 112a, which includes, from bottom to top, an optional etch stop layer 106a, an intermediate layer 108a, and an optional polishing stop layer 110a.
[0059] refer to Figure 5C and Figure 6 In step 306, the MTJ layer 122 is formed over the second dielectric layer 112a and fills the opening 114. In some embodiments, the MTJ layer 122 is conformally formed on the top surface of the second dielectric layer 112a and on the sidewalls and bottom of the opening 114. In some embodiments, the MTJ layer 122 is in physical contact with a bottom electrode (e.g., conductive structure 104). In some embodiments, the MTJ layer 122 includes a fixed layer 116, a free layer 120, and a tunnel layer 118 located between the fixed layer 116 and the free layer 120.
[0060] Continue to refer to Figure 5C and Figure 6 In step 308, a top electrode (e.g., conductive layer 124) is formed over the MTJ layer 112 and fills the opening 114. In some embodiments, the top electrode (e.g., conductive layer 124) fills the opening 114.
[0061] refer to Figure 5D , Figure 5E as well as Figure 6 In step 310, a planarization step is performed until the surface of the second dielectric layer 112a / 112b is exposed. In some embodiments, the top electrode (e.g., conductive layer 124) and MTJ layer 122 outside the opening 114 are removed. More specifically, the top electrode (e.g., conductive layer 124) and MTJ layer 122 are partially removed to form a top electrode (e.g., conductive layer 124a) and MTJ layer 122a (including a fixed layer 116a, a free layer 120a, and a tunnel layer 118a located between the fixed layer 116a and the free layer 120a) inside the opening 114. In some embodiments, the planarization step includes performing a CMP process using a polishing stop layer 110a as a stop layer.
[0062] In some embodiments, such as Figure 5DAs shown, the planarization step stops at the surface of the polishing stop layer 110a. This completes the MRAM device 50 of this disclosure. In some embodiments, the MRAM device 50 has a variable resistance storage cell 107, which is formed and embedded in the second dielectric layer 112a via a bottom electrode (e.g., conductive structure 104), an MTJ layer 122a, and a top electrode (e.g., conductive layer 124a).
[0063] In optional embodiments, such as Figure 5E As shown, according to process requirements, the planarization step removes the polishing stop layer 110a and stops on the surface of the intermediate layer 108a. This completes the MRAM device 60 of this disclosure. In some embodiments, the MRAM device 60 has a variable resistance storage cell 107, which is formed and embedded in the second dielectric layer 112b via a bottom electrode (e.g., conductive structure 104), an MTJ layer 122a, and a top electrode (e.g., conductive layer 124a).
[0064] In the above embodiments, the width of the opening 114 is smaller than the width of the bottom electrode (e.g., conductive structure 104), but this disclosure is not limited thereto. In alternative embodiments, such as Figure 7 As shown, the width of the opening 114 is substantially equal to the width of the bottom electrode (e.g., conductive structure 104). This completes the MRAM device 70 of this disclosure. In some cases, the sidewall of the bottom electrode (e.g., conductive structure 104) is aligned with the sidewall of the opening 114.
[0065] In another alternative embodiment, such as Figure 8 As shown, the width of the opening 114 is greater than the width of the bottom electrode (e.g., conductive structure 104). This completes the MRAM device 80 of this disclosure.
[0066] In the process of forming the variable resistance memory cell 107, the bottom electrode (e.g., conductive structure 104) can be fabricated using steps of forming metal lines, metal plugs, metal gates, polysilicon gates, silicide layers, and / or doped layers, while the top electrode (e.g., conductive layer 124a) can be fabricated using steps of forming metal lines or metal plugs. That is, the process of forming the variable resistance memory cell 107 can be easily integrated with existing logic or CMOS processes, thus simplifying the process steps and saving process costs.
[0067] According to some embodiments of the present invention, an MRAM device includes a dielectric layer, a variable resistance memory cell, and a conductive layer. The dielectric layer is located above a substrate and has an opening. The variable resistance memory cell is located within the opening and includes a first electrode, a second electrode, and an MTJ layer located between the first electrode and the second electrode. The conductive layer fills the reserved portion of the opening and is electrically connected to one of the first electrode and the second electrode of the variable resistance memory cell.
[0068] According to an optional embodiment of the present invention, an MRAM device includes a conductive structure, a first dielectric layer, a second dielectric layer, a conductive layer, and a variable-resistance memory cell. The conductive structure is located above a substrate and embedded in the first dielectric layer. The second dielectric layer is located above the substrate and has an opening that exposes the conductive structure. The conductive layer is located in the opening 114. The variable-resistance memory cell is located between the conductive layer and the conductive structure, and is also located between the conductive layer and the second dielectric layer. The variable-resistance memory cell includes a bottom electrode, a top electrode, and a magnetic tunnel junction layer located between the bottom electrode and the top electrode.
[0069] According to another optional embodiment of the present invention, a method for forming an MRAM device includes the following steps: A substrate is provided, a conductive structure is formed on the substrate, and a first dielectric layer is formed around the conductive structure. A second dielectric layer is formed over the first dielectric layer. An opening is formed in the second dielectric layer, wherein the opening exposes the conductive structure. A bottom electrode is formed over a second electrode layer and the bottom electrode fills the opening. A magnetic tunnel junction layer is formed over the bottom electrode and fills the opening. A top electrode is formed over the magnetic tunnel junction layer and fills the opening. A conductive layer is formed over the top electrode and fills the opening. A planarization step is performed until the surface of the second dielectric layer is exposed.
[0070] According to some embodiments of the present invention, a magnetoresistive random access memory (MRAM) device is provided, comprising: a dielectric layer located above a substrate and having an opening; a variable resistance memory cell located in the opening and including a first electrode, a second electrode, and a magnetic tunnel junction layer located between the first electrode and the second electrode; and a conductive layer filling the remaining portion of the opening and electrically connected to one of the first electrode and the second electrode of the variable resistance memory cell.
[0071] In the above-mentioned magnetoresistive random access memory device, the top surface of the conductive layer is coplanar with the top surface of the dielectric layer.
[0072] In the above-described magnetoresistive random access memory device, the variable resistance storage cell includes: a first electrode located on the sidewall and bottom of the opening; a second electrode located on the sidewall and bottom of the opening; and a magnetic tunnel junction layer located between the first electrode and the second electrode.
[0073] In the above-mentioned magnetoresistive random access memory device, each of the first electrode and the second electrode includes Pt, Al, Cu, AlCu, Au, Ti, TiN, Ta, TaN, W, WN or combinations thereof.
[0074] In the above-mentioned magnetoresistive random access memory device, the magnetic tunnel junction layer includes a fixed layer, a free layer, and a tunnel layer located between the fixed layer and the free layer. The fixed layer has fixed magnetic poles, and the free layer has variable magnetic poles.
[0075] In the aforementioned magnetoresistive random access memory device, the other electrode of the first electrode and the second electrode of the variable resistance memory cell are electrically connected to a conductive structure located below the dielectric layer.
[0076] In the above-mentioned magnetoresistive random access memory device, the width of the opening is smaller than the width of the conductive structure.
[0077] In the above-described magnetoresistive random access memory device, the width of the opening is equal to the width of the conductive structure.
[0078] In the above-mentioned magnetoresistive random access memory device, the width of the opening is greater than the width of the conductive structure.
[0079] In the above-mentioned magnetoresistive random access memory device, the dielectric layer includes an etch stop layer and an intermediate layer located above the etch stop layer.
[0080] In the above-mentioned magnetoresistive random access memory device, the dielectric layer includes an etch stop layer, an intermediate layer above the etch stop layer, and a polishing stop layer above the intermediate layer.
[0081] According to other embodiments of the present invention, a magnetoresistive random access memory (MRAM) device is also provided, comprising: a conductive structure located above a substrate and embedded in a first dielectric layer; a second dielectric layer located above the substrate and having an opening exposing the conductive structure; a conductive layer located in the opening; and a variable resistance memory cell located between the conductive layer and the conductive structure and between the conductive layer and the second dielectric layer, wherein the variable resistance memory cell includes a bottom electrode, a top electrode, and a magnetic tunnel junction layer located between the bottom electrode and the top electrode.
[0082] In the above-described magnetoresistive random access memory device, each of the bottom electrode and the top electrode comprises Pt, Al, Cu, AlCu, Au, Ti, TiN, Ta, TaN, W, WN, or a combination thereof.
[0083] In the above-mentioned magnetoresistive random access memory device, the magnetic tunnel junction layer includes a fixed layer, a free layer, and a tunnel layer located between the fixed layer and the free layer. The fixed layer has fixed magnetic poles, and the free layer has variable magnetic poles.
[0084] In the above-described magnetoresistive random access memory device, the second dielectric layer includes an etch stop layer and an intermediate layer located above the etch stop layer.
[0085] In the above-described magnetoresistive random access memory device, the second dielectric layer includes an etch stop layer, an intermediate layer above the etch stop layer, and a polishing stop layer above the intermediate layer.
[0086] In the above-mentioned magnetoresistive random access memory device, the conductive structure includes at least one of a metal line, a metal plug, a metal gate, a polysilicon gate, a silicide layer, and a doped layer.
[0087] According to further embodiments of the present invention, a method for forming a resistive random access memory (RRAM) device is also provided, comprising: providing a substrate having a conductive structure formed on the substrate and a first dielectric layer formed around the conductive structure; forming a second dielectric layer over the first dielectric layer; forming an opening in the second dielectric layer, wherein the opening exposes the conductive structure; forming a bottom electrode over the second dielectric layer, wherein the bottom electrode fills the opening; forming a magnetic tunnel junction layer over the bottom electrode, wherein the magnetic tunnel junction layer fills the opening; forming a top electrode over the magnetic tunnel junction layer, wherein the top electrode fills the opening; forming a conductive layer over the top electrode, wherein the conductive layer fills the opening; and performing a planarization step until the surface of the second dielectric layer is exposed.
[0088] In the above method, the second dielectric layer includes an etch stop layer and an intermediate layer located above the etch stop layer, as well as a polishing stop layer located above the intermediate layer.
[0089] In the above method, the planarization step includes performing a chemical mechanical polishing process.
[0090] The foregoing summary outlines the features of several embodiments, enabling those skilled in the art to better understand various aspects of the invention. Those skilled in the art should understand that other processes and structures can be readily designed or modified based on this invention to achieve the same objectives and / or benefits as the embodiments described herein. Those skilled in the art should also recognize that these equivalent structures do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of the invention.
Claims
1. A magnetoresistive random access memory (MRAM) device, comprising: A first dielectric layer is located above the substrate and has a first opening; A second dielectric layer is located above the first dielectric layer and has a second opening; A variable resistance memory cell includes a first electrode, a second electrode, and a magnetic tunnel junction layer located between the first electrode and the second electrode. The first electrode is located in a first opening and has a rectangular cross-section. The top surface of the first electrode is in contact with the bottom surface of the magnetic tunnel junction layer. The second electrode and the magnetic tunnel junction layer are located in a second opening. The magnetic tunnel junction has a U-shaped cross-section and surrounds the sidewalls and bottom surface of the second electrode; Wherein, the top surface of the second electrode is coplanar with the top surface of the second dielectric layer; and The second dielectric layer includes an etch stop layer and an intermediate layer located above the etch stop layer. Wherein, the outer width of the first electrode is less than or equal to the outer width of the U-shaped cross-section of the magnetic tunnel junction. The magnetic tunnel layer includes a fixed layer, a free layer, and a tunnel layer located between the fixed layer and the free layer. The fixed layer has fixed magnetic poles, and the free layer has variable magnetic poles.
2. The magnetoresistive random access memory device according to claim 1, wherein, The top surface of the first electrode is coplanar with the top surface of the first dielectric layer.
3. The magnetoresistive random access memory device according to claim 1, wherein, The magnetic tunnel layer is located on the sidewall and bottom of the second opening.
4. The magnetoresistive random access memory device according to claim 1, wherein, Each of the first electrode and the second electrode comprises Pt, Al, Cu, AlCu, Au, Ti, TiN, Ta, TaN, W, WN, or combinations thereof.
5. The magnetoresistive random access memory device according to claim 1, wherein, The tunnel layer comprises MgO or Al2O3.
6. The magnetoresistive random access memory device according to claim 1, wherein, The first electrode of the variable resistance memory cell includes at least one of a metal line, a metal plug, a metal gate, a polysilicon gate, a silicide layer, and a doped layer.
7. The magnetoresistive random access memory device according to claim 1, wherein, The first electrode and the second electrode are made of the same material.
8. The magnetoresistive random access memory device according to claim 6, wherein, The width of the second opening is equal to the width of the first opening.
9. The magnetoresistive random access memory device according to claim 6, wherein, The width of the second opening is greater than the width of the first opening.
10. The magnetoresistive random access memory device according to claim 1, wherein, The second dielectric layer also includes a polishing stop layer located above the intermediate layer.
11. A magnetoresistive random access memory (MRAM) device, comprising: The bottom electrode is located above the substrate and embedded in the first dielectric layer, and has a rectangular cross-section; A second dielectric layer is located above the first dielectric layer and has an opening that exposes the bottom electrode; as well as A variable resistance storage cell is located in the opening, and the variable resistance storage cell includes a bottom electrode, a top electrode, and a magnetic tunnel junction layer located between the bottom electrode and the top electrode, the magnetic tunnel junction layer surrounding the sidewall and bottom surface of the top electrode; The top electrode is physically separated from the second dielectric layer. The top surface of the bottom electrode is in contact with the bottom surface of the magnetic tunnel junction layer, and the outer width of the bottom electrode is less than or equal to the outer width of the magnetic tunnel junction layer. The magnetic tunnel layer includes a fixed layer, a free layer, and a tunnel layer located between the fixed layer and the free layer. The fixed layer has fixed magnetic poles, and the free layer has variable magnetic poles.
12. The magnetoresistive random access memory device according to claim 11, wherein, Each of the bottom electrode and the top electrode comprises Pt, Al, Cu, AlCu, Au, Ti, TiN, Ta, TaN, W, WN, or combinations thereof.
13. The magnetoresistive random access memory device according to claim 11, wherein, The tunnel layer comprises MgO or Al2O3.
14. The magnetoresistive random access memory device according to claim 11, wherein, The second dielectric layer includes an etch stop layer and an intermediate layer located above the etch stop layer.
15. The magnetoresistive random access memory device according to claim 11, wherein, The second dielectric layer includes an etch stop layer and an intermediate layer above the etch stop layer, and a polishing stop layer above the intermediate layer.
16. The magnetoresistive random access memory device according to claim 11, wherein, The bottom electrode includes at least one of a metal wire, a metal plug, a metal gate, a polysilicon gate, a silicide layer, and a doped layer.
17. A method for forming a magnetoresistive random access memory (MRAM) device, comprising: A substrate is provided having a bottom electrode formed on the substrate and a first dielectric layer formed around the bottom electrode, the bottom electrode having a rectangular cross-section; A second dielectric layer is formed above the first dielectric layer; An opening is formed in the second dielectric layer, wherein the opening exposes the bottom electrode; A magnetic tunnel junction layer is formed above the second dielectric layer, wherein the magnetic tunnel junction layer fills the opening; A top electrode is formed above the magnetic tunnel junction layer, wherein the top electrode fills the opening, and the magnetic tunnel junction layer surrounds the sidewalls and bottom surface of the top electrode; and A planarization step is performed until the surface of the second dielectric layer is exposed, thereby physically separating the top electrode from the second dielectric layer. The top surface of the bottom electrode is in contact with the bottom surface of the magnetic tunnel layer, and the outer width of the bottom electrode is less than or equal to the outer width of the magnetic tunnel layer.
18. The method for forming a magnetoresistive random access memory device according to claim 17, wherein, The second dielectric layer includes an etch stop layer and an intermediate layer above the etch stop layer, and a polishing stop layer above the intermediate layer.
19. The method for forming a magnetoresistive random access memory device according to claim 17, wherein, The planarization step includes performing a chemical mechanical polishing process.