Manufacturing method of resistive memory and resistive memory

Abstract

The present invention provides a manufacturing method of a resistive random access memory and a resistive random access memory, comprising the following steps: opening a lower electrode through hole in a first isolation layer; filling the lower electrode through hole with the same metal material as the metal wiring layer; depositing a second isolation layer, a lower electrode metal layer, a resistive random access layer and an upper electrode metal layer in sequence on the top of the first isolation layer and the top of the lower electrode through hole filled with the metal material; performing a first etching process on the upper electrode metal layer and the resistive random access layer, so that the first etching process stays on the top surface of the lower electrode metal layer, and depositing a sidewall protection layer on the upper electrode metal layer and the resistive random access layer after the first etching process; after the sidewall protection layer is deposited, performing a second etching process on the second isolation layer and the lower electrode metal layer, so that the second etching process stays on the upper surface of the first isolation layer. The present invention can solve the problems of easy appearance of holes and easy formation of side digging in the existing manufacturing process.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and more specifically, to a method for manufacturing a resistive random access memory and a resistive random access memory. Background Art

[0002] The existing RRAM (resistive random access memory) structure is mostly a metal injection molding (MIM) structure, and the upper and lower electrodes are both metal plates. The traditional manufacturing process is generally: the lower electrode metal layer is deposited, and then the lower electrode metal layer is patterned through steps such as photolithography / etching / cleaning, and then the resistive layer and the upper electrode metal layer are deposited, and then the upper electrode is masked and etched to form an RRAM device.

[0003] The above-mentioned traditional manufacturing process has the following defects: First, the metal wiring layer is generally made of copper, but when filling the lower electrode through hole, the traditional process generally uses TIN as the through hole filling material. The BE Via TIN filling capacity is limited, and holes are prone to appear; there are great restrictions on the BE Via CD / profile (lower electrode through hole electrode / lower electrode through hole layer). The lower electrode W CD (tungsten electrode) is limited by the upper electrode lithography and etching process capabilities, and the CD (electrode) is large, resulting in the RRAM Cell resistive random access memory structure filaments are not concentrated and fluctuate greatly; when etching the lower electrode, it is easy to form a side digging phenomenon, which affects the subsequent spacer dep morphology and easily causes voids at the bottom. Summary of the invention

[0004] In view of the above problems, the purpose of the present invention is to provide a manufacturing method of a resistive random access memory and a resistive random access memory, so as to solve the problems existing in the current traditional manufacturing process of resistive random access memory, such as the use of a material different from the metal wiring layer as the lower electrode through-hole filling material, which makes it easy to form holes in the electrode through-hole, and the use of a one-step etching method, which makes it easy to form side digging when etching the lower electrode.

[0005] The present invention provides a method for manufacturing a resistive random access memory, comprising the following steps:

[0006] A lower electrode through hole is opened in the first isolation layer, so that the bottom of the lower electrode through hole is connected to the top of the metal wiring layer; wherein the first isolation layer is arranged on the top of the metal wiring layer;

[0007] Filling the lower electrode through hole with the same metal material as that of the metal wiring layer;

[0008] Depositing a second isolation layer, a lower electrode metal layer, a resistive switching layer and an upper electrode metal layer in sequence on top of the first isolation layer and on top of the lower electrode through hole filled with metal material;

[0009] Performing a first etching process on the upper electrode metal layer and the resistive switching layer, so that the first etching process stops at the top surface of the lower electrode metal layer, and depositing a sidewall protection layer on the upper electrode metal layer and the resistive switching layer after the first etching process;

[0010] After the sidewall protection layer is deposited, a second etching process is performed on the second isolation layer and the lower electrode metal layer, so that the second etching process stays on the upper surface of the first isolation layer.

[0011] In addition, a preferred solution is that the first isolation layer includes a SIN or NDC layer arranged on the top of the metal wiring layer and an oxide layer arranged on the top of the SIN or NDC layer.

[0012] In addition, a preferred solution is that the material of the metal wiring layer and the metal material filling the lower electrode through hole are both copper.

[0013] In addition, a preferred solution is that the material of the second isolation layer is TaN or TIN.

[0014] In addition, a preferred solution is that the material of the resistive switching layer is metal oxide.

[0015] In addition, a preferred solution is that the upper electrode metal layer includes an inert metal layer arranged on the top of the resistive layer and a TIN layer arranged on the top of the inert metal layer.

[0016] In addition, a preferred solution is that an upper electrode protection layer is deposited on top of the upper electrode metal layer.

[0017] In addition, a preferred solution is that the material of the upper electrode protection layer is SIN.

[0018] The present invention provides a resistive random access memory, which is manufactured by adopting the manufacturing method of the resistive random access memory as described above.

[0019] It can be seen from the above technical scheme that the manufacturing method of the resistive random access memory and the resistive random access memory provided by the present invention fill the lower electrode through hole with the same metal material as the metal wiring layer, so that the bottom of the metal layer formed inside the lower electrode through hole is in close contact with the metal wiring layer to avoid the appearance of holes; at the same time, the size of the through hole is also reduced, so that the size of the electrode is also reduced. Compared with the prior art, the size of the upper electrode can be greatly reduced; the etching of the electrode is completed in two steps, firstly, the upper electrode metal layer and the resistive random access layer are etched, and then the sidewall protection layer is deposited on the etched upper electrode metal layer and the resistive random access layer, thereby providing protection for the upper electrode layer and the resistive random access layer in the next etching step, and preventing them from being damaged by subsequent etching steps.

[0020] In order to achieve the above and related purposes, one or more aspects of the present invention include the features that will be described in detail later. The following description and the accompanying drawings describe some exemplary aspects of the present invention in detail. However, these aspects indicate only some of the various ways in which the principles of the present invention can be used. In addition, the present invention is intended to include all these aspects and their equivalents. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] By referring to the following description in conjunction with the accompanying drawings, and with a more comprehensive understanding of the present invention, other objects and results of the present invention will become more apparent and easy to understand. In the accompanying drawings:

[0022] Figure 1 is a flow chart of a method for manufacturing a resistive random access memory according to an embodiment of the present invention;

[0023] Figure 2 is a process flow chart of a method for manufacturing a resistive random access memory according to an embodiment of the present invention;

[0024] Figure 3 FIG. 4 is a schematic diagram of the structure of a resistive random access memory according to an embodiment of the present invention.

[0025] In the accompanying drawings, 11-SIN or NDC layer, 12-oxide layer, 2-lower electrode through hole, 3-metal wiring layer, 4-lower electrode metal layer, 5-resistive layer, 6-deposited sidewall protection layer, 7-second isolation layer, 81-inert metal layer, 82-TIN layer, 9-upper electrode protection layer.

[0026] The same reference numerals throughout the drawings indicate similar or corresponding features or functions. DETAILED DESCRIPTION

[0027] In the following description, for the purpose of explanation, numerous specific details are set forth in order to provide a thorough understanding of one or more embodiments. However, it is apparent that these embodiments may also be implemented without these specific details.

[0028] In view of the above-mentioned problems existing in the conventional manufacturing process of the current resistive memory, such as the use of a material different from the metal wiring layer as the filling material for the lower electrode through hole, which makes it easy for holes to appear in the electrode through hole, and the use of a one-step etching method, which makes it easy to form side digging when etching the lower electrode, a manufacturing method of a resistive memory and a resistive memory are proposed.

[0029] The specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0030] In order to illustrate the manufacturing method of the resistive random access memory and the resistive random access memory provided by the present invention, Figure 1 The process of manufacturing a resistive random access memory according to an embodiment of the present invention is shown; Figure 2 The process flow of the manufacturing method of the resistive random access memory according to the embodiment of the present invention is shown; Figure 3 The structure of the resistive memory according to the embodiment of the present invention is shown.

[0031] like Figures 1 to 3 As shown together, the manufacturing method of the resistive random access memory provided by the present invention comprises the following steps:

[0032] S1, opening a lower electrode through hole 2 in the first isolation layer, so that the bottom of the lower electrode through hole 2 is connected to the top of the metal wiring layer 3; wherein the first isolation layer is arranged on the top of the metal wiring layer 3;

[0033] S2, filling the lower electrode through hole 2 with the same metal material as the metal wiring layer 3;

[0034] S3, sequentially depositing a second isolation layer 7, a lower electrode metal layer 4, a resistive switching layer 5 and an upper electrode metal layer on top of the first isolation layer and on top of the lower electrode through hole 2 filled with metal material;

[0035] S4, performing a first etching process on the upper electrode metal layer and the resistive layer 5, so that the first etching process stays on the top surface of the lower electrode metal layer 4, and depositing a sidewall protection layer 6 on the upper electrode metal layer and the resistive layer 5 after the first etching process;

[0036] S5. After the sidewall protection layer 6 is deposited, a second etching process is performed on the second isolation layer 7 and the lower electrode metal layer 4, so that the second etching process stays on the upper surface of the first isolation layer.

[0037] By filling the lower electrode through hole 2 with the same metal material as the metal wiring layer 3, the bottom of the metal layer formed inside the lower electrode through hole 2 is in close contact with the metal wiring layer 3 to avoid the formation of holes; at the same time, the size of the through hole is also reduced, so that the size of the electrode is also reduced. Compared with the prior art, the size of the upper electrode can be greatly reduced; the etching of the electrode is completed in two steps, firstly, the upper electrode metal layer and the resistive layer are etched, and then the side wall protection layer 6 is deposited on the etched upper electrode metal layer and the resistive layer 5, thereby providing protection for the upper electrode layer and the resistive layer in the next etching step and preventing them from being damaged by subsequent etching steps.

[0038] As a preferred embodiment of the present invention, the first isolation layer includes a SIN or NDC layer 11 disposed on top of the metal wiring layer 3 and an oxide layer 12 disposed on top of the SIN or NDC layer. The first isolation layer protects the metal wiring layer 3 to prevent damage to the metal wiring layer 3 from the outside.

[0039] As a preferred embodiment of the present invention, the material of the metal wiring layer 3 and the metal material filling the lower electrode through hole 2 are both copper. The main advantages of copper metal compared to other metals are high electrical conductivity, high thermal conductivity, corrosion resistance, suitable strength, easy processing and forming, etc. The metal material filling the lower electrode through hole is the same metal copper as the material of the metal wiring layer, so that the bottom of the copper material filled in the through hole can be in close contact with the metal wiring layer to prevent the formation of holes, and the use of the same copper material as the filling material can further reduce the size of the lower electrode through hole, thereby reducing the size of the electrode.

[0040] As a preferred embodiment of the present invention, the material of the second isolation layer 7 is TaN or TIN. The second isolation layer 7 protects the lower electrode metal layer 4 and the first isolation layer.

[0041] As a preferred embodiment of the present invention, the material of the resistance change layer 5 is metal oxide, which is used to change the resistance between the upper and lower electrode layers.

[0042] As a preferred embodiment of the present invention, the upper electrode metal layer includes an inert metal layer 81 disposed on the top of the resistive layer and a TIN layer 82 disposed on the top of the inert metal layer 81. The inert metal electrode is preferably W and Pt.

[0043] As a preferred embodiment of the present invention, an upper electrode protection layer 9 is deposited on the top of the upper electrode metal layer. The upper electrode protection layer 9 protects the top of the upper electrode.

[0044] As a preferred embodiment of the present invention, the material of the upper electrode protection layer 9 is SIN. This is a preferred material.

[0045] The resistive random access memory provided by the present invention is manufactured by the resistive random access memory manufacturing method as described above. The resistive random access memory provided by the present invention has all the advantages of the resistive random access memory manufacturing method as described above.

[0046] It can be seen from the above specific embodiments that the manufacturing method of the resistive random access memory and the resistive random access memory provided by the present invention fill the lower electrode through hole with the same metal material as the metal wiring layer, so that the bottom of the metal layer formed inside the lower electrode through hole is in close contact with the metal wiring layer to avoid the appearance of holes; at the same time, the size of the through hole is also reduced, so that the size of the electrode is also reduced. Compared with the prior art, the size of the upper electrode can be greatly reduced; the etching of the electrode is completed in two steps, firstly, the upper electrode metal layer and the resistive random access layer are etched, and then the sidewall protection layer is deposited on the etched upper electrode metal layer and the resistive random access layer, thereby providing protection for the upper electrode layer and the resistive random access layer in the next etching step, so as not to be damaged by subsequent etching steps.

[0047] As described above, the manufacturing method of the resistive random access memory and the resistive random access memory proposed in the present invention are described by way of example with reference to the accompanying drawings. However, it should be understood by those skilled in the art that various improvements can be made to the manufacturing method of the resistive random access memory and the resistive random access memory proposed in the present invention without departing from the content of the present invention. Therefore, the protection scope of the present invention should be determined by the content of the attached claims.

Claims

1. A method for manufacturing a resistive random access memory, characterized in that: The steps include: A lower electrode through hole is opened in the first isolation layer, so that the bottom of the lower electrode through hole is connected to the top of the metal wiring layer; wherein the first isolation layer is arranged on the top of the metal wiring layer; Filling the lower electrode through hole with the same metal material as that of the metal wiring layer; Depositing a second isolation layer, a lower electrode metal layer, a resistive switching layer and an upper electrode metal layer in sequence on top of the first isolation layer and on top of the lower electrode through hole filled with metal material; Performing a first etching process on the upper electrode metal layer and the resistive switching layer, so that the first etching process stops at the top surface of the lower electrode metal layer, and depositing a sidewall protection layer on the upper electrode metal layer and the resistive switching layer after the first etching process; After the sidewall protection layer is deposited, a second etching process is performed on the second isolation layer and the lower electrode metal layer, so that the second etching process stays on the upper surface of the first isolation layer.

2. The method for manufacturing a resistive random access memory according to claim 1, wherein: The first isolation layer includes a SIN or NDC layer disposed on the top of the metal wiring layer and an oxide layer disposed on the top of the SIN or NDC layer.

3. The method for manufacturing a resistive random access memory according to claim 1, wherein: The material of the metal wiring layer and the metal material filling the lower electrode through hole are both copper.

4. The method for manufacturing a resistive random access memory according to claim 1, wherein: The material of the second isolation layer is TaN or TIN.

5. The method for manufacturing a resistive random access memory according to claim 1, wherein: The material of the resistive switching layer is metal oxide.

6. The method for manufacturing a resistive random access memory according to claim 1, characterized in that: The upper electrode metal layer includes an inert metal layer disposed on the top of the resistive layer and a TIN layer disposed on the top of the inert metal layer.

7. The method for manufacturing a resistive random access memory according to claim 1, characterized in that: An upper electrode protection layer is also deposited on top of the upper electrode metal layer.

8. The method for manufacturing a resistive random access memory according to claim 7, characterized in that: The material of the upper electrode protection layer is SIN.

9. A resistive random access memory, characterized in that: The resistive random access memory is manufactured by the manufacturing method according to any one of claims 1 to 8.

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