hart-enabled device with reduced communication lines and interrupt expansion protocol

Abstract

The current loop (100) includes a receiver assembly (122) and a transmitter assembly (102). The current loop (100) also includes a first conductor (132) between the receiver assembly (122) and the transmitter assembly (102) and a second conductor (134) between the receiver assembly (122) and the transmitter assembly (102) to complete the current loop (100). The transmitter assembly (102) includes a Highway Addressable Remote Transducer (HART) modem, a component in communication with the HART modem via a set of partial Universal Asynchronous Receiver-Transmitter (UART) communication lines, and an interrupt expansion protocol controller coupled to or included in the HART modem and configured to support UART and non-UART communications between the HART modem and the component using the set of partial UART communication lines.

Description

BACKGROUND

[0001] The proliferation of electronic devices and integrated circuit (IC) technology has led to the commercialization of IC products. As new electronic devices are developed and IC technology advances, new IC products are commercialized. One example IC product that is desired is a current loop device with high- addressable remote transducer (HART) protocol compatibility. Such current loop devices are referred to herein as HART-enabled devices, where the HART protocol supports communication over a traditional 4 mA - 20 mA analog instrument current loop by sharing a pair of wires in the current loop with a purely analog host system. Other components used in conjunction with HART-enabled devices in the current loop include sensors, transducers, analog-to-digital converters (ADCs), digital-to-analog converters (DACs), microcontrollers (MCUs), and isolators.

[0002] One of the problems faced by HART-enabled devices is the need to accommodate universal asynchronous receiver-transmitter (UART) and serial peripheral interface (SPI) interfaces for MCU host connections and / or data converters. Two example HART-enabled devices that face this UART and SPI interface problem include HART protocol smart transmitter devices and HART protocol current input modules. Conventional techniques to address this problem involve high-cost isolation circuitry and / or high-cost HART software stacks. In one example, the MCU interface of a conventional HART-enabled device uses more than 10 signals to accommodate UART and SPI communications. Efforts to reduce the complexity and cost of HART-enabled devices are ongoing. SUMMARY

[0003] According to at least one example, a current loop includes a receiver assembly and a transmitter assembly. The current loop also includes a first conductor between the receiver assembly and the transmitter assembly and a second conductor between the receiver assembly and the transmitter assembly to complete the current loop. The transmitter assembly includes a high-addressable remote transducer (HART) modem, a component in communication with the HART modem via a set of partial universal asynchronous receiver-transmitter (UART) communication lines, and an interrupt expansion protocol controller coupled to or included in the HART modem and configured to support UART and non-UART communications between the HART modem and the component using the set of partial UART communication lines.

[0004] According to at least one example, a HART-enabled device includes a UART TXD communication line and a UART RXD communication line. The HART-enabled device also includes a HART modem coupled to the UART TXD communication line and the UART RXD communication line, and the HART modem is configured to support UART communication and non- UART communication using the UART TXD communication line and the UART RXD communication line.

[0005] According to at least one example, a current loop transmitter module includes a microcontroller (MCU) and a transducer configured to convert an analog signal to a digital signal or a digital signal to an analog signal. The current loop transmitter module also includes a HART modem coupled to the MCU and the transducer via a UART TXD communication line and a UART RXD communication line. The current loop transmitter module also includes an interrupt expansion protocol controller coupled to or included in the HART modem and configured to support UART communication and non- UART communication between the HART modem and the MCU using the UART TXD communication line and the UART RXD communication line and between the HART modem and the transducer. BRIEF DESCRIPTION OF DRAWINGS

[0006] For a detailed description of various examples, reference will now be made to the accompanying drawings in which:

[0007] Figure 1 is a block diagram illustrating a current loop according to an example;

[0008] Figure 2 is a schematic diagram illustrating a HART-enabled smart transmitter module according to an example;

[0009] Figure 3 is a block diagram illustrating a HART-enabled current input module according to an example;

[0010] Figure 4 is a block diagram illustrating a current loop transmitter assembly according to an example;

[0011] Figure 5 is a diagram illustrating a 2-wire current loop according to an example; and

[0012] Figure 6 is a diagram illustrating a 4-wire current loop according to an example. DETAILED DESCRIPTION

[0013] Described herein are HART-enabled devices in a current loop transmitter assembly, where the HART-enabled devices are configured to support Universal Asynchronous Receiver-Transmitter (UART) communication and Serial Peripheral Interface (SPI) communication using a reduced number of communication lines (e.g., a UART TXD communication line and a UART RXD communication line). To reduce the number of communication lines and still support conventional UART signaling and SPI signaling, the HART-enabled devices (e.g., HART protocol smart transmitter devices or HART protocol current input modules) employ an interrupt extension protocol. In some examples, the HART-enabled devices use the interrupt extension protocol and two UART communication lines (a UART TXD communication line and a UART RXD communication line) for UART communication and SPI communication with a microprocessor (MCU) and / or other components such as a digital-to-analog converter (DAC) and an analog-to-digital converter (ADC). More specifically, an interrupt condition on the UART TXD line when sending data from the MCU to the HART-enabled device can indicate, for example, a control write command or control write data to a HART modem, DAC, or ADC. Further, an interrupt condition on the RXD communication line when receiving data from the HART-enabled device to the MCU can indicate, for example, control read data, status exception, or acknowledgement of an interrupt write command. In some examples, the interrupt condition occurs when the UART TXD communication line or the UART RXD communication line is at a "space" (logical low) level for longer than or equal to a predetermined interval (e.g., 11 bits in a UART telegraph). This interrupt condition will be equivalent to an all-zero bit character with a parity error and is used as an exception condition for special control commands and control data in addition to HART telegraph data.

[0014] In some examples, the proposed HART-enabled device employs different options to reduce cost, complexity, and power consumption. For example, using UART communication lines enables the proposed HART-enabled device to keep most of the HART stack software unchanged, where UART TXD communication line and UART RXD communication line are the minimum number of communication lines required for communication between the MCU and the HART-enabled device. Other communication lines such as: ADC and DAC SPI lines (typically 4 lines); HART modem to MCU interrupt request (IRQ) line; and UART control signal lines (RTS / CTS / CD lines) are optional as interrupt commands and interrupt exceptions can perform these same functions. In the proposed HART-enabled device, the interrupt extension protocol implements the enhanced features described herein (to support UART signaling and SPI signaling with limited communication lines) without adding additional power consumption. Since the interface UART bus carries most of the capacitive load of the system, the power consumption of the proposed interrupt extension protocol is dominated by the transition events of the UART bus. While the proposed HART-enabled device uses a higher UART baud rate, the total number of bus transitions per unit HART telegrams transaction remains almost the same.

[0015] In some examples, the proposed HART-enabled device implements integrated transducer (ADC or DAC) control, compatible HART modem protocol control, and low power consumption. For better understanding, various HART-enabled device options and related transmitter component or current loop scenarios are described using the following figures.

[0016] Figure 1 is a block diagram illustrating a current loop 100 in accordance with an example. In Figure 1 the current loop 100 is formed using a transmitter component 102, a receiver component 122, a first line 132 between the transmitter component 102 and the receiver component 122, and a second line 134 between the transmitter component 102 and the receiver component 122. In Figure 1 In examples of the transmitter component 102 corresponds to an integrated circuit (IC) part, or a combination of IC parts and discrete parts. If multiple IC parts and / or discrete parts are used, a printed circuit board (PCB) can be used to couple the multiple IC parts and / or discrete parts of the transmitter component 102 together. Also, the receiver component 122 corresponds to an IC part, or a combination of IC parts and discrete parts. Again, if multiple IC parts and / or discrete parts are used, a PCB can be used to couple the multiple IC parts and / or discrete parts of the receiver component 122 together.

[0017] In Figure 1In the example of FIG. 1, transmitter assembly 102 includes sensor 104 coupled to ADC 106 to provide digital sensing data from sensor 104. Examples of sensor 104 include a pressure sensor or a temperature sensor. The output of ADC 106 is coupled to MCU 108 configured to process, store, and / or forward the sensing data to HART-enabled device 110. Examples of HART-enabled device 110 include a smart transmitter device or a current input module. In different examples, HART-enabled device 110 includes a HART modem, an ADC, a DAC, and / or other components. Regardless of the particular components included in HART-enabled device 110, UART interface 112 is included to support communication with MCU 108 and / or other components of transmitter assembly 102. In Figure 1 In the proposed example of FIG. 1, UART interface 112 includes interrupt expansion protocol controller 114 to support UART communication and SPI communication between HART-enabled device 110 and other components of transmitter assembly 102 using a limited set of communication lines. In some examples, HART-enabled device 110 uses only a UART TXD communication line and a UART RXD communication line to support UART communication and SPI communication with other components of transmitter assembly 102. In other examples, HART-enabled device 110 uses one or more additional communication lines corresponding to SPI lines (typically 4 lines), a HART modem to MCU interrupt request (IRQ) line, and a UART control signal line (RTS / CTS / CD lines).

[0018] With interrupt expansion protocol controller 114, HART-enabled device 110 is able to perform UART signaling and SPI signaling with other components of transmitter assembly 102 using a reduced number of communication lines compared to conventional HART-enabled devices. As shown, receiver assembly 122 includes power supply 124 to supply voltage and current for current loop 100. Receiver assembly 122 also includes sensing circuit 126 configured to detect signaling from transmitter assembly 102. Receiver assembly 122 also includes other component(s) 128, such as an ADC, a processor, and / or other components configured to demodulate, store, process, and / or respond to the signaling from transmitter assembly 102.

[0019] Figure 2 is a schematic diagram illustrating a HART-enabled smart transmitter module 200 according to an example. In Figure 2 In the example of FIG. 2, HART-enabled smart transmitter module 200 is a transmitter assembly (e.g., transmitter assembly 102) of a current loop (e.g., current loop 100 in FIG. 1). Figure 1 In the example of FIG. 2, HART-enabled smart transmitter module 200 is a transmitter assembly (e.g., transmitter assembly 102) of a current loop (e.g., current loop 100 in FIG. 1). Figure 1transmitter assembly 102) of FIG. 1. As shown, the HART-enabled smart transmitter module 200 includes a DAC HART modem 208. The HART-enabled smart transmitter module 200 also includes an MCU 204 coupled to the DAC HART modem 208 via a UART interface. As shown, the MCU 204 is also coupled to a DAC 206, where the MCU 204 and the DAC 206 communicate via an SPI interface. The MCU 204 is also coupled to a sensor and ADC block 202, which is represented as separate from the HART-enabled smart transmitter module 200, where the sensor and ADC block 202 is configured to provide digitized sensor data to the MCU 204. In operation, the MCU 204 stores and / or processes the digitized sensor data. As needed, the MCU 204 communicates with the DAC 206 and / or the DAC HART modem 208 via the SPI interface and the UART interface. To modulate data for transmission by a current loop conductor coupled to a current loop terminal 222A or 222B, the DAC HART modem 208 provides the data via a modulation output (MOD OUT).

[0020] In Figure 2 In an example, the HART-enabled smart transmitter module 200 includes various components to perform a modulation operation based on data output from the MOD OUT. More specifically, the modulation of data by the HART-enabled smart transmitter module 200 is a function of Cl, Rl-R6, operational amplifier buffers 210 and 212, a switch (NPN transistor Ql), a full rectifier 220, and the DAC 206. In Figure 2 In an example, the full rectifier 220 is part of the HART-enabled smart transmitter module 200. In other examples, the full rectifier 220 is external to the HART-enabled smart transmitter module 200.

[0021] More specifically, the modulation operation of the HART-enabled smart transmitter module 200 involves operational amplifier buffer 212 summing the modulation of data on the MOD OUT with a signal provided to operational amplifier buffer 210 from the DAC 206. In addition, NPN transistor Ql boosts the output signal of operational amplifier buffer 212 to the BUS node 221. In Figure 2 In an example, the voltage (V+) supplied to the BUS node 221 can be adjusted using different voltage regulation supply blocks 214, 216, and 218. The voltage regulation supply blocks 214, 216, and 218 also supply power to the MCU 204, the DAC HART modem 208, the V REF Voltage circuitry (not shown) provides power to provide V REF where V REFIt is supplied to DAC 206 and voltage regulator supply block 216. Voltage regulator supply blocks 214, 216 and 218 are also supplied to V CC An analog circuit system (not shown) provides power to supply V to the voltage regulator power supply block 218, DAC 206, and operational amplifier buffers 210 and 212. CC .

[0022] In some examples, HART-enabled smart transmitter modules (such as...) Figure 2 The HART-enabled smart transmitter module 200 includes a HART-enabled device (e.g., HART-enabled device 110) that combines the components of the HART-enabled smart transmitter module 200. In some examples, the HART-enabled device for the HART-enabled smart transmitter module 200 includes a DAC 206 and a DAC HART modem 208. In other examples, the HART-enabled device for the HART-enabled smart transmitter module 200 includes all the components of the HART-enabled smart transmitter module 200 except for the MCU 204. Additionally, in some examples, the full rectifier 220 is omitted from the HART-enabled device (e.g., the full rectifier is external to the HART-enabled device and / or the HART-enabled smart transmitter module 200). Regardless of the specific combination of components, as described herein, the HART-enabled device for the HART-enabled smart transmitter module 200 uses an interrupt extension protocol and a reduced set of communication lines.

[0023] In one example, the HART-enabled device of the smart transmitter module 200 for enabling HART reduces the number of communication lines used (e.g., the SPI communication line between DAC 206 and MCU 204 is no longer needed, and the UART communication line between DAC HART modem 208 and MCU 204 is reduced). With the HART-enabled device of the smart transmitter module 200 for enabling HART, DAC HART modem 208 is able to communicate with MCU 204 using an interrupt extension protocol and a reduced set of communication lines (e.g., UART TXD and UART RXD communication lines); communicate with DAC 206 using an interrupt extension protocol and a reduced set of communication lines (e.g., UART TXD and UART RXD communication lines); and / or communicate with any other components typically controlled via SPI / I2C or other protocols.

[0024] In some examples, the HART-enabled device of the HART-enabled smart transmitter module 200 is capable of performing SPI and UART communications with components of the HART-enabled device and / or components of the HART-enabled smart transmitter module 200 using only two communication lines (e.g., a compact two-wire integrated interface having a UART TXD communication line and a UART RXD communication line) and an interrupt extension protocol. In different examples, different SPI signaling options (e.g., / CS, SDI, SDO, SCLK) and UART signaling options (e.g., TXD, RXD, RTS, CTS, CD, MCU, IRQ) are performed using only the UART TXD communication line and the UART RXD communication line and the interrupt extension protocol. In other examples, the HART-enabled device of the HART-enabled smart transmitter module 200 uses a reduced set of communication lines (compared to a traditional HART-enabled device) to support UART and SPI communications (e.g., a UART TXD communication line and a UART RXD communication line and at least one additional communication line related to / CS, SDI, SDO, SCLK, RTS, CTS, CD, MCU, and / or IRQ signaling). By using the interrupt extension protocol with the HART-enabled device and a reduced set of communication lines to support UART, SPI, and / or other communication protocols, the complexity of the HART-enabled smart transmitter module 200 is simplified, which reduces IC footprint and related costs compared to traditional HART-enabled smart transmitter modules. Additionally, fewer isolators are required (e.g., the DAC HART modem 208 uses 2 instead of 10 isolators), which reduces cost and complexity.

[0025] Figure 3 is a block diagram illustrating a HART-enabled current input module 300 according to an example. In Figure 3 the example, the HART-enabled current input module 300 is a transmitter assembly (e.g., a transmitter assembly of a current loop (e.g., the current loop 100 in Figure 1 Figure 1 ​the transmitter assembly 102 in FIG. 1). As shown, the HART-enabled current input module 300 includes a DAC HART modem 305 configured to communicate with an external MCU 314 via UART communication lines and isolation blocks 308 (e.g., isolators for each UART communication line). The HART-enabled current input module 300 also includes an ADC 304 configured to communicate with the external MCU 314 via SPI communication lines and isolation blocks 310 (e.g., isolators for each SPI communication line). The HART-enabled current input module 300 also includes a load (RLOAD) and signal conditioning block 302 coupled to current loop terminals 316A and 316B, where the output of the signal conditioning block 302 is provided to the DAC HART modem 305 and the ADC 304. In Figure 3 In examples of the HART-enabled current input module 300, the operation of the ADC 304 is a function of a reference voltage received from a reference voltage source 306, where the reference voltage source 306 receives an input voltage from a voltage regulator 312. In some examples, the HART-enabled device applied to the HART-enabled current input module 300 includes the ADC 304 and the HART-enabled device 110B, where the interrupt expansion protocol and the compact two-wire integrated interface are used for communication between the ADC 304 and the HART-enabled device 110B.

[0026] In some examples, the HART-enabled current input module (such as the HART-enabled current input module 300 of Figure 3 The HART-enabled device (e.g., the HART-enabled device 110) that combines the components of the HART-enabled current input module 300. In some examples, the HART-enabled device for the HART-enabled current input module 300 includes the ADC 304 and the DAC HART modem 305. In other examples, the HART-enabled device for the HART-enabled current input module 300 includes all of the components of the HART-enabled current input module 300. Regardless of the specific combination of components, as described herein, the HART-enabled device for the HART-enabled current input module 300 uses the interrupt expansion protocol and the reduced set of communication lines.

[0027] In one example, the HART-enabled device for the HART-enabled current input module 300 reduces the number of communication lines used (e.g., no longer requires an SPI communication line between the ADC 304 and the external MCU 314, and reduces the UART communication line between the DAC HART modem 305 and the external MCU 314). Also, the HART-enabled device for the HART-enabled current input module 300 reduces the number of isolators (e.g., 2 instead of 10), such that the isolation block 310 is eliminated and the isolation block 308 is simplified. With the HART-enabled device for the HART-enabled smart transmitter module 300, the DAC HART modem 305 is able to communicate with the external MCU 314 using the interrupt expansion protocol and a reduced set of communication lines (e.g., the UART TXD communication line and the UART RXD communication line); communicate with the ADC 304 using the interrupt expansion protocol and a reduced set of communication lines (e.g., the UART TXD communication line and the UART RXD communication line); and / or communicate with any other components that are typically controlled through SPI / I2C or other protocols.

[0028] In some examples, the HART-enabled device for the HART-enabled current input module 300 is able to perform SPI communication and UART communication using only two communication lines (e.g., the UART TXD communication line and the UART RXD communication line) and the interrupt expansion protocol. In different examples, the UART TXD communication line and the UART RXD communication line and the interrupt expansion protocol are used to perform different SPI signaling options (e.g., / CS, SDI, SDO, SCLK) and UART signaling options (e.g., TXD, RXD, RTS, CTS, CD, MCU, IRQ) only. In other examples, the HART-enabled device for the HART-enabled current input module 300 uses a reduced set of communication lines to support UART communication and SPI communication (e.g., the UART TXD communication line and the UART RXD communication line and at least one additional communication line related to / CS, SDI, SDO, SCLK, RTS, CTS, CD, MCU, and / or IRQ signaling). By using the interrupt expansion protocol with the HART-enabled device for the HART-enabled current input module 300 and a reduced set of communication lines to support UART communication and SPI communication, the complexity of the HART-enabled current input module 300 is simplified, which reduces IC footprint and related costs compared to traditional HART-enabled current input modules. Also, fewer isolators are required (e.g., 2 instead of 10), which reduces cost and complexity.

[0029] Figure 4 is a block diagram illustrating at least a portion of transmitter assembly 102 in FIG. 1 in accordance with an example. As shown, current loop transmitter assembly 400 includes MCU 402 coupled to HART-enabled device 404. In Figure 1 examples, HART-enabled device 404 is an example of HART-enabled device 110 in FIG. 1, Figure 4 HART-enabled device 110A in FIG. 1, or Figure 1 HART-enabled device 110B in FIG. 1. As shown, HART-enabled device 404 includes transmitter finite state machine (FSM) 406 and receiver FSM 408 coupled to respective transmit (TX) outputs and receive (RX) inputs of MCU 402. More specifically, in some examples, transmitter FSM 406 is coupled to a TX output of MCU 402 via UART TXD communication line 450, where transmitter FSM 406 is configured to process transmit data from MCU 402. Further, receiver FSM 408 is coupled to a RX input of MCU 402 via UART RXD communication line 452, where receiver FSM 408 is configured to process receive data to MCU 402. Figure 2 Figure 3 In examples where HART-enabled device 404 is HART-enabled device 110 in FIG. 1, HART-enabled device 110A in FIG. 1, or

[0030] HART-enabled device 110B in FIG. 1, HART-enabled device 404 enables MCU 402 to transmit data to current loop 434 via transmitter FSM 406, demultiplexer 410 controlled by a transmit interrupt control signal (“TX BREAK DETECT”) indicating occurrence of an interrupt condition, first-in-first-out (FIFO) buffer 414, HART modem 423, and signal conditioning component 432. In examples where HART-enabled device 404 is HART-enabled device 110 in FIG. 1, Figure 4 HART-enabled device 110A in FIG. 1, or Figure 4 HART-enabled device 110B in FIG. 1, HART-enabled device 404 further enables MCU 402 to receive data from current loop 434 via signal conditioning component 432, HART modem 423, FIFO buffer 416, multiplexer 412 controlled by a receive interrupt control signal (“RX BREAK GENERATE”), and RX FSM 408. In examples where HART-enabled device 404 is HART-enabled device 110 in FIG. 1, Figure 4 HART-enabled device 110A in FIG. 1, or HART-enabled device 110B in FIG. 1, HART modem 423 demodulates data received as telegrams data 424 according to the HART protocol using receive HART component 428.

[0031] Figure 4 In examples where HART-enabled device 404 is HART-enabled device 110 in FIG. 1,In some examples, the TX BREAK DETECT becomes active when an interrupt condition persists for at least a predetermined interval in the data transmitted from MCU 402 to current loop 434. In some examples, an interrupt condition is detected when the UART TXD communication line is at a logic low level for a duration longer than a predetermined interval (e.g., 11 bits in a UART telegram). Furthermore, in some examples, an interrupt condition on the UART TXD communication line 450 (e.g., when MCU 402 transmits data to HART-enabled device 404) indicates a control write command or control write data for components included in HART-enabled device 404. In this case, HART-enabled device 404 uses the interrupt extension protocol controller 420 (… Figure 1 The interrupt extension protocol controller 420 is configured to perform any of the first set of control operations 421 (such as modem control, DAC control, and / or ADC control operations), as shown in the example of interrupt extension protocol controller 420. The interrupt extension protocol controller 420 is additionally or alternatively configured to perform any of the second set of control operations 422 (such as control command / data and / or exception operations). As needed, the control operations of the interrupt extension protocol controller 420 involve SPI or UART communication with the MCU 402 and / or the block 430 corresponding to the ADC and / or DAC. As shown, the block 430 is coupled to the interrupt extension protocol controller 420, the HART modem 423, and the signal conditioning unit 432. In different examples, the interrupt extension protocol controller 420 is coupled to or within the HART modem (e.g., HART modem 423). Furthermore, in different example embodiments, the interrupt extension protocol controller 420 is a combination of hardware (e.g., a processor, application-specific integrated circuit or ASIC, programmable logic), software (instructions executed by the hardware), and / or gates.

[0032] exist Figure 4In the example of FIG. 4, the RXBREAK GENERATE is asserted when there is an interruption in receiving data from the current loop 434 for at least a predetermined interval. In one example, the interruption condition is detected when the UART RXD communication line 452 is at a logic low for longer than a predetermined interval (e.g., 11 bits in a UART telegraph). Further, the interruption condition on the UART RXD communication line (when the MCU 402 is sending data to the HART-enabled device 404) indicates a control read data, status exception, or acknowledgement of an interrupt write command for a component included in the HART-enabled device 404. In this case, the HART-enabled device 404 uses the interrupt expansion protocol controller 420 to perform any of a first set of control operations 421 or to perform any of a second set of control operations 422. As needed, the control operations of the interrupt expansion protocol controller 420 involve SPI communication or UART communication with the MCU 402 and / or the block 430. In different examples, the interrupt expansion protocol and a reduced set of communication lines (e.g., the UART TXD communication line 450 and the UART RDX communication line 452) are used for communication between the HART modem 423 and the MCU 402, communication between the HART modem 423 and the DAC of the block 430, communication between the HART modem 423 and the ADC of the block 430, and / or communication between the HART modem 423 and any other component that is typically controlled through SPI / I2C or other protocol.

[0033] Figure 5 FIG. 5 is a diagram illustrating a 2-wire current loop 500, according to an example. In the example of FIG. 5, the 2-wire current loop 500 includes an input-isolated 2-wire sensor transmitter module 502 having current loop terminals 516 and 518. As shown, the input-isolated 2-wire sensor transmitter module 502 also includes a transmitter 512 having a voltage supply terminal coupled to the current loop terminal 516 and having an output current (IOUT) output coupled to the current loop terminal 518. The transmitter 512 is also coupled to a 2-wire ground 514. The voltage at the current loop terminal 516 is also provided to a transformer (Tl) having a primary coil (LI) and a secondary coil (L2), where a first end of LI is coupled to the current loop terminal 516 and a second end of LI is the 2-wire ground 514, and where a first end of L2 is coupled to an ADC and processor block 504 and an isolation ground 508. As shown, the ADC and processor block 504 is also coupled to the isolation ground 508 and a sensor 506. Between the ADC and processor block 504 and the transmitter 512 is a data isolation block 510 that enables communication (e.g., sensor data or a result signal) from the ADC and processor block 504 to the transmitter 512. Figure 5 In the example of FIG. 5, the 2-wire current loop 500 includes an input-isolated 2-wire sensor transmitter module 502 having current loop terminals 516 and 518. As shown, the input-isolated 2-wire sensor transmitter module 502 also includes a transmitter 512 having a voltage supply terminal coupled to the current loop terminal 516 and having an output current (IOUT) output coupled to the current loop terminal 518. The transmitter 512 is also coupled to a 2-wire ground 514. The voltage at the current loop terminal 516 is also provided to a transformer (Tl) having a primary coil (LI) and a secondary coil (L2), where a first end of LI is coupled to the current loop terminal 516 and a second end of LI is the 2-wire ground 514, and where a first end of L2 is coupled to an ADC and processor block 504 and an isolation ground 508. As shown, the ADC and processor block 504 is also coupled to the isolation ground 508 and a sensor 506. Between the ADC and processor block 504 and the transmitter 512 is a data isolation block 510 that enables communication (e.g., sensor data or a result signal) from the ADC and processor block 504 to the transmitter 512.

[0034] In Figure 5 the example, the 2-wire current loop 500 also includes a 2-wire analog input module 522 coupled to the input-isolated 2-wire sensor transmitter module 502. As shown, the 2-wire analog input module 522 includes current loop terminals 532 and 534, where the current loop terminal 534 is coupled to a sense resistor (R SENSE ) as described above. In Figure 5 the example, the voltage across R SENSE is digitized by the ADC 524. The 2-wire analog input module 522 also includes a power supply 526 for the current loop 500, where the power supply 526 is coupled between the current loop ground 528 and the current loop terminal 532.

[0035] In operation, the power supply 526 is configured to supply sufficient voltage for a current (4mA - 20mA) to flow in the current loop 500 from the 2-wire analog input module 522 to the input-isolated 2-wire sensor transmitter 502 (via current loop terminals 532 and 516) and back to the current loop ground 528 (via current loop terminals 518 and 534). As needed, the input-isolated 2-wire sensor transmitter module 502 communicates sensor data or related signaling to the 2-wire analog input module 522, where the transmitter 512 includes a HART-enabled device (e.g., a HART-enabled device 1101 in Figure 1 , a HART-enabled device 110A in Figure 2 , a HART-enabled device 110B in Figure 3 , or a HART-enabled device 404 in Figure 4 , as described herein, that supports UART communication and SPI communication using the interrupt extension protocol and a reduced number of UART communication lines.

[0036] Figure 6 is a diagram illustrating a 4-wire current loop 600, according to an example. In Figure 6In the example, the 4-wire current loop 600 includes a fully isolated 4-wire sensor transmitter module 602 with current loop terminals 614, 616, 618, and 620. As shown, the fully isolated 4-wire sensor transmitter module 602 also includes a sensor 604 having a voltage supply output coupled to the current loop terminal 614 via a transformer (T2) having a primary coil (L3) and a secondary coil (L4). The fully isolated 4-wire sensor transmitter module 602 also includes a transmitter 608 having a voltage supply output coupled to the current loop terminal 614 via a transformer (T3) having a primary coil (L5) and a secondary coil (L6). In other words, T2 provides a voltage supply to the sensor 604, while T3 provides a voltage supply to the transmitter 608.

[0037] exist Figure 6 The example illustrates various grounding methods, including current loop ground 640, 4-wire ground 612, and isolation ground 610. As shown, the first end of L3 is coupled to current loop terminal 614, and the second end of L3 is coupled to current loop ground 640. Furthermore, the first end of L4 is coupled to sensor 604, and the second end of L4 is coupled to isolation ground 610. Additionally, the first end of L5 is coupled to current loop terminal 614, and the second end of L5 is coupled to current loop ground 640. Furthermore, the first end of L6 is coupled to transmitter 608, and the second end of L6 is coupled to 4-wire ground 612. Between sensor 604 and transmitter 608 is a data isolation block 606, which enables communication (e.g., sensor data or result signals) from sensor 604 to transmitter 608.

[0038] exist Figure 6 In the example, the 4-wire current loop 600 also includes a 4-wire analog input module 622 coupled to a fully isolated 4-wire sensor transmitter module 602. As shown, the 4-wire analog input module 622 includes current loop terminals 632, 634, 636, and 638, wherein current loop terminals 634 and 636 are coupled to a sensing resistor (R... SENSE Both ends. At Figure 6 In the example, R SENSE The voltage across the terminals is digitized by the ADC 624. The 4-wire analog input module 622 also includes a power supply 626 for the current loop 600, wherein the power supply 626 is coupled between the current loop ground 640 and the current loop terminal 632. Figure 6 The arrangement is such that terminal 638 of the 4-wire analog input module 622 is coupled to current loop ground 640 and terminal 620 of the fully isolated 4-wire sensor transmitter module 602 to extend the current loop ground to the fully isolated 4-wire sensor transmitter module 602.

[0039] In operation, the power supply 626 is configured to supply sufficient voltage for current (4mA - 20mA) to flow from the 4-wire analog input module 622 to the fully isolated 4-wire sensor transmitter 602 (via current loop terminals 632 and 614) and back to the current loop ground 640 (via current loop terminals 638 and 620) in the current loop 600, where L3 and L5 are coupled to the current loop ground 640. Further, the transmitter 608 outputs the differential signal communicated from the fully isolated 4-wire sensor transmitter 602 to the 4-wire analog input module 622 via current loop terminals 616, 618 of the fully isolated 4-wire sensor transmitter 602 and current loop terminals 634, 636 of the 4-wire analog input module 622. As needed, the fully isolated 4-wire sensor transmitter module 602 communicates sensor data or related signaling to the 4-wire analog input module 622, where the transmitter 608 comprises a HART-enabled device (e.g., Figure 1 the HART-enabled device 108 in FIG. 1, Figure 2 the HART-enabled device 108A in FIG. 2, Figure 3 the HART-enabled device 108B in FIG. 3, or Figure 4 the HART-enabled device 404 in FIG. 4), which supports UART communication and SPI communication using a reduced number of UART communication lines and interrupt expansion protocol, as described herein.

[0040] In some examples, the interrupt command format comprises 4 bytes (byte 1 - byte 4), where byte 1 indicates an interrupt condition, byte 2 includes a command identifier (ID), and byte 3 and byte 4 correspond to command data. Further, in some examples, the interrupt command response format comprises 4 bytes (byte 1 - byte 4), where byte 1 indicates an interrupt condition, byte 2 includes a command response ID, and byte 3 and byte 4 correspond to command response data. Further, in some examples, the interrupt exception format comprises 4 bytes (byte 1 - byte 4), where byte 1 indicates an interrupt condition, byte 2 includes an exception ID, and byte 3 and byte 4 correspond to exception data.

[0041] In some examples, the current loop (e.g., Figure 1 the current loop 100 in FIG. 1; Figure 5 the current loop 500 in FIG. 2, or Figure 6 the current loop 600 in FIG. 3) comprises: a receiver component (e.g., Figure 1 the receiver component 122 in FIG. 1, Figure 5 the receiver module 522 in FIG. 2, or Figure 6 the receiver module 622 in FIG. 3); a transmitter component (e.g., Figure 1 the transmitter component 102 in FIG. 1, Figure 5Transmitter module 502, or Figure 6 The transmitter module 602 in the receiver assembly; a first conductor (132) between the receiver assembly and the transmitter assembly; and a second conductor (134) between the receiver assembly and the transmitter assembly to complete a current loop. The transmitter assembly includes: a HART modem (e.g., Figure 2 DAC HART modem 208 Figure 3 DAC HART modem 305 or Figure 4 HART modem 423 in the middle); components (e.g., Figure 1 MCU 108 in Figure 2 MCU 204 in Figure 3 External MCU 314 Figure 4 MCU 402 in Figure 2 DAC 206 in Figure 3 ADC 304 in, or Figure 4 Block 430 in the middle), which is connected via a set of partial UART communication lines (e.g., Figure 4 The UART TXD communication line 450 and UART RXD communication line 452 communicate with the HART modem. In some examples, the component includes an MCU (e.g., Figure 1 MCU 108 in Figure 2 MCU 204 in Figure 3 External MCU 314, or Figure 4 MCU 402 in the example. In some examples, the component includes an ADC (e.g., Figure 3 ADC 304 in; or Figure 4 Block 430 in the middle) or DAC (e.g., Figure 2 DAC 206 in, or Figure 4 (Block 430 in the text). The transmitter component also includes: an interrupt extension protocol controller (e.g., ... Figure 1 Interrupt extension protocol controller 114, or Figure 4 The interrupt extension protocol controller 420 is coupled to or included in the HART modem and is configured to support UART and non-UART communication between the HART modem and the component using a set of partial UART communication lines.

[0042] In some examples, the HART modem and interrupt extension protocol controller are HART-enabled smart transmitter modules (e.g., Figure 2 The HART-enabled smart transmitter module 200 is a component of this module. In some examples, the HART modem and interrupt extension protocol controller are HART-enabled current input modules (e.g.,Figure 3 a component of the HART-enabled current input module 300 in FIG. 1. In some examples, the interrupt extension protocol controller is configured to detect an interrupt condition on the set of partial UART communication lines to support UART communication and non- UART communication between the HART modem and the component. In some examples, the interrupt extension protocol controller is configured to detect the interrupt condition when any one of the set of partial UART communication lines is at a logical low level for longer than a predetermined interval, and the predetermined interval corresponds to 11 bits in a telegraph data 424 in FIG. 1. In some examples, the interrupt extension protocol controller is configured to detect the interrupt condition when data sent from the component via one of the set of partial UART communication lines indicates a control write command or control write data. In some examples, the interrupt extension protocol controller is configured to detect the interrupt condition when data sent from the HART modem via one of the set of partial UART communication lines indicates a control read data, a status exception, or an acknowledgement of an interrupt write command. Figure 4

[0043] In some examples, the HART-enabled device (e.g., the HART-enabled device 110 in FIG. 1, or the HART-enabled device 404 in FIG. 4) includes: a UART TXD communication line (e.g., the UART TXD communication line 450 in FIG. 4); a UART RXD communication line (e.g., the UART RXD communication line 452 in FIG. 4); and a HART modem (e.g., the DAC HART modem 208 in FIG. 2, Figure 1 Figure 4 Figure 4 Figure 4 Figure 2 Figure 3 Figure 4 Figure 2 Figure 4 Figure 3 Figure 4 ​​​​​​​​​​​​

[0044] In some examples, the current loop emitter module (e.g., Figure 1 The transmitter assembly 102 in the middle Figure 5 Transmitter module 502, or Figure 6 The transmitter module 602 in the middle includes: MCU (e.g., Figure 1 MCU 108 in Figure 2 MCU 204 in Figure 3 External MCU 314, or Figure 4 MCU 402 in the middle); converter (e.g., Figure 2 DAC 206 in Figure 3 ADC305 or Figure 4 Block 430 in the middle), which is configured to convert analog signals to digital signals or digital signals to analog signals; HART modem (e.g., Figure 2 DAC HART modem 208 Figure 3 The DAC HART modem 305, or Figure 4 The HART modem 423 in the middle, which communicates via the TXD and RXD communication lines (e.g., Figure 4 The UART TXD communication line 450 and UART RXD communication line 452 are coupled to the MCU and converter; and the interrupt extension protocol controller (e.g., Figure 1 Interrupt extension protocol controller 114, or Figure 4 The interrupt extension protocol controller 420, which is coupled to or included in the HART modem, is configured to support the use of UART TXD and UART RXD communication lines (450, 452). Figure 4 Between the HART modem and the MCU, and between the HART modem (423) and the converter (DAC 206). Figure 2 ADC 305, Figure 3 Block 430, Figure 4 UART communication and non-UART communication between ( ).

[0045] In some examples, the interrupt extension protocol controller is configured to support UART communications and non-UART communications between the HART modem and the MCU or between the HART modem and the converter in response to an interrupt condition on the UART TXD communication line detected when data on the UART TXD communication line indicates a control write command or control write data. In some examples, the interrupt extension protocol controller is configured to support UART communications and non-UART communications between the HART modem and the MCU or between the HART modem and the converter in response to an interrupt condition on the UART RXD communication line detected when data on the UART RXD communication line indicates control read data, a status exception, or an acknowledgment of an interrupt write command. In some examples, the interrupt extension protocol controller is configured to support UART communications and non-UART communications between the HART modem and the MCU or between the HART modem and the converter in response to an interrupt condition on the UART TXD communication line or the UART RXD communication line detected when the UART TXD communication line or the UART RXD communication line is at a logical low for longer than a predetermined interval, and the predetermined interval corresponds to 11 bits in a UART telegraph.

[0046] In this specification, the term“coupled” can encompass a connection, communication, or signal path that enables a functional relationship consistent with this specification. For example, if device A generates a signal to control device B to perform an action: (a) in a first example, device A is coupled to device B by a direct connection; or (b) in a second example, device A is coupled to device B by an intermediate component C, such that device B is controlled by device A via a control signal generated by device A, if the intermediate component C does not change the functional relationship between device A and device B.

[0047] Modifications in the described embodiments are possible, and other embodiments are possible. For example, the modem functionality is not limited to the UART interface described herein. In some examples, the modem has an SPI interface. In these examples, a HART-enabled device with a modem can use the interrupt extension protocol and a reduced set of SPI communication lines to achieve similar benefits as described herein.

Claims

1. A current loop, comprising: a receiver assembly; a transmitter assembly; a first conductor between the receiver assembly and the transmitter assembly; and a second conductor between the receiver assembly and the transmitter assembly to complete the current loop, wherein the transmitter assembly includes: a Highway Addressable Remote Transducer modem (HART modem); a component that communicates with the HART modem via a set of partial Universal Asynchronous Receiver-Transmitter communication lines (partial UART communication lines); and an interrupt expansion protocol controller coupled to or included in the HART modem and configured to support UART and non-UART communications between the HART modem and the component using the set of partial UART communication lines.

2. The current loop of claim 1, wherein the set of partial UART communication lines includes a UART TXD communication line and a UART RXD communication line.

3. The current loop of claim 1, wherein the HART modem and the interrupt expansion protocol controller are components of a HART-enabled smart transmitter module.

4. The current loop of claim 1, wherein the HART modem and the interrupt expansion protocol controller are components of a HART-enabled current input module.

5. The current loop of claim 1, wherein the interrupt expansion protocol controller is configured to detect an interrupt condition on the set of partial UART communication lines to support UART and non-UART communications between the HART modem and the component.

6. The current loop of claim 5, wherein the interrupt expansion protocol controller is configured to detect the interrupt condition when any one of the set of partial UART communication lines is at a logic low for longer than a predetermined interval, wherein the predetermined interval corresponds to 11 bits in a UART telegraph.

7. The current loop of claim 5, wherein the interrupt expansion protocol controller is configured to detect the interrupt condition when data sent from the component via one of the set of partial UART communication lines indicates a control write command or control write data.

8. The current loop of claim 5, wherein the interrupt expansion protocol controller is configured to detect the interrupt condition when data sent from the HART modem via one of the set of partial UART communication lines indicates control read data, a status exception, or an acknowledgement of an interrupt write command.

9. The current loop of claim 1, wherein the component includes a microcontroller (MCU).

10. The current loop of claim 1, wherein the component includes an analog-to-digital converter (ADC) or a digital-to-analog converter (DAC).

11. A Highway Addressable Remote Transducer enabled device (HART enabled device), comprising: ​ a universal asynchronous receiver-transmitter TXD communication line, i.e., UART TXD communication line; a UART RXD communication line; and a highway addressable remote transducer modem, i.e., HART modem, coupled to the UART TXD communication line and the UART RXD communication line, wherein the HART modem is configured to support UART communication and non-UART communication using the UART TXD communication line and the UART RXD communication line based on an interrupt extension protocol.

12. The HART-enabled device of claim 11, further comprising a digital-to-analog converter, i.e., DAC, coupled to the HART modem via the UART TXD communication line and the UART RXD communication line.

13. The HART-enabled device of claim 11, further comprising an analog-to-digital converter, i.e., ADC, coupled to the HART modem via the UART TXD communication line and the UART RXD communication line.

14. The HART-enabled device of claim 11, wherein an interrupt condition of the interrupt extension protocol is detected when the UART TXD communication line or the UART RXD communication line is at a logic low for longer than a predetermined interval, wherein the predetermined interval corresponds to 11 bits in a UART telegraph.

15. The HART-enabled device of claim 11, wherein an interrupt condition of the interrupt extension protocol is detected when data sent from a component to the HART modem via the UART TXD communication line indicates a control write command or control write data.

16. The HART-enabled device of claim 11, wherein an interrupt condition of the interrupt extension protocol is detected when data sent from the HART modem to a component via the UART RXD communication line indicates control read data, a status exception, or an acknowledgment of an interrupt write command.

17. A current loop transmitter module, comprising: a microcontroller, i.e., MCU; a transducer configured to convert an analog signal to a digital signal or a digital signal to an analog signal; a high way addressable remote transducer modem, i.e., HART modem, coupled to the MCU and the transducer via a universal asynchronous receiver-transmitter TXD communication line, i.e., UART TXD communication line, and a UART RXD communication line; and an interrupt extension protocol controller coupled to or included in the HART modem and configured to support universal asynchronous receiver-transmitter, i.e., UART, communication and non-UART communication between the HART modem and the MCU and between the HART modem and the transducer using the UART TXD communication line and the UART RXD communication line. ​ 18. The current loop transmitter module of claim 17, wherein the interrupt expansion protocol controller is configured to support the UART communications and the non- UART communications between the HART modem and the MCU or between the HART modem and the converter in response to an interrupt condition on the UART TXD communication line detected when data on the UART TXD communication line indicates a control write command or control write data.

19. The current loop transmitter module of claim 17, wherein the interrupt expansion protocol controller is configured to support the UART communications and the non- UART communications between the HART modem and the MCU or between the HART modem and the converter in response to an interrupt condition on the UART RXD communication line detected when data on the UART RXD communication line indicates control read data, a status exception, or an acknowledgement of an interrupt write command.

20. The current loop transmitter module of claim 17, wherein the interrupt expansion protocol controller is configured to support the UART communications and the non- UART communications between the HART modem and the MCU or between the HART modem and the converter in response to an interrupt condition on the UART TXD communication line or the UART RXD communication line detected when the UART TXD communication line or the UART RXD communication line is at a logic low for longer than a predetermined interval, wherein the predetermined interval corresponds to 11 bits in a UART telegraph.

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