Light sensor

Abstract

The light sensor (1) of the present application is provided with: a charge generation region (29) that generates charges in accordance with incident light; a charge collection region (33) that transfers the charges generated in the charge generation region (29); and at least one transfer gate electrode (41) that is arranged on a transfer region (35) between the charge generation region (29) and the charge collection region (33). The charge generation region (29) includes: an avalanche multiplication region (23) that generates avalanche multiplication; and a sloped potential formation region (59) that forms a sloped potential that is sloped in such a manner that the potential becomes lower as the transfer region (35) is approached, in the charge generation region (29).

Description

TECHNICAL FIELD

[0001] One aspect of the present application relates to a light sensor. BACKGROUND

[0002] As a light sensor, a light sensor including a charge generation region that generates a charge according to incident light, a charge collection region that transports the charge generated in the charge generation region, and a transport gate electrode disposed on a region between the charge generation region and the charge collection region is known. (For example, refer to Patent Literature 1.) In such a light sensor, it is possible to transport the charge from the charge generation region to the charge collection region at high speed.

[0003] PRIOR ART DOCUMENTS

[0004] PATENT LITERATURE

[0005] Patent Literature 1: Japanese Patent Application Publication No. 2015-5752 SUMMARY

[0006] PROBLEMS TO BE SOLVED BY THE INVENTION

[0007] In the light sensor described above, sometimes it is required to increase the area of the charge generation region in order to expand the light receiving region. However, in the case where the area of the charge generation region is large, the movement of the charge within the charge generation region takes time, and thus the charge transport from the charge generation region to the charge collection region can be slow.

[0008] One aspect of the present application aims to provide a light sensor that is capable of transporting a charge at high speed even in the case where the area of the light receiving region is large.

[0009] MEANS FOR SOLVING THE PROBLEM

[0010] The light sensor of one aspect of the present application has a charge generation region that generates a charge according to incident light, a charge collection region that transports the charge generated in the charge generation region, and at least one transport gate electrode disposed on a transport region between the charge generation region and the charge collection region, the charge generation region including an avalanche multiplication region that generates avalanche multiplication, and a tilt potential formation region that forms a tilt potential that tilts in a manner that the potential becomes lower as it approaches the transport region in the charge generation region.

[0011] In the optical sensor, the charge generation region includes an avalanche multiplication region that generates avalanche multiplication. Thus, avalanche multiplication can be generated in the charge generation region, and high sensitivity can be achieved. In addition, the charge generation region includes a tilted potential formation region that forms a tilted potential that tilts in a manner in which the potential becomes lower as the charge generation region approaches the transfer region. Thus, a tilted potential that tilts in a manner in which the potential becomes lower as the charge generation region approaches the transfer region can be formed in the charge generation region, and the moving speed of the charges within the charge generation region can be accelerated. Therefore, according to the optical sensor, even in a case where the area of the light receiving region is large, the charges can be transferred at high speed.

[0012] Also, the at least one transfer gate electrode can include a first transfer gate electrode and a second transfer gate electrode that is disposed on the charge generation region side with respect to the first transfer gate electrode. In this case, as described later, suppression of noise generation and expansion of the dynamic range can be performed.

[0013] Also, in the charge transfer processing in which the charges generated in the charge generation region are transferred to the charge collection region, the potentials of the first transfer gate electrode and the second transfer gate electrode can be given in such a manner that a first potential that is the potential of the region directly below the first transfer gate electrode and a second potential that is the potential of the region directly below the second transfer gate electrode become higher than the potential of the boundary portion between the charge generation region and the transfer region after becoming lower than the potential of the boundary portion. In this case, the charges can be transferred from the charge generation region to the charge collection region at high speed using the first transfer gate electrode and the second transfer gate electrode, and the movement of the charges from the charge generation region to the charge collection region after the charge transfer can be suppressed.

[0014] Also, in the charge transfer processing, the potentials of the first transfer gate electrode and the second transfer gate electrode can be given in such a manner that the second potential becomes higher than the first potential. In this case, the return of the charges from the region directly below the first transfer gate electrode to the charge generation region can be suppressed, and thus the generation of noise can be suppressed. In addition, the amount of readout of the charges can be increased by utilizing the capacitance of the region directly below the first transfer gate electrode, and the dynamic range can be expanded.

[0015] Also, in a state where the potential of the first transfer gate electrode and the potential of the second transfer gate electrode are equal to each other, the second potential can be higher than the first potential. In this case, by giving the same potential to the first transfer gate electrode and the second transfer gate electrode, the second potential can be made higher than the first potential. As a result, for example, compared to a case where the second potential is made higher than the first potential by applying different potentials to the first transfer gate electrode and the second transfer gate electrode, the structure for giving the potentials can be simplified.

[0016] Also, the transfer region can include a potential adjustment layer that makes the second potential higher than the first potential. In this case, the second potential can be made higher than the first potential by the potential adjustment layer.

[0017] Also, in the charge transfer processing, the first potential and the second potential can be below the potential of the boundary portion, the second potential can be equal to the potential of the boundary portion, and the first potential can be lower than the potential of the boundary portion. In this case, accumulation of charges in the region directly below the second transfer gate electrode can be suppressed, and generation of noise due to return of charges from the region directly below the second transfer gate electrode to the charge generation region can be suppressed.

[0018] Also, in the charge transfer processing, from a state in which the first potential and the second potential are below the potential of the boundary portion, the first potential can be made higher than the potential of the boundary portion after the second potential becomes higher than the potential of the boundary portion. In this case, return of charges from the region directly below the first transfer gate electrode to the charge generation region can be reliably suppressed, and generation of noise can be reliably suppressed.

[0019] Also, the avalanche multiplication region can be formed in a layer shape along a prescribed plane, and when a side on which the transfer gate electrode is located with respect to the avalanche multiplication region in a direction perpendicular to the plane is set as a first side, and an opposite side of the first side is set as a second side, the inclined potential formation region can be located on the first side with respect to the avalanche multiplication region. In this case, the proportion of charges existing in a region close to the transfer gate electrode increases, and charges can be transferred at a higher speed. Also, by forming the inclined potential in the vicinity of the transfer gate electrode, charges can be transferred at a higher speed.

[0020] Also, the inclined potential formation region can include a plurality of semiconductor regions arranged in a manner that impurity concentration becomes higher as the transfer region is approached. In this case, the inclined potential can be appropriately formed in the charge generation region.

[0021] Also, the inclined potential formation region can include a first semiconductor region including a first portion and a second portion, and a second semiconductor region having higher impurity concentration than the first semiconductor region, disposed between the first portion and the second portion, and expanding in width as the transfer region is approached. In this case, the inclined potential can be appropriately formed in the charge generation region.

[0022] Also, the avalanche multiplication region can be formed in layers along a prescribed plane, and when a side on which the gate electrode is located with respect to the avalanche multiplication region in a direction perpendicular to the plane is set as a first side, and a side opposite to the first side is set as a second side, the inclined potential formation region is located on the second side with respect to the avalanche multiplication region. In this case, since it is difficult to generate a restriction related to the inclination height of the inclined potential, it is possible to increase the inclination of the inclined potential, and it is possible to transport the electric charges at a higher speed. Also, since the electric charges collected by the inclined potential are multiplied in the avalanche multiplication region, it is possible to limit the generation site of the multiplication, and it is possible to improve the uniformity of the multiplication.

[0023] Also, the inclined potential formation region can include a first semiconductor layer, and a second semiconductor layer located on a second side with respect to the first semiconductor layer, and the inclined potential can be formed by forming a step portion between the first semiconductor layer and the second semiconductor layer. In this case, it is possible to appropriately form the inclined potential in the charge generation region.

[0024] Also, a through-hole can be formed in the first semiconductor layer, and the through-hole can overlap with the boundary portion of the charge generation region and the transport region in a direction perpendicular to the plane. In this case, it is possible to collect the electric charges guided by the inclined potential at the boundary portion between the charge generation region and the transport region.

[0025] Also, the charge generation region can have a buried photodiode structure. In this case, it is possible to suppress the generation of the dark current in the charge generation region.

[0026] Effects of Invention

[0027] According to one aspect of the present application, it is possible to provide a light sensor capable of transporting electric charges at a high speed even when the area of the light receiving region is large. BRIEF DESCRIPTION OF DRAWINGS

[0028] Figure 1 FIG. 1 is a structural view of a light detection device according to an embodiment.

[0029] Figure 2 FIG. 2 is a cross-sectional view along the line II-II of FIG. 1. Figure 1

[0030] Figure 3 FIGS. 3(a) and 3(b) are potential distribution diagrams for explaining an example of the operation of the light sensor.

[0031] Figure 4 FIGS. 4(a) and 4(b) are potential distribution diagrams for explaining an example of the operation of the light sensor.

[0032] Figure 5 FIG. 5 is a potential distribution diagram for explaining an example of the operation of the light sensor according to the first modified example.

[0033] ​Figure 6 is a plan view of a light sensor of a first modification example.

[0034] Figure 7 is a cross-sectional view of a light sensor of a third modification example. DETAILED DESCRIPTION

[0035] Hereinafter, one embodiment of the present application will be described in detail with reference to the drawings. In the following description, the same or corresponding elements are designated by the same reference numerals, and overlapping description is omitted.

[0036] [Light detection device]

[0037] As shown in Figure 1 , the light detection device 100 includes a light sensor (image sensor) 1 and a control section 70. The control section 70 controls the light sensor 1. The control section 70 is constituted by, for example, an on-chip integrated circuit mounted on a semiconductor substrate constituting the light sensor 1, but can be constituted separately from the light sensor 1.

[0038] As shown in Figure 1 and Figure 2 , the light sensor 1 includes a semiconductor layer 2, an electrode layer 4, and a protective layer 6. The semiconductor layer 2 has a first surface 2a and a second surface 2b. The second surface 2b is a surface on the opposite side of the first surface 2a. The light sensor 1 includes a plurality of pixels 10 arranged along the first surface 2a. The plurality of pixels 10 are, for example, two-dimensionally arranged along the first surface 2a. Hereinafter, the thickness direction of the semiconductor layer 2 is referred to as a Z direction, one direction perpendicular to the Z direction is referred to as an X direction, and a direction perpendicular to both the Z direction and the X direction is referred to as a Y direction. Further, one side in the Z direction is referred to as a first side, and the other side (the opposite side of the first side) in the Z direction is referred to as a second side. In Figure 1 , the illustration of a part of the structure (a part of the electrode layer 4, the protective layer 6, and the like) is omitted.

[0039] Each pixel 10 has, in the semiconductor layer 2, a semiconductor region 21, a semiconductor region 22, an avalanche multiplication region 23, a charge accumulation region 24, an intervening region 25, a well region 31, 32, a charge collection region 33, and a channel region 34. Each region 21 to 26, 31 to 34 is formed by performing various processes (for example, etching, film formation, impurity implantation, and the like) on a semiconductor substrate (for example, a silicon substrate).

[0040] The semiconductor region 21 is a region of p type (first conductive type) and is formed in a layer shape along the second surface 2b of the semiconductor layer 2. The carrier concentration of the semiconductor region 21 is higher than the carrier concentration of the semiconductor region 22. It is preferable that the thickness of the semiconductor region 21 be as thin as possible. As an example, the semiconductor region 21 is 1 x 10 16 cm-3 The p-type region of the above carrier concentration (impurity concentration) has a thickness of 1 μm or less. Further, the semiconductor region 21 can be formed by accumulation of a transparent electrode formed on the second surface 2b through an insulating film.

[0041] The semiconductor region 22 is a p-type region, and is located on the first side with respect to the semiconductor region 21 when the semiconductor layer 2 is formed in layers. As an example, the semiconductor region 22 has a carrier concentration of 1 x 1014cm-3or more and 1 x 1016cm-3or less. 15 cm -3 The p-type region of the following carrier concentration has a thickness of 2 μm or more, and as an example, 10 μm or less.

[0042] The avalanche multiplication region 23 includes a first multiplication region 23a and a second multiplication region 23b. The first multiplication region 23a is a p-type region, and is located on the first side with respect to the semiconductor region 22 when the semiconductor layer 2 is formed in layers. As an example, the first multiplication region 23a has a carrier concentration of 1 x 1014cm-3or more and 1 x 1016cm-3or less. 16 cm -3 The p-type region of the above carrier concentration has a thickness of 1 μm or less. The second multiplication region 23b is an n-type (second conductive type) region, and is located on the first side with respect to the first multiplication region 23a when the semiconductor layer 2 is formed in layers. As an example, the second multiplication region 23b has a carrier concentration of 1 x 1014cm-3or more and 1 x 1016cm-3or less. 16 cm -3 The n-type region of the above carrier concentration has a thickness of 1 μm or less. The first multiplication region 23a and the second multiplication region 23b form a pn junction. The avalanche multiplication region 23 is a region in which avalanche multiplication occurs.

[0043] The charge accumulation region 24 is an n-type region, and is located on the first side with respect to the avalanche multiplication region 23 when the semiconductor layer 2 is formed in layers. As an example, the charge accumulation region 24 has a thickness of 1 μm or less. Details of the charge accumulation region 24 are described later.

[0044] The intervening region 25 is a p-type region, and is located on the first side with respect to the charge accumulation region 24 when the semiconductor layer 2 is formed in layers along the first surface 2a. That is, the intervening region 25 has a different conductive type from the charge accumulation region 24. The semiconductor region 21, the semiconductor region 22, the first multiplication region 23a, the second multiplication region 23b, the charge accumulation region 24, and the intervening region 25 are formed in layers along the XY plane (a plane perpendicular to the Z direction), and are arranged in order along the Z direction. As an example, the intervening region 25 has a carrier concentration of 1 x 1014cm-3or more and 1 x 1016cm-3or less. 15 cm -3 The p-type region of the above carrier concentration has a thickness of 0.2 μm or less.

[0045] The charge accumulation region 24 and the intervention region 25 form a pn junction and constitute a buried photodiode. That is, the charge generation region 29 has a buried photodiode structure. The semiconductor regions 21 and 22, the avalanche multiplication region 23, the charge accumulation region 24, and the intervention region 25 function as a charge generation region (light absorption region, photoelectric conversion region) 29 that generates charge according to incident light. In other words, the charge generation region 29 includes: semiconductor regions 21 and 22, avalanche multiplication region 23, charge accumulation region 24, and intervention region 25.

[0046] Well regions 31 and 32 are p-type regions, formed in a layered manner along the first surface 2a of semiconductor layer 2. Well regions 31 and 32 are located on the first side relative to avalanche multiplication region 23. Well region 31 is configured to be adjacent to charge accumulation region 24 and intervention region 25 in the X direction. Well region 32 is configured to surround charge accumulation region 24, intervention region 25, and well region 31 when viewed from the Z direction. As an example, well regions 31 and 32 have a size of 1 × 10⁻⁶. 16 ~5×10 17 cm -3 The p-type region has a carrier concentration of approximately 1 μm in thickness. The well regions 31 and 32 form multiple readout circuits (e.g., source follower amplifiers, reset transistors, etc.). These multiple readout circuits are electrically connected to the charge collection region 33.

[0047] A charge collection region 33 and a channel region 34 are formed in the well regions 31 and 32. The charge collection region 33 is an n-type region, formed in a layered manner along the first surface 2a of the semiconductor layer 2, and disposed at the boundary between the well regions 31 and 32. As an example, the charge collection region 33 has a size of 1×10⁻⁶. 18 cm -3 The n-type region with the above-mentioned carrier concentration has a thickness of approximately 0.2 μm. The charge collection region 33 functions as floating diffusion. The channel region 34 is an n-type region, formed in a layer along the first surface 2a of the semiconductor layer 2, and disposed within the well region 32. The intervention region 25, the charge collection region 33, and the channel region 34 are arranged sequentially along the X-direction. Figure 1 In this example, the width (length along the Y direction) of the charge collection region 33 is smaller than the width (length along the Y direction) of the fourth region 54, but the width of the charge collection region 33 can also be the same as the width of the fourth region 54. In this case, charge transfer occurs smoothly through a transport path of the same width.

[0048] An electrode layer 4 is disposed on the first surface 2a of the semiconductor layer 2. Each pixel 10 has a transfer gate electrode 41 and an exit gate electrode 42 on the electrode layer 4. The transfer gate electrode 41 and the exit gate electrode 42 are formed on the electrode layer 4 and disposed on the first surface 2a of the semiconductor layer 2 with an insulating layer 49 in between. The insulating layer 49 is, for example, a silicon nitride film, a silicon oxide film, etc. The transfer gate electrode 41 and the exit gate electrode 42 are, for example, formed of polysilicon.

[0049] A transfer gate electrode 41 is disposed on a transfer region 35 of the well region 31, between the intervention region 25 and the charge collection region 33. The transfer region 35 is the region directly below the transfer gate electrode 41. The transfer gate electrode 41 has a first transfer gate electrode 43 and a second transfer gate electrode 44. The second transfer gate electrode 44 is disposed on the intervention region 25 side relative to the first transfer gate electrode 43. Furthermore, in this specification, "the region directly below an electrode" refers to the region overlapping with that electrode in the Z direction.

[0050] The second transmission gate electrode 44 is formed to climb onto the first transmission gate electrode 43 and has a climbing portion 44a disposed on the first transmission gate electrode 43. An insulating layer 45 is formed on the surface of the first transmission gate electrode 43, and the first transmission gate electrode 43 is electrically isolated from the second transmission gate electrode 44 by the insulating layer 45. When viewed from the Z direction, the first transmission gate electrode 43 and the second transmission gate electrode 44 are each rectangles with their long sides parallel to the Y direction.

[0051] A potential adjustment layer 36 is formed in the transmission region 35. The potential adjustment layer 36 is configured to overlap with the second transmission gate electrode 44 in the Z direction and be adjacent to the intervention region 25 in the X direction. As an example, the potential adjustment layer 36 has a size of 1×10⁻⁶. 15 ~1×10 18 cm -3 A P-type region with a carrier concentration of a certain degree and a thickness of 0.1 μm.

[0052] By forming a potential adjustment layer 36, such as Figure 3 As shown in (a), the second potential φ44, which is the potential of the region directly below the second transmission gate electrode 44, becomes higher than the first potential φ43, which is the potential of the region directly below the first transmission gate electrode 43. Figure 3 In (a), the potential distribution along the X direction is shown. Figure 3 In the state shown in (a), the potential of the first transmission gate electrode 43 and the potential of the second transmission gate electrode 44 are equal to each other.

[0053] The discharge gate electrode 42 is disposed in the region of the well region 32 between the charge collection region 33 and the channel region 34. The discharge gate electrode 42 is, for example, rectangular in shape with two opposite sides in the X direction and two opposite sides in the Y direction. The electrode layer 4 is covered by a protective layer 6. The protective layer 6 is, for example, an insulating layer such as a BPSG (Boro-phospho silicate glass) film.

[0054] like Figure 1 and Figure 2 As shown, the charge accumulation region 24 comprises: region 51, region 52, region 53, and region 54. Each region 51-54 is an n-type region. The impurity concentration in regions 51-54 increases in the order of region 51, region 52, region 53, and region 54. That is, region 52 has a higher impurity concentration than region 51, region 53 has a higher impurity concentration than region 52, and region 54 has a higher impurity concentration than region 53. The impurity concentration in region 51 is 1 × 10⁻⁶. 13 ~1×10 16 cm -3 The degree of impurity concentration in regions 2 (52), 3 (53), and 4 (54) is 1 × 10⁻⁶. 16 ~1×10 19 cm -3 The degree of [something]. Furthermore, the first region 51 can also be a p-type region. In this case, charge can be accumulated by increasing the potential in a portion of the first region 51 through a depletion layer generated between the second region 52, the third region 53, and the fourth region 54.

[0055] Region 51 is rectangular when viewed from the Z direction. Regions 52, 53, and 54 are arranged sequentially along the X direction. Region 54 is adjacent to the transport region 35 in the X direction. That is, regions 52, 53, and 54 are arranged such that the impurity concentration increases as they approach the transport region 35. When viewed from the Z direction, regions 52, 53, 54, the second transport gate electrode 44, the first transport gate electrode 43, and the charge collection region 33 are arranged sequentially along the X direction. Regions 52, 53, and 54 are disposed in the Y direction between the first portion 51a and the second portion 51b of region 51.

[0056] The width (length along the Y direction) Wl of the region demarcated by the 2nd region 52, the 3rd region 53, and the 4th region 54 continuously increases as it approaches the transfer region 35 when viewed from the Z direction. The 2nd region 52, the 3rd region 53, and the 4th region 54 each have a trapezoidal shape when viewed from the Z direction. The width Wl increases linearly in each of the 2nd region 52, the 3rd region 53, and the 4th region 54. The width Wl continuously changes at each of the boundary between the 2nd region 52 and the 3rd region 53, and the boundary between the 3rd region 53 and the 4th region 54.

[0057] The charge accumulation region 24 has a 1st region 51, a 2nd region 52, a 3rd region 53, and a 4th region 54, so as to have a sloped potential A formed therein as shown in Figure 3 and Figure 4 The charge accumulation region 24 has a 1st region 51, a 2nd region 52, a 3rd region 53, and a 4th region 54, so as to have a sloped potential A formed therein as shown in Figure 3 and Figure 4 A potential distribution diagram along the X direction is shown. In this example, the potential φ24 of the charge accumulation region 24 linearly decreases as it approaches the transfer region 35. In this way, the 1st region 51, the 2nd region 52, the 3rd region 53, and the 4th region 54 (charge accumulation region 24) function as a sloped potential formation region 59 that forms the sloped potential A. The sloped potential formation region 59 is located on the 1st side with respect to the avalanche multiplication region 23 in the Z direction. The 1st side is the side on which the transfer gate electrode 41 is located with respect to the avalanche multiplication region 23 in the Z direction.

[0058] [Light detection method]

[0059] An example of the light detection operation of the light sensor 1 will be described with reference to Figure 3 and Figure 4 The operation of the light sensor 1 is controlled by the control section 70. More specifically, the control section 70 controls the voltage applied to the transfer gate electrode 41 and the drain gate electrode 42, thereby controlling the operation of the light sensor 1. Hereinafter, the operation will be described with focus on one pixel 10, and the operation of the other pixels 10 is the same.

[0060] First, a charge accumulation process of accumulating charges in the charge accumulation region 24 is performed. In the charge accumulation process, a negative voltage (for example, -50 V) is applied to the semiconductor region 21 with the potential of the intervening region 25 as a reference. That is, a reverse bias is applied to the pn junction formed in the avalanche multiplication region 23. As a result, 3 x 1014 5 ~ 4 x 1014 5V / cm. In this state, when light is incident on the semiconductor layer 2 from the second surface 2b, electrons (charges) are generated in the semiconductor regions 21, 22 due to the absorption of the light. The generated charges are multiplied in the avalanche multiplication region 23, and move to the charge accumulation region 24. In the photo sensor 1, a region in the charge generation region 29 that overlaps the charge accumulation region 24 in the Z direction functions as a light receiving region. Further, the intervening region 25 is electrically connected to the ground electrode, and is grounded.

[0061] As shown in (a) of FIG. 9, the charges that move to the charge accumulation region 24 are accumulated in the charge accumulation region 24. As described above, the charge accumulation region 24 is formed with a sloped potential A that slopes in a manner such that the potential becomes lower as it approaches the transfer region 35. Therefore, the charges move at high speed within the charge accumulation region 24 toward the transfer region 35 side. Figure 3

[0062] In the charge accumulation process, the first potential φ43 of the region directly below the first transfer gate electrode 43 and the second potential φ44 of the region directly below the second transfer gate electrode 44 are made higher than the potential Pa of the lower end of the sloped potential A. The potential Pa of the lower end of the sloped potential A corresponds to the potential of the boundary portion of the charge accumulation region 24 and the transfer region 35. Due to this, the charges do not move from the charge accumulation region 24 to the charge collection region 33, but are accumulated in the charge accumulation region 24.

[0063] In this example, the control section 70 controls the voltage applied to the first transfer gate electrode 43 and the second transfer gate electrode 44 in two stages of being turned on and off. In the charge accumulation process, the voltage applied to the first transfer gate electrode 43 and the second transfer gate electrode 44 is turned off. The off voltage applied to the first transfer gate electrode 43 is equal to the off voltage applied to the second transfer gate electrode 44, and is, for example, 0 V. As shown in (a) of FIG. 10, in the state where the voltage applied to the first transfer gate electrode 43 and the second transfer gate electrode 44 is turned off, the second potential φ44 is higher than the first potential φ43. Figure 3 Figure 3 As shown in (a) of FIG. 10, at the start time of the charge accumulation process, a certain amount of charges B remain in the charge collection region 33 and the channel region 34. The charges B are charges that remain in the charge collection region 33 and the channel region 34 at the time of the reset process described later.

[0064] Next, a charge transfer process of transferring the charges to the charge collection region 33 is performed. In the charge transfer process, the first potential φ43 and the second potential φ44 are made higher than the potential Pa of the lower end of the sloped potential A after becoming lower than the potential Pa. ​​

[0065] More specifically, first, as shown in (a) of FIG. 4, the voltage applied to the first transfer gate electrode 43 and the second transfer gate electrode 44 is turned on, and the first potential φ43 and the second potential φ44 become potentials Pa or more of the lower end of the inclined potential A. In this state, the first potential φ43 and the second potential φ44 are equal to the potential Pa. Thus, the charges accumulated in the charge accumulation region 24 move to the region directly below the first transfer gate electrode 43 and the charge collection region 33. The region directly below the second transfer gate electrode 44 does not accumulate charges. In this case, the first potential φ43 and the second potential φ44 are equal to each other. Thus, the potential of the region directly below the first transfer gate electrode 43 and the potential of the region directly below the second transfer gate electrode 44 are equal to each other. Figure 3 As shown in (b) of FIG. 4, the voltage applied to the first transfer gate electrode 43 and the second transfer gate electrode 44 is turned on, and the first potential φ43 and the second potential φ44 become potentials Pa or more of the lower end of the inclined potential A. In this state, the first potential φ43 and the second potential φ44 are equal to the potential Pa. Thus, the charges accumulated in the charge accumulation region 24 move to the region directly below the first transfer gate electrode 43 and the charge collection region 33. The region directly below the second transfer gate electrode 44 does not accumulate charges. In this case, the first potential φ43 and the second potential φ44 are equal to each other. Thus, the potential of the region directly below the first transfer gate electrode 43 and the potential of the region directly below the second transfer gate electrode 44 are equal to each other. Figure 3 As shown in (b) of FIG. 4, the voltage applied to the first transfer gate electrode 43 and the second transfer gate electrode 44 is turned on, and the first potential φ43 and the second potential φ44 become potentials Pa or more of the lower end of the inclined potential A. In this state, the first potential φ43 and the second potential φ44 are equal to the potential Pa. Thus, the charges accumulated in the charge accumulation region 24 move to the region directly below the first transfer gate electrode 43 and the charge collection region 33. The region directly below the second transfer gate electrode 44 does not accumulate charges. In this case, the first potential φ43 and the second potential φ44 are equal to each other. Thus, the potential of the region directly below the first transfer gate electrode 43 and the potential of the region directly below the second transfer gate electrode 44 are equal to each other.

[0066] In this example, the on voltages of the first transfer gate electrode 43 and the second transfer gate electrode 44 are equal to each other. As shown in (a) of FIG. 5, in a state where the voltage applied to the first transfer gate electrode 43 and the second transfer gate electrode 44 is turned on, the first potential φ43 and the second potential φ44 are equal to each other. Figure 3 As shown in (b) of FIG. 5, in a state where the voltage applied to the first transfer gate electrode 43 and the second transfer gate electrode 44 is turned on, the first potential φ43 and the second potential φ44 are equal to each other.

[0067] Next, as shown in (a) of FIG. 6, the voltage applied to the first transfer gate electrode 43 is turned on, and the voltage applied to the second transfer gate electrode 44 is turned off, and the second potential φ44 becomes higher than the potential Pa of the lower end of the inclined potential A. At this time, since the region directly below the second transfer gate electrode 44 does not accumulate charges, no movement of charges occurs. Figure 4 Next, as shown in (b) of FIG. 6, the voltage applied to the first transfer gate electrode 43 is turned off, and the first potential φ43 becomes higher than the potential Pa of the lower end of the inclined potential A. Thus, the charges accumulated in the region directly below the first transfer gate electrode 43 move to the charge collection region 33. In this way, in the charge transfer processing, from the state where the first potential φ43 and the second potential φ44 are potentials Pa or less ( (b) of FIG. 4), after the second potential φ44 becomes higher than the potential Pa ( (a) of FIG. 6), the first potential φ43 becomes higher than the potential Pa ( (b) of FIG. 6).

[0068] Figure 4 Next, as shown in (b) of FIG. 6, the voltage applied to the first transfer gate electrode 43 is turned off, and the first potential φ43 becomes higher than the potential Pa of the lower end of the inclined potential A. Thus, the charges accumulated in the region directly below the first transfer gate electrode 43 move to the charge collection region 33. In this way, in the charge transfer processing, from the state where the first potential φ43 and the second potential φ44 are potentials Pa or less ( (b) of FIG. 4), after the second potential φ44 becomes higher than the potential Pa ( (a) of FIG. 6), the first potential φ43 becomes higher than the potential Pa ( (b) of FIG. 6). Figure 3 Figure 4 In any of the states shown in (b) of FIG. 4, (a) of FIG. 5, and (b) of FIG. 6, the second potential φ44 is higher than the first potential φ43. Thus, it is possible to suppress the return of charges from the region directly below the first transfer gate electrode 43 to the charge accumulation region 24. Figure 4

[0069] In any of the states shown in (b) of FIG. 4, (a) of FIG. 5, and (b) of FIG. 6, the second potential φ44 is higher than the first potential φ43. Thus, it is possible to suppress the return of charges from the region directly below the first transfer gate electrode 43 to the charge accumulation region 24. Figure 3 Figure 4 In any of the states shown in (b) of FIG. 4, (a) of FIG. 5, and (b) of FIG. 6, the second potential φ44 is higher than the first potential φ43. Thus, it is possible to suppress the return of charges from the region directly below the first transfer gate electrode 43 to the charge accumulation region 24. Figure 4 ​​​​​

[0070] Next, readout processing of reading out the electric charges accumulated in the charge collection region 33 is performed. The electric charges accumulated in the charge collection region 33 are read out by the readout circuit described above. Next, reset processing of resetting the charge collection region 33 is performed. In the reset processing, the potential of the drain gate electrode 42 is controlled in such a manner that the electric potential φ42 of the region directly below the drain gate electrode 42 becomes lower. Thereby, the electric charges in the charge collection region 33 are drained to the outside via the channel region 34, and the charge collection region 33 is reset. After the reset processing is completed, the electric potential φ42 is restored.

[0071] [Effects]

[0072] In the optical sensor 1, the charge generation region 29 includes an avalanche multiplication region 23 that generates avalanche multiplication. Thereby, it is possible to generate avalanche multiplication in the charge generation region 29, and it is possible to achieve high sensitivity. Further, the charge generation region 29 includes a tilt potential forming region 59 that forms a tilt potential A that tilts in such a manner that the electric potential becomes lower as approaching the transfer region 35 in the charge generation region 29. Thereby, it is possible to form the tilt potential A that tilts in such a manner that the electric potential becomes lower as approaching the transfer region 35 in the charge generation region 29, and it is possible to accelerate the moving speed of the electric charges in the charge generation region 29. Therefore, according to the optical sensor 1, even in the case where the area of the light receiving region is large, it is possible to transfer the electric charges at high speed.

[0073] The optical sensor 1 includes a first transfer gate electrode 43, and a second transfer gate electrode 44 that is arranged on the charge generation region 29 side with respect to the first transfer gate electrode 43. Thereby, as described later, it is possible to perform suppression of noise generation, and expansion of the dynamic range.

[0074] In the electric charge transfer processing of transferring the electric charges generated in the charge generation region 29 to the charge collection region 33, the first potential φ43 that is the electric potential of the region directly below the first transfer gate electrode 43, and the second potential φ44 that is the electric potential of the region directly below the second transfer gate electrode 44, are controlled in such a manner that, after becoming lower than the electric potential Pa (the electric potential of the boundary portion of the charge generation region 29 and the transfer region 35) that is the lower end of the tilt potential A, they become higher than the electric potential Pa, with respect to the first transfer gate electrode 43 and the second transfer gate electrode 44. Thereby, it is possible to transfer the electric charges from the charge generation region 29 to the charge collection region 33 at high speed using the first transfer gate electrode 43 and the second transfer gate electrode 44, and it is possible to suppress the movement of the electric charges from the charge generation region 29 to the charge collection region 33 after the electric charge transfer.

[0075] In the charge transfer processing, the potential is applied to the first transfer gate electrode 43 and the second transfer gate electrode 44 in a manner that the second potential φ44 becomes higher than the first potential φ43. Thereby, it is possible to suppress the return of the charge from the area directly below the first transfer gate electrode 43 to the charge accumulation region 24 (charge generation region 29), and it is possible to suppress the generation of noise. Further, it is possible to increase the readout amount of the charge using the capacitance of the area directly below the first transfer gate electrode 43, and it is possible to expand the dynamic range.

[0076] With regard to this point, reference is made to Figure 5 Further description is made. Figure 5 is a potential distribution diagram for explaining an action example of the light sensor of the first modified example. The transfer gate electrode 41A of the first modified example is configured only by a single electrode. In the first modified example, it is also possible to apply the potential to the transfer gate electrode 41A in a manner that the potential φ41A of the area directly below the transfer gate electrode 41A becomes higher than the potential Pa after the potential Pa becomes the lower end of the inclined potential A, thereby performing the charge transfer. Therefore, as with the above-described embodiment, it is possible to achieve the high sensitivity, and even in the case where the area of the light receiving region is large, it is possible to transfer the charge at high speed.

[0077] However, in the first modified example, as shown in Figure 5 , the readout amount of the charge is an amount corresponding to the difference DF between the potential Pa of the lower end of the inclined potential A and the potential φ33 of the charge collection region 33. On the other hand, in the above-described embodiment, since it is possible to utilize the capacitance of the area directly below the first transfer gate electrode 43 as the readout amount of the charge, as shown in Figure 4 (a) and Figure 4 (b), the readout amount of the charge is increased by the amount of the capacitance of the area directly below the first transfer gate electrode 43 compared to the case of the first modified example. In this way, according to the above-described embodiment, it is possible to increase the readout amount of the charge using the capacitance of the area directly below the first transfer gate electrode 43, and it is possible to expand the dynamic range.

[0078] In the state where the potential of the first transfer gate electrode 43 and the potential of the second transfer gate electrode 44 are equal to each other, the second potential φ44 is higher than the first potential φ43. Thereby, by applying the same potential to the first transfer gate electrode 43 and the second transfer gate electrode 44, it is possible to make the second potential φ44 higher than the first potential φ43. As a result, for example, compared to the case where the second potential φ44 is made higher than the first potential φ43 by applying different potentials to the first transfer gate electrode 43 and the second transfer gate electrode 44, it is possible to simplify the structure for applying the potential.

[0079] The transmission region 35 includes a potential adjustment layer 36 for making the second potential φ44 higher than the first potential φ43. Thus, the potential adjustment layer 36 can make the second potential φ44 higher than the first potential φ43.

[0080] In the charge transfer process, when the first potential φ43 and the second potential φ44 are below the potential Pa at the lower end of the inclined potential A, the second potential φ44 is equal to the potential Pa, and the first potential φ43 is lower than the potential Pa. Therefore, it is possible to suppress the accumulation of charge in the region directly below the second transfer gate electrode 44, and to suppress the generation of noise caused by charge returning from the region directly below the second transfer gate electrode 44 to the charge accumulation region 24 (charge generation region 29).

[0081] In the charge transfer process, starting from a state where the first potential φ43 and the second potential φ44 are below the lower end of the inclined potential A, after the second potential φ44 becomes higher than the potential Pa, the first potential φ43 becomes higher than the potential Pa. Therefore, it is possible to reliably suppress the return of charge from the region directly below the first transfer gate electrode 43 to the charge accumulation region 24 (charge generation region 29), and to reliably suppress noise generation. This is because, compared to simultaneously increasing the first potential φ43 and the second potential φ44, the potential barrier between the region directly below the first transfer gate electrode 43 and the charge accumulation region 24 can be increased.

[0082] In a structure where the charge generation region 29 includes the avalanche multiplication region 23, when a tilted potential A is formed in the charge generation region 29, it is difficult to ensure the tilt height of the tilted potential A for the following reasons. First, to increase the tilt height, it is considered to increase the potential Pb at the upper end of the tilted potential A. However, in order to prevent a short circuit from occurring between the intervention region 25 and the semiconductor region 21, the potential Pb needs to be higher than... Figure 5 The punch-through line PL shown is low. Furthermore, to increase the potential Pb, the potential at the upper end of the tilt potential A needs to be lowered. In this case, leakage current may occur at the upper end of the tilt potential A between the intervention region 25 and the semiconductor region 21. Therefore, there are limitations to increasing the potential Pb. Additionally, at the upper end of the tilt potential A, where the potential is low, the reverse bias voltage becomes low; therefore, the multiplication rate may decrease in the portion of the avalanche multiplication region 23 corresponding to the upper end of the tilt potential A.

[0083] Second, to increase the tilt height, consider lowering the potential Pa (depletion potential) at the lower end of the tilt potential A. However, if the potential Pa is lowered, the difference DF between the potential Pa and the potential φ33 of the charge collection region 33 will increase. Figure 5 As the potential Pa decreases, the amount of charge readout decreases. Therefore, there are limitations to reducing the potential Pa.

[0084] In contrast, in the optical sensor 1 of the above embodiment, as described above, since the charge is transferred to the charge collection region 33 using the first transmission gate electrode 43 and the second transmission gate electrode 44, noise generation can be suppressed, and the charge readout can be increased by utilizing the capacitance of the region directly below the first transmission gate electrode 43, thereby expanding the dynamic range. As a result, the dynamic range and the tilt height of the tilt potential A can be ensured to a greater extent.

[0085] The tilt potential formation region 59 is located on the first side relative to the avalanche multiplication region 23. As a result, the proportion of charge present in the region near the transfer gate electrode 41 increases, enabling faster charge transfer. Furthermore, by forming the tilt potential A near the transfer gate electrode 41, faster charge transfer is also possible.

[0086] The tilt potential forming region 59 includes a second region 52, a third region 53, and a fourth region 54 arranged such that the impurity concentration increases as it approaches the transmission region 35. Thus, a tilt potential A can be appropriately formed in the charge generation region 29.

[0087] The charge generation region 29 has an embedded photodiode structure. This allows for the suppression of dark current generation in the charge generation region 29.

[0088] [Variation Example]

[0089] Figure 6 The charge storage region 24A of the second modified example shown includes a first region (first semiconductor region) 55 and a second region (second semiconductor region) 56. The first region 55 includes a first portion 55a and a second portion 55b. The second region 56 is disposed in the Y direction between the first portion 55a and the second portion 55b. Both the first region 55 and the second region 56 are n-type regions. The second region 56 has a higher impurity concentration than the first region 55. The impurity concentration of the first region 55 is 1 × 10⁻⁶. 13 ~1×10 16 cm -3 The degree of impurity concentration in region 2, 56 is 1 × 10⁻⁶. 16 ~1×10 19 cm -3 The degree of. Region 1, 55, can also be a p-type region.

[0090] The 2nd region 56 is adjacent to the transfer region 35 in the X direction. The width (length along the Y direction) W2 of the 2nd region 56 increases as it approaches the transfer region 35. The charge accumulation region 24A having the 1st region 55 and the 2nd region 56 functions as a tilt potential formation region 59A that forms a tilt potential A that tilts in a manner in which the potential becomes lower as it approaches the transfer region 35. The tilt potential formation region 59A is located on the 1st side with respect to the avalanche multiplication region 23 in the Z direction. According to the 2nd modification as well, as with the above-described embodiment, high sensitivity can be achieved, and charges can be transferred at high speed even in a case where the area of the light-receiving region is large.

[0091] In Figure 7 The light sensor 1B of the 3rd modification illustrated in FIG. 8 has a tilt potential formation region 59B located on the 2nd side with respect to the avalanche multiplication region 23. The tilt potential formation region 59B includes a 1st semiconductor layer 61 and a 2nd semiconductor layer 62 located on the 2nd side with respect to the 1st semiconductor layer 61. The 1st semiconductor layer 61 has a through-hole 63 formed therethrough along the Z direction.

[0092] The 1st semiconductor layer 61 and the 2nd semiconductor layer 62 are p-type regions. The impurity concentration of the 1st semiconductor layer 61 and the 2nd semiconductor layer 62 is 1 x 1010cm-2or more and 1 x 1011cm-2or less. 14 16 -3 The 1st semiconductor layer 61 and the 2nd semiconductor layer 62 can also be considered to constitute a 1st multiplication region 23a of the avalanche multiplication region 23. In other words, the avalanche multiplication region 23 can also be considered to have the 1st semiconductor layer 61 and the 2nd semiconductor layer 62.

[0093] In the 3rd modification, a step portion 64 is formed between the 1st semiconductor layer 61 and the 2nd semiconductor layer 62, thereby forming the tilt potential A. The step portion 64 is formed between a portion of the surface of the 1st semiconductor layer 61 that is not covered by the 2nd semiconductor layer 62. In this example, a pair of step portions 64 are provided, each extending along the Y direction. The through-hole 63 is disposed between the pair of step portions 64 in the X direction.

[0094] The charge generation region 29 includes, in addition to the tilt potential formation region 59B, a charge accumulation region 24B disposed on the 1st side with respect to the avalanche multiplication region 23. The charge accumulation region 24B is an n-type region. The impurity concentration of the charge accumulation region 24B is 1 x 1010cm-2or more and 1 x 1011cm-2or less. 16 19 -3

[0095] ​​​​​The through-hole 63 overlaps the boundary portion of the charge generation region 29 and the transfer region 35 in the Z direction. In this example, the through-hole 63 overlaps the charge accumulation region 24B in the Z direction. In the third modification, the charge collected by the inclined potential A reaches the avalanche multiplication region 23 through the through-hole 63. The charge multiplied by the avalanche multiplication region 23 is accumulated in the charge accumulation region 24B. The charge accumulated in the charge accumulation region 24B is transferred to the charge collection region 33 using the transfer gate electrode 41. Further, in Figure 7 The transfer gate electrode 41 is described as being composed of a single electrode, but the transfer gate electrode 41 can have the first transfer gate electrode 43 and the second transfer gate electrode 44 as in the above-described embodiments. In Figure 7 In the above-described embodiments, the illustration of a portion of the electrode layer 4 and the protective layer 6 and the like is omitted. The ground electrode 46 disposed on the intervening region 25 is illustrated.

[0096] According to the third modification, as in the above-described embodiments, high sensitivity can be achieved, and even in the case where the area of the light-receiving region is large, the charge can be transferred at high speed. Further, the inclined potential formation region 59B is located on the second side with respect to the avalanche multiplication region 23. In such a structure, it is difficult to produce the above-described restriction on the inclination height of the inclined potential A. Therefore, the inclination of the inclined potential A can be increased, and the charge can be transferred at higher speed. Further, since the charge collected by the inclined potential A is multiplied in the avalanche multiplication region 23, the site of multiplication generation can be limited, and the uniformity of multiplication can be improved.

[0097] In the inclined potential formation region 59B, a step portion 64 is formed between the first semiconductor layer 61 and the second semiconductor layer 62, thereby forming the inclined potential A. Thereby, the inclined potential A can be appropriately formed in the charge generation region 29.

[0098] The through-hole 63 formed in the first semiconductor layer 61 overlaps the boundary portion of the charge generation region 29 and the transfer region 35 in the Z direction. Thereby, the charge guided by the inclined potential A can be collected in the boundary portion of the charge generation region 29 and the transfer region 35.

[0099] The present application is not limited to the above-described embodiments and modifications. For example, the materials and shapes of the respective structures are not limited to the above-described materials and shapes, and various materials and shapes can be employed.

[0100] In the above embodiment, the second potential φ44 is made higher than the first potential φ43 by giving the same potential to the first transfer gate electrode 43 and the second transfer gate electrode 44, but an additional bias circuit can be provided, and the second potential φ44 can be made higher than the first potential φ43 by giving different potentials to the first transfer gate electrode 43 and the second transfer gate electrode 44. In this case, the first potential φ43 and the second potential φ44 can also be equal at the start and end of the charge transfer process.

[0101] The transfer gate electrode 41 can be composed of a single electrode. In this case, the second potential φ44 can be made higher than the first potential φ43 by forming the potential adjustment layer 36 as in the above embodiment. For example, the potential adjustment layer 36 can be formed on the lower side of the portion of the transfer gate electrode 41 composed of a single electrode, which corresponds to the second transfer gate electrode 44.

[0102] The first potential φ43 and the second potential φ44 can also be made higher than the potential Pa simultaneously from a state in which the first potential φ43 and the second potential φ44 are below the potential Pa, which is the lower end of the inclined potential A. The conductive types of the p-type and the n-type can also be reversed from the above. A plurality of pixels 10 can also be arranged one-dimensionally along the first surface 2a of the semiconductor layer 2. The light sensor 1 can also have only a single pixel 10. The light sensor 1 can also be a distance measuring sensor that acquires a distance image (an image including information about the distance d to an object) of an object using an indirect TOF method. The light sensor 1 can also include two or more charge collection regions 33 in each pixel 10. The light sensor 1 can also include two or more transfer gate electrodes 41 in each pixel 10.

[0103] In the above embodiment and the modified example, the avalanche multiplication region 23 can also not be formed. That is, the charge generation region 29 can also not include the avalanche multiplication region 23. According to such a structure, as in the above embodiment, even in the case in which the area of the light receiving region is large, the charges can be transferred at high speed.

[0104] Explanation of Reference Numerals

[0105] 1, 1B … light sensor; 23 … avalanche multiplication region; 29 … charge generation region; 33 … charge collection region; 35 … transfer region; 36 … potential adjustment layer; 41, 41A … transfer gate electrode; 43 … first transfer gate electrode; 44 … second transfer gate electrode; 52 … second region (semiconductor region); 53 … third region (semiconductor region); 54 … fourth region (semiconductor region); 55 … first region (first semiconductor region); 55a … first portion; 55b … second portion; 56 … second region (second semiconductor region); 59, 59A, 59B … inclined potential formation region; 61 … first semiconductor layer; 62 … second semiconductor layer; 63 … through-hole; 64 … step portion; A … inclined potential; Pa … potential at lower end of inclined potential (potential at boundary portion of charge generation region and transfer region); W2 … width; φ43 … first potential; φ44 … second potential.

Claims

1. An optical sensor, wherein, have: The charge-generating region, which generates charge based on incident light; A charge collection region that transmits the charge generated in the charge generation region; and At least one transfer gate electrode is disposed on the transfer region between the charge generation region and the charge collection region. The charge generation region includes: Avalanche multiplication zones, which generate avalanche multiplication; and A tilted potential forming region is formed in the charge generating region, wherein the tilted potential decreases as it approaches the transmission region. The at least one transfer gate electrode includes: a first transfer gate electrode and a second transfer gate electrode disposed relative to the first transfer gate electrode on the charge generation region side. In the charge transfer process that transfers the charge generated in the charge generation region to the charge collection region, a first potential, which is the potential of the region directly below the first transfer gate electrode, and a second potential, which is the potential of the region directly below the second transfer gate electrode, are applied to the first transfer gate electrode and the second transfer gate electrode in such a way that the potential becomes higher than the potential of the boundary between the charge generation region and the transfer region after it becomes lower than the potential of the boundary. In the charge transfer process, from a state where the first potential and the second potential are below the potential of the boundary portion, a process is performed to make the second potential higher than the potential of the boundary portion without changing the first potential. After this process is completed, a process is performed to make the first potential higher than the potential of the boundary portion.

2. The optical sensor according to claim 1, wherein, In the charge transfer process, the first transfer gate electrode and the second transfer gate electrode are given a potential in such a way that the second potential becomes higher than the first potential.

3. The optical sensor according to claim 2, wherein, When the potentials of the first transmission gate electrode and the second transmission gate electrode are equal, the second potential is higher than the first potential.

4. The optical sensor according to claim 3, wherein, The transmission region includes a potential adjustment layer for making the second potential higher than the first potential.

5. The optical sensor according to claim 1, wherein, When the first potential and the second potential in the charge transfer process are below the potential of the boundary portion, the second potential is equal to the potential of the boundary portion, and the first potential is lower than the potential of the boundary portion.

6. The optical sensor according to claim 2, wherein, When the first potential and the second potential in the charge transfer process are below the potential of the boundary portion, the second potential is equal to the potential of the boundary portion, and the first potential is lower than the potential of the boundary portion.

7. The optical sensor according to claim 3, wherein, When the first potential and the second potential in the charge transfer process are below the potential of the boundary portion, the second potential is equal to the potential of the boundary portion, and the first potential is lower than the potential of the boundary portion.

8. The optical sensor according to claim 4, wherein, When the first potential and the second potential in the charge transfer process are below the potential of the boundary portion, the second potential is equal to the potential of the boundary portion, and the first potential is lower than the potential of the boundary portion.

9. The optical sensor according to any one of claims 1 to 8, wherein, The avalanche multiplication zone forms in layers along a defined plane. When the side on which the transmission gate electrode is located relative to the avalanche multiplication region in a direction perpendicular to the plane is designated as the first side, and the opposite side of the first side is designated as the second side, the tilt potential forming region is located on the first side relative to the avalanche multiplication region.

10. The optical sensor according to claim 9, wherein, The tilt potential forming region comprises a plurality of semiconductor regions arranged such that the impurity concentration increases as it approaches the transmission region.

11. The optical sensor according to claim 9, wherein, The tilt potential forming region includes: a first semiconductor region comprising a first portion and a second portion; and a second semiconductor region having a higher impurity concentration than the first semiconductor region, disposed between the first portion and the second portion, and increasing in width as it approaches the transmission region.

12. The optical sensor according to claim 10, wherein, The tilt potential forming region includes: a first semiconductor region comprising a first portion and a second portion; and a second semiconductor region having a higher impurity concentration than the first semiconductor region, disposed between the first portion and the second portion, and increasing in width as it approaches the transmission region.

13. The optical sensor according to any one of claims 1 to 8, wherein, The avalanche multiplication zone forms in layers along a defined plane. When the side on which the transmission gate electrode is located relative to the avalanche multiplication region in a direction perpendicular to the plane is designated as the first side, and the opposite side of the first side is designated as the second side, the tilt potential forming region is located on the second side relative to the avalanche multiplication region.

14. The optical sensor according to claim 13, wherein, The tilt potential forming region includes: a first semiconductor layer and a second semiconductor layer located on the second side relative to the first semiconductor layer. The tilted potential is formed by forming a step between the first semiconductor layer and the second semiconductor layer.

15. The optical sensor according to claim 14, wherein, A through-hole is formed in the first semiconductor layer. The through hole overlaps with the boundary between the charge generation region and the transmission region in a direction perpendicular to the plane.

16. The optical sensor according to any one of claims 1 to 8, wherein, The charge generation region has an embedded photodiode structure.

17. The optical sensor according to claim 9, wherein, The charge generation region has an embedded photodiode structure.

18. The optical sensor according to claim 10, wherein, The charge generation region has an embedded photodiode structure.

19. The optical sensor according to claim 11, wherein, The charge generation region has an embedded photodiode structure.

20. The optical sensor according to claim 12, wherein, The charge generation region has an embedded photodiode structure.

21. The optical sensor according to claim 13, wherein, The charge generation region has an embedded photodiode structure.

22. The optical sensor according to claim 14, wherein, The charge generation region has an embedded photodiode structure.

23. The optical sensor according to claim 15, wherein, The charge generation region has an embedded photodiode structure.

24. An optical sensor, wherein, have: The charge-generating region, which generates charge based on incident light; A charge collection region that transmits the charge generated in the charge generation region; and At least one transfer gate electrode is disposed on the transfer region between the charge generation region and the charge collection region. The charge generation region includes: Avalanche multiplication zones, which generate avalanche multiplication; and A tilted potential forming region is formed in the charge generating region, wherein the tilted potential decreases as it approaches the transmission region. The avalanche multiplication zone forms in layers along a defined plane. When the side on which the transmission gate electrode is located relative to the avalanche multiplication region in a direction perpendicular to the plane is designated as the first side, and the opposite side of the first side is designated as the second side, the tilt potential forming region is located on the second side relative to the avalanche multiplication region.

25. The optical sensor according to claim 24, wherein, The tilt potential forming region includes: a first semiconductor layer and a second semiconductor layer located on the second side relative to the first semiconductor layer. The tilted potential is formed by forming a step between the first semiconductor layer and the second semiconductor layer.

26. The optical sensor according to claim 25, wherein, A through-hole is formed in the first semiconductor layer. The through hole overlaps with the boundary between the charge generation region and the transmission region in a direction perpendicular to the plane.

27. The optical sensor according to any one of claims 24 to 26, wherein, The charge generation region has an embedded photodiode structure.

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