Power supply device, power supply unit, test device

Abstract

The present application provides a power supply device, a power supply unit, and a test device. A plurality of channel power supply units (200) each include an output stage (210) that generates an output voltage (V i ) between a positive output (OUTP) and a negative output (OUTN) in accordance with a control signal (Vctrl), and a voltage detector (220) that generates a voltage detection signal (Vs i ) that indicates the output voltage (V i ). A feedback signal generation section (230) of a master channel power supply unit (200_1) that is one of the plurality of channels receives voltage detection signals (Vs2 to Vs N ) from slave channel power supply units (200_2 to 200_N) that are remaining channels of the plurality of channels, and generates a feedback signal (Vfb) that is based on the voltage detection signals (Vs1 to Vs N ) of all channels. A feedback controller (240) generates the control signal (Vctrl) so that the feedback signal (Vfb) approaches a target value (Vref). The output stage (210) of the slave channel operates based on the control signal (Vctrl) generated in the master channel.

Description

Technical Field

[0001] This disclosure relates to a power supply device for supplying power supply voltage or power supply current to a device. Background Technology

[0002] In recent years, research and development of power devices such as SiC (silicon carbide) FETs (Field-Effect Transistors) and GaN (gallium nitride) HEMTs (High Electron Mobility Transistors), which achieve high-efficiency power conversion through high-speed switching of high voltages with the aim of energy saving, has been booming. Along with this, the need for high-voltage device testing has increased, and the requirement for shorter testing times has become stronger. These device tests require the application of high voltages of 1000V, and sometimes 2000V depending on the device, and also require high-precision DC voltages.

[0003] When the maximum output voltage of the power supply unit used in the test equipment is insufficient to supply the high voltage to the load, it is necessary to connect multiple channels of power supply units (hereinafter referred to as power supply units) in series (hereinafter referred to as stacked connection).

[0004] Prior art literature

[0005] Patent documents

[0006] Patent Document 1: Japanese Patent Application Publication No. 2013-138557

[0007] Patent Document 2: Japanese Patent Publication No. 2013-535949 Summary of the Invention

[0008] The problem that the invention aims to solve

[0009] Figure 1 This is a block diagram of a 100R high-voltage power supply. (Refer to...) Figure 1 The high-voltage power supply 100R comprises multiple power supply units 110_1 to 110_N with stacked channels CH1 to CHN. Each channel's power supply unit 110 has a primary side P and a secondary side S, which are insulated from each other by an isolation barrier 112, such as a transformer or capacitor. The grounding terminal GND of the primary side P of the multiple power supply units 110_1 to 110_N is connected to each other.

[0010] A positive output OUTP and a negative output OUTN are provided on the secondary side S of the power supply unit 110, and an output stage 120 is provided between the positive output OUTP and the negative output OUTN. Figure 1 In this structure, all channels operate independently. The output stage 120 of the i-th (i = 1 to N) channel is controlled by a constant voltage, causing its output voltage V to be controlled.i Approaching the target value V REF .

[0011] The negative output OUTN of the power supply unit 110_i of the i-th (1≦i≦N-1) channel is connected to the positive output OUTP of the power supply unit 110_(i+1) of the (i+1)-th channel. The positive output OUTP of the power supply unit 110_1 of the first channel is connected to load 1, and the negative output OUTN of the power supply unit 110 of the N-th channel is grounded.

[0012] The high voltage V supplied between the two ends of load 1 OUTH The output voltages V1 to V1 of each channel's output stage 120 are... N The sum of these can be expressed by the following formula.

[0013] V OUTH =Σ 1：N V i

[0014] In V1~V N They were stabilized to V respectively REF Under steady-state conditions, the output voltage V OUTH Become N×V REF .

[0015] This section explains the issues that arise when multiple power supply units with multiple channels are stacked and connected. Figure 2 (a) is a waveform diagram of the output voltage of the high-voltage power supply (simulation result). Figure 2 (b) is a graph showing the relationship between the number of stacking stages N and the settling time. It should be noted that the voltage waveform is normalized by dividing by the stabilized voltage level. The "simulation" section shows the result from... Figure 2 The relationship between the stacking level N and the settling time obtained from the waveform in (a) shows that the more the stacking level N increases, the longer the settling time becomes. On the other hand, as shown in "expectation", the expected settling time is fixed regardless of the stacking level N.

[0016] One aspect of this disclosure is achieved under the aforementioned conditions, and one of its exemplary purposes is to provide a high-voltage power supply with a shortened settling time.

[0017] Solution for solving the problem

[0018] A power supply device according to one aspect of this disclosure includes multiple power supply units with multiple channels stacked together. Each power supply unit with multiple channels includes: a positive output and a negative output; an output stage that generates an output voltage between the positive and negative outputs according to a control signal; and a voltage detector that generates a voltage detection signal representing the output voltage. The power supply unit of the main channel, which is one of the multiple channels, further includes: a feedback signal generation unit that receives voltage detection signals from the power supply units of the main channel and the power supply units of the remaining channels, and generates a feedback signal based on the voltage detection signals of all channels; and a feedback controller that generates a control signal to make the feedback signal approach a target value. The output stages of all channels operate based on the same control signal generated by the feedback controller of the main channel.

[0019] One aspect of this disclosure is a power supply unit. Multiple power supply units can be stacked to form a power supply device. The power supply unit includes: a positive output and a negative output; an output stage that generates an output voltage between the positive and negative outputs according to a control signal; a voltage detector that generates a voltage detection signal representing the output voltage; a feedback signal generation unit that, when set as a master channel, generates a feedback signal based on the voltage detection signals of all channels; a feedback controller that, when set as a master channel, generates a control signal to make the feedback signal approach a target value; and an interface circuit that, when set as a master channel, receives voltage detection signals from other channels and sends the same control signal to other channels, and when set as a slave channel, receives the same control signal from the master channel and sends a voltage detection signal to the master channel.

[0020] It should be noted that any combination of the above-mentioned constituent elements, constituent elements of this disclosure, and expressions that are interchanged among methods, apparatuses, systems, etc., are also valid solutions obtained as solutions of this disclosure.

[0021] Invention Effects

[0022] According to one of the solutions disclosed herein, the stabilization time can be shortened when there are many stacking levels. Attached Figure Description

[0023] Figure 1 This is a block diagram of a high-voltage power supply.

[0024] Figure 2 (a) is a waveform diagram of the output voltage of the high-voltage power supply (simulation result). Figure 2 (b) is a graph showing the relationship between the stacking level N and the settling time.

[0025] Figure 3 yes Figure 1 The equivalent circuit diagram of the high-voltage power supply.

[0026] Figure 4 This is a block diagram showing a test apparatus with a power supply device having an embodiment.

[0027] Figure 5 This is a block diagram illustrating a structural example of the power supply unit of the main channel in Embodiment 1.

[0028] Figure 6 This is a block diagram of the power supply unit in Embodiment 2.

[0029] Figure 7 (a) and (b) illustrate the primary and secondary modes. Figure 6 A diagram showing the state of the power supply unit.

[0030] Figure 8 This is a block diagram showing a specific structural example of a power supply unit.

[0031] Figure 9 It is Figure 8 The power supply unit is combined with two to obtain the operating waveform diagram of the power supply device. Detailed Implementation

[0032] (Summary of the implementation method)

[0033] A summary of several exemplary embodiments of this disclosure is provided. This summary serves as a prelude to the detailed description that follows, and aims to provide a basic understanding of the embodiments, simplifying the explanation of several concepts of one or more embodiments without limiting the breadth of the invention or disclosure. Furthermore, this summary is not a comprehensive overview of all embodiments considered, nor does it limit the essential components of the embodiments. For convenience, "an embodiment" is sometimes used to refer to one or more embodiments (examples, variations) disclosed in this specification.

[0034] First, the results of the inventor's research on the reason why the larger the stacking level N is, the longer the stabilization time will be explained.

[0035] Figure 3 yes Figure 1 The equivalent circuit diagram of a 100R high-voltage power supply. (See diagram below.) Figure 1 As shown, each channel's power supply unit 110 has an isolation capacitor C between the ground terminal GND on the primary side P and the negative output OUTN on the secondary side S. ISO .like Figure 3 As shown, the isolation capacitor C ISO The output stage 120 is considered as an electrostatic capacitive load. The more the number of stacked stages (channels) N increases, the larger the electrostatic capacitive load becomes.

[0036] The capacitance load varies for each channel; therefore, the stability performance varies for each channel. This stability performance deviation is reflected in the output voltage V of the high-voltage power supply 100R. OUTH One of the reasons is that the stabilization time has become longer.

[0037] In addition, most power supply units 110 (output stage 120) are equipped with current clamping function (overcurrent protection function). Specifically, regarding the output stage 120 of power supply unit 110, constant voltage control is effective when its output current is lower than the specified limit value, but when the output current exceeds the limit value, constant voltage control becomes ineffective, and the output current is limited to the limit value (also known as current clamping control or constant current control).

[0038] When voltage is applied in the presence of a capacitive load, an inrush current flows into the capacitive load. The output current of each output stage 120 is the sum of the load current flowing to the load and the inrush current, and the magnitude of the inrush current sometimes varies for each channel. That is, the isolation capacitor C is not visible in the channel of the first stage. ISO Therefore, it is difficult to generate surge current. In contrast, electrostatic capacitance C can be seen in channels after the second stage. ISO Therefore, it is easy to generate inrush current.

[0039] When a large inrush current is generated in a portion of the channel, the operating mode of the output stage 120 in that channel changes from constant voltage control to current clamping control. When current clamping control and constant voltage control coexist, such as... Figure 2 As shown in (a), the output voltage V of the high-voltage power supply 100R is... OUTH An inflection point appears, and the waveform becomes distorted. Furthermore, the more stacked levels there are, the more electrostatic capacitance needs to be charged, thus affecting the output voltage V. OUTH The upward slope becomes smaller, so the settling time becomes longer.

[0040] The following describes the techniques used to suppress the increase in settling time.

[0041] One embodiment of the power supply device includes power supply units with multiple channels stacked together. Each power supply unit with multiple channels includes a positive output and a negative output, an output stage that generates an output voltage between the positive and negative outputs according to a control signal, and a voltage detector that generates a voltage detection signal representing the output voltage. The power supply unit of the master channel, one of the multiple channels, further includes: a feedback signal generation unit that receives voltage detection signals from the power supply units of the slave channels (the remaining channels) and generates a feedback signal based on the voltage detection signals of all channels; and a feedback controller that generates a control signal to make the feedback signal approach a target value. The output stages of all channels operate based on the control signal generated by the feedback controller of the master channel.

[0042] According to this structure, the output stages of the power supply units with multiple channels operate based on the same control signal. Therefore, it is possible to eliminate the deviation in the stability performance of each channel, thereby suppressing the increase in settling time when the number of channels is increased.

[0043] In one embodiment, the power supply unit of the main channel may also include a current detector that generates a current detection signal representing the output current of the output stage. The feedback controller may also generate a control signal to bring the current detection signal closer to the limit value when the current detection signal exceeds a predetermined limit value.

[0044] Current clamping control is dominated by the main channel and is effective simultaneously in all channels. Therefore, it can prevent current clamping control from mixing with constant voltage control and suppress the increase in settling time.

[0045] Each power supply unit with multiple channels can also have a feedback signal generation unit and a feedback controller, and they are configured similarly. Alternatively, each power supply unit can select between a master mode and a slave mode. When set to master mode, the feedback signal generation unit and the feedback controller are enabled; when set to slave mode, they are disabled. It should be noted that "disabling a circuit component" includes not only preventing the component from operating, but also preventing its use by cutting off or shielding its output, even if it is operating.

[0046] By preparing multiple identical power supply units, rearranging their connections, and appropriately setting their modes, the number of loads can be varied. For example, with N power supply units, if N are stacked and one is set to master mode while the rest are set to slave mode, power can be supplied to one load. Alternatively, if all N are set to master mode and used independently, power can be supplied to N loads.

[0047] The feedback signal can also be the average of the voltage detection signals from all channels. This allows for the generation of an accurate voltage by taking into account the deviations in the characteristics of the output stages and voltage detectors across all channels.

[0048] The main channel can also be located at the top of multiple channels. By setting the top channel with the least inrush current as the main channel, it is difficult to apply current clamping, which can shorten the settling time.

[0049] One embodiment of the power supply unit can be stacked to form a power supply device. The power supply unit includes: a positive output and a negative output; an output stage that generates an output voltage between the positive output and the negative output according to a control signal; a voltage detector that generates a voltage detection signal representing the output voltage; a feedback signal generation unit that is active when set as a master channel and generates a feedback signal based on the voltage detection signals of all channels; a feedback controller that is active when set as a master channel and generates a control signal to make the feedback signal approach a target value; and an interface circuit that, when set as a master channel, receives voltage detection signals from other channels and sends control signals to other channels, and when set as a slave channel, receives control signals from the master channel and sends voltage detection signals to the master channel.

[0050] According to this structure, even with multiple channels stacked, the output stages of all power supply units operate based on the same control signal. Therefore, deviations in the stability performance of each channel can be eliminated, thereby suppressing the increase in settling time when the number of channels increases. Furthermore, by preparing multiple identical power supply units, reorganizing the connection relationships, and appropriately setting the mode, the number of loads can be varied.

[0051] (Implementation Method)

[0052] The embodiments will now be described with reference to the accompanying drawings. Identical or equivalent constituent elements, components, and processes shown in the figures will be labeled with the same reference numerals, and repeated descriptions will be omitted where appropriate. Furthermore, the embodiments are not intended to limit the invention, but are merely illustrative; all features and combinations thereof described in the embodiments may not necessarily be essential features of the invention.

[0053] In this specification, "the state of connection between component A and component B" includes not only the case where component A and component B are physically directly connected, but also the case where component A and component B are indirectly connected through other components that do not substantially affect their electrical connection state or impair the function or effect achieved by their combination.

[0054] Similarly, "the state in which component C is positioned between component A and component B" includes not only the case where component A and component C or component B and component C are directly connected, but also the case where they are indirectly connected via other components that do not substantially affect their electrical connection state or impair the function or effect achieved through their combination.

[0055] Figure 4 This is a block diagram showing the test apparatus 2 of the power supply device 100 according to the embodiment. The test apparatus 2 applies test signals such as voltage signals and current signals to the DUT (Device Under Test) 1 and measures the response of the DUT 1. There is no particular limitation on the type of DUT 1, but devices that require voltage application of high voltages such as high-voltage power transistors and power modules, or circuits or circuit systems including such devices, are suitable as test objects of this test apparatus 2.

[0056] Test apparatus 2 includes a power supply device 100 that supplies a power signal to DUT1. The power signal is typically a voltage signal V stabilized at a specified voltage level. OUTH It should be noted that, in Figure 4 In the middle, a power signal V is directly supplied to DUT1. OUTH However, it is not limited to this; the power signal V OUTH It can also be supplied to the peripheral circuits of DUT1, the circuits that drive DUT1, or the circuits that interface with DUT1.

[0057] In addition to the power supply unit 100, the test apparatus 2 may also include voltage sensors, current sensors, signal generators, drivers, comparators, A / D converters, D / A converters, etc., but these will correspond to the type and test items of the DUT1. Figure 4 Omitted in .

[0058] The power supply unit 100 includes multiple N-channel (CH1 to CHN) power supply units 200_1 to 200_N stacked together. Each power supply unit 200 has a positive output OUTP and a negative output OUTN. The power supply units 200 and... Figure 1 The power supply unit 110 also has an insulated primary side and a secondary side, but Figure 4 Only the secondary side structure is shown. The negative output OUTN becomes the reference potential (ground) of the secondary side.

[0059] The negative output OUTN of the power supply unit 110_i of the i-th (1≦i≦N-1) channel is connected to the positive output OUTP of the power supply unit 110_(i+1) of the (i+1)-th channel. The positive output OUTP of the power supply unit 110_1 of the first channel is connected to load 1, and the negative output OUTN of the power supply unit 110 of the N-th channel is grounded.

[0060] The power supply units 200 with multiple channels each have an output stage 210 and a voltage detector 220. The output stage 210 of the i-th (i = 1 to N) power supply unit 200 generates an output voltage V between the positive output OUTP and the negative output OUTN according to the control signal Vctrl. i Additionally, the voltage detector 220 of the i-th power supply unit 200_i generates a value representing the corresponding output voltage V. i Voltage detection signal Vs i .

[0061] In this embodiment, one of the multiple N channels CH1 to CHN is designated as the master channel, and the remaining channels are designated as slave channels. However, this is not the only embodiment. Figure 4 In the diagram, the first channel CH1 is the main channel, and the second to Nth channels CH2 to CHN are the slave channels.

[0062] The master channel and slave channel can transmit and receive signals. The power supply units 200_2 to 200_N of the slave channel transmit voltage detection signals Vs1 to Vs N Power supply unit 200_1 sent to the main channel.

[0063] In addition to the output stage 210 and voltage detector 220, the main channel power supply unit 200-1 also has a feedback signal generation unit 230 and a feedback controller 240.

[0064] The feedback signal generation unit 230 receives voltage detection signal Vs1 from the power supply unit 200-1 of the main channel, and receives voltage detection signals Vs2 to Vs3 from the power supply units 200-2 to 200-N of the slave channels. N Generate voltage detection signals Vs1 to Vs based on all channels CH1 to CHN. N The feedback signal Vfb. For example, the feedback signal Vfb can also be multiple voltage detection signals Vs1 to Vs2. N The simple average value. It should be noted that the feedback signal Vfb is not limited to this.

[0065] For example, when there are deviations in the power supply units 200_1 to 200_N of multiple channels, a weighted average can be obtained by using a coefficient that takes into account the deviation.

[0066] The target value Vref is input to the feedback controller 240. The feedback controller 240 performs feedback control on the signal level (magnitude) of the control signal Vctrl, so that the feedback signal Vfb is close to the target value Vref.

[0067] The control signal Vctrl generated by the feedback controller 240 is supplied to the output stage 210 of the main channel. Furthermore, this control signal Vctrl is transmitted from the power supply unit 200_1 of the main channel to the power supply units 200_2 to 200_N of the slave channels. Then, the output stages 210 of all channels CH1 to CHN operate based on the control signal Vctrl generated by the feedback controller 240 of the main channel CH1.

[0068] The above describes the basic structure of the power supply device 100.

[0069] According to this structure, the output stage 210 of the power supply units 200_1 to 200_N with multiple channels CH1 to CHN operates based on the same control signal Vctrl. Therefore, deviations in the stability performance of each channel can be eliminated, thereby suppressing the increase in settling time when the number of channels N is increased.

[0070] This disclosure serves as Figure 4 The block diagrams and circuit diagrams are understood, or relate to various devices and methods derived from the above description, and are not limited to a specific structure. Hereinafter, more specific structural examples and embodiments are described to aid in understanding the nature and operation of the invention and to make them clear, rather than to narrow the scope of the invention.

[0071] (Example 1)

[0072] Figure 5 This is a block diagram illustrating a structural example of the power supply unit 200_1 of the main channel in Embodiment 1. The power supply unit 200_1 has a current clamping function. Specifically, the power supply unit 200_1, in addition to having… Figure 4 In addition to the power supply unit 200-1, it also includes a current detector 250. The current detector 250 generates an output current I representing the output current of the output stage 210. OUT The current detection signal Is1 is input to the feedback controller 240.

[0073] When the current detection signal Is1 is lower than a predetermined limit value, the feedback controller 240 generates a control signal Vctrl as described above, causing the feedback signal Vfb to approach the target value Vref (constant voltage control). On the other hand, when the current detection signal Is1 exceeds the limit value, constant voltage control becomes ineffective, and the control signal Vctrl is generated to cause the current detection signal Is1 to approach the limit value (current clamping control).

[0074] Even if the hardware related to the current clamping function is only set in the main channel or as described later, the hardware is disabled in the slave channel.

[0075] When the current detection signal Is1 in the main channel exceeds the limit value, a control signal Vctrl for current clamping control is generated, thereby activating the output stages 210 of all channels. That is, current clamping control is dominated by the main channel and is effective simultaneously in all channels. Therefore, it can prevent... Figure 1 The current clamping control generated in the structure is mixed with the constant voltage control, which can suppress the increase of settling time.

[0076] It should be noted that, as referred to Figure 3 As explained, when multiple channels are stacked, the channel closest to the highest potential is less susceptible to isolation by the isolation capacitor C. ISO The influence of this makes it difficult to generate inrush current. Therefore, when a current clamping function is installed on the main channel, by setting the uppermost channel, which is unlikely to generate inrush current, as the main channel, it is difficult to apply current clamping, thus further shortening the settling time.

[0077] (Example 2)

[0078] The power supply unit 200 of the main channel and the power supply unit 200 of the slave channel can be designed with different structures from the beginning, but as explained below, they can also be configured with the same structure to switch between the mode of operating as the main channel and the mode of operating as the slave channel.

[0079] Figure 6 This is a block diagram of the power supply unit 200 of Embodiment 2. The power supply unit 200 can be used as both a master channel and a slave channel. The power supply unit 200 includes a mode selector 260 and a multiplexer (switch) 270.

[0080] The mode selector 260 generates a mode control signal MODE, which indicates the master mode when used as the master channel and the slave mode when used as the slave channel. The mode control signal MODE is input to the enable terminals of the feedback signal generation unit 230, the feedback controller 240, and the current detector 250. These components are enabled when the mode control signal MODE indicates the master mode and disabled when it indicates the slave mode.

[0081] The output of the feedback controller 240 within the same power supply unit 200 is connected to one input node of the multiplexer 270. Additionally, a control signal Vctrl generated in another power supply unit 200 can be input to another input node of the multiplexer 270. When the mode control signal MODE indicates master mode, the multiplexer 270 selects the control signal (internal control signal) Vctrl_int from the same power supply unit 200; when indicating slave mode, it selects the external control signal Vctrl_ext generated by another power supply unit 200.

[0082] In addition, the power supply unit 200 can process the control signal Vctrl_int and the voltage detection signal Vs generated internally. i Output to the outside. Additionally, the power supply unit 200 can receive externally generated control signals Vctrl_ext and voltage detection signals Vs. i .

[0083] Figure 7 (a) and (b) illustrate the primary and secondary modes. Figure 6 A diagram showing the state of the power supply unit 200. Figure 7 In (a) and (b), components and signal lines that are disabled are indicated by a single-dot dash.

[0084] Figure 8 This is a block diagram illustrating a specific structural example of the power supply unit 200. The control system of this power supply unit 200 is installed with a digital circuit architecture, and the detection signals and control signals are digital signals.

[0085] Output stage 210 includes a D / A converter 212 and a power amplifier 214. Output stage 210 converts the input digital control signal Vctrl into an analog control signal. Power amplifier 214 amplifies the analog control signal and outputs it to the positive output OUTP.

[0086] The voltage detector 220 includes a voltage sensing amplifier 222 and an A / D converter 224. The voltage sensing amplifier 222 converts the voltage V between the two outputs OUTPT and OUTN into voltage. i Amplification. The A / D converter 224 converts the output of the sensing amplifier 222 into a digital voltage detection signal Vs. i It can share the voltage detection signal Vs with other channels via interface circuit 280. i .

[0087] The feedback signal generation unit 230 includes an adder / subtractor 232 and a divider 234. The adder / subtractor 232 converts the voltage detection signals Vs of the same channel and other channels. iAddition. Divider 234 divides the output of adder / subtractor 232 by the number of channels N to generate a feedback signal Vfb based on the average value. Divider 234 can also be understood as a coefficient circuit that multiplies the output of adder / subtractor 232 by a coefficient of 1 / N.

[0088] The current detector 250 includes a sensing resistor 252, a sensing amplifier 254, and an A / D converter 256. The sensing resistor 252 is set to the output current I of the output stage 210. OUT On the path. In the sensing resistor 252, the output current I is generated. OUT A proportional voltage drop. Sensing amplifier 254 amplifies the voltage drop across sensing resistor 252. A / D converter 256 converts the output of sensing amplifier 254 into a digital current detection signal Is. i The target voltage value Vref and the limit value of the current Ilim are input to the feedback controller 240.

[0089] Adder / subtractor 242 generates the difference (voltage error Verr) between the target value Vref and the feedback signal Vfb. Adder / subtractor 246 generates the limit value Ilim and the current detection signal Is. i The difference (current error Ierr).

[0090] Selector 248 in Is i When <Ilim, select voltage error Verr (constant voltage control), in Is i When Ilim > I, select the current error Ierr (current clamping control).

[0091] Filter 244 generates a control signal Vctrl based on the output of selector 248. However, filter 244 can be constructed from a PI (proportional-integral) controller, a PID (proportional-integral-derivative) controller, or similar components. In constant voltage control, the level of the control signal Vctrl is adjusted through feedback to bring the voltage error Verr close to zero. In current clamping control, the level of the control signal Vctrl is adjusted through feedback to bring the current error Ierr close to zero. The parameters of filter 244 can also be switched between constant voltage control and current clamping control.

[0092] The feedback controller 240 and the feedback signal generation unit 230 can be composed of a CPU (Central Processing Unit), a DSP (Digital Signal Processor), or an FPGA (Field Programmable Gate Array).

[0093] The interface circuit 280 is capable of sending and receiving voltage detection signals and control signals Vctrl between the interface circuits 280 of other channels.

[0094] Figure 9 It is Figure 8 The waveform diagrams of the power supply devices obtained by combining two power supply units 200 are shown. The waveforms of the power supply device of the embodiment and the conventional power supply device are shown respectively. A single-stage 1000V output power supply unit with two channels is stacked, and the output voltage is 2000V. In the waveform (ii) of the conventional method, the voltage rises quickly immediately after application, but the rise becomes slow after approximately exceeding 1000V. This is because the upper channel becomes a stable waveform for voltage application control, while the lower channel becomes a current clamping control caused by the surge current flowing to the electrostatic capacitor, resulting in an increase in settling time. In contrast, in the waveform (i) of the embodiment, the two channels operate in balance during voltage application control, thus shortening the settling time. According to this embodiment, it can be confirmed that the settling time to reach 2000V is reduced from 12ms in the conventional method to 4ms, a reduction of less than 1 / 3 compared to the past.

[0095] The present disclosure has been described above based on embodiments. These embodiments are illustrative, and various modifications can exist in their constituent elements, processing procedures, and combinations thereof. Such modifications will be described below.

[0096] exist Figure 8 The description focuses on the power supply unit 200, which is installed with a digital circuit architecture for its control system. However, it is not limited to this and the control system can also be constructed with analog circuits.

[0097] Regarding the current clamping function, the output current is monitored in the main channel, but it is not limited to this. For example, the output current can also be monitored in a slave channel, and the current detection value obtained from the slave channel can be sent to the main channel. The feedback controller 240 of the main channel can also apply current clamping control based on the current detection signal Is from the slave channel.

[0098] Alternatively, current detectors in all channels can be enabled, sending current detection signals from the slave channels to the main channel. The feedback controller 240 of the main channel can also apply current clamping control in such a way that the maximum value of the current detection signals in all channels does not exceed the limit value Ilim.

[0099] The embodiments merely illustrate the principles and applications of the invention. Many modifications and configuration changes to the embodiments are permitted without departing from the spirit of the invention as defined in the claims.

[0100] Industrial utilization

[0101] This invention relates to a power supply device for supplying power voltage or power current to a device.

[0102] Explanation of reference numerals in the attached figures

[0103] 1…DUT, 2…Test apparatus, 100…Power supply unit, 200…Power supply unit, 210…Output stage, 220…Voltage detector, 230…Feedback signal generator, 240…Feedback controller, 250…Current detector, 260…Mode selector, 270…Multiplexer, 280…Interface circuit.

Claims

1. A power supply device, characterized in that, The power supply device has multiple channels of power supply units that are stacked and connected together. The power supply units of the multiple channels each have: Positive and negative outputs; An output stage that generates an output voltage between the positive output and the negative output according to a control signal; and A voltage detector that generates a voltage detection signal representing the output voltage. The power supply unit for the main channel, which is one of the multiple channels, also includes: The feedback signal generation unit receives the voltage detection signal from the power supply unit of the main channel and the power supply unit of the slave channel, which is the remaining channel of the plurality of channels, and generates a feedback signal based on the voltage detection signal of all channels. as well as A feedback controller generates the control signal such that the feedback signal approaches the target value. The output stages of all channels operate based on the same control signal generated by the feedback controller of the main channel.

2. The power supply device according to claim 1, characterized in that, The power supply unit of the main channel also includes a current detector that generates a current detection signal representing the output current of the output stage. When the current detection signal exceeds a predetermined limit value, the feedback controller generates the control signal so that the current detection signal approaches the limit value.

3. The power supply device according to claim 2, characterized in that, The power supply units of the multiple channels include the feedback signal generation unit, the feedback controller, and the current detector, and are configured similarly. Each power supply unit can select a master mode and a slave mode. When set to the master mode, the feedback signal generation unit and the feedback controller are enabled. When set to the slave mode, the feedback signal generation unit and the feedback controller are disabled.

4. The power supply device according to any one of claims 1 to 3, characterized in that, The feedback signal is the average value of the voltage detection signals of all channels.

5. The power supply device according to any one of claims 1 to 3, characterized in that, The main channel is located at the top level among the multiple channels.

6. A power supply unit, wherein multiple power supply units can be stacked to form a power supply device, characterized in that, The power supply unit includes: Positive and negative outputs; The output stage generates an output voltage between the positive output and the negative output according to a control signal. A voltage detector that generates a voltage detection signal representing the output voltage; The feedback signal generation unit becomes active when the main channel is set, and generates a feedback signal based on the voltage detection signals of all channels; A feedback controller, which becomes active when set as the main channel, generates a control signal that makes the feedback signal approach a target value; and The interface circuit, when set as the main channel, receives the voltage detection signal from other channels and sends the same control signal to other channels; when set as a slave channel, it receives the same control signal from the main channel and sends the voltage detection signal to the main channel.

7. The power supply unit according to claim 6, characterized in that, The power supply unit also includes a current detector that generates a current detection signal representing the output current of the output stage. When the current detection signal is set as the main channel, the feedback controller generates the control signal when the current detection signal exceeds the specified limit value, so that the current detection signal approaches the limit value.

8. The power supply unit according to claim 6 or 7, characterized in that, The feedback signal is the average value of the voltage detection signals of all channels.

9. A power supply device, characterized in that, The power supply device is constructed by stacking and connecting multiple power supply units as described in any one of claims 6 to 8.

10. A testing apparatus, characterized in that, The test apparatus includes a power supply device according to any one of claims 1 to 5 and 9 that supplies power to the device under test.

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