A peak voltage sampling circuit

Abstract

This application provides a peak voltage sampling circuit. The peak voltage sampling circuit includes: a first sampling capacitor, a second sampling capacitor, and a sampling control branch; a first terminal of the sampling control branch is electrically connected to an external voltage, a second terminal of the sampling control branch is electrically connected to a peak voltage output terminal, a third terminal of the sampling control branch is electrically connected to a first plate of the first sampling capacitor, and a fourth terminal of the sampling control branch is electrically connected to a first plate of the second sampling capacitor; the second plates of both the first and second sampling capacitors are grounded; in a first state, the sampling control branch controls the first sampling capacitor to sample the peak voltage, and the second sampling capacitor to transmit the peak voltage; in a second state, it controls the second sampling capacitor to sample the peak voltage, and the first sampling capacitor to transmit the peak voltage. This peak voltage sampling circuit can synchronize peak voltage sampling and processing, improving the real-time performance of sampling, thereby increasing the utilization of the time domain.

Description

Technical Field

[0001] This application relates to the field of voltage sampling technology, and in particular to a peak voltage sampling circuit. Background Technology

[0002] Capacitors are fundamental components in electrical engineering, capable of storing electrical charge. In the absence of an external discharge path, a capacitor can ensure that the voltage difference across its terminals does not decay over a relatively long period. In analog circuits, capacitors are commonly used in voltage sampling circuits to store voltage information. For example, in the design of switching power supplies, the peak values ​​of the input voltage, output voltage, and switching node voltage are crucial parameters for ensuring system stability. The accuracy of sampling these voltage peaks determines the power supply's stability, response speed, and efficiency.

[0003] In the prior art, the voltage sampling circuit can sample the peak value of the input voltage and output the peak value of the input voltage. When the sampled voltage of the input voltage is greater than the input voltage, the voltage sampling circuit can output a voltage, and the output voltage is the peak voltage.

[0004] However, the voltage sampling circuit needs to complete the peak voltage sampling first, and then transmit the peak voltage to the subsequent circuit for further processing, resulting in poor real-time sampling and low utilization of the time domain. Summary of the Invention

[0005] In view of the above problems, this application provides a peak voltage sampling circuit that can simultaneously sample and process peak voltage, improve the real-time performance of sampling, and thus improve the utilization of the time domain.

[0006] In a first aspect, embodiments of this application provide a peak voltage sampling circuit, including: a first sampling capacitor, a second sampling capacitor, and a sampling control branch;

[0007] The first terminal of the sampling control branch is electrically connected to an external voltage, the second terminal of the sampling control branch is electrically connected to the peak voltage output terminal, the third terminal of the sampling control branch is electrically connected to the first plate of the first sampling capacitor, and the fourth terminal of the sampling control branch is electrically connected to the first plate of the second sampling capacitor. The second plates of the first sampling capacitor and the second plate of the second sampling capacitor are both grounded.

[0008] The sampling control branch is used to control the first sampling capacitor to sample the peak voltage of the external voltage in a first state, and to control the second sampling capacitor to transmit the peak voltage to the peak voltage output terminal; and to control the second sampling capacitor to sample the peak voltage in a second state, and to control the first sampling capacitor to transmit the peak voltage to the peak voltage output terminal.

[0009] In some embodiments, the sampling control branch includes: a first switch, a second switch, a third switch, and a fourth switch;

[0010] The first terminal of the first switch and the first terminal of the third switch are both electrically connected to the external voltage. The second terminal of the first switch is electrically connected to the first plate of the first sampling capacitor and the first terminal of the second switch. The second terminal of the third switch is electrically connected to the first plate of the second sampling capacitor and the first terminal of the fourth switch. The second terminals of the second switch and the second terminals of the fourth switch are both electrically connected to the peak voltage output terminal.

[0011] In the first state, the first switch and the fourth switch are in the ON state, and the second switch and the third switch are in the OFF state; in the second state, the first switch and the fourth switch are in the OFF state, and the second switch and the third switch are in the ON state.

[0012] In some embodiments, the peak voltage sampling circuit further includes: a state control branch and a logic processing branch;

[0013] The first input terminal of the state control branch is electrically connected to the external voltage, the second input terminal of the state control branch is electrically connected to the voltage threshold, the output terminal of the state control branch is electrically connected to the input terminal of the logic processing branch, and the output terminal of the logic processing branch is electrically connected to the control terminal of the sampling control branch.

[0014] The state control branch is used to generate a working state signal based on the external voltage and the voltage threshold.

[0015] The logic processing branch is used to generate a status control signal based on the working status signal.

[0016] In some embodiments, the state control branch includes a voltage comparison module and a state control module;

[0017] The positive input terminal of the voltage comparison module is electrically connected to the external voltage, the negative input terminal of the voltage comparison module is electrically connected to the voltage threshold, the output terminal of the voltage comparison module is electrically connected to the input terminal of the state control module, and the output terminal of the state control module is electrically connected to the input terminal of the logic processing branch.

[0018] The voltage comparison module is used to compare the external voltage with the voltage threshold and generate a sampling window signal based on the comparison result;

[0019] The state control module is used to determine the working state signal based on the duration of the target signal and preset conditions when the sampling window signal is the target signal;

[0020] Specifically, when the operating status signal switches from the first status signal to the second status signal, the first sampling capacitor samples the peak voltage; when the operating status signal switches from the second status signal to the first status signal, the second sampling capacitor samples the peak voltage.

[0021] In some embodiments, the state control module includes a state judgment unit, a delay unit, a first inverter, and a second inverter;

[0022] The input terminal of the state judgment unit is electrically connected to the output terminal of the voltage comparison module and the first input terminal of the logic processing branch. The output terminal of the state judgment unit is electrically connected to the input terminal of the delay unit, the input terminal of the first inverter, and the second input terminal of the logic processing branch. The output terminal of the delay unit is electrically connected to the input terminal of the second inverter and the third input terminal of the logic processing branch. The output terminal of the first inverter is electrically connected to the fourth input terminal of the logic processing branch. The output terminal of the second inverter is electrically connected to the fifth input terminal of the logic processing branch.

[0023] In some embodiments, the logic processing branch includes: an AND gate module and an inverter module;

[0024] The first input terminal of the AND gate module is electrically connected to the output terminal of the voltage comparison module; the second input terminal of the AND gate module is electrically connected to the output terminal of the state judgment unit; the third input terminal of the AND gate module is electrically connected to the first input terminal of the inverter module, both of which are electrically connected to the output terminal of the delay unit; the fourth input terminal of the AND gate module is electrically connected to the output terminal of the first inverter; the fifth input terminal of the AND gate module and the second input terminal of the inverter module are both electrically connected to the output terminal of the second inverter; the first output terminal of the AND gate module is electrically connected to the first control terminal of the sampling control branch; the second output terminal of the AND gate module is electrically connected to the third control terminal of the sampling control branch; the first output terminal of the inverter module is electrically connected to the second control terminal of the sampling control branch; and the second output terminal of the inverter module is electrically connected to the fourth control terminal of the sampling control branch.

[0025] In some embodiments, the AND gate module includes a first AND gate and a second AND gate;

[0026] The first input terminal of the first AND gate and the first input terminal of the second AND gate are both electrically connected to the output terminal of the voltage comparison module. The second input terminal of the first AND gate is electrically connected to the output terminal of the first inverter. The third input terminal of the first AND gate is electrically connected to the output terminal of the second inverter. The second input terminal of the second AND gate is electrically connected to the output terminal of the state judgment unit. The third input terminal of the second AND gate is electrically connected to the output terminal of the delay unit. The output terminal of the first AND gate is electrically connected to the first control terminal of the sampling control branch. The output terminal of the second AND gate is electrically connected to the third control terminal of the sampling control branch.

[0027] The inverter module includes: a third inverter, a fourth inverter, a fifth inverter, and a sixth inverter;

[0028] The input terminal of the third inverter is electrically connected to the output terminal of the delay unit. The output terminal of the third inverter is electrically connected to the second control terminal of the sampling control branch through the fourth inverter. The input terminal of the fifth inverter is electrically connected to the output terminal of the second inverter. The output terminal of the fifth inverter is electrically connected to the fourth control terminal of the sampling control branch through the sixth inverter.

[0029] In some embodiments, the peak voltage sampling circuit further includes a voltage processing branch;

[0030] The input terminal of the voltage processing branch is electrically connected to the external voltage, and the output terminal of the voltage processing branch is electrically connected to the first terminal of the sampling control branch.

[0031] The voltage processing branch is used to perform voltage reduction and filtering on the external voltage.

[0032] In some embodiments, the voltage processing branch includes: a first resistor, a second resistor, a third resistor, a filter capacitor, and a buffer;

[0033] The first end of the first resistor is electrically connected to the external voltage. The second end of the first resistor is electrically connected to the first end of the second resistor and the first end of the third resistor. The second end of the second resistor is electrically connected to the input end of the buffer and the first plate of the filter capacitor. The second end of the third resistor and the second plate of the filter capacitor are both grounded. The output end of the buffer is electrically connected to the first end of the sampling control branch.

[0034] In some embodiments, the peak voltage sampling circuit further includes a buffer branch;

[0035] The input terminal of the buffer branch is electrically connected to the second terminal of the sampling control branch, and the output terminal of the buffer branch is electrically connected to the peak voltage output terminal.

[0036] In the technical solution of this application embodiment, the peak voltage sampling circuit includes a first sampling capacitor, a second sampling capacitor, and a sampling control branch. The first end of the sampling control branch is electrically connected to an external voltage, the second end of the sampling control branch is electrically connected to the peak voltage output terminal, the third end of the sampling control branch is electrically connected to the first plate of the first sampling capacitor, and the fourth end of the sampling control branch is electrically connected to the first plate of the second sampling capacitor. The second plates of both the first and second sampling capacitors are grounded. Through the sampling control branch, in a first state, the first sampling capacitor can be controlled to sample the peak voltage of the external voltage, and the second sampling capacitor can be controlled to transmit the peak voltage to the peak voltage output terminal. In a second state, the second sampling capacitor can be controlled to sample the peak voltage, and the first sampling capacitor can be controlled to transmit the peak voltage to the peak voltage output terminal. In this way, while sampling the peak voltage of the external voltage, the peak voltage sampling circuit can transmit the peak voltage to the subsequent circuit, so that the sampling and processing of the peak voltage can be performed synchronously, improving the real-time performance of sampling and thus improving the utilization rate of the time domain.

[0037] The above description is merely an overview of the technical solutions of the embodiments of this application. In order to better understand the technical means of the embodiments of this application and to implement them in accordance with the contents of the specification, and to make the above and other objects, features and advantages of the embodiments of this application more obvious and understandable, specific implementation methods of this application are described below. Attached Figure Description

[0038] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0039] Figure 1 A schematic diagram of a voltage sampling circuit provided for the present technology;

[0040] Figure 2 This is a schematic diagram of a peak voltage sampling circuit provided in an embodiment of this application;

[0041] Figure 3 This is a schematic diagram of another peak voltage sampling circuit provided in an embodiment of this application;

[0042] Figure 4 A schematic diagram of another peak voltage sampling circuit provided in the embodiments of this application;

[0043] Figure 5 A schematic diagram of another peak voltage sampling circuit provided in the embodiments of this application;

[0044] Figure 6 A schematic diagram of another peak voltage sampling circuit provided in the embodiments of this application;

[0045] Figure 7 A schematic diagram of another peak voltage sampling circuit provided in the embodiments of this application;

[0046] Figure 8 for Figure 7 The voltage waveforms of each node in the peak voltage sampling circuit are shown. Detailed Implementation

[0047] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0048] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains; the terminology used herein in the specification of the application is for the purpose of describing particular embodiments only and is not intended to limit the application; the terms “comprising” and “having”, and any variations thereof, in the specification, claims and drawings of this application are intended to cover non-exclusive inclusion.

[0049] The term "embodiment" as used herein means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of the phrase "embodiment" in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0050] Furthermore, the terms "first," "second," etc., in the specification and claims of this application or in the aforementioned drawings are used to distinguish different objects rather than to describe a specific order, and may explicitly or implicitly include one or more of the features.

[0051] In the description of the present application, unless otherwise clearly specified or limited, the terms "connected" and "coupled" should be understood in a broad sense. For example, the "connection" or "coupling" of a circuit structure can refer not only to a physical connection but also to an electrical connection or a signal connection. For example, it can be a direct connection, that is, a physical connection, or it can be indirectly connected through at least one intermediate component, as long as the circuit is connected. It can also be the connection inside two components; the signal connection can refer not only to the signal connection through a circuit but also to the signal connection through a media medium. For example, radio waves.

[0052] In order to enable those skilled in the art to better understand the solution of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings.

[0053] Figure 1 FIG. shows a schematic structural diagram of a voltage sampling circuit provided by the prior art. Figure 1 As shown, the voltage sampling circuit includes a comparator 1 and a sample-and-hold unit 2. The positive input terminal of the comparator 1 is electrically connected to the input voltage Vin, the negative input terminal of the comparator 1 is electrically connected to the output terminal of the sample-and-hold unit 2, and the output terminal of the comparator 1 is electrically connected to the input terminal of the sample-and-hold unit 2.

[0054] As Figure 1 shown, the output terminal of the sample-and-hold unit 2 is the output terminal of the voltage sampling circuit, and the output voltage Vout of the voltage sampling circuit is the voltage representing the peak value of the input voltage Vin after sampling. Exemplarily, when Vin > Vout, it indicates that the peak voltage of Vin has not been sampled at this time, and the output signal of the comparator 1 still needs to control the sample-and-hold unit 2 to continue charging the capacitor; when Vin < Vout, it indicates that Vout is already the peak voltage of Vin, and Vin itself has dropped to less than the peak voltage. At this time, the output signal of the comparator 1 should control the sample-and-hold unit 2 to stop charging the capacitor and maintain the current Vout.

[0055] The circuit structure of the above voltage sampling circuit is relatively simple and easy to implement. However, the voltage sampling circuit needs to first complete the peak voltage sampling and then transmit the peak voltage to the subsequent circuit so that the subsequent circuit can perform subsequent processing on the peak voltage. That is to say, the peak voltage sampling and the peak voltage processing cannot be carried out synchronously, resulting in poor sampling real-time performance and low utilization rate of the time domain.

[0056] To address the aforementioned technical problems, this application provides a peak voltage sampling circuit, comprising: a first sampling capacitor, a second sampling capacitor, and a sampling control branch. A first terminal of the sampling control branch is electrically connected to an external voltage; a second terminal of the sampling control branch is electrically connected to a peak voltage output terminal; a third terminal of the sampling control branch is electrically connected to a first plate of the first sampling capacitor; and a fourth terminal of the sampling control branch is electrically connected to a first plate of the second sampling capacitor. The second plates of both the first and second sampling capacitors are grounded. In a first state, the sampling control branch can control the first sampling capacitor to sample the peak voltage of the external voltage and control the second sampling capacitor to transmit the peak voltage to the peak voltage output terminal. In a second state, the second sampling capacitor can be controlled to sample the peak voltage, and the first sampling capacitor can be controlled to transmit the peak voltage to the peak voltage output terminal. Thus, while sampling the peak voltage of the external voltage, the peak voltage sampling circuit can simultaneously transmit the peak voltage to subsequent circuits, enabling synchronous sampling and processing of the peak voltage, thereby improving the real-time performance of the sampling.

[0057] The technical solutions provided in this application are described in detail below with reference to several specific embodiments.

[0058] Figure 2 This is a schematic diagram of a peak voltage sampling circuit provided in an embodiment of this application, as shown below. Figure 2 As shown, the peak voltage sampling circuit 100 includes: a first sampling capacitor CS1, a second sampling capacitor CS2, and a sampling control branch 110.

[0059] The sampling control branch 110 is electrically connected to the external voltage VD at its first end, to the peak voltage output terminal OUT at its second end, to the first plate of the first sampling capacitor CS1 at its third end, and to the first plate of the second sampling capacitor CS2 at its fourth end. The second plates of both the first and second sampling capacitors are grounded.

[0060] The sampling control branch 110 can control the first sampling capacitor CS1 to sample the peak voltage VD_pk of the external voltage VD in the first state, and control the second sampling capacitor CS2 to transmit the peak voltage VD_pk to the peak voltage output terminal OUT; in the second state, it can control the second sampling capacitor CS2 to sample the peak voltage VD_pk, and control the first sampling capacitor CS1 to transmit the peak voltage VD_pk to the peak voltage output terminal OUT.

[0061] For example, the control terminal of the sampling control branch 110 can receive a status control signal, and the sampling control branch 110 is in different working states based on different status control signals. For example, if the status control signal is a first status control signal, the sampling control branch 110 is in the first state; if the status control signal is a second status control signal, the sampling control branch 110 is in the second state.

[0062] The status control signal may include one signal or multiple signals. If the status control signal includes one signal, then the first status control signal is a high-level signal and the second status control signal is a low-level signal; or, the first status control signal is a low-level signal and the second status control signal is a high-level signal.

[0063] If the state control signal includes multiple signals, for example, if the state control signal includes a first signal and a second signal, then the first signal in the first state control signal is a high-level signal, the second signal in the first state control signal is a low-level signal, the first signal in the second state control signal is a low-level signal, and the second signal in the second state control signal is a high-level signal; or, the first signal in the first state control signal is a low-level signal, the second signal in the first state control signal is a high-level signal, the first signal in the second state control signal is a high-level signal, and the second signal in the second state control signal is a low-level signal. As another example, if the state control signal includes a first signal, a second signal, a third signal, and a fourth signal, then the first signal, the second signal, the third signal, and the fourth signal in the first state control signal can each be either a high-level signal or a low-level signal, and the first signal, the second signal, the third signal, and the fourth signal in the second state control signal are of the opposite types to their corresponding signals in the first state control signal.

[0064] It should be noted that the above embodiments only exemplify that the state control signal includes one signal, two signals, or four signals. In practical applications, the number of signals in the state control signal can also be three, five, or more. This application embodiment does not impose specific limitations on the number of signals in the state control signal.

[0065] For example, Figure 3 This is a schematic diagram of another peak voltage sampling circuit provided in an embodiment of this application. Figure 3 for Figure 2Based on the illustrated embodiment, the sampling control branch 110 includes a first switch K1, a second switch K2, a third switch K3, and a fourth switch K4. The first terminals of both the first and third switches K3 are electrically connected to an external voltage VD. The second terminal of the first switch K1 is electrically connected to the first plate of the first sampling capacitor CS1 and the first terminal of the second switch K2. The second terminal of the third switch K3 is electrically connected to the first plate of the second sampling capacitor CS2 and the first terminal of the fourth switch K4. The second terminals of both the second and fourth switches K4 are electrically connected to the peak voltage output terminal OUT.

[0066] For example, the first switch K1, the second switch K2, the third switch K3, and the fourth switch K4 can be at least one of a transmission gate, a metal-oxide-semiconductor (MOS) transistor, and a bipolar transistor. The control terminals of the first switch K1, the second switch K2, the third switch K3, and the fourth switch K4 are all electrically connected to a state control signal. If the state control signal contains only one signal, then the first switch K1 and the fourth switch K4 are of the same type, the second switch K2 and the third switch K3 are of the same type, and the first switch K1 and the second switch K2 are of different types. For example, the first switch K1 and the fourth switch K4 are in a conducting state under a high-level signal, and the second switch K2 and the third switch K3 are in a conducting state under a low-level signal; or, the first switch K1 and the fourth switch K4 are in a conducting state under a low-level signal, and the second switch K2 and the third switch K3 are in a conducting state under a high-level signal.

[0067] If the status control signal includes a first signal and a second signal, then the first switch K1, the second switch K2, the third switch K3, and the fourth switch K4 are all of the same type, and the control terminals of the first switch K1 and the fourth switch K4 are both electrically connected to the first signal, while the control terminals of the second switch K2 and the third switch K3 are both electrically connected to the second signal. For example, the first switch K1, the second switch K2, the third switch K3, and the fourth switch K4 are all in a conducting state under the action of a low-level signal; or, the first switch K1, the second switch K2, the third switch K3, and the fourth switch K4 are all in a conducting state under the action of a high-level signal.

[0068] If the status control signal includes a first signal, a second signal, a third signal, and a fourth signal, the control terminals of the first switch K1, the second switch K2, the third switch K3, and the fourth switch K4 are electrically connected to the first signal, the second signal, the third signal, and the fourth signal, respectively. The types of the first switch K1, the second switch K2, the third switch K3, and the fourth switch K4 can be arbitrary.

[0069] When the state control signal is the first state control signal, the first switch K1 is in the on state and the second switch K2 is in the off state. The external voltage VD is connected to the first plate of the first sampling capacitor CS1, and the first sampling capacitor CS1 is in the charging state. That is, the first sampling capacitor CS1 samples according to the external voltage VD until the peak voltage VD_pk is sampled. At the same time, the fourth switch K4 is in the on state and the third switch K3 is in the off state. The first plate of the second sampling capacitor CS2 is connected to the peak voltage output terminal OUT. The peak voltage VD_pk stored on the second sampling capacitor CS2 can be transmitted to the peak voltage output terminal OUT so that the subsequent circuit can process the peak voltage VD_pk.

[0070] When the state control signal is the second state control signal, the third switch K3 is in the on state and the fourth switch K4 is in the off state. The external voltage VD is connected to the first plate of the second sampling capacitor CS2, and the second sampling capacitor CS2 is in the charging state. That is, the second sampling capacitor CS2 follows the external voltage VD to sample until the peak voltage VD_pk is sampled. At the same time, the second switch K2 is in the on state and the first switch K1 is in the off state. The first plate of the first sampling capacitor CS1 is connected to the peak voltage output terminal OUT. The peak voltage VD_pk stored on the first sampling capacitor CS1 can be transmitted to the peak voltage output terminal OUT so that the subsequent circuit can process the peak voltage VD_pk.

[0071] In summary, in the first state, the first switch K1 and the fourth switch K4 are in the ON state while the second switch K2 and the third switch K3 are in the OFF state. The first sampling capacitor CS1 samples the peak voltage VD_pk, and the second sampling capacitor CS2 transmits the peak voltage VD_pk to the subsequent circuit simultaneously. In the second state, the first switch K1 and the fourth switch K4 are in the OFF state while the second switch K2 and the third switch K3 are in the ON state. The second sampling capacitor CS2 samples the peak voltage VD_pk, and the first sampling capacitor CS1 transmits the peak voltage VD_pk to the subsequent circuit simultaneously. Thus, as the first and second states continuously switch, the peak voltage sampling circuit 100 can continuously and synchronously sample and process the peak voltage VD_pk.

[0072] In this embodiment, the peak voltage sampling circuit includes a first sampling capacitor, a second sampling capacitor, and a sampling control branch. The first terminal of the sampling control branch is electrically connected to an external voltage, the second terminal is electrically connected to the peak voltage output terminal, the third terminal is electrically connected to the first plate of the first sampling capacitor, and the fourth terminal is electrically connected to the first plate of the second sampling capacitor. The second plates of both the first and second sampling capacitors are grounded. In a first state, the sampling control branch can control the first sampling capacitor to sample the peak voltage of the external voltage and control the second sampling capacitor to transmit the peak voltage to the peak voltage output terminal. In a second state, the second sampling capacitor can be controlled to sample the peak voltage, and the first sampling capacitor can be controlled to transmit the peak voltage to the peak voltage output terminal. Thus, while sampling the peak voltage of the external voltage, the peak voltage sampling circuit can transmit the peak voltage to subsequent circuits, allowing peak voltage sampling and processing to be performed synchronously, improving the real-time performance of the sampling and thus providing better time-domain utilization.

[0073] In some embodiments, Figure 4 This is a schematic diagram of another peak voltage sampling circuit provided in an embodiment of this application. Figure 4 for Figure 2 Based on the embodiment shown, the peak voltage sampling circuit 100 further includes a state control branch 120 and a logic processing branch 130.

[0074] The first input terminal of the state control branch 120 is electrically connected to the external voltage VD, the second input terminal of the state control branch 120 is electrically connected to the voltage threshold Vth, the output terminal of the state control branch 120 is electrically connected to the input terminal of the logic processing branch 130, and the output terminal of the logic processing branch 130 is electrically connected to the control terminal of the sampling control branch 110.

[0075] The state control branch 120 is used to generate a working state signal based on the external voltage VD and the voltage threshold Vth; the logic processing branch 130 is used to generate a state control signal based on the working state signal.

[0076] For example, the voltage threshold Vth is a voltage value related to the external voltage VD. The voltage threshold Vth includes, but is not limited to, the following types of thresholds: fixed single threshold, fixed double threshold, dynamic threshold, and threshold with hysteresis. Typically, the voltage threshold Vth can be determined based on the fluctuation range of the input voltage VD. Clearly, the voltage threshold Vth is a pre-set quantity according to actual needs and is not directly related to the real-time input voltage VD.

[0077] For example, Figure 5 This is a schematic diagram of another peak voltage sampling circuit provided in an embodiment of this application. Figure 5 for Figure 4 Based on the illustrated embodiment, the state control branch 120 includes a voltage comparison module 121 and a state control module 122. Among them, the positive input terminal of the voltage comparison module 121 is electrically connected to the external voltage VD, the negative input terminal of the voltage comparison module 122 is electrically connected to the voltage threshold Vth, the output terminal of the voltage comparison module 121 is electrically connected to the input terminal of the state control module 122, and the output terminal of the state control module 122 is electrically connected to the input terminal of the logic processing branch 130.

[0078] As Figure 5 shown, the voltage comparison module 121 includes a comparator CMP. The positive input terminal of the comparator CMP is electrically connected to the external voltage VD, the negative input terminal of the comparator CMP is electrically connected to the voltage threshold Vth. The positive input terminal of the comparator CMP is the positive input terminal of the voltage comparison module 121, and the negative input terminal of the comparator CMP is the negative input terminal of the voltage comparison module 121. The comparator CMP can compare the input voltage VD and the voltage threshold Vth and generate a sampling window signal Window based on the comparison result. Among them, if VD > Vth, the generated sampling window signal Window is a high-level signal; if VD < Vth, the generated sampling window signal Window is a low-level signal. Thus, the voltage comparison module 121 can compare the input voltage VD and the voltage threshold Vth and generate a sampling window signal Window based on the comparison result.

[0079] It should be noted that Figure 5 only one comparator CMP is exemplarily shown in the voltage comparison module 121. In practical applications, the voltage comparison module 121 may also include multiple comparators CMP. The embodiment of the present application does not specifically limit the number of comparators CMP in the voltage comparison module 121.

[0080] In summary, during the working process of the peak voltage sampling circuit 100, the voltage threshold Vth does not change, making the generation process of the sampling window signal Window an open loop, which can avoid the stability problems caused by the closed loop, improve the accuracy of the peak voltage VD_pk sampling, and thus improve the accuracy of the calculation results of the subsequent circuit.

[0081] Exemplarily, continue to refer to Figure 5, the state control module 122 includes a state judgment unit 1221, a time delay unit 1222, a first inverter Inv1, and a second inverter Inv2. Among them, the input end of the state judgment unit 1221 is electrically connected to the output end of the voltage comparison module 121 and the first input end of the logic processing branch 130, the output end of the state judgment unit 1221 is electrically connected to the input end of the time delay unit 1222, the input end of the first inverter Inv1, and the second input end of the logic processing branch 130, the output end of the time delay unit 1222 is electrically connected to the input end of the second inverter Inv2 and the third input end of the logic processing branch 130, the output end of the first inverter Inv1 is electrically connected to the fourth input end of the logic processing branch 130, and the output end of the second inverter Inv2 is electrically connected to the fifth input end of the logic processing branch 130.

[0082] The state judgment unit 1221 can receive a sampling window signal Window, and a preset condition is set inside the state judgment unit 1221. For example, the preset condition can be a volt-second threshold S_th. When the sampling window signal Window is a target signal, for example, the target signal is a high-level signal, the state judgment unit 1221 can start detecting the area S enclosed by the input voltage VD and the voltage threshold Vth over time, and determine whether the area S reaches the volt-second threshold S_th, that is, whether the area S is greater than the volt-second threshold S_th. Among them, if S > S_th, it means that the first sampling capacitor CS1 or the second sampling capacitor CS2 has effectively sampled the peak voltage VD_pk; if S < S_th, it means that the voltage information sampled on the first sampling capacitor CS1 or the second sampling capacitor CS2 cannot correctly represent the peak voltage VD_pk, and continuous following sampling is still required.

[0083] Based on whether the area S is greater than the volt-second threshold S_th and the current state, the state judgment unit 1221 can generate a state judgment signal Hold_pre. For example, in the case of the current being in the first state, if S > S_th, the state judgment signal Hold_pre generated by the state judgment unit 1221 is a second state judgment signal; if S < S_th, the state judgment signal Hold_pre generated by the state judgment unit 1221 is a first state judgment signal. In the case of the current being in the second state, if S > S_th, the state switching signal Hold_pre generated by the state judgment unit 1221 is a first state judgment signal; if S < S_th, the state switching signal Hold_pre generated by the state judgment unit 1221 is a second state judgment signal. Here, the first state judgment signal is a high-level signal, and the second state judgment signal is a low-level signal; or, the first state judgment signal is a low-level signal, and the second state judgment signal is a high-level signal.

[0084] It should be noted that the embodiments of this application only use the volt-second threshold S_th as an example to illustrate the preset conditions. In practical applications, the preset conditions can be current thresholds, voltage thresholds, or time presets. The preset conditions can also be the calculation results of at least two of the current thresholds, voltage thresholds, and time presets. The embodiments of this application do not impose specific limitations on the preset conditions.

[0085] like Figure 5 As shown, the state judgment signal Hold_pre is input to delay unit 1222 and first inverter Inv1. Delay unit 1222 delays the state judgment signal Hold_pre to obtain the working state sub-signal Hold_1, and sends the working state sub-signal Hold_1 to second inverter Inv2. Second inverter Inv2 inverts the working state sub-signal Hold_1 and outputs the working state sub-signal Hold_2. First inverter Inv1 inverts the state judgment signal Hold_pre and outputs the working state sub-signal Hold_pre_n. The working state sub-signals Hold_2, Hold_1, Hold_pre_n, and Hold_pre are all components of the working state signal; that is, the working state signal includes: working state sub-signals Hold_2, Hold_1, Hold_pre_n, and Hold_pre.

[0086] If the current operating state signal is the first state signal, meaning it is currently in the first state, the first sampling capacitor CS1 is in the sampling state, and the second sampling capacitor CS2 is in the holding state. When the state judgment signal Hold_pre is the second state judgment signal, the operating state signal determined by the state control module 122 is the second state signal, and the operating state signal switches from the first state signal to the second state signal. At this time, the first sampling capacitor CS1 samples the peak voltage VD_pk. If the current operating state signal is the second state signal, meaning it is currently in the second state, the second sampling capacitor CS2 is in the sampling state, and the first sampling capacitor CS1 is in the holding state. When the state judgment signal Hold_pre is the first state judgment signal, the operating state signal determined by the state control module 122 is the first state signal, and the operating state signal switches from the second state signal to the first state signal. At this time, the second sampling capacitor CS2 samples the peak voltage VD_pk.

[0087] Thus, when the sampling window signal Window is the target signal, the state control module 122 can determine the working state signal based on the duration of the target signal and preset conditions. Under the condition that the sampling window signal Window is the target signal, it can determine the peak voltage VD_pk in combination with the preset conditions, so that the peak sampling circuit can meet different application environments.

[0088] It should be noted that, Figure 5 This example only demonstrates the use of a time delay to trigger the operating state signal. The operating state is set based on a time delay or advance. In practical applications, the operating state can be set by comparing and determining voltage and current quantities, or by triggering the result of mathematical calculations or conversions of voltage and current quantities. This application does not impose specific limitations on the specific structure and method of setting and triggering the operating state.

[0089] For example, see [link to example]. Figure 5 The logic processing branch 130 includes: AND gate module 131 and inverter module 132. Specifically, the first input terminal of AND gate module 131 is electrically connected to the output terminal of voltage comparison module 121; the second input terminal of AND gate module 131 is electrically connected to the output terminal of state judgment unit 1221; the third input terminal of AND gate module 131 and the first input terminal of inverter module 132 are both electrically connected to the output terminal of delay unit 1222; the fourth input terminal of AND gate module 131 is electrically connected to the output terminal of first inverter Inv1; the fifth input terminal of AND gate module 131 and the second input terminal of inverter module 132 are both electrically connected to the output terminal of second inverter Inv2; the first output terminal of AND gate module 131 is electrically connected to the first control terminal of sampling control branch 110; the second output terminal of AND gate module 131 is electrically connected to the third control terminal of sampling control branch 110; the first output terminal of inverter module 132 is electrically connected to the second control terminal of sampling control branch 110; and the second output terminal of inverter module 132 is electrically connected to the fourth control terminal of sampling control branch 110.

[0090] For example, such as Figure 5As shown, the AND gate module 131 includes a first AND gate AND1 and a second AND gate AND2. The first input terminal of the first AND gate AND1 and the first input terminal of the second AND gate AND2 are both electrically connected to the output terminal of the voltage comparison module 121. The second input terminal of the first AND gate AND1 is electrically connected to the output terminal of the first inverter Inv1. The third input terminal of the first AND gate AND1 is electrically connected to the output terminal of the second inverter Inv2. The second input terminal of the second AND gate AND2 is electrically connected to the output terminal of the state judgment unit 1221. The third input terminal of the second AND gate AND2 is electrically connected to the output terminal of the delay unit 1222. The output terminal of the first AND gate AND1 is electrically connected to the first control terminal of the sampling control branch 110. The output terminal of the second AND gate AND2 is electrically connected to the third control terminal of the sampling control branch 110.

[0091] like Figure 5 As shown, the first AND gate AND1 receives the sampling window signal Window, the working state sub-signal Hold_pre_n, and the working state sub-signal Hold_2, and performs an AND operation on these signals to obtain the first signal K1_c. The second AND gate AND2 receives the sampling window signal Window, the working state sub-signal Hold_pre_n, and the working state sub-signal Hold_2, and performs an AND operation on these signals to obtain the third signal K3_c.

[0092] See also Figure 5 The inverter module 132 includes: a third inverter Inv3, a fourth inverter Inv4, a fifth inverter Inv5, and a sixth inverter Inv6. The input terminal of the third inverter Inv3 is electrically connected to the output terminal of the delay unit 1222. The output terminal of the third inverter Inv3 is electrically connected to the second control terminal of the sampling control branch 110 through the fourth inverter Inv4. The input terminal of the fifth inverter Inv5 is electrically connected to the output terminal of the second inverter Inv2. The output terminal of the fifth inverter Inv5 is electrically connected to the fourth control terminal of the sampling control branch 110 through the sixth inverter Inv6.

[0093] like Figure 5As shown, the third inverter Inv3 receives the working state sub-signal Hold_1. After inverting Hold_1, Inv3 sends the signal to the fourth inverter Inv4. Inv4 inverts Hold_1 again to obtain the second signal K2_c. The fifth inverter Inv5 receives the working state sub-signal Hold_2. After inverting Hold_2, Inv5 sends the signal to the sixth inverter Inv6. Inv6 inverts Hold_2 again to obtain the fourth signal K4_c.

[0094] The control terminal of the first switch K1 is electrically connected to the first signal K1_c, and the on / off state of the first switch K1 can be controlled based on the first signal K1_c. The control terminal of the third switch K3 is electrically connected to the third signal K3_c, and the on / off state of the third switch K3 can be controlled based on the third signal K3_c. The control terminal of the second switch K2 is electrically connected to the second signal K2_c, and the on / off state of the second switch K2 can be controlled based on the second signal K2_c. The control terminal of the fourth switch K4 is electrically connected to the fourth signal K4_c, and the on / off state of the fourth switch K4 can be controlled based on the fourth signal K4_c. The first signal K1_c, the second signal K2_c, the third signal K3_c, and the fourth signal K4_c are all components of the state control signal, that is, the state control signal includes the first signal K1_c, the second signal K2_c, the third signal K3_c, and the fourth signal K4_c. Therefore, the logic processing branch 130 can generate the state control signal based on the working state signal.

[0095] It should be noted that the embodiments of this application only take AND gate module 131 and inverter module 132 as examples to illustrate the specific circuit structure of logic processing branch 130. In practical applications, logic processing branch 130 may also include at least one of OR gate module, NOT gate module, NAND gate module, AND-OR gate module, NOR gate module, AND-OR-NOT module, register module and latch module. This application does not impose specific limitations on the specific circuit structure of logic processing branch 130.

[0096] In this embodiment, the state control branch includes a voltage comparison module and a state control module. The positive input terminal of the voltage comparison module is electrically connected to an external voltage, the negative input terminal is electrically connected to a voltage threshold, the output terminal is electrically connected to the input terminal of the state control module, and the output terminal of the state control module is electrically connected to the input terminal of the logic processing branch. The voltage comparison module can compare the external voltage and the voltage threshold and generate a sampling window signal based on the comparison result. When the sampling window signal is the target signal, the state control module can determine the working state signal based on the duration of the target signal and preset conditions. Specifically, when the working state signal switches from the first state signal to the second state signal, the first sampling capacitor samples the peak voltage; when the working state signal switches from the second state signal to the first state signal, the second sampling capacitor samples the peak voltage. Thus, under the condition that the sampling window signal is the target signal, the sampling timing of the peak voltage can be determined by combining preset conditions, so that the peak sampling circuit can meet different application environments.

[0097] In some embodiments, Figure 6 This is a schematic diagram of another peak voltage sampling circuit provided in an embodiment of this application. Figure 6 for Figure 2 or Figure 4 Based on the illustrated embodiment, the peak voltage sampling circuit 100 further includes a voltage processing branch 140. The input terminal of the voltage processing branch 140 is electrically connected to an external voltage VD, and the output terminal of the voltage processing branch 140 is electrically connected to the first terminal of the sampling control branch 110.

[0098] The voltage processing branch 140 is used to step down and filter the external voltage VD.

[0099] For example, Figure 7 This is a schematic diagram of another peak voltage sampling circuit provided in an embodiment of this application. Figure 7 for Figure 6 Based on the illustrated embodiment, the voltage processing branch 140 includes: a first resistor R1, a second resistor R2, a third resistor R3, a filter capacitor C, and a buffer. The first terminal of the first resistor R1 is electrically connected to an external voltage VD; the second terminal of the first resistor R1 is electrically connected to the first terminals of the second resistor R2 and the third resistor R3; the second terminal of the second resistor R2 is electrically connected to the input terminal of the buffer and the first plate of the filter capacitor C; the second terminal of the third resistor R3 and the second plate of the filter capacitor C are both grounded; and the output terminal of the buffer is electrically connected to the first terminal of the sampling control branch 110.

[0100] Typically, the external voltage VD may have a large amplitude and significant ripple interference. The first resistor R1 and the third resistor R3 form a voltage divider unit, as follows: Figure 7 As shown, the voltage divider unit can step down the external voltage VD input to the voltage processing branch 140. Simultaneously, the second resistor R2 and the filter capacitor C form a filter unit, as shown... Figure 7 As shown, the filtering unit can filter the stepped-down external voltage VD to obtain the voltage signal VD_1 to be sampled.

[0101] It should be noted that, Figure 7 This example only demonstrates how voltage processing branch 140 implements voltage reduction based on a voltage divider unit. In practical applications, other methods can also be used for voltage reduction, and this embodiment does not impose specific limitations on these methods. It should also be noted that... Figure 7 The voltage processing branch 140 is shown as an example only, which implements filtering based on an RC filter unit. In practical applications, other methods can also be used for filtering, and this application does not impose specific limitations on this.

[0102] In this embodiment, the peak voltage sampling circuit further includes a voltage processing branch. The input terminal of the voltage processing branch is electrically connected to an external voltage, and the output terminal of the voltage processing branch is electrically connected to the first terminal of the sampling control branch. The voltage processing branch can perform step-down and filtering processing on the external voltage, so that the peak voltage sampling circuit can sample based on the stepped-down and filtered external voltage, which can improve the accuracy of the sampling results.

[0103] In some embodiments, see continue to see Figure 6 The peak voltage sampling circuit 100 also includes a buffer branch 150, the input terminal of which is electrically connected to the second terminal of the sampling control branch 110, and the output terminal of the buffer branch 150 is electrically connected to the peak voltage output terminal OUT.

[0104] For example, see Figure 7 As shown, the buffer branch 150 includes an operational amplifier OP. The positive input terminal of the operational amplifier OP is electrically connected to the second terminal of the sampling control branch 110, and the negative input terminal of the operational amplifier OP is electrically connected to the output terminal and the peak voltage output terminal OUT of the operational amplifier OP. The operational amplifier OP can receive the peak voltage VD_pk. Since the driving capability of the peak voltage VD_pk is weak, the operational amplifier OP can perform follower processing on the peak voltage VD_pk to obtain the target peak voltage VD_pk_buf, thereby improving the driving capability of the voltage VD_pk.

[0105] It should be noted that, Figure 7The illustrated embodiments only exemplarily show that the buffer branch 150 enhances the driving ability for the peak voltage VD_pk based on the operational amplifier OP. In practical applications, the buffer branch 150 can enhance the driving ability for the peak voltage VD_pk based on other structures, and this application does not limit the specific circuit structure for enhancing the driving ability for the peak voltage VD_pk.

[0106] In the embodiments of this application, the peak voltage sampling circuit further includes a buffer branch. The input end of the buffer branch is electrically connected to the second end of the sampling control branch, and the output end of the buffer branch is electrically connected to the peak voltage output end, which can enhance the driving ability for the peak voltage.

[0107] Exemplarily, Figure 8 For Figure 7 the voltage waveform diagrams of each node in the illustrated peak voltage sampling circuit, in combination with Figure 7 and Figure 8 as shown, in the first state of the peak voltage sampling circuit 100, the first sampling capacitor CS1 is responsible for the acquisition and transfer of the peak voltage. In the second state of the peak voltage sampling circuit 100, the second sampling capacitor CS2 is responsible for the acquisition and transfer of the peak voltage. The specific working principle is as follows:

[0108] During the time period from 0 to A0: VD_1 < Vth, the peak voltage sampling is not triggered. At this time, Window is low, indicating that the sampling window is not triggered. K1_c is low, and the first switch K1 is in the off state; K2_c is low, and the second switch K2 is in the off state.

[0109] At the moment of A0: VD_1 > Vth, the sampling window is triggered. At this time, Window becomes high, indicating that the sampling window starts to appear. K1_c becomes high, and the first switch K1 is in the on state. At this time, the voltage information of VD_1 can be transferred to the first sampling capacitor CS1, and the voltage V1 of the first plate of the first sampling capacitor CS1 changes with VD_1. K2_c is low, and the second switch K2 is in the off state, and the voltage information on the first sampling capacitor CS1 cannot be transferred to the subsequent stage yet.

[0110] [[ID=*23]]From A0 to A1: VD_1 > Vth, the rising edge of the Window signal triggers the state judgment unit to start working. The state judgment unit has specific preset conditions built in, for example, the volt-second threshold S_th. The state judgment unit will detect the area S enclosed by the VD_1 signal and the Vth signal over time, and the area S has not reached S_th. At this time, the voltage of VD is still changing, and the voltage information on the first sampling capacitor CS1 cannot correctly represent the peak voltage of VD, and sampling needs to continue to follow.

[0111] During the time period from A1 to A2: The working state is the same as that in the time period from 0 to A0. Note: The text marked with * has been adjusted according to the context to make the translation more fluent. If you have any other questions, please feel free to let me know.

[0112] The time period A2 to A3 is consistent with the working status of A0 to A1.

[0113] Time period A3~A4: The work status is consistent with that in time period 0~A0.

[0114] The time period A4 to A5 is consistent with the working status of A0 to A1.

[0115] The time period A5 to A6 is consistent with the working status of 0 to A0.

[0116] The time period A6 to A7 is consistent with the working status of A0 to A1.

[0117] At time A7: The area S enclosed by VD_1 and Vth over time has reached the volt-second threshold S_th, and the peak value of the VD voltage has been effectively captured on the first sampling capacitor CS1. At this time, K1_c goes low, the first switch K1 is in the open state, and the voltage on the first sampling capacitor CS1 no longer follows the change of VD_1.

[0118] The time period A7 to A8 can be understood as the delay duration T-dly of the delay device, during which all voltage signals maintain the same state as the signal at time A7.

[0119] At time A8: K2_c goes high after a delay, and the second switch K2 is in the conducting state, transferring the voltage V1 stored on the first sampling capacitor CS1 to the subsequent stage to form the VD_pk voltage. The VD_pk voltage is then processed by the follower circuit composed of operational amplifiers to generate the final voltage VD_pk_buf, completing the sampling action of the VD peak voltage.

[0120] In the second state, the sampling process of the second sampling capacitor CS2 begins, and its working principle is basically the same as in the first state. At this time, the sampled voltage information obtained by the first sampling capacitor CS1 has already been passed to the subsequent stage for further calculations. The sampled data V2 of the second sampling capacitor CS2 does not affect the data already obtained by the first sampling capacitor CS1, ensuring that calculations can be performed using the already sampled data while simultaneously sampling new data. This ensures full utilization of the time domain and also guarantees that the sampled signal can be updated in real time, improving the control accuracy of the subsequent system.

[0121] The above-disclosed embodiments are merely specific examples of this application. However, the embodiments of this application are not limited thereto, and any variations that can be conceived by those skilled in the art should fall within the protection scope of this application.

[0122] The term "comprising" as used in this application does not exclude the presence of elements or steps not listed in the claims. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. This application can be implemented by means of hardware comprising several different elements and by means of a suitably programmed computer. In the unit claims listing several means, several units of these means may be embodied by the same item of hardware. The use of "first," "second," and "third," etc., does not indicate any order and should be interpreted as names. Unless otherwise specified, the steps in the above embodiments should not be construed as limiting the order of execution.

[0123] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A peak voltage sampling circuit, characterized in that, include: The first sampling capacitor, the second sampling capacitor, and the sampling control branch; The first terminal of the sampling control branch is electrically connected to an external voltage, the second terminal of the sampling control branch is electrically connected to the peak voltage output terminal, the third terminal of the sampling control branch is electrically connected to the first plate of the first sampling capacitor, and the fourth terminal of the sampling control branch is electrically connected to the first plate of the second sampling capacitor. The second plates of the first sampling capacitor and the second plate of the second sampling capacitor are both grounded. The sampling control branch is used to control the first sampling capacitor to sample the peak voltage of the external voltage in a first state, and to control the second sampling capacitor to transmit the peak voltage to the peak voltage output terminal; and to control the second sampling capacitor to sample the peak voltage in a second state, and to control the first sampling capacitor to transmit the peak voltage to the peak voltage output terminal.

2. The peak voltage sampling circuit according to claim 1, characterized in that, The sampling control branch includes: a first switch, a second switch, a third switch, and a fourth switch; The first terminal of the first switch and the first terminal of the third switch are both electrically connected to the external voltage. The second terminal of the first switch is electrically connected to the first plate of the first sampling capacitor and the first terminal of the second switch. The second terminal of the third switch is electrically connected to the first plate of the second sampling capacitor and the first terminal of the fourth switch. The second terminals of the second switch and the second terminals of the fourth switch are both electrically connected to the peak voltage output terminal. In the first state, the first switch and the fourth switch are in the ON state, and the second switch and the third switch are in the OFF state; in the second state, the first switch and the fourth switch are in the OFF state, and the second switch and the third switch are in the ON state.

3. The peak voltage sampling circuit according to claim 1, characterized in that, Also includes: State control branch and logic processing branch; The first input terminal of the state control branch is electrically connected to the external voltage, the second input terminal of the state control branch is electrically connected to the voltage threshold, the output terminal of the state control branch is electrically connected to the input terminal of the logic processing branch, and the output terminal of the logic processing branch is electrically connected to the control terminal of the sampling control branch. The state control branch is used to generate a working state signal based on the external voltage and the voltage threshold. The logic processing branch is used to generate a status control signal based on the working status signal.

4. The peak voltage sampling circuit according to claim 3, characterized in that, The state control branch includes a voltage comparison module and a state control module; The positive input terminal of the voltage comparison module is electrically connected to the external voltage, the negative input terminal of the voltage comparison module is electrically connected to the voltage threshold, the output terminal of the voltage comparison module is electrically connected to the input terminal of the state control module, and the output terminal of the state control module is electrically connected to the input terminal of the logic processing branch. The voltage comparison module is used to compare the external voltage with the voltage threshold and generate a sampling window signal based on the comparison result; The state control module is used to determine the working state signal based on the duration of the target signal and preset conditions when the sampling window signal is the target signal; Specifically, when the operating status signal switches from the first status signal to the second status signal, the first sampling capacitor samples the peak voltage; when the operating status signal switches from the second status signal to the first status signal, the second sampling capacitor samples the peak voltage.

5. The peak voltage sampling circuit according to claim 4, characterized in that, The state control module includes a state judgment unit, a delay unit, a first inverter, and a second inverter; The input terminal of the state judgment unit is electrically connected to the output terminal of the voltage comparison module and the first input terminal of the logic processing branch. The output terminal of the state judgment unit is electrically connected to the input terminal of the delay unit, the input terminal of the first inverter, and the second input terminal of the logic processing branch. The output terminal of the delay unit is electrically connected to the input terminal of the second inverter and the third input terminal of the logic processing branch. The output terminal of the first inverter is electrically connected to the fourth input terminal of the logic processing branch. The output terminal of the second inverter is electrically connected to the fifth input terminal of the logic processing branch.

6. The peak voltage sampling circuit according to claim 5, characterized in that, The logic processing branch includes: an AND gate module and an inverter module; The first input terminal of the AND gate module is electrically connected to the output terminal of the voltage comparison module; the second input terminal of the AND gate module is electrically connected to the output terminal of the state judgment unit; the third input terminal of the AND gate module is electrically connected to the first input terminal of the inverter module, both of which are electrically connected to the output terminal of the delay unit; the fourth input terminal of the AND gate module is electrically connected to the output terminal of the first inverter; the fifth input terminal of the AND gate module and the second input terminal of the inverter module are both electrically connected to the output terminal of the second inverter; the first output terminal of the AND gate module is electrically connected to the first control terminal of the sampling control branch; the second output terminal of the AND gate module is electrically connected to the third control terminal of the sampling control branch; the first output terminal of the inverter module is electrically connected to the second control terminal of the sampling control branch; and the second output terminal of the inverter module is electrically connected to the fourth control terminal of the sampling control branch.

7. The peak voltage sampling circuit according to claim 6, characterized in that, The AND gate module includes a first AND gate and a second AND gate; The first input terminal of the first AND gate and the first input terminal of the second AND gate are both electrically connected to the output terminal of the voltage comparison module. The second input terminal of the first AND gate is electrically connected to the output terminal of the first inverter. The third input terminal of the first AND gate is electrically connected to the output terminal of the second inverter. The second input terminal of the second AND gate is electrically connected to the output terminal of the state judgment unit. The third input terminal of the second AND gate is electrically connected to the output terminal of the delay unit. The output terminal of the first AND gate is electrically connected to the first control terminal of the sampling control branch. The output terminal of the second AND gate is electrically connected to the third control terminal of the sampling control branch. The inverter module includes: a third inverter, a fourth inverter, a fifth inverter, and a sixth inverter; The input terminal of the third inverter is electrically connected to the output terminal of the delay unit, and the output terminal of the third inverter is electrically connected to the second control terminal of the sampling control branch through the fourth inverter. The input terminal of the fifth inverter is electrically connected to the output terminal of the second inverter, and the output terminal of the fifth inverter is electrically connected to the fourth control terminal of the sampling control branch through the sixth inverter.

8. The peak voltage sampling circuit according to any one of claims 1-7, characterized in that, Also includes: Voltage processing branch; The input terminal of the voltage processing branch is electrically connected to the external voltage, and the output terminal of the voltage processing branch is electrically connected to the first terminal of the sampling control branch. The voltage processing branch is used to perform voltage reduction and filtering on the external voltage.

9. The peak voltage sampling circuit according to claim 8, characterized in that, The voltage processing branch includes: a first resistor, a second resistor, a third resistor, a filter capacitor, and a buffer; The first end of the first resistor is electrically connected to the external voltage. The second end of the first resistor is electrically connected to the first end of the second resistor and the first end of the third resistor. The second end of the second resistor is electrically connected to the input end of the buffer and the first plate of the filter capacitor. The second end of the third resistor and the second plate of the filter capacitor are both grounded. The output end of the buffer is electrically connected to the first end of the sampling control branch.

10. The peak voltage sampling circuit according to any one of claims 1-7, characterized in that, Also includes: Buffer branch; The input terminal of the buffer branch is electrically connected to the second terminal of the sampling control branch, and the output terminal of the buffer branch is electrically connected to the peak voltage output terminal.

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