Test method and system for UART chip

Abstract

The application provides a UART chip testing method and system, and belongs to the field of integrated circuit testing. In the testing of the UART chip, the time from receiving the instruction at the RX to returning the data to the testing machine at the TX port is uncertain, which causes the testing machine to be unable to determine when the TX port starts to transmit the data. The application does not need the testing machine to configure the Match function, and saves the collected data in the releasable variable space of the host computer, processes the collected data, obtains the output character, and compares the output character with the expected character, so that the writing and use of the output expected result pattern are saved, and the space use of the testing machine LVM is reduced. Meanwhile, the collected data is converted into characters through processing, which facilitates the engineers to determine the reason for the chip testing failure. The testing method does not need special testing board design, and can perform parallel testing of the UART protocol of multiple sites.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuit testing, more particularly, to a test method and system for UART chip. BACKGROUND

[0002] UART (Universal Asynchronous Receiver / Transmitter), that is, a universal asynchronous receiver / transmitter, is a kind of serial and asynchronous communication protocol. Serial communication refers to transmitting data one bit at a time in sequence by using a single transmission line. Asynchronous communication refers to that the time interval between two bytes in communication is not fixed, while the time interval of each bit within a byte is fixed, and the sending end can start sending characters at any time, so for asynchronous communication, a data start bit and an end bit must be added at the beginning and end of each character respectively, so that the receiving end can correctly receive each character. And the receiving and transmitting ports of asynchronous communication are independent clock signals, so the transmission between asynchronous communication needs to specify the same transmission data rate to realize transmission, and the transmission data rate is represented by baud rate.

[0003] For UART protocol, it also specifies the content of the data packet, which is composed of start bit, main data, check bit and stop bit, and the data packet format of the two parties must be consistent to normally receive and send data, and when the bus is in idle state, the state of the signal line is "1", that is, high level, indicating that there is no data transmission on the current line. In summary, the communication between two UART devices needs to specify the same baud rate, idle bit, start bit, check bit and end bit protocol for the two UART devices to realize data transmission.

[0004] For the test of UART protocol chip, most external instructions can only be transmitted to the chip through the UART protocol, and the ports of the UART protocol include the power port VCC, the ground port GND, the receiving port RX and the transmitting port TX, so only the TX port and the RX port of the UART protocol chip to be tested are connected to two digital resource channels of the tester, the tester sends instructions to the RX port through the digital resource channel, the chip receives the instructions and performs corresponding operations according to the instructions, but the engineer cannot determine whether the instructions are successfully executed by the chip, so the engineer adds instructions to return the state of the chip to the tester through the TX port, and judges whether the chip successfully executes the instructions according to whether the returned data meets the expected result. However, there is a difficulty in this test process, that is, the time from receiving the instructions from the RX port to starting to return the data from the TX port to the tester is uncertain, and the chip data manual can only provide the response time range of the TX port, but cannot provide the specific response time. The tester does not have the UART communication protocol, and the UART communication protocol has no clock signal, so the tester cannot determine when the data returned by the TX port starts to be transmitted. Because the UART protocol stipulates that when the bus is in an idle state, the state of the signal line is "1", that is, high level, so the start bit of the data transmission is low level.

[0005] Based on the above characteristics, the tester bench designs a Match function, the principle of which is that after sending instructions to the RX port, the tester starts the Match function of the digital channel connected to the TX port, sets a reasonable Match time according to the maximum response time of the TX given in the chip data manual, and monitors and compares each BIT data returned by the TX port in real time within this time, each BIT needs to be judged N times, N is a multiple of the baud rate of the UART protocol, if "L" is not matched within this time, the sending function of the UART protocol does not pass the test. When the tester monitors and compares N "L" continuously within this time, it means that the "L" is the start bit of the effective output data transmitted by the TX, and the Match function is completed and closed.

[0006] At this time, the start bit of the valid data sent by TX to the tester can be determined, but the end bit of the valid data has not been confirmed, but the size of the valid data transmitted by TX is known, so the prior art is to write the expected output result into a pattern in advance and store it in the linear vector memory LVM (Linear Vector Memory) of the tester, wherein the pattern is a sequence of vectors arranged in a certain pattern, which is essentially a truth table, and mainly includes the symbolic combination of input level and expected output level, and also includes microinstructions for implementing some complex functions. The symbols in the pattern generally mean: "0" for input low level, "1" for input high level, "L" for output low level, "H" for output high level, "Z" for output high impedance, and "X" for not caring about the output state. Then the data returned from the TX port starting from the start bit is compared with the expected output result stored in the LVM, i.e. the pattern, in real time bit by bit. Specifically, by setting the data sampling point, the state of each sampling period is compared at the data sampling point until the end of the pattern. If the comparison result of each bit is consistent, it means that the chip successfully executes the instruction, and if there is an inconsistent bit, it means that the chip does not successfully execute the instruction.

[0007] This test method has certain limitations:

[0008] a. It is difficult to implement multi-site testing: Chip testing pursues multi-site testing to improve efficiency, and the Match function of the tester is limited, not one digital channel has one Match function, but a group of digital channels share one Match function. The number of digital channels included in the digital channel group of different machines is not the same. Therefore, when designing the test board, the digital channels connected to the TX port of each site should be allocated to different digital channel groups to realize parallel testing. Otherwise, only serial testing can be performed, which increases the test time and reduces the test efficiency. However, the location of the digital channel resource is fixed on the test board, which makes it difficult to allocate the digital channels connected to the TX port of each site to different groups, increases the design difficulty of the test board, and increases the cost of the test board. Or only the number of parallel test sites can be reduced to realize the above allocation rule.

[0009] b.Pattern storage increases test cost: The above test method needs to compare the effective data returned by the TX to the test machine with the expected output result pattern in real time. Different return values have corresponding patterns, and the writing of a large number of patterns increases the workload of engineers. After the test program is loaded, the pattern is stored in the LVM of the test machine for quick reading during testing. Each line of the pattern is called a line vector, and multiple line vectors form a test pattern. The vector depth of the LVM, that is, the number of lines of vectors that can be stored, is limited, and the test machine is usually only configured with the minimum vector depth specification. A licence needs to be purchased to unlock a larger vector depth. Therefore, the existing test method requires a large number of patterns, which will increase the vector depth, resulting in an increase in the occupation of the LVM. When the LVM is not enough, the test program cannot run, and unlocking the vector depth increases the test cost.

[0010] c. Cannot directly determine the cause of test failure: When using the pattern real-time comparison method for testing, if the test item fails, only the inconsistent BIT can be seen, and the cause of the failure cannot be directly determined.

[0011] Chinese patent application CN 111796977 A, "A multi-port UART function test method based on a test bench", describes a multi-port UART function test method based on a test bench, which solves the problem of difficulty in implementing accurate and simple UART general function testing. The method includes the following steps: connecting the UART chip under test to the test bench and performing connection testing, if the connection testing passes, initializing the UART chip under test using the test bench; using the test bench to perform function testing on the initialized UART chip under test, wherein the function testing includes automatic software flow control function; and receiving one or more of the function testing, data sending function testing, and output high and low level function testing. In this invention, the method used for data sending function is to determine the start bit of TX port sending data through the test machine Match function, and to determine the validity of the result by comparing bit by bit with the pattern. This method does not overcome the limitations described above. SUMMARY

[0012] 1. Technical problem to be solved

[0013] Based on the above shortcomings, the present application proposes a test method for UART chips, which does not need to design a special test board and can save the space of the test machine LVM without outputting the expected result pattern, and is convenient for determining the reason why the instructions sent by the test machine through the UART protocol are not successfully executed by the chip.

[0014] 2. Technical solution

[0015] The object of the present application is achieved by the following technical solutions.

[0016] First, connect the tester to the UART chip, the pins of the UART protocol include VCC, GND, TX and RX, the tester's DPS resource channel connects the chip VCC pin, the tester's DGND resource channel connects the chip's GND pin, and the tester's two digital resource channels are connected to the chip's TX pin and RX pin.

[0017] Tester and UART chip connectivity test: the tester tests the VCC, GND, TX and RX pins for open and short circuit, and if it passes the open and short circuit test, the tester and the measured UART chip have no abnormal connection.

[0018] Test the UART chip: the tester switches the chip working state through instructions, and after the switching is successful, tests the required test items of the UART chip under the corresponding working state; repeat the step until all the test items corresponding to the working states to be tested are tested.

[0019] If all the test items of the above test process pass, it means that the measured chip is qualified, otherwise the chip is unqualified.

[0020] Specifically, the specific process of the tester switching the working state of the UART chip through instructions includes:

[0021] The tester sends a working state conversion instruction to the RX port of the chip; the format of the instruction data should conform to the data packet format of the measured UART chip protocol, otherwise the RX port cannot receive the instruction;

[0022] Further, the chip changes the working state of the chip according to the instruction received by the RX port;

[0023] Further, the chip returns the current working state of the chip through the TX port according to the instruction;

[0024] The tester receives the data returned by the TX port, and judges whether the chip successfully executes the instruction and whether the chip enters the specified working state according to the received data. The specific implementation of the tester receiving the data returned by the TX port is as follows:

[0025] The tester sets the waiting time and the sampling time: according to the chip data manual, the shortest response time T1 and the longest response time T2 of the TX port after receiving the instruction can be obtained, the waiting time is the shortest response time T1, the transmission time of a bit of data is calculated according to the known baud rate of the UART, and the transmission time T3 of the effective data sent by the TX port is calculated according to the known number of effective data BIT sent by the TX port, and the sampling time is set to T2-T1+T3;

[0026] Test machine sets sampling period: set as 1 / N times of the time of transmitting one BIT valid data through UART, N>1, preferably, 8≤N≤16.

[0027] Data sampling: after the test machine sends the instruction to the RX port, it waits for a time T1 window without operation; after T1, the test machine starts sampling the data transmitted by the TX port according to the set sampling period and stores it; after a sampling time T2-T1+T3, the sampling is ended. Further, all sites are sampled in parallel at the same time, that is, the test machine simultaneously samples the data of all dies to be tested.

[0028] Sampling data processing: the test machine extracts the stored data for processing and converts the valid test data into characters. After the sampling is ended, the data in the variable space of the host computer should be "a certain length of idle bits at the beginning" plus "valid test data". An algorithm is written in the test program to extract the data in the variable space of the host computer for data processing to determine the starting bit and the corresponding data BIT, and to convert the corresponding binary data into characters.

[0029] Sampling data comparison: the test machine compares the obtained characters with the expected output characters, and the characters meeting the expected results indicate that the chip successfully executes the instruction sent by the test machine, and the characters not meeting the expected results indicate that the chip does not successfully execute the instruction sent by the test machine.

[0030] Failure reason judgment: when the test fails, the characters are compared with the error code to determine the reason for the unsuccessful execution of the instruction sent by the test machine.

[0031] After the chip successfully executes the instruction sent by the test machine, the chip enters the working state specified by the instruction, and the next step is to test all the test items required in the working state, and after the completion, the test machine sends a new instruction to the chip through the UART protocol, and the chip changes the working state according to the instruction, and the next step is to test all the test items required in the state, and the above process is repeated until all the test items in all the working states are tested. If the entire test flow passes, the chip is qualified, otherwise it is not qualified.

[0032] 3. Advantages

[0033] Compared with the prior art, the advantages of the present application are:

[0034] (1) The parallel test of the UART protocol of multiple sites can be performed without special test board design;

[0035] (2) The collected data is saved in the releasable variable space applied from the host computer, so that the writing and use of the output expected result pattern are saved, and the space use of the test machine LVM is reduced.

[0036] (3) The test method of the application processes the collected data into characters and compares them with error codes, which facilitates the engineers to determine the reason why the instructions sent by the test machine through the UART protocol are not successfully executed by the chip. BRIEF DESCRIPTION OF DRAWINGS

[0037] Figure 1 The test flow chart of the chip of the UART protocol;

[0038] Figure 2 The test flow chart of the prior art for changing the working state of the UART chip;

[0039] Figure 3 The test flow chart of the application for changing the working state of the UART chip. DETAILED DESCRIPTION

[0040] The application will be described in detail below in combination with the accompanying drawings and specific embodiments.

[0041] The test flow of the chip of the UART protocol is shown in Figure 1 The chip of the UART protocol is first connected to the test machine, and an open short circuit test is performed. The open short circuit test indicates that the tested chip is connected to the test machine in good condition. Next, the working state of the chip is changed through the UART communication protocol. If the chip successfully enters the specified working state, the next step is to test the required test items of the chip in the working state. The above two steps are repeated until all the required test items in all the working states are completed, and the test flow is completed. If the chip passes all the test items of the test flow, it is qualified. If it does not pass, it is unqualified.

[0042] The specific implementation flow is as follows:

[0043] First, the test machine is connected to the UART chip. The pins of the UART protocol include VCC, GND, TX, and RX. The VCC pin is connected to the power supply DPS resource channel of the test machine, the GND pin is connected to the ground GND resource channel of the test machine, and the TX pin and the RX pin are connected to two digital resource channels of the test machine. An open short circuit test is performed on these pins. If the open short circuit test is passed, it indicates that the connection between the test machine and the tested UART chip is normal.

[0044] After the connection test, the test item for changing the working state of the UART chip is performed. The difficulty of this test lies in that the time from receiving the instruction of the test machine from the RX port to changing the working state of the chip according to the instruction and starting the TX port to send valid data to the test machine is not fixed.

[0045] The prior art is to use the Match function and the pattern comparison method to complete the test item, and the detailed flow is shown in Figure 2 . Specifically, the tester performs the following operations: first, storing the expected output result pattern written in advance in the LVM, then confirming the valid data start bit returned by the TX through the Match function, then comparing the received valid data with the real-time BIT to confirm the termination bit, and finally confirming whether the chip successfully executes the instruction according to the comparison result.

[0046] However, this test method has the deficiencies pointed out in the background art.

[0047] Embodiment 1

[0048] In order to solve the deficiencies of the prior art, the present application proposes a new test method for testing the change of the working state of the UART chip, and the specific flow is shown in Figure 3 . This method does not need to design a special test board, and can not output the expected result pattern, so as to save the space use of the LVM of the tester, and facilitate the judgment of the reason why the instruction sent by the tester through the UART protocol is not successfully executed by the chip.

[0049] The specific implementation is as follows:

[0050] First, the tester sends an instruction to the RX port, and the format of the instruction data should conform to the data packet format of the protocol of the tested UART chip, otherwise the RX port cannot receive the instruction;

[0051] Further, the chip changes the working state of the chip according to the instruction received by the RX port;

[0052] Further, the chip returns the current working state of the chip through the TX port according to the instruction;

[0053] The specific method for the tester to receive the data returned by the TX port and determine the test result is as follows: setting the waiting time and the sampling time: according to the chip data manual, the shortest response time T1 and the longest response time T2 after the TX port receives the instruction can be obtained, after the instruction to the RX port is sent, the tester starts sampling the data sent by the TX port after waiting for a shortest response time T1, because the sampling of the tester is one-time, the sampled data cannot be monitored and compared in real time, all the sampled data is saved in the variable space applied by the host computer, and will not be stored in the LVM of the tester, and the variable space can be released after use. Therefore, we need to set a sampling time for the sampling of the tester. Because the baud rate of the UART is known, the transmission time of a bit of data can be calculated, and the size of the effective data sent by the TX port is also known, so the transmission time T3 of the effective data sent by the TX port can be calculated, and the sampling time is set to T2-T1+T3.

[0054] Setting the sampling period: set to 1 / N times of the time of transmitting one BIT of effective data of the UART, N>1, preferably, 8≤N≤16.

[0055] Data sampling: after the instruction to the RX port is sent, the tester does not operate within the T1 window; after T1, the tester starts sampling the data sent by the TX port according to the set sampling period and stores it, and ends the sampling after the sampling time T2-T1+T3; the above sampling is all sites parallel sampling at the same time, and does not need to design a special test board

[0056] Sampling data processing: extracting the stored data for processing, and converting the effective test data into characters. After the sampling is completed, the data in the variable space of the host computer at this time should be "a certain length of idle bits at the beginning" plus "effective test data". In the test program, an algorithm is written to extract the data in the variable space of the host computer for data processing. Because the UART communication protocol is not working, it is in "H", when it starts to work, the starting bit will become "L", therefore we compare the data obtained in each sampling period with "H" and "L", when N "L"s are obtained by continuous comparison, the data of the continuous N "L"s is the starting bit signal of the test data signal sent by the TX. The data after that is the test data of continuous N "H" or "L". N same "H" is one BIT 1, and N same "L" is one BIT 0, after conversion, the corresponding binary data can be determined, and the binary data is converted into characters through the coding rule (such as ASCII).

[0057] Sample data comparison: compare the obtained character with the expected output character, and if the expected result is met, it means that the chip successfully executes the instruction sent by the tester, and if the expected result is not met, it means that the chip does not successfully execute the instruction sent by the tester.

[0058] Failure reason judgment: when the test fails, compare the character with the error code to determine the reason why the chip does not successfully execute the instruction sent by the tester. The error code is preset during the design of the chip, and different codes are returned according to different types of errors when the chip fails to work normally.

[0059] After the test item indicating entering the specified working state is passed, the required test item in the working state can be tested, and the step is repeated: sending an instruction to change the working state of the chip through the UART protocol → passing the test item entering the working state → testing the required test item in the working state. For example, an instruction is sent through the UART protocol to make the chip enter the sleep working state, then the sleep current in the sleep working state is tested, if it passes the test, then an instruction is sent through the UART protocol to make the chip enter the wake up working state, and then the wake up current in the wake up working state is tested.

[0060] Until all the test items are tested, the test process ends. If all the test items in the above test process are passed, it means that the tested chip is qualified, otherwise it is not qualified.

[0061] Embodiment 2

[0062] A test system of a UART chip, used for executing the test method of the UART chip in embodiment 1.

[0063] The above describes the present application and its embodiments in a schematic manner, which is not limited, and the present application can be realized in other specific forms without departing from the spirit or essential characteristics of the present application. The embodiments shown in the drawings are only one of the embodiments of the present application, and the actual structure is not limited thereto, and any reference signs in the claims should not limit the claims involved. Therefore, if a person skilled in the art is inspired by it, without departing from the spirit of the present application, similar structural forms and embodiments can be designed without creativity, which should belong to the protection scope of the present patent. In addition, the word “comprising” does not exclude other elements or steps, and the word “one” before an element does not exclude “multiple” of the element. Multiple elements stated in the product claims can also be realized by software or hardware. The words “first”, “second” and the like are used to represent names, and do not represent any specific order.

Claims

1. A testing method for a UART chip, characterized in that, The method includes the following steps: The tester is connected to the UART chip: the tester's DPS resource channel is connected to the chip's VCC pin, the tester's GND resource channel is connected to the chip's GND pin, and the tester's two digital resource channels are connected to the chip's TX and RX pins; Connectivity test between the tester and the UART chip: The tester performs open and short circuit tests on the VCC, GND, TX and RX pins. If the open and short circuit test is passed, the connectivity between the tester and the UART chip under test is normal. Testing the UART chip: The tester switches the chip's operating state via commands, specifically including the following steps: Based on the chip datasheet, obtain the shortest response time T1 and longest response time T2 after the TX port receives the command; first, calculate the time required to transmit one bit of data based on the UART's baud rate, then combine this with the number of valid data bits sent by the TX port to calculate the transmission time T3 of the valid data sent by the TX port; the sampling period is 1 / N times the time it takes for the UART to transmit one valid data bit; after sending a command to the RX port, the tester waits for a shortest response time T1, then starts sampling and storing the data sent by the TX port according to the set sampling period, ending sampling after T2-T1+T3; the tester extracts and processes the stored data, converting the valid test data into characters; the tester compares the obtained characters with the expected output characters to determine whether the chip successfully executed the command and whether the chip entered the specified operating state; after a successful switch, test the required test items for the corresponding operating state of the UART chip; repeat this process until all test items for all operating states under test have been tested. If all the tests in the above testing process pass, the chip under test is qualified; otherwise, the chip is unqualified.

2. The testing method for a UART chip according to claim 1, characterized in that, It also includes a failure reason determination step: when the test fails, the character is compared with the error code to determine the reason why the instruction sent by the test machine was not successfully executed.

3. The testing method for a UART chip according to claim 2, characterized in that, The number of samples N within a valid data period of one bit is 8 ≤ N ≤ 16.

4. The testing method for a UART chip according to claim 3, characterized in that, After sampling the data sent by the TX port, the test machine saves the data in the variable space allocated by the host. The variable space is released after use.

5. The testing method for a UART chip according to claim 4, characterized in that, The specific data processing process is as follows: the data collected in each sampling period is compared with "H" and "L". When N consecutive "L"s are obtained, the data of these N consecutive "L"s is the start bit signal of the test data signal sent by TX. The subsequent data is the test data of N consecutive identical "H"s or "L". N identical "H"s are a BIT 1, and N identical "L"s are a BIT 0. After conversion, the corresponding binary data is determined, and then the binary data is converted into characters according to the encoding rules.

6. A testing method for a UART chip according to any one of claims 1 to 5, characterized in that, The testing machine simultaneously samples data from all dies that need to be tested.

7. A test system for a UART chip, used to perform a test method for a UART chip according to any one of claims 1 to 5.

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