Display panel and display terminal

Abstract

The present application discloses a display panel and a display terminal, comprising an array substrate, an opposing substrate, and a display medium layer sandwiched between the array substrate and the opposing substrate. The display panel also comprises a scanning drive circuit, a plurality of first signal lines, and a plurality of second signal lines. The plurality of first signal lines are arranged on the array substrate and connected to the scanning drive circuit. The first signal lines are used to transmit a scanning auxiliary signal to the scanning drive circuit. The scanning auxiliary signal is used to drive the scanning drive circuit to generate and output a scanning signal to control the pixel electrodes in the display panel to form an electric field. The plurality of second signal lines are arranged on the opposing substrate, wherein the plurality of first signal lines and the plurality of second signal lines are electrically connected in parallel in a one-to-one correspondence manner. By simultaneously arranging parallel signal lines on the array substrate and the opposing substrate, the line impedance can be effectively reduced, thereby reducing the heating of the line, and thus improving the driving capability.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display terminal. Background Art

[0002] The Gate Driver Less (GDL) technology uses the original array process of the LCD panel to manufacture the driving circuit of the horizontal scan line on the substrate around the display area, so that it can replace the external integrated circuit (IC) to complete the driving of the horizontal scan line. GDL technology can reduce the welding process of the external IC, making the LCD panel more suitable for the production of narrow-frame or borderless display products.

[0003] At present, since the GDL driving circuit has many lines, such as the clock signal line for transmitting the clock signal, the start signal line for transmitting the start signal, and the reset signal line for transmitting the reset signal, etc., due to the influence of the impedance in the signal line, the further the clock signal is transmitted, the more serious the signal attenuation is, which leads to signal instability and thus reduces the driving ability. Therefore, how to maintain the stability of the signal and improve the driving ability is an urgent problem to be solved. Summary of the invention

[0004] In view of the above-mentioned deficiencies in the prior art, the present application proposes a display panel and a display terminal that can effectively maintain signal stability.

[0005] The present application provides a display panel including an array substrate, an opposing substrate, and a display medium layer sandwiched between the array substrate and the opposing substrate, wherein an electric field is formed between the array substrate and the opposing substrate to drive the display medium layer to transmit light to perform image display. The display panel also includes a scanning drive circuit, a plurality of first signal lines, and a plurality of second signal lines, wherein the plurality of first signal lines are arranged on the array substrate and connected to the scanning drive circuit, the first signal lines are used to transmit a scanning auxiliary signal to the scanning drive circuit, the scanning auxiliary signal is used to drive the scanning drive circuit to generate and output a scanning signal, and the scanning signal is used to control the transmission of a data signal for image display to a pixel electrode in the display panel to form an electric field, and the plurality of second signal lines are arranged on the opposing substrate, wherein the plurality of first signal lines and the plurality of second signal lines are electrically connected in parallel in a one-to-one correspondence manner.

[0006] Optionally, the multiple first signal lines and the multiple second signal lines include multiple signal line groups, wherein one signal line group includes a first signal line and a second signal line that are arranged opposite each other along the thickness direction of the display panel, and the display panel also includes multiple first conductors and multiple second conductors. In one signal line group, the two ends of the first signal line and the second signal line are respectively connected to each other through a first conductor and a second conductor, so that a first signal line and a second signal line are electrically connected in parallel.

[0007] Optionally, the display panel also includes a timing control circuit, a plurality of first signal lines electrically connecting the timing control circuit and the scan drive circuit, the timing control circuit is used to output a scan auxiliary signal, and the scan auxiliary signal is transmitted to the scan drive circuit through a plurality of first conductors and a plurality of signal line groups.

[0008] Optionally, the display panel also includes a display area and a non-display area that are adjacent to each other, the display area includes pixel units arranged in an array for displaying images, and a plurality of first signal lines are arranged in the non-display area on both sides of the display area for transmitting a scanning auxiliary signal to a scanning drive circuit arranged in the non-display area, and the scanning drive circuit outputs a scanning signal based on the scanning auxiliary signal to control the pixel unit to receive a data signal for image display and perform image display.

[0009] Optionally, the display panel also includes a display area and a non-display area that are adjacent to each other, the display area includes pixel units arranged in an array for displaying images, and a plurality of first signal lines are arranged in the non-display area on one side of the display area for transmitting a scanning auxiliary signal to a scanning drive circuit arranged in the non-display area, and the scanning drive circuit outputs a scanning signal based on the scanning auxiliary signal to control the pixel unit to receive a data signal for image display and perform image display.

[0010] Optionally, the opposing substrate includes a common electrode, which is arranged at a position corresponding to the display area of ​​the opposing substrate, and is used to provide a common voltage for driving the display medium layer for the pixel unit, and the common voltage and the data signal in the pixel electrode form an electric field. Multiple second signal lines are arranged at positions corresponding to the non-display area of ​​the opposing substrate, and are used to be connected in parallel with the multiple first signal lines through the first conductor and the second conductor.

[0011] Optionally, the common electrode and the plurality of second signal lines are made of the same material and are manufactured in the same process.

[0012] Optionally, the display panel also includes multiple feedback lines, which are connected to multiple first conductors and a timing control circuit, and are used to detect the size of a scanning auxiliary signal transmitted in each signal line group and output a feedback signal to the timing control circuit. The timing control circuit adjusts the scanning auxiliary signal output to the signal line group based on the feedback signal so that the adjusted scanning auxiliary signal is within a preset range.

[0013] Optionally, the display panel also includes a data driving circuit, which is arranged in the non-display area, for receiving data control signals from multiple signal line groups and outputting data signals to pixel units based on the data control signals. The pixel units receive the data signals under the control of the scanning signals to perform image display.

[0014] The present application also discloses a display terminal, comprising a power module and the aforementioned display panel, wherein the power module is arranged on a side of the display panel away from the emitted light, and is used to provide a driving voltage for the display panel when displaying images.

[0015] Compared with the existing technical problems, the scanning auxiliary signals output by the timing control circuit are transmitted to the scanning driving circuit or other functional modules through the parallel first signal line and the second signal line, so that the impedance of the signal line can be reduced, thereby improving the stability of the scanning auxiliary signal, and the scanning auxiliary signal in the first signal line is detected and fed back through the second signal line, so that the output scanning auxiliary signal can be adjusted within a preset range, thereby improving the stability of the scanning auxiliary signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians, other drawings can be obtained based on these drawings without paying any creative work.

[0017] Figure 1 A schematic diagram of a display terminal provided in the first embodiment of the present application

[0018] Figure 2 for Figure 1 A schematic diagram of the side structure of the display panel;

[0019] Figure 3 for Figure 2 A schematic diagram of the plane layout of an array substrate in the display panel shown;

[0020] Figure 4 for Figure 3 Schematic diagram of the layout of the middle array substrate and the opposite substrate;

[0021] Figure 5 for Figure 4 A schematic diagram of the cross-sectional structure of the display panel is shown in FIG.

[0022] Figure 6 for Figure 4 A schematic diagram of the circuit layout of the array substrate;

[0023] Figure 7 for Figure 4 A schematic diagram of a circuit layout of another array substrate;

[0024] Figure 8 for Figure 4 Schematic diagram of circuit layout of the middle facing substrate;

[0025] Fig. 9 A schematic diagram of a circuit layout of a facing substrate provided in the second embodiment of the present application.

[0026] Reference numerals:

[0027] Display terminal-100, display panel-10, power supply module-20, supporting frame-30, display area-10a, non-display area-10b, m data lines-S1~Sm, n scan lines-G1~Gn, pixel unit-P, array substrate-10c, opposite substrate-10d, display medium layer-10e, timing control circuit-11, data driving circuit-12, scanning driving circuit-13, backlight module-17, first direction-F1, second direction-F2, horizontal synchronization signal-Hsyn, vertical synchronization signal-Vsyn, scanning control signal-Cg, data control signal-Cs, first signal line-L1, second signal line-L2, first conductor-14A, second conductor-14B, third conductor-14C, common electrode-Vcom, common electrode line-LM. DETAILED DESCRIPTION

[0028] In order to facilitate the understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thoroughly and comprehensively understood.

[0029] The following descriptions of the embodiments are with reference to the attached diagrams to illustrate specific embodiments that the present application can be used to implement. The serial numbers for the components herein, such as "first", "second", etc., are only used to distinguish the objects described and do not have any order or technical meaning. The "connection" and "coupling" mentioned in the present application, unless otherwise specified, include direct and indirect connections (couplings). The directional terms mentioned in the present application, such as "upper", "lower", "front", "back", "left", "right", "inside", "outside", "side", etc., are only with reference to the directions of the attached drawings. Therefore, the directional terms used are for better and clearer explanation and understanding of the present application, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation to the present application.

[0030] In the description of the present application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection; it can be directly connected, or indirectly connected through an intermediate medium, or it can be internal communication between two components. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances. It should be noted that the terms "first", "second", etc. in the specification, claims, and drawings of the present application are used to distinguish different objects, rather than to describe a specific order.

[0031] In addition, the terms "include", "may include", "contain", or "may include" used in the present application indicate the existence of the corresponding functions, operations, elements, etc. disclosed, and do not limit one or more other functions, operations, elements, etc. In addition, the terms "include" or "contain" indicate the existence of the corresponding features, numbers, steps, operations, elements, components, or combinations thereof disclosed in the specification, and do not exclude the existence or addition of one or more other features, numbers, steps, operations, elements, components, or combinations thereof, and are intended to cover non-exclusive inclusions. In addition, when describing the embodiments of the present application, "may" is used to indicate "one or more embodiments of the present application". And, the term "exemplary" is intended to refer to an example or illustration.

[0032] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0033] See also Figure 1 , Figure 1 This is a schematic diagram of the structure of a display terminal provided in the first embodiment of the present application. Figure 1 As shown, the display terminal 100 includes a display panel 10, a power module 20 and a support frame 30. The display panel 10 and the power module 20 are fixed to the support frame 30. The power module 20 is arranged on the back of the display panel 10, that is, the non-display surface of the display panel 10. The power module 20 is used to provide a driving voltage for the display panel 10 to display an image, and the support frame 30 provides a fixing and protection function for the display panel 10 and the power module 20. In other embodiments of the present application, the display terminal 100 may not need to be provided with a support frame 30, for example, it is a portable electronic device, such as a mobile phone, a tablet computer, etc.

[0034] See also Figure 2 , Figure 2 for Figure 1 Schematic diagram of the side structure of the display panel.

[0035] like Figure 2 As shown, the display panel 10 includes an array substrate (AS) 10c and an opposite substrate 10d, and a display medium layer 10e sandwiched between the array substrate 10c and the opposite substrate 10d. Driving elements are arranged on the array substrate 10c and the opposite substrate 10d to generate corresponding electric fields according to data signals (Data), thereby driving the display medium layer 10e to emit light of corresponding brightness to perform image display.

[0036] In an exemplary embodiment, the display panel 10 may be a liquid crystal display panel, that is, the display medium layer 10e is a liquid crystal molecule. In other embodiments of the present application, it may also be other types of display panels, which are not limited in the present application. In this embodiment, the driving elements may be a common electrode (not shown) disposed on the counter substrate 10d and a pixel electrode (not shown) disposed on the array substrate 10c.

[0037] Take the liquid crystal display panel as an example, in which the display medium layer 10e is liquid crystal molecules, and the liquid crystal molecules display images by deflecting and transmitting light of preset brightness. The display panel 10 also includes a backlight module 17 (BM), which is used to provide light for display to the display area 10a of the display panel 10. The display panel 10 emits corresponding light according to the image signal to be displayed to perform image display. Among them, the display panel 10 also includes other elements or components, such as a signal processor module and a signal sensing module.

[0038] Please also read Figure 3 , Figure 3 for Figure 2 FIG. 1 is a schematic diagram of the planar layout of the array substrate in the display panel. Figure 3As shown, the display panel 10 further includes a timing control circuit 11, a data driving circuit 12, and a scan driving circuit 13. The timing control circuit 11, the data driving circuit 12, and the scan driving circuit 13 are arranged in the non-display area 10b.

[0039] In the display area 10a of the display panel 10, m data lines (Source lines) S1 to Sm and n scan lines (Gate lines) G1 to Gn are arranged in a grid shape. The m data lines S1 to Sm extend along a first direction F1, and the n scan lines G1 to Gn extend along a second direction F2. The first direction F1 and the second direction F2 are perpendicular to each other. The intersections of the n scan lines G1 to Gn and the data lines S1 to Sm are all correspondingly provided with pixel units P.

[0040] The timing control circuit 11 receives an image signal representing image information, a horizontal synchronization signal Hsyn and a vertical synchronization signal Vsyn from an external signal source, and outputs a clock signal for controlling the scan drive circuit 13 , a scan control signal Cg, and a data control signal Cs for controlling the data drive circuit 12 .

[0041] The m data lines S1-Sm are connected to the data driving circuit 11 for receiving data signals stored and transmitted in the form of grayscale values ​​provided by the data driving circuit 12. The n scanning lines G1-Gn are connected to the scanning driving circuit 13 for receiving scanning signals from the scanning driving circuit 13.

[0042] Each pixel unit P includes at least one pixel electrode (not shown), which receives a data voltage of a grayscale value in a corresponding data signal provided by data lines S1 to Sm in a predetermined time period under the control of n scanning lines G1 to Gn. The pixel electrode loaded with the data voltage cooperates with the common electrode loaded with the common voltage to generate a corresponding driving electric field, and drives the display medium layer 10e to deflect a corresponding angle based on the electric field, so that the received backlight emits light of corresponding brightness according to the corresponding deflection angle, so as to achieve image display by emitting light of corresponding brightness according to the image signal.

[0043] The scan drive circuit 13 receives the scan control signal Cg output by the timing control circuit 11, and outputs the scan signal to each scan line G1 to Gn. The data drive circuit 12 receives the data control signal Cs output by the timing control circuit 11, and outputs the data signal for driving the element in each pixel unit P in the display area 10a to perform image display to each data line S1 to Sm. The data signal provided to the display panel 10 is a grayscale voltage in analog form. The scan drive circuit 13 outputs the scan signal to control the pixel unit P to receive the data signal output by the data drive circuit 12, so as to control the pixel unit P to display the corresponding image.

[0044] In this embodiment, the circuit elements in the scan driving circuit 13 and the pixel units P in the array substrate 10 c are manufactured in the array substrate 10 c in the same process, which is also the GOA (Gate Driver on Array) technology.

[0045] Please also read Figure 4 , Figure 4 for Figure 3 Schematic diagram of the layout of the array substrate and the opposing substrate.

[0046] like Figure 4 As shown, the display panel 10 further includes a plurality of first signal lines L1 and a plurality of second signal lines L2, wherein the plurality of first signal lines L1 are laid on the non-display area 10b of the array substrate 10c and connected to the scan drive circuit 13, and the first signal lines L1 are used to transmit a scan auxiliary signal to the scan drive circuit 13 to drive the scan drive circuit 13 to generate and output a scan signal. The plurality of second signal lines L2 are respectively laid on the opposite substrate 10d, wherein the plurality of second signal lines L2 are respectively electrically connected in parallel with the plurality of first signal lines L1 in a one-to-one correspondence manner.

[0047] The scanning auxiliary signal includes a clock signal, a start signal, a reset signal and a low-voltage electrical signal, that is, among the multiple first signal lines L1 and the second signal lines L2, some signal lines can be clock signal lines for transmitting clock signals, or can be start signal lines for transmitting start signals, or can be reset signal lines for transmitting reset signals to the scanning drive circuit 13 and other functional modules.

[0048] The display panel 10 further includes a plurality of first conductors 14A and a plurality of second conductors 14B, wherein one first conductor 14A and one second conductor 14B are respectively disposed at both ends of a first signal line L1 and a second signal line L2 for connecting a first signal line L1 and a second signal line L2 in parallel.

[0049] The array substrate 10c further includes a plurality of common electrode lines LM and a plurality of third conductors 14C, each common electrode line LM is connected to the third conductors 14C at both ends, and is connected to the common electrode Vcom in the opposite substrate 10d through the third conductors 14C, for transmitting a common voltage to the common electrode Vcom. The common voltage in the common electrode Vcom and the pixel voltage in the pixel unit form an electric field, which is used to drive the liquid crystal molecules in the display medium layer 10e to deflect and emit light of a preset brightness, thereby performing image display.

[0050] Please also read Figure 5 , Figure 5 for Figure 4 A schematic diagram of the cross-sectional structure of the display panel is shown in FIG.

[0051] like Figure 5 As shown, the plurality of first signal lines L1 and the plurality of second signal lines L2 include a plurality of signal line groups, that is, the plurality of first signal lines L1 and the plurality of second signal lines L2 may form a plurality of signal line groups, wherein one signal group includes one first signal line L1 and one second signal line L2 which are arranged opposite to each other along the thickness direction of the display panel 10. In one signal line group, both ends of the first signal line L1 and the second signal line L2 are connected respectively through a first conductor 14A and a second conductor 14B, so that one first signal line L1 and one second signal line L2 are electrically connected in parallel.

[0052] In an exemplary embodiment, the conductor 14 may be a conductive gold ball (Au dot), or may be other conductive bodies as required, which is not limited in the present application.

[0053] See also Figure 6 , Figure 6 for Figure 4 Schematic diagram of the circuit layout of the array substrate.

[0054] like Figure 6 As shown, a plurality of first signal lines L1 and a plurality of common electrode lines LM are laid along the first direction F1 in the non-display area 10b on both sides of the display area 10a, and the scan drive circuits 13 are respectively arranged in the non-display area 10b on both sides of the display area 10a. The plurality of first signal lines L1 are connected to the scan drive circuit 13 and the timing control circuit 11, and are used to receive the scan auxiliary signal from the timing control circuit 11, and transmit it to the scan drive circuit 13 through the plurality of first conductors 14A and the plurality of signal line groups to drive the scan drive circuit 13 to output the scan signal to the pixel unit P in the display area 10a, and the pixel unit P receives the data signal under the control of the scan signal. The two ends of the common electrode line LM are respectively connected to the third conductor 14C, and are connected to the common electrode Vcom in the opposite substrate 10d through the third conductor 14C, and are used to transmit the common voltage to the common electrode Vcom. The pixel electrode (not shown) in the pixel unit P forms an electric field according to the data signal and the common voltage in the common electrode Vcom to drive the liquid crystal molecules in the display medium layer 10e to deflect and emit light of a preset grayscale, thereby performing image display.

[0055] Among them, the first signal lines L1 are connected to the timing control circuit 11 through the first conductor 14A at one end adjacent to the timing control circuit 11, and are used to receive the scan auxiliary signal from the timing control circuit 11 and transmit it to the scan drive circuit 13 and other functional modules, and the first signal line L1 is connected to the second conductor 14B at one end away from the timing control circuit 11. The two ends of the second signal line L2 disposed in the opposite substrate 10d are respectively connected to the first conductor 14A and the second conductor 14B, and are used to be connected in parallel with the first signal line L1.

[0056] See also Figure 7 , Figure 7 for Figure 4 A schematic diagram of the circuit layout of another array substrate.

[0057] like Figure 7 As shown, a plurality of first signal lines L1 and a plurality of common electrode lines LM are laid along a first direction F1 in a non-display area 10b on one side of a display area 10a, respectively. A scan drive circuit 13 and a plurality of first signal lines L1 are arranged in the non-display area 10b on the same side of the display area 10a, that is, a plurality of first signal lines L1 are arranged adjacent to the scan drive circuit 13. The plurality of first signal lines L1 are connected to the timing control circuit 11 and the scan drive circuit 13, and are used to receive a scan auxiliary signal from the timing control circuit 11, and transmit the signal to the scan drive circuit 13 through a plurality of first conductors 14A and a plurality of signal line groups to drive the scan drive circuit 13 to output a scan signal to a pixel unit P in the display area 10a, and the pixel unit P receives a data signal under the control of the scan signal. Both ends of the common electrode line LM are respectively connected to the third conductor 14C, and are connected to the common electrode Vcom in the opposite substrate 10d through the third conductor 14C, and are used to transmit a common voltage to the common electrode Vcom. The pixel electrode (not shown) in the pixel unit P forms an electric field according to the data signal and the common voltage in the common electrode Vcom to drive the liquid crystal molecules in the display medium layer 10e to deflect and emit light of a preset grayscale, thereby performing image display.

[0058] Among them, a plurality of first signal lines L1 are connected to the timing control circuit 11 through the first conductor 14A at one end adjacent to the timing control circuit 11, and are used to receive the scan auxiliary signal from the timing control circuit 11 and transmit it to the scan drive circuit 13 and other functional modules, and the first signal line L1 is connected to the second conductor 14B at one end away from the timing control circuit 11. The two ends of the second signal line L2 disposed in the opposite substrate 10d are respectively connected to the first conductor 14A and the second conductor 14B, and are used to be connected in parallel with the first signal line L1. That is, the timing control circuit 11 transmits the scan auxiliary signal and the like to the scan drive circuit 13 and other functional modules through a plurality of signal line groups.

[0059] Please also read Figure 8 , Figure 8 for Figure 4 Schematic diagram of the circuit layout of the opposing substrate.

[0060] like Figure 8As shown, the counter substrate 10d includes a plurality of second signal lines L2 and a common electrode Vcom, wherein the plurality of second signal lines L2 are laid along the first direction F1 at positions corresponding to the non-display area 10b in the counter substrate 10d, and are respectively connected in parallel with the plurality of first signal lines L1 through the first conductor 14A and the second conductor 14B, that is, they are respectively arranged in a one-to-one correspondence with the plurality of first signal lines L1. The common electrode Vcom is connected to the common electrode line LM arranged in the array substrate 10c through the third conductor 14C, and is used to receive a common voltage from the plurality of common electrode lines LM, and is used to drive the liquid crystal molecules to deflect to emit light in conjunction with the data signal in the pixel unit, thereby performing image display. The common electrode Vcom is a transparent electrode arranged at a position corresponding to the display area 10a in the counter substrate 10d. The multiple second signal lines L2 and the common electrode Vcom are made of the same conductive material and in the same process. In other words, the multiple second signal lines L2 are formed by cutting the material used to make the common electrode Vcom. The multiple second signal lines L2 are independent of each other and are not connected to the common electrode Vcom.

[0061] Among them, the second signal line L2 is connected to the first conductor 14A at one end adjacent to the timing control circuit 11, and is connected to the second conductor 14B at one end away from the timing control circuit 11, so that the second signal line L2 is connected in parallel with the first signal line L1 through the first conductor 14A and the second conductor 14B arranged on both sides.

[0062] When the timing control circuit 11 outputs a scan auxiliary signal, it can be transmitted to the scan drive circuit 13 or other functional modules through the parallel first signal line L1 and the second signal line L2 at the same time, so that the scan auxiliary signal output by the timing control circuit 11 can be transmitted through the two parallel signal lines to reduce the impedance of the signal line, thereby maintaining the stability of the scan auxiliary signal, and due to the reduction in impedance, the heat generation of the first signal line and the second signal line is further reduced, the influence of line heating on the liquid crystal is reduced, and the display effect is improved. At the same time, the heat dissipation of the signal line through the substrates on both sides, that is, the heat dissipation of the signal line through the array substrate 10c and the opposite substrate 10d can also effectively improve the overall heat dissipation capacity of the display panel, thereby improving the driving capacity of the scan drive circuit 13.

[0063] See also Fig. 9 , Fig. 9 A schematic diagram of a circuit layout of a facing substrate provided in the second embodiment of the present application. Fig. 9As shown, the opposing substrate 10d includes multiple control units FC, multiple second signal lines L2 and a common electrode Vcom, wherein the multiple second signal lines L2 are respectively laid along the first direction F1 at positions corresponding to the non-display area 10b in the opposing substrate 10d, the second signal lines L2 are connected to the second conductor 14B, and are connected to the first conductor 14A via the control unit FC, and the control unit FC is used to control the conduction and disconnection between the second signal lines L2 and the first conductor 14A.

[0064] The timing control circuit 11 is connected to the plurality of first conductors 14A and the plurality of control units FC respectively. When the control unit FC controls the second signal line L2 to be conductive with the first conductor 14A, the second signal line L2 is connected in parallel with the first signal line L1 between the first conductor 14A and the second conductor 14B. The second signal line L2 is connected to the first conductor 14A at one end adjacent to the timing control circuit 11, and is connected to the second conductor 14B at one end away from the timing control circuit 11, so that the second signal line L2 is connected in parallel with the first signal line L1 through the first conductor 14A and the second conductor 14B disposed on both sides.

[0065] When the control unit FC controls the second signal line L2 to be disconnected from the first conductor 14A, the second signal line L2 is connected between the second conductor 14B and the control unit FC, and is connected to the timing control circuit 11 through the control unit FC, wherein the first signal line L1, the second conductor 14B, the second signal line L2 and the control unit FC are connected in series in sequence. At this time, the second signal line L2 is a feedback signal line, which is used to receive a feedback signal from the second conductor 14B and transmit it to the timing control circuit 11 through the control unit FC, wherein the feedback signal is used to characterize the size of the scanning auxiliary signal and the potential maintenance time, and the timing control circuit 11 adjusts the output scanning auxiliary signal to be within a preset range according to the feedback signal. Among them, the potential of the scanning auxiliary signal can be adjusted within the preset range, and the output duration of the scanning auxiliary signal can be adjusted within the preset range. When the scanning auxiliary signal is within the preset range, the image display effect of the pixel unit P is in a better state.

[0066] The common electrode Vcom is connected to the common electrode line LM disposed in the array substrate 10c through the third conductor 14C, and is used to receive a common voltage from the plurality of common electrode lines LM, and is used to drive the liquid crystal molecules to deflect to emit light in coordination with the data signal in the pixel unit, thereby performing image display. The common electrode Vcom is a transparent electrode disposed at a position corresponding to the display area 10a in the counter substrate 10d. The plurality of second signal lines L2 and the common electrode Vcom are made of the same conductive material and in the same process. In other words, the plurality of second signal lines L2 are formed by cutting the material for making the common electrode Vcom, and the plurality of second signal lines L2 are independent of each other and are not connected to the common electrode Vcom.

[0067] In addition, the scan auxiliary signal in the first signal line is detected through the second signal line L2 and a feedback signal is transmitted to the timing control circuit 11. The timing control circuit 11 adjusts the output clock signal and other signals according to the feedback signal to be within a preset range, thereby improving the stability of the clock signal and other signals, thereby improving the driving capability of the scan drive circuit.

[0068] It should be understood that the application of the present invention is not limited to the above examples. For ordinary technicians in this field, improvements or changes can be made based on the above description. All these improvements and changes should fall within the scope of protection of the claims attached to the present invention.

Claims

1. A display panel, comprising an array substrate, an opposite substrate, and a display medium layer sandwiched between the array substrate and the opposite substrate, wherein an electric field is formed between the array substrate and the opposite substrate to drive the display medium layer to transmit light to perform image display; It is characterized in that The display panel further includes a scan drive circuit, a plurality of first signal lines and a plurality of second signal lines, wherein the plurality of first signal lines are arranged on the array substrate and connected to the scan drive circuit, the first signal lines are used to transmit a scan auxiliary signal to the scan drive circuit, the scan auxiliary signal is used to drive the scan drive circuit to generate and output a scan signal, the scan signal is used to control the data signal for image display to be transmitted to the pixel electrode in the display panel to form the electric field, and the plurality of second signal lines are arranged on the counter substrate, wherein the plurality of first signal lines and the plurality of second signal lines are electrically connected in parallel in a one-to-one correspondence manner, The display panel further includes a plurality of control units, a plurality of first conductors and a plurality of second conductors, wherein the first signal line is connected between the first conductors and the second conductors, the second signal line is connected to the second conductors and connected to the first conductors via the control unit, and the control unit is used to control the conduction and disconnection between the second signal line and the first conductors; When the control unit controls the second signal line to be conductive with the first conductor, the second signal line is connected in parallel with the first signal line between the first conductor and the second conductor; when the control unit controls the second signal line to be disconnected from the first conductor, the second signal line is connected between the second conductor and the control unit, and the first signal line, the second conductor, the second signal line and the control unit are connected in series in sequence.

2. The display panel according to claim 1, wherein: The multiple first signal lines and the multiple second signal lines include multiple signal line groups, wherein one of the signal line groups includes one of the first signal lines and one of the second signal lines that are arranged opposite to each other along the thickness direction of the display panel, and when the control unit controls the second signal line to be conductive with the first conductor, in one of the signal line groups, the two ends of the first signal line and the second signal line are respectively connected through one of the first conductors and one of the second conductors, so that one of the first signal lines and one of the second signal lines are electrically connected in parallel.

3. The display panel according to claim 2, wherein: The display panel also includes a timing control circuit, which is respectively connected to the multiple first conductors and the multiple control units. The multiple first signal lines are electrically connected to the scan drive circuit and are electrically connected to the timing control circuit via the multiple first conductors. The timing control circuit is used to output the scan auxiliary signal through the multiple first conductors. When the control unit controls the second signal line to be connected to the first conductor, the scan auxiliary signal is transmitted to the scan drive circuit via the multiple first conductors and the multiple signal line groups. When the control unit controls the second signal line to be disconnected from the first conductor, the scan auxiliary signal is transmitted to the scan drive circuit via the multiple first conductors and the multiple first signal lines.

4. The display panel according to claim 3, wherein: When the control unit controls the second signal line to be disconnected from the first conductor, the second signal line receives a feedback signal from the second conductor and transmits it to the timing control circuit via the control unit. The timing control circuit adjusts the scan auxiliary signal to be within a preset range according to the feedback signal.

5. The display panel according to claim 4, wherein: The display panel also includes a display area and a non-display area that are adjacent to each other. The display area includes pixel units arranged in an array for displaying images. The plurality of first signal lines are arranged in the non-display areas on both sides of the display area for transmitting the scan auxiliary signal to the scan drive circuit arranged in the non-display area. The scan drive circuit outputs a scan signal based on the scan auxiliary signal to control the pixel unit to receive a data signal for image display and perform image display.

6. The display panel according to claim 4, wherein: The display panel also includes a display area and a non-display area that are adjacent to each other. The display area includes pixel units arranged in an array for displaying images. The plurality of first signal lines are arranged in the non-display area on one side of the display area for transmitting the auxiliary scanning signal to the scanning driving circuit arranged in the non-display area. The scanning driving circuit outputs a scanning signal based on the auxiliary scanning signal to control the pixel unit to receive the data signal for image display and perform image display.

7. The display panel according to claim 5 or 6, characterized in that: The opposing substrate includes a common electrode, which is arranged at a position of the opposing substrate corresponding to the display area, and is used to provide a common voltage for driving the display medium layer for the pixel unit, and the common voltage and the data signal in the pixel electrode form the electric field. The multiple second signal lines are arranged at positions of the opposing substrate corresponding to the non-display area, and are used to be connected in parallel with the multiple first signal lines through the first conductor and the second conductor.

8. The display panel according to claim 7, wherein: The common electrode and the plurality of second signal lines are made of the same material and are manufactured in the same process.

9. A display terminal, characterized in that: It comprises a power supply module and a display panel as described in any one of claims 1 to 8, wherein the power supply module is arranged on a side of the display panel away from the outgoing light, and is used to provide a driving voltage for the display panel when displaying images.

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