Low voltage drop linear regulator circuit, circuit board, low voltage drop linear regulator

Abstract

The present application discloses a low-voltage-difference linear voltage regulator circuit, a circuit board, and a low-voltage-difference linear voltage regulator, and relates to the field of electronic circuit technology. During the operation of the circuit, the compensation subcircuit is used to compensate the load subcircuit according to the comparison result. The current mirror is used to sample the current flowing through the first field-effect transistor, so the voltage at the output end of the current mirror is close to the voltage of the drain of the first field-effect transistor. Since one end of the compensation capacitor is connected to the drain of the first field-effect transistor and the other end is connected to the output end of the current mirror, the voltage difference between the two ends of the compensation capacitor is small, so that the compensation capacitor can work normally and play a compensation role. Therefore, the present application can use the compensation capacitor as the compensation capacitor, reduce the occupied area of ​​the circuit compensation capacitor, thereby reducing the area of ​​the chip, reducing the cost, and is conducive to the miniaturization of the equipment.

Description

Technical Field

[0001] The present application relates to the technical field of electronic circuits, and in particular to a low voltage difference linear voltage regulator circuit, a circuit board, and a low voltage difference linear regulator. Background Art

[0002] With the rapid development of industrial control, communications, automotive electronics, aerospace, and other fields, the power requirements of various devices are constantly increasing. High voltage and high current have become an inevitable trend in industrial development. How to ensure the stability of low dropout regulator (LDO) systems in high voltage and high current applications has become an important research topic.

[0003] To ensure that NMOS LDOs output stable voltage under various load conditions, the system loop needs to be compensated. In related technologies, capacitors with higher withstand voltage values ​​are used as compensation capacitors in high-voltage and high-current applications. However, capacitors with higher withstand voltage values ​​occupy a larger chip area, thereby increasing the circuit area and hindering device miniaturization. Summary of the Invention

[0004] The present application aims to solve at least one of the technical problems existing in the prior art. To this end, the present application proposes a low-dropout linear voltage regulator circuit, a circuit board, and a low-dropout linear voltage regulator that can use capacitors with lower withstand voltages as compensation capacitors, thereby reducing the area occupied by the compensation capacitors and thus reducing the chip area, which is conducive to device miniaturization.

[0005] In a first aspect, an embodiment of the present application provides a low voltage dropout linear voltage regulator circuit, comprising:

[0006] load subcircuit;

[0007] a voltage regulation subcircuit, the voltage regulation subcircuit comprising a first field-effect transistor and a first current source, wherein the gate of the first field-effect transistor is connected to the output end of the first current source, the source of the first field-effect transistor is connected to the load subcircuit, and the drain of the first field-effect transistor is connected to the input voltage;

[0008] an error amplifying subcircuit, the error amplifying subcircuit being connected to a reference voltage and further connected to the load subcircuit, the error amplifying subcircuit being configured to sample an output voltage of the load subcircuit to obtain a sampled voltage, and to compare the reference voltage with the sampled voltage to obtain a comparison result;

[0009] a compensation subcircuit, the compensation subcircuit being configured to compensate the load subcircuit according to the comparison result, the compensation subcircuit comprising a current mirror, a compensation capacitor, a second field-effect transistor M2, a third field-effect transistor M3, and a second current source, wherein the gate of the third field-effect transistor is connected to the output of the error amplification subcircuit, the source of the third field-effect transistor is grounded, and the drain of the third field-effect transistor is connected to the output of the second current source; the input of the second current source is connected to the drain of the first field-effect transistor; the drain of the second field-effect transistor is connected to the drain of the first field-effect transistor, the gate of the second field-effect transistor is connected to the gate of the first field-effect transistor, and the source of the second field-effect transistor is connected to the input of the current mirror; one end of the compensation capacitor is connected to the drain of the first field-effect transistor, and the other end is connected to the output of the current mirror;

[0010] A super source follower, the output end of the current mirror is connected to the super source follower; the super source follower is connected to the gate of the first field effect tube, and the super source follower is used to adjust the voltage of the gate of the first field effect tube.

[0011] The low-voltage-dropout linear voltage regulator circuit according to the embodiment of the present application has at least the following beneficial effects: when the output voltage of the load subcircuit changes, the error amplification subcircuit is used to compare the reference voltage with the sampled voltage to obtain a comparison result, and the super source follower is used to adjust the voltage of the gate of the first field-effect transistor according to the voltage change of the drain of the third field-effect transistor, thereby adjusting the output voltage of the load subcircuit to reduce the change in the output voltage. During circuit operation, the compensation subcircuit is used to compensate the load subcircuit according to the comparison result. The current mirror is used to sample the current flowing through the first field-effect transistor, so that the voltage at the output end of the current mirror is close to the voltage of the drain of the first field-effect transistor. Since one end of the compensation capacitor is connected to the drain of the first field-effect transistor and the other end is connected to the output end of the current mirror, the voltage difference between the two ends of the compensation capacitor is small. Therefore, a capacitor with a lower withstand voltage can be used as the compensation capacitor, reducing the area occupied by the compensation capacitor, thereby reducing the area of ​​the chip and facilitating device miniaturization.

[0012] According to some embodiments of the first aspect of the present application, the current mirror includes a fourth field-effect transistor, a fifth field-effect transistor, a sixth field-effect transistor, and a seventh field-effect transistor, the drain of the fourth field-effect transistor serves as the input end of the current mirror, the drain of the fourth field-effect transistor is connected to the gate of the fourth field-effect transistor and the gate of the fifth field-effect transistor, and the source of the fourth field-effect transistor is grounded; the source of the fifth field-effect transistor is grounded, and the drain of the fifth field-effect transistor is connected to the drain of the sixth field-effect transistor; the source of the sixth field-effect transistor is connected to the source of the first field-effect transistor, the gate of the sixth field-effect transistor is connected to the drain of the sixth field-effect transistor and the gate of the seventh field-effect transistor, the source of the seventh field-effect transistor is connected to the source of the first field-effect transistor, and the drain of the seventh field-effect transistor serves as the output end of the current mirror.

[0013] According to some embodiments of the first aspect of the present application, the compensation sub-circuit further includes a first resistor, one end of which is connected to the output end of the current mirror, and the other end of which is connected to the source of the first field effect transistor.

[0014] According to some embodiments of the first aspect of the present application, the super source follower includes an eighth field effect transistor, a ninth field effect transistor and a third current source, the source of the eighth field effect transistor is connected to the gate of the first field effect transistor, the gate of the eighth field effect transistor is connected to the drain of the third field effect transistor, the drain of the eighth field effect transistor is connected to the input end of the third current source, and the output end of the third current source is grounded; the gate of the ninth field effect transistor is connected between the input end of the third current source and the drain of the eighth field effect transistor, the source of the ninth field effect transistor is connected to the gate of the first field effect transistor, and the source of the ninth field effect transistor is grounded.

[0015] According to some embodiments of the first aspect of the present application, the error amplification sub-circuit includes a second resistor, a third resistor and an operational amplifier, one end of the second resistor is connected to the load sub-circuit, the other end of the second resistor is grounded through the third resistor, the positive input end of the operational amplifier is connected between the second resistor and the third resistor, the reverse input end of the operational amplifier is connected to the reference voltage, and the output end of the operational amplifier serves as the output end of the error amplification sub-circuit.

[0016] According to some embodiments of the first aspect of the present application, the error amplification sub-circuit further includes a fourth resistor and a first capacitor, one end of the fourth resistor is connected to the output end of the operational amplifier, and the other end of the fourth resistor is grounded through the first capacitor.

[0017] According to some embodiments of the first aspect of the present application, the load sub-circuit includes a load capacitor and a load resistor, one end of the load resistor is grounded, and the other end is connected to the source of the first field-effect transistor, and the load capacitor is connected in parallel with the load resistor.

[0018] According to some embodiments of the first aspect of the present application, the voltage regulation subcircuit further includes a charge pump connected to an input end of the first current source.

[0019] In a second aspect, an embodiment of the present application provides a circuit board comprising a low voltage difference linear voltage regulator circuit as described in any embodiment of the first aspect.

[0020] In a third aspect, an embodiment of the present application provides a low voltage dropout linear regulator, comprising the circuit board as described in the embodiment of the second aspect.

[0021] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become obvious from the description below, or will be learned through practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The present application is further described below with reference to the accompanying drawings and embodiments, wherein:

[0023] Figure 1 Schematic diagram of a low voltage difference linear voltage regulator circuit according to an embodiment of the present application;

[0024] Figure 2 A small signal equivalent circuit diagram of the compensation sub-circuit according to an embodiment of the present application;

[0025] Figure 3 for Figure 1 The equivalent circuit diagram of the super source follower is shown;

[0026] Figure 4 yes Figure 3 The small signal equivalent circuit diagram of the circuit shown;

[0027] Figure 5 1 is a gain change curve of the low voltage difference linear voltage regulator circuit under light load according to an embodiment of the present application;

[0028] Figure 6 This is a phase change curve of the low voltage difference linear voltage regulator circuit under light load according to an embodiment of the present application;

[0029] Figure 7 1. The gain variation curve of the low voltage difference linear voltage regulator circuit of the embodiment of the present application when the poles coincide;

[0030] Figure 8 The phase change curve of the low voltage difference linear voltage regulator circuit of the embodiment of the present application when the poles coincide;

[0031] Figure 9 1 is a gain change curve of the low voltage difference linear voltage regulator circuit under heavy load according to an embodiment of the present application;

[0032] Figure 10 1 is a phase change curve of the low voltage difference linear voltage regulator circuit under heavy load according to an embodiment of the present application.

[0033] Reference numerals:

[0034] Voltage regulation subcircuit 100; error amplifier subcircuit 200; compensation subcircuit 300; super source follower 400; load subcircuit 500; first field effect transistor M1; second field effect transistor M2; third field effect transistor M3; fourth field effect transistor M4; fifth field effect transistor M6; sixth field effect transistor M7; seventh field effect transistor M8; eighth field effect transistor M10; ninth field effect transistor M9; compensation capacitor C4; first resistor R4; second resistor R1; third resistor R2; operational amplifier EA_STEP1; first current source A1; second current source A2; third current source A3; load resistor R L ; Load capacitance C O ; fourth resistor R3; first capacitor C3. DETAILED DESCRIPTION

[0035] The following describes in detail embodiments of the present application. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application and are not to be construed as limiting the present application.

[0036] In the description of this application, it should be understood that descriptions involving orientations, such as up, down, front, back, left, right, etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, they cannot be understood as limitations on this application.

[0037] In the description of this application, "several" means more than one, "plurality" means more than two, "greater than," "less than," and "exceed" are understood to exclude the number itself, while "above," "below," and "within" are understood to include the number itself. The use of "first" and "second" in the description is solely for the purpose of distinguishing technical features and should not be construed as indicating or implying relative importance, implicitly specifying the number of the indicated technical features, or implicitly specifying the order of the indicated technical features.

[0038] In the description of this application, unless otherwise clearly defined, terms such as setting, installing, and connecting should be understood in a broad sense, and technicians in the relevant technical field can reasonably determine the specific meanings of the above terms in this application based on the specific content of the technical solution.

[0039] In the description of this application, reference to the terms "one embodiment," "some embodiments," "illustrative embodiments," "examples," "specific examples," or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of this application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in any appropriate manner in any one or more embodiments or examples.

[0040] In order to ensure that the NMOS type LDO outputs a stable voltage under various load conditions, it is necessary to use a compensation capacitor to compensate the system loop. In high voltage and high current applications, the low voltage difference linear voltage regulator circuit in the related art usually has one end of the compensation capacitor grounded and the other end connected to a high voltage. Therefore, it can only withstand capacitors with higher voltage values. Due to process limitations, the capacitance per unit area of ​​high voltage capacitors is very small, and the required area will be very large. Therefore, under the same capacitance requirements, high voltage capacitors will occupy a larger area of ​​the chip, thereby increasing the circuit area, increasing production costs, and being unfavorable for device miniaturization. Based on this, the embodiments of the present application provide a low voltage difference linear voltage regulator circuit, a circuit board, and a low voltage difference linear regulator, which can use a compensation capacitor as a compensation capacitor, reduce the area occupied by the circuit compensation capacitor, thereby reducing the area of ​​the chip, reducing costs, and being conducive to device miniaturization.

[0041] First, refer to Figure 1 , an embodiment of the present application provides a low voltage difference linear voltage regulator circuit, comprising:

[0042] load subcircuit 500;

[0043] The voltage regulation subcircuit 100 includes a first field effect transistor M1 and a first current source A1. The gate of the first field effect transistor M1 is connected to the output terminal of the first current source A1. The source of the first field effect transistor M1 is connected to the load subcircuit 500. The drain of the first field effect transistor M1 is connected to the input voltage.

[0044] The error amplifier subcircuit 200 is connected to a reference voltage and is also connected to the load subcircuit 500. The error amplifier subcircuit 200 is used to sample the output voltage of the load subcircuit 500 to obtain a sampled voltage, and to compare the reference voltage with the sampled voltage to obtain a comparison result.

[0045] The compensation subcircuit 300 is used to compensate the load subcircuit 500 based on the comparison result. The compensation subcircuit 300 includes a current mirror, a compensation capacitor C4, a second field-effect transistor M2M2, a third field-effect transistor M3M3, and a second current source A2. The gate of the third field-effect transistor M3 is connected to the output of the error amplifier subcircuit 200, the source of the third field-effect transistor M3 is grounded, and the drain of the third field-effect transistor M3 is connected to the output of the second current source A2; the input of the second current source A2 is connected to the drain of the first field-effect transistor M1; the drain of the second field-effect transistor M2 is connected to the drain of the first field-effect transistor M1, the gate of the second field-effect transistor M2 is connected to the gate of the first field-effect transistor M1, and the source of the second field-effect transistor M2 is connected to the input of the current mirror; one end of the compensation capacitor C4 is connected to the drain of the first field-effect transistor, and the other end is connected to the output of the current mirror;

[0046] A super source follower 400 (SSF) is connected to the output end of the current mirror; the super source follower 400 is connected to the gate of the first field effect transistor M1, and the super source follower 400 is used to adjust the voltage of the gate of the first field effect transistor M1.

[0047] According to the low-voltage-dropout linear voltage regulator circuit of the embodiment of the present application, when the output voltage of the load subcircuit 500 changes, the error amplifier subcircuit 200 is used to compare the reference voltage with the sampled voltage to obtain a comparison result. The super source follower 400 is used to adjust the gate voltage of the first field-effect transistor M1 based on the voltage change of the drain of the third field-effect transistor M3, thereby adjusting the output voltage of the load subcircuit 500 to reduce the change in the output voltage. During circuit operation, the compensation subcircuit 300 is used to compensate the load subcircuit 500 based on the comparison result. The current mirror is used to sample the current flowing through the first field-effect transistor M1. Therefore, the voltage at the output end of the current mirror is close to the voltage at the drain of the first field-effect transistor M1. Since one end of the compensation capacitor C4 is connected to the drain of the first field-effect transistor and the other end is connected to the output end of the current mirror, the voltage difference between the two ends of the compensation capacitor C4 is small, allowing the compensation capacitor C4 to operate normally and play a compensation role. Therefore, the present application can adopt the compensation capacitor C4 as the compensation capacitor C4, reducing the occupied area of ​​the circuit compensation capacitor C4, thereby reducing the area of ​​the chip, reducing costs, and facilitating the miniaturization of the device.

[0048] Specifically, when the output voltage of the load sub-circuit 500 increases, the error amplifier sub-circuit 200 is used to compare the reference voltage with the sampled voltage to obtain a comparison result, and the super source follower 400 is used to adjust the gate voltage of the first field effect transistor M1 based on the voltage change at the drain of the third field effect transistor M3, so as to reduce the gate voltage of the first field effect transistor M1, thereby reducing the current flowing through the first field effect transistor M1, and thus reducing the output voltage of the load sub-circuit 500. When the output voltage of the load sub-circuit 500 decreases, the error amplifier sub-circuit 200 is used to compare the reference voltage with the output voltage of the load sub-circuit 500 to obtain a comparison result, and the super source follower 400 is used to adjust the gate voltage of the first field effect transistor M1 based on the voltage change at the drain of the third field effect transistor M3, so as to increase the gate voltage of the first field effect transistor M1, thereby increasing the current flowing through the first field effect transistor M1, and thus regulating the output voltage of the load sub-circuit 500.

[0049] It should be noted that, in some embodiments of the present application, the withstand voltage of the compensation capacitor C4 is 5V to 6V, for example, 5V, 5.5V, or 6V. It should be noted that the withstand voltage of the compensation capacitor C4 of 5V to 6V is only an example and is not to be construed as limiting the present application. Those skilled in the art can set the withstand voltage of the voltage capacitor according to actual needs.

[0050] It can be understood that the current mirror includes a fourth field-effect transistor M4, a fourth field-effect transistor M6, a sixth field-effect transistor M7, and a seventh field-effect transistor M8, the drain of the fourth field-effect transistor M4 serves as the input end of the current mirror, the drain of the fourth field-effect transistor M4 is connected to the gate of the fourth field-effect transistor and the gate of the fourth field-effect transistor M6, and the source of the fourth field-effect transistor M4 is grounded; the source of the fourth field-effect transistor M6 is grounded, and the drain of the fourth field-effect transistor M6 is connected to the drain of the sixth field-effect transistor M7; the source of the sixth field-effect transistor M7 is connected to the source of the first field-effect transistor M1, the gate of the sixth field-effect transistor M7 is connected to the drain of the sixth field-effect transistor M7 and the gate of the seventh field-effect transistor M8, the source of the seventh field-effect transistor M8 is connected to the source of the first field-effect transistor M1, and the drain of the seventh field-effect transistor M8 serves as the output end of the current mirror.

[0051] It is understandable that the compensation sub-circuit 300 further includes a first resistor R4 , one end of the first resistor R4 is connected to the output end of the current mirror, and the other end of the first resistor R4 is connected to the source of the first field effect transistor M1 .

[0052] It is worth noting that, referring to Figure 1The first field-effect transistor M1, the second field-effect transistor M2, the third field-effect transistor M3, the fourth field-effect transistor M4, and the fourth field-effect transistor M6 are all N-channel field-effect transistors, while the sixth field-effect transistor M7 and the seventh field-effect transistor M8 are P-channel field-effect transistors. The first field-effect transistor M1 and the second field-effect transistor M2 are current mirrors with the same gate. Therefore, the second field-effect transistor M2 is used to sample the current I1 flowing through the first field-effect transistor M1 according to the size ratio. The current flowing through the second field-effect transistor M2 also flows through the fourth field-effect transistor M4. The currents of the fourth field-effect transistor M4 and the fourth field-effect transistor M6 are equal. The current flowing through the fourth field-effect transistor M6 also flows through the sixth field-effect transistor M7. The currents of the sixth field-effect transistor M7 and the seventh field-effect transistor M8 are equal. Therefore, the current flowing through the second field-effect transistor M2 and the current flowing through the seventh field-effect transistor M8 are equal. Therefore, the voltage at the gate of the seventh field-effect transistor M8 is proportional to the current I1. It should be noted that the present application does not make any specific limitation on the size ratio between the various field effect transistors, and those skilled in the art can set the size of each field effect transistor according to actual needs.

[0053] It can be understood that the super source follower 400 includes an eighth field effect transistor M10, a ninth field effect transistor M9 and a third current source A3, the source of the eighth field effect transistor M10 is connected to the gate of the first field effect transistor M1, the gate of the eighth field effect transistor M10 is connected to the drain of the third field effect transistor M3, the drain of the eighth field effect transistor M10 is connected to the input end of the third current source A3, and the output end of the third current source A3 is grounded; the gate of the ninth field effect transistor M9 is connected between the input end of the third current source A3 and the drain of the eighth field effect transistor M10, the source of the ninth field effect transistor M9 is connected to the gate of the first field effect transistor M1, and the source of the ninth field effect transistor M9 is grounded.

[0054] It should be noted that the functions of the first current source A1 , the second current source A2 , and the third current source A3 are to turn on the circuit and enable each field effect transistor to operate normally.

[0055] It can be understood that the error amplification sub-circuit 200 includes a second resistor R1, a third resistor R2 and an operational amplifier EA_STEP1, one end of the second resistor R1 is connected to the load sub-circuit 500, the other end of the second resistor R1 is grounded through the third resistor R2, the positive input end of the operational amplifier EA_STEP1 is connected between the second resistor R1 and the third resistor R2, the reverse input end of the operational amplifier EA_STEP1 is connected to the reference voltage, and the output end of the operational amplifier EA_STEP1 serves as the output end of the error amplification sub-circuit 200.

[0056] It is understandable that the error amplification subcircuit 200 further includes a fourth resistor R3 and a first capacitor C3. One end of the fourth resistor R3 is connected to the output end of the operational amplifier EA_STEP1, and the other end of the fourth resistor R3 is grounded via the first capacitor C3.

[0057] It is understood that the load subcircuit 500 is used to connect to a load and provide an output voltage to the load. The load subcircuit 500 includes a load capacitor C O and the load resistor R L , load resistance R L One end of the capacitor is grounded, and the other end is connected to the source of the first field effect transistor M1. O With the load resistor R L It should be noted that the load resistance R L The voltage is the output voltage of the load sub-circuit 500.

[0058] It is understandable that the voltage regulation sub-circuit 100 further includes a charge pump, which is connected to the input end of the first current source A1.

[0059] It should be noted that the charge pump is used to make the voltage of the gate of the first field effect transistor M1 greater than the voltage of the source of the first field effect transistor M1 so that the first field effect transistor M1 can be turned on.

[0060] It is worth noting that, referring to Figure 1 , the eighth field effect transistor M10 is a P-channel field effect transistor, and the ninth field effect transistor M9 is an N-channel field effect transistor. The second resistor R1 and the third resistor R2 sample the output voltage of the load sub-circuit 500 and input the sampled voltage to the inverting input terminal of the operational amplifier EA_STEP1. When the output voltage of the load sub-circuit 500 increases, that is, when the sampled voltage is greater than the reference voltage, the comparison result of the operational amplifier EA_STEP1 is that the voltage at the inverting input terminal of the operational amplifier EA_STEP1 is greater than the voltage at the positive input terminal, then the voltage at the output terminal of the operational amplifier EA_STEP1 increases, that is, the gate voltage of the third field effect transistor M3 increases, so the current flowing through the third field effect transistor M3 is greater than the current I2 of the second current source A2, so the voltage at the drain of the third field effect transistor M3 decreases, that is Figure 1The voltage at point A decreases, that is, the voltage at the gate of the eighth field effect transistor M10 decreases, so the current flowing through the eighth field effect transistor M10 increases, and the current flowing through the eighth field effect transistor M10 is greater than the current I of the first current source A1. Since the current of the eighth field effect transistor M10 increases, the voltage at the gate of the ninth field effect transistor M9 increases, so that the current flowing through the ninth field effect transistor M9 increases. Since the current flowing through the eighth field effect transistor M10 and the current flowing through the ninth field effect transistor M9 both increase, the voltage at the gate of the first field effect transistor M1 decreases, thereby causing the current flowing through the first field effect transistor M1 to decrease, that is, the current I1 decreases. Since the source of the first field effect transistor M1 is connected to the load resistor R L The output voltage of the load sub-circuit 500 can be reduced by connecting the load sub-circuit 500 to the load sub-circuit 500 .

[0061] When the output voltage of the load sub-circuit 500 decreases, that is, the sampling voltage is less than the reference voltage, the comparison result of the operational amplifier EA_STEP1 is that the voltage at the inverting input terminal of the operational amplifier EA_STEP1 is less than the voltage at the positive input terminal. Then, the voltage at the output terminal of the operational amplifier EA_STEP1 decreases, that is, the gate voltage of the third field effect transistor M3 decreases. Therefore, the current flowing through the third field effect transistor M3 is less than the current I2 of the second current source A2. Therefore, the voltage at the drain of the third field effect transistor M3 increases, that is, Figure 1 The voltage at point A increases, that is, the voltage at the gate of the eighth field effect transistor M10 increases, so the current flowing through the eighth field effect transistor M10 decreases, and the current flowing through the eighth field effect transistor M10 is less than the current I of the first current source A1. Since the current of the eighth field effect transistor M10 decreases, the voltage at the gate of the ninth field effect transistor M9 decreases, so that the current flowing through the ninth field effect transistor M9 decreases. Since the current flowing through the eighth field effect transistor M10 and the current flowing through the ninth field effect transistor M9 both decrease, the voltage at the gate of the first field effect transistor M1 increases, thereby causing the current flowing through the first field effect transistor M1 to increase, that is, the current I1 increases. Since the source of the first field effect transistor M1 is connected to the load resistor R L The output voltage of the load sub-circuit 500 is increased by the super source follower 400. When the output voltage of the load sub-circuit 500 increases, the output voltage of the load sub-circuit 500 decreases via the super source follower 400. When the output voltage of the load sub-circuit 500 decreases, the output voltage of the load sub-circuit 500 increases via the super source follower 400, thereby maintaining a stable output voltage of the load sub-circuit 500.

[0062] It is worth noting that, referring to Figure 1, one end of the compensation capacitor C4 is connected to the gate of the eighth field effect transistor M10, and the other end is connected to the drain of the seventh field effect transistor M8, and the source of the seventh field effect transistor M8 is connected to VOUT. This folding structure can be regarded as the compensation capacitor C4 connected across point A and VOUT. The maximum voltage that capacitor C4 can withstand is Vgs1-Vgs10. This structure avoids high voltage being applied to both ends of the low voltage capacitor C4, where Vgs1 is the gate-source voltage of the first field effect transistor M1, and Vgs10 is the gate-source voltage of the eighth field effect transistor M10. At the same time, this folding structure does not affect the system compensation effect, because when the load capacitor C O When the voltage is large, VOUT can be regarded as a virtual ground in the AC small signal, which ensures that the compensation effect of the capacitor folded and connected to VOUT through the seventh field-effect transistor M8 is the same as the compensation effect of connecting the compensation capacitor C4 directly to the ground at point A. Therefore, this capacitor folding structure can achieve the purpose of compensating high voltage with a capacitor with a low withstand voltage value while ensuring the compensation effect.

[0063] Reference below Figures 1 to 10 The compensation principle of the low voltage dropout linear regulator circuit according to the embodiment of the present application is described in detail with a specific embodiment. It is worth noting that the following description is only for illustrative purposes and is not intended to limit the present application.

[0064] The error amplifier sub-circuit 200 and the voltage regulation sub-circuit 100 of the embodiment of the present application are analyzed as a whole. The overall gain is relatively small, and the position of the pole can be estimated to be approximately gm / C3, where C3 is the resistance of the first capacitor C3C3 and gm is the output impedance of the operational amplifier EA_STEP1. Since the value of C3 is very small, the pole fp1 of the error amplifier sub-circuit 200 is at a high frequency and can be ignored when analyzing the zero-pole effect of the entire low-voltage difference linear voltage regulator circuit.

[0065] Reference Figure 2 , Figure 2 3 is a small signal equivalent circuit diagram of the compensation sub-circuit 300 of the embodiment of the present application. Figure 1The first FET M1 and the second FET M2 form a current mirror with the same gate. The second FET M2 samples the current I1 flowing through the first FET M1 according to the size ratio. The current flowing through the second FET M2 also flows through the fourth FET M4. The currents flowing through the fourth FET M4 and the fourth FET M6 are equal. The current flowing through the fourth FET M6 also flows through the sixth FET M7. The currents flowing through the sixth FET M7 and the seventh FET M8 are equal. Therefore, the current flowing through the second FET M2 and the current flowing through the seventh FET M8 are equal. Therefore, the voltage at the gate of the seventh FET M8 is proportional to the current I1. R4 is a large resistor in the mega-range, connecting VOUT to the D terminal of M8. Its main function is to set an initial value for the drain of the seventh FET M8 to prevent it from being pulled low. The seventh field effect transistor M8 works in the linear region, which is equivalent to a resistor. The linear region resistance R8 of the seventh field effect transistor M8 is expressed as:

[0066]

[0067] Wherein, (W / L)8 is the width-to-length ratio of the seventh field effect transistor M8, V th8 is the turn-on voltage of the seventh field effect transistor M8, μ n is the electron mobility of the seventh field effect transistor M8, C ox is the gate oxide capacitance per unit area of ​​the seventh field effect transistor M8, V gs8 is the gate-source voltage of the seventh field effect transistor M8. Figure 2 , the transfer function of the compensation sub-circuit 300 is:

[0068]

[0069] Among them, g m3 is the transconductance of the third field effect tube M3, r o3 is the output impedance of the third field effect transistor M3, and s is the Laplace operator. There is a pole and a zero in the compensation sub-circuit 300, and the position of the pole fpA is:

[0070]

[0071] The position of the zero point fzA is:

[0072]

[0073] Due to r o3 >>R8, R4>>R8, the position of the pole fpA is approximately The position of the zero point fzA is approximately As the load of the load sub-circuit 500 increases, R8 begins to decrease, and the zero point begins to move toward higher frequencies, while the pole point remains essentially unchanged regardless of the load.

[0074] Reference Figure 3 and Figure 4 , Figure 3 yes Figure 1 The equivalent circuit diagram of the super source follower 400 is shown in FIG. Figure 4 yes Figure 3 The small signal equivalent circuit diagram of the circuit. The transfer function of the super source follower 400 is:

[0075]

[0076]

[0077] Among them, s is the Laplace operator, R o is the output impedance of the super source follower 400, g m10 is the transconductance of the eighth field effect transistor M10, g mb10 is the substrate transconductance generated by the substrate effect in the eighth field effect transistor M10, r o10 is the output impedance of the eighth field effect transistor M10, g m9 is the transconductance of the ninth field effect transistor M9, r o9 is the output impedance of the ninth field effect transistor M9, r1 and r2 are the internal resistances of the current sources A1 and A2, and Cgs is the parasitic capacitance of the first field effect transistor M1.

[0078] Assume that current sources A1 and A2 are ideal current sources, and the loop gain A v and output impedance R o The following approximation can be made:

[0079]

[0080]

[0081] Therefore, the super source follower 400 can reduce the output impedance to 1 / ro10gm9 of the original value. From the transfer function of the super source follower 400, it can be seen that there is a pole fp3:

[0082] [r o10 g m9 (g m10 +g mb10 )] / C gs ;

[0083] Since the load capacitance C OIt is much larger than the parasitic capacitance Cgs of the first field effect tube M1, and the numerator of the pole fp3 is relatively large. Therefore, the pole fp3 is located at a high frequency and is not considered when analyzing the zero poles of the entire low voltage difference linear voltage regulator circuit.

[0084] The load subcircuit 500 has an output pole fpo=1 / (Co*RL), where Co is the load capacitance and R L is the load resistance, and R L The equivalent output load consists of the on-resistance of the power transistor and the actual external load. The position of the output pole fpo moves with load changes. As the output load increases, the output pole fpo moves toward higher frequencies, in the same direction as the zero fzA.

[0085] Reference Figures 5 to 10 , Figure 5 FIG4 shows a gain change curve of the low voltage difference linear voltage regulator circuit under light load of an embodiment of the present application. Figure 6 The phase change curve of the low voltage difference linear voltage regulator circuit of the embodiment of the present application under light load is shown. Figure 7 FIG4 shows a gain change curve of the low voltage difference linear voltage regulator circuit of the embodiment of the present application when the poles coincide. Figure 8 FIG4 shows a phase change curve of the low voltage difference linear voltage regulator circuit of the embodiment of the present application when the poles coincide. Figure 9 The gain change curve of the low voltage difference linear voltage regulator circuit under heavy load in the embodiment of the present application is shown. Figure 10 The phase change curve of the low voltage difference linear voltage regulator circuit under heavy load in the embodiment of the present application is shown.

[0086] When the load connected to load subcircuit 500 is lightly loaded or unloaded, the output pole fpo becomes the dominant pole. Within the bandwidth, only the output pole fpo exists, while the pole fpA and the zero fzA are outside the bandwidth. In this case, the low-dropout linear voltage regulator circuit is a single-pole system and is absolutely stable. As the load gradually increases, the output pole fpo and the zero fzA simultaneously move toward higher frequencies, while the position of the pole fpA remains relatively unchanged. When the load increases to the point where the output poles fpo and fpA coincide, the zero fzA is slightly higher than the dual-pole position but lower than the bandwidth. Zero fzA improves the phase margin, ensuring system stability when the poles coincide. As the load continues to increase, the output pole fpo becomes greater than the pole fpA, and the dominant pole switches to fpA. At this point, the zero fzA is located between the two poles. When the zero fzA encounters the gain curve, the phase curve increases, effectively compensating for the dominant pole through the zero fzA, improving the phase margin and ensuring system stability.

[0087] In a second aspect, an embodiment of the present application provides a circuit board, comprising:

[0088] A low voltage difference linear voltage regulator circuit as described in any embodiment of the first aspect.

[0089] Since the circuit board includes a protection circuit as in any one of the embodiments of the first aspect of the present application, the corresponding contents of the low-voltage difference linear voltage regulator circuit in the embodiments mentioned in the first aspect are also applicable to the circuit board in the embodiments mentioned in the second aspect, and have the same implementation principles and technical effects. In order to avoid redundant description, it will not be described in detail here.

[0090] In a third aspect, an embodiment of the present application provides a low-dropout linear regulator, comprising:

[0091] A circuit board as described in the embodiment of the second aspect.

[0092] Since the low-voltage difference linear regulator includes the circuit board of the embodiment of the second aspect, and the circuit board includes the low-voltage difference linear regulator circuit of the embodiment of the first aspect, the corresponding contents of the low-voltage difference linear regulator circuit in the embodiment mentioned in the first aspect are also applicable to the low-voltage difference linear regulator in the embodiment mentioned in the third aspect, and have the same implementation principles and technical effects. In order to avoid redundant description, it will not be described in detail here.

[0093] The embodiments of the present application have been described in detail above with reference to the accompanying drawings. However, the present application is not limited to the above embodiments. Various modifications can be made within the scope of knowledge possessed by ordinary technicians in the relevant technical field without departing from the purpose of the present application. In addition, the embodiments of the present application and the features of the embodiments can be combined with each other unless there is a conflict.

Claims

1. A low voltage difference linear voltage regulator circuit, characterized in that: include: load subcircuit; a voltage regulation subcircuit, the voltage regulation subcircuit comprising a first field-effect transistor and a first current source, wherein the gate of the first field-effect transistor is connected to the output end of the first current source, the source of the first field-effect transistor is connected to the load subcircuit, and the drain of the first field-effect transistor is connected to the input voltage; an error amplifying subcircuit, the error amplifying subcircuit being connected to a reference voltage and further connected to the load subcircuit, the error amplifying subcircuit being configured to sample an output voltage of the load subcircuit to obtain a sampled voltage, and to compare the reference voltage with the sampled voltage to obtain a comparison result; a compensation subcircuit, the compensation subcircuit being configured to compensate the load subcircuit based on the comparison result, the compensation subcircuit comprising a current mirror, a compensation capacitor, a second field-effect transistor, a third field-effect transistor, and a second current source, wherein the gate of the third field-effect transistor is connected to the output of the error amplification subcircuit, the source of the third field-effect transistor is grounded, and the drain of the third field-effect transistor is connected to the output of the second current source; the input of the second current source is connected to the drain of the first field-effect transistor; the drain of the second field-effect transistor is connected to the drain of the first field-effect transistor, the gate of the second field-effect transistor is connected to the gate of the first field-effect transistor, and the source of the second field-effect transistor is connected to the input of the current mirror; One end of the compensation capacitor is connected to the drain of the first field effect transistor, and the other end is connected to the output end of the current mirror; a super source follower, the output end of the current mirror being connected to the super source follower; The super source follower is connected to the gate of the first field effect tube, and is also connected to the drain of the third field effect tube. The super source follower is used to adjust the voltage of the gate of the first field effect tube.

2. The low voltage difference linear voltage regulator circuit according to claim 1, characterized in that: The current mirror includes a fourth field-effect transistor, a fifth field-effect transistor, a sixth field-effect transistor, and a seventh field-effect transistor. The drain of the fourth field-effect transistor serves as the input end of the current mirror, the drain of the fourth field-effect transistor is connected to the gate of the fourth field-effect transistor and the gate of the fifth field-effect transistor, and the source of the fourth field-effect transistor is grounded; the source of the fifth field-effect transistor is grounded, and the drain of the fifth field-effect transistor is connected to the drain of the sixth field-effect transistor; the source of the sixth field-effect transistor is connected to the source of the first field-effect transistor, the gate of the sixth field-effect transistor is connected to the drain of the sixth field-effect transistor and the gate of the seventh field-effect transistor, the source of the seventh field-effect transistor is connected to the source of the first field-effect transistor, and the drain of the seventh field-effect transistor serves as the output end of the current mirror.

3. The low voltage difference linear voltage regulator circuit according to claim 1, characterized in that: The compensation sub-circuit further includes a first resistor, one end of which is connected to the output end of the current mirror, and the other end of which is connected to the source of the first field effect transistor.

4. The low voltage difference linear voltage regulator circuit according to claim 1, characterized in that: The super source follower includes an eighth field effect transistor, a ninth field effect transistor and a third current source, the source of the eighth field effect transistor is connected to the gate of the first field effect transistor, the gate of the eighth field effect transistor is connected to the drain of the third field effect transistor, the drain of the eighth field effect transistor is connected to the input end of the third current source, and the output end of the third current source is grounded; the gate of the ninth field effect transistor is connected between the input end of the third current source and the drain of the eighth field effect transistor, the source of the ninth field effect transistor is connected to the gate of the first field effect transistor, and the source of the ninth field effect transistor is grounded.

5. The low voltage difference linear voltage regulator circuit according to claim 1, characterized in that: The error amplification subcircuit includes a second resistor, a third resistor and an operational amplifier, one end of the second resistor is connected to the load subcircuit, the other end of the second resistor is grounded through the third resistor, the positive input end of the operational amplifier is connected between the second resistor and the third resistor, the negative input end of the operational amplifier is connected to the reference voltage, and the output end of the operational amplifier serves as the output end of the error amplification subcircuit.

6. The low voltage difference linear voltage regulator circuit according to claim 5, characterized in that: The error amplification subcircuit further includes a fourth resistor and a first capacitor, one end of the fourth resistor is connected to the output end of the operational amplifier, and the other end of the fourth resistor is grounded through the first capacitor.

7. The low voltage difference linear voltage regulator circuit according to claim 1, characterized in that: The load subcircuit includes a load capacitor and a load resistor. One end of the load resistor is grounded, and the other end is connected to the source of the first field effect transistor. The load capacitor is connected in parallel with the load resistor.

8. The low voltage difference linear voltage regulator circuit according to claim 1, characterized in that: The voltage regulation subcircuit further includes a charge pump connected to an input end of the first current source.

9. A circuit board, characterized in that: The invention comprises the low voltage difference linear voltage regulator circuit according to any one of claims 1 to 8.

10. A low voltage dropout linear regulator, characterized in that: Comprising the circuit board as claimed in claim 9.

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