A Reusable Register Performance Interaction Verification System Based on UVM and Its Application

Abstract

The present invention relates to the field of integrated circuit design, and particularly to a reusable register performance interaction verification system based on UVM and its application. The verification system is applied to a verification device including a host and a slave. The verification system is written in the system verilog language, created based on the UVM library, and runs in the host of the verification device. The slave is communicatively connected to the host through an interface; the slave is an RTL design solution written in the verilog or system verilog language. The register performance interaction verification system provided by the present invention includes: a configuration module, a test case module, an excitation sequence library module, a verification layer, and a transaction-level modeling communication unit. The verification system can be used for verification of other projects without changing the internal code, only by configuring the communication content between the host and the slave. Therefore, the present invention can solve the problem of high simulation and verification costs of projects caused by the inability to reuse verification systems and tools between different projects in the existing chip design process.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit design, and in particular to a reusable register performance interactive verification system based on UVM and an application thereof. Background Art

[0002] As an important support and core technology component for the informatization and intelligence of modern science and technology and scientific and technological products, chips play a pivotal role in the national science and technology strategy. Chip design and production is a high-tech, high-investment, and high-risk industry. Especially under new processes, the capital investment for the output of a single chip can even reach tens of millions. Often, a small mistake in the entire process of integrated circuit development may cause the performance of the produced chip to fail to meet the standards, and all the previous work will fail.

[0003] The design of the chip starts with the architecture design, and then goes through the algorithm simulation. After the simulation is correct, the design specification is formulated, and the RTL (Register Transfer Level) design is carried out according to this design specification. After the design scheme is formed, the RTL code needs to be simulated and verified to verify the correctness of the RTL design, and the design specification is used as the standard to verify whether the design scheme accurately meets all the requirements in the specification. Finally, after repeated iterations of the design scheme and simulation verification, until the verification results show that it fully meets the specification standards, logic synthesis, static timing analysis, formal verification, layout and routing, layout physical verification and other work will be carried out. After all the tasks in the entire chip design stage are completed, the chip manufacturing stage can be officially started.

[0004] In the entire chip design and manufacturing process, simulation verification is a very important link. Only when the accuracy and completeness of the verification are very high can the correctness of the RTL design be guaranteed. Therefore, the requirements for chip verification in the chip development link are getting higher and higher, and the construction of the verification platform is also more complicated. The traditional directional test platform is based on the Verilog language, which not only cannot cover all the functional points to be tested, but also cannot be reused between different projects. Therefore, technicians need to specially configure the corresponding verification program for the designed RTL design scheme. There is no solution specifically for reusable verification host-slave interaction between multiple projects in the existing technology. These have greatly affected the verification efficiency; greatly extended the chip R&D cycle, and increased the simulation and verification costs in the design stage. Summary of the invention

[0005] In order to solve the problem that verification systems and tools cannot be reused between different projects in the existing chip design process, resulting in high simulation and verification costs of the projects, the present invention provides a reusable register performance interactive verification system based on UVM and its application.

[0006] The present invention is implemented by the following technical solutions:

[0007] A reusable register performance interaction verification system based on UVM is applied to a verification device including a host and a slave. The reusable register performance interaction verification system based on UVM is written in the system verilog language, created based on the UVM library, and runs in the host of the verification device. The slave is communicatively connected to the host through an interface; the slave is an RTL design solution written in the verilog or system verilog language.

[0008] The reusable register performance interaction verification system based on UVM provided by the present invention includes: a configuration module, a test case module, an excitation sequence library module, a verification layer, and a transaction-level modeling communication unit.

[0009] Among them, the configuration module is used to create a corresponding configuration file according to the currently connected slave and the corresponding verification task, and then declare the information library file and the definition library file in the configuration file. The configuration module is also used to instantiate the virtual interface between the host and the slave.

[0010] The test case module is used to establish each test case required for the host and the slave in the verification phase, and the test case is used to instantiate each instruction required in the verification phase.

[0011] The excitation sequence library module contains a large number of excitation sequences generated according to each test case, and each excitation sequence contains all the information to be transmitted during the communication between the host and the slave. The excitation sequence library module uses a series of excitation sequences to constitute a sequence library required for verifying different register functions.

[0012] The verification layer contains all functional modules for performing verification tasks, including agents, register models, self-comparators, and first-in-first-out queues. Among them, the agent contains a sequence generator, a driver, and a monitor. The sequence generator is responsible for data transmission, and then sequentially sends the sequence information in the stimulus sequence library module to the driver according to the requirements of the slave. The driver defines functions under different commands, drives the sequence information to the interface between the host and the slave, and then realizes the two-way transmission of signals between the agent and the slave through the virtual interface. The monitor is connected to the interfaces between the host and the slave, collects the information on the signal lines between the interfaces, and verifies the function and timing of the signals sent by the driver during the verification phase. The register model is used to simulate the actual registers in the design under test; and then, according to the signals fed back from the slave to the host during the verification phase, virtual operations for the full-function verification process of the registers under test are realized in the host. The driver is also connected to the self-comparator through a first-in-first-out queue to enable the driver to send the information to be verified to the self-comparator in sequence while sending signals to the slave. The self-comparator also receives the feedback information from the register module, and compares the received transmitted signal with the feedback information. If the two are the same, the verification is correct; otherwise, the verification is incorrect.

[0013] The transaction-level modeling communication unit is used for the communication connection status between different functional modules instantiated in the verification layer, specifically including establishing communication connections within the agent and the driver, between the agent and the first-in-first-out queue, and between the first-in-first-out queue and the self-comparator; and finally ensuring that a stable information communication link can be established between the driver and the self-comparator.

[0014] As a further improvement of the present invention, the information library file is derived from an object class. All fixed information required for the entire register performance interaction verification system is defined in the information library file; including: the length of read and write data, the number of read and write data, the formats of commands and feedbacks during the interaction between the master and the slave, and so on. The information library file defines the fixed information as local variables and uses the automatic domain mechanism to register these variables into the entire register performance interaction verification system for use by all components.

[0015] As a further improvement of the present invention, the definition library file is written to more conveniently observe the verification results. The definition library file defines the sampling rules for the feedback signals on the signal lines and defines each state during the verification phase using an enumeration type. The definition library file contains the statuses of each command sent by the host, the statuses of each command fed back by the slave, the address statuses of each command sent by the host, and so on. So that all the interacting signals in the debug waveform of the verification process correspond to the different progress of each command.

[0016] In the solution provided by the present invention, the interface between the host and the slave includes the definitions of all the slave interface signals required to achieve data communication between the host and the slave. The virtual interface is used to instantiate the communication link between the host and the slave during the verification process of each register chip, so as to ensure that when the slave changes, only the virtual interface needs to be changed, and the signal can be transmitted between the components in the host and slave test verification layers through the UVM config_db mechanism.

[0017] As a further improvement of the present invention, in the test case module, the test cases are divided into two types: basic test cases and extended test cases. The test cases for basic tests respectively need to instantiate the verification environment, set the default sequence, set the timeout exit time of the entire system, and set the values of some parameters in the verification environment. The extended test cases are combined based on the basic test cases to further expand multiple test cases for completing verification tasks such as data reading, writing, and erasing.

[0018] As a further improvement of the present invention, in the stimulus sequence library module, when the slave or the test case is adjusted, the sequence library needs to be changed; at this time, only a new stimulus sequence needs to be generated to add, delete, or modify the original stimulus sequence.

[0019] As a further improvement of the present invention, the verification layer is recreated before the execution of multiple verification tasks for each IP. The agent is the execution module of the verification task and uses the driver, monitor, and sequence generator to complete the task. For different verification tasks in the same IP, only some parts in the agent need to be adaptively modified; for some general IPs, a dedicated agent is selected to be directly replaced during the creation of the verification layer.

[0020] As a further improvement of the present invention, the verification layer also includes a verification component, which is communicatively connected to the monitor. The verification component is used to count all the monitoring information collected by the monitor, and then judge whether the stimulus signal sent by the driver has included the verification of all the functions of the slave, and finally output a coverage rate index representing the completion degree of the verification function. In the reusable register performance interaction verification system based on UVM, the verification component is selected to be an integrator or a coverage collector.

[0021] As a further improvement of the present invention, a top-level module is included in the top layer of the verification device. The top-level module defines the clock and reset variables and generates the clock and reset signals. The top-level module instantiates the interface between the host and the slave; the top-level module also instantiates the slave and connects the signals on the slave to the interface signals.

[0022] The present invention further includes an application of a reusable register performance interaction verification system based on UVM. In this application, the aforementioned reusable register performance interaction verification system based on UVM is used as the host, and the RTL design solution written in Verilog or SystemVerilog language is used as the slave. The interface between the host and the slave is instantiated through the top-level module, and then a virtual verification device for verifying the register performance of the RTL design solution can be built. This virtual verification device is used to complete the verification tasks related to data reading, writing, and erasing of registers in the RTL design solution.

[0023] Among them, in the virtual verification device constructed by the present invention, the verification process of the data write function includes the following steps:

[0024] S1: In the register performance interaction verification system of the host, configure the write information of the information library file and the definition library file. The write information includes the host's write command, the slave's write feedback, the host's write address, the slave's address feedback, the host's write data, the slave's write data feedback, etc.

[0025] S2: Instantiate and start the corresponding sequence in the sequence library according to the scenario requirements in the virtual sequence. The verification tasks executed after the sequence is started include multiple write operations, and the addresses and data of the multiple write operations are allocated in two ways: specified and random.

[0026] S3: Write a test case corresponding to the write operation verification scheme. The test case inherits from the test layer, and finally mounts the virtual sequence to the sequence sender in the way of default_sequence to start the corresponding sequence.

[0027] S4: Pass a string to run_test() to create an instance of the class represented by this string, and then automatically start the register performance interaction verification system, and execute the phase mechanism of each component in turn. After all phases are executed, the simulation ends.

[0028] S5: The automatic comparator will generate the verification data for each verification, and then run an external script to directly summarize and analyze the relevant data of multiple verifications, and give the final verification result.

[0029] The technical solution provided by the present invention has the following beneficial effects:

[0030] 1. The verification system provided by the present invention has high versatility. Since the verification system uses the most mainstream UVM verification methodology to build the verification environment, it can be reasonably reused. This not only ensures the correctness of the verification system code but also avoids the repeated development of verification components. Only a small amount of code modification is required in different projects to be put into other verification processes; thus, it can effectively reduce the R & D cost invested in the verification stage during the chip design process.

[0031] 2. The verification system provided by the present invention has powerful functions. It is not limited to the IP module-level verification platform but can also be reused in the system-level chip verification platform. For different development projects, only multiple groups of corresponding signals need to be configured to be applied in complex IP and system levels.

[0032] 3. The verification system provided by the present invention has strong scalability. It supports communication between hosts and slaves with various configurations. The interface supports bidirectional signals shared by the host and the slave. The register model supports front-door access and back-door access, supports different bus widths, and supports modification to other bus protocols.

[0033] 4. The operation of the verification system provided by the present invention during the application process is simple. Only by flexibly constructing various required test cases and adding constrained random stimuli can the convergence of verification completeness be accelerated. The verification efficiency of the written test cases is high, and it can simulate more comprehensive scenarios, greatly shortening the R & D cycle of IC design. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The drawings are used to provide a further understanding of the present invention and constitute a part of the specification. They are used together with the embodiments of the present invention to explain the present invention and do not constitute a limitation to the present invention. In the drawings:

[0035] Figure 1 is a functional schematic diagram of the verification device including a host and a slave in Embodiment 1 of the present invention.

[0036] Figure 2 is a system topology diagram of a reusable register performance interaction verification system based on UVM provided in Embodiment 1 of the present invention.

[0037] Figure 3 is a schematic diagram of the two-level check method of back-door access adopted in the register model.

[0038] Figure 4 is an architecture diagram of the virtualized verification device created in Embodiment 2 of the present invention.

[0039] Figure 5 is a working flow diagram of the verification stage of the virtualized device shown by taking the data write operation of the register as an example in Embodiment 2. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0040] In order to make the objectives, technical solutions and advantages of the present invention more clear and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0041] Embodiment 1

[0042] In the actual development process of a chip design project, although the designs between projects are not completely the same as a whole, we can always find similarities in key points. For different RTL designs, no matter how complex the design scheme is, it always contains many common basic designs and requires single basic function tests. For the verification link of a specific chip design project, the most important work is to establish communication between the external system and the RTL design. The external system is equivalent to a host, and the RTL design is equivalent to a slave. Then the host sends corresponding commands, and the slave receives and gives feedback. Finally, the correctness of the RTL design is judged according to the evaluation result of the feedback received by the host.

[0043] Therefore, for the above application scenarios, this embodiment provides a reusable register performance interaction verification system based on UVM. The core advantage of this register performance interaction verification system is reusability, that is, it can be applied to the functional verification of different RTL designs. During the application process, there is no need to change the internal code of the verification system, and only the communication content between the host and the slave needs to be reconfigured. Therefore, it belongs to a flexible, highly adaptable and scalable verification system.

[0044] Specifically, the solution of this embodiment is applied to a verification device including a host and a slave. Among them, the reusable register performance interaction verification system based on UVM is written in the system verilog language and created based on the UVM library. This verification system runs in the host of the verification device and serves as the execution entity of the verification task. The slave is connected to the host through an interface for communication; the slave is an RTL design scheme written in verilog or system verilog language, and the slave is the execution object of the verification task. The logical relationship between the two is as Figure 1 shown.

[0045] As Figure 2 shown, the reusable register performance interaction verification system based on UVM designed in this embodiment includes: a configuration module, a test case module, an excitation sequence library module, a verification layer, and a transaction-level modeling communication unit.

[0046] The configuration module is used to create a corresponding configuration file according to the currently connected slave and the corresponding verification task, and then declare the information library file and the definition library file in the configuration file. The configuration module is also used to instantiate the virtual interface between the host and the slave.

[0047] The information library file is derived from the object class. The information library file defines all the fixed information required by the entire register performance interaction verification system, including the length of read and write data, the number of read and write data, the format of commands and feedback during master-slave interaction, etc. The information library file defines the fixed information as local variables and uses the automatic domain mechanism to register these variables to the entire register performance interaction verification system for use by all components.

[0048] The information library file declared in the configuration file can realize the change of the verification system configuration from the top level, thus avoiding the problem of modifying the content of the information library file in different projects. There is no need to worry about the hidden danger of accidentally modifying the wrong place and causing the entire verification system to collapse. This configuration method greatly reduces the error rate. At the same time, the solution of this embodiment also defines set and get functions for changing or printing out these editable information to ensure that the platform does not need to be changed as much as possible in future transplants. When the slave changes, a lot of fixed information will also change. At this time, you only need to change it once in this file, and there is no need to modify the relevant information anywhere else.

[0049] The definition library file is written to make it easier to observe the verification results. Because the host and slave verification devices established in this embodiment have relatively few interactive signal lines, all 8-bit, 24-bit or 32-bit data are displayed serially. This results in the serial waveform being very inconvenient to observe when the verification process reaches the waveform analysis stage. For better debugging, this embodiment uses the definition library file to define the sampling rules of the feedback signal on the signal line, and uses an enumeration type to define each state of the verification stage. The definition library file contains the various command states sent by the host, the various command states fed back by the slave, the address states of the host sending each command, and so on. So that all interactive signals in the verification process debugging waveform correspond to the different progress of each command.

[0050] In the solution provided in this embodiment, the interface between the host and the slave contains the definition of all the slave interface signals needed to realize data communication between the host and the slave. With the interface module, the host can drive the generated excitation sequence to the slave, the slave can receive the excitation sequence and then output the result to the host, and the host can further operate the slave according to the feedback result. To some extent, the interface simplifies the connection between modules, avoids hierarchical references, eliminates absolute paths, and avoids modifying all signals when changing the slave.

[0051] In view of the disadvantages that traditional hardware interfaces cannot be well applied to an object - oriented test platform and cannot be instantiated in programs and classes, in this embodiment, a virtual interface is adopted between the host and the slave. The virtual interface instantiates the communication link between the host and the slave during the verification process of each register chip, so as to ensure that when the slave changes, only the virtual interface needs to be changed, and the signal can be transmitted between components in the host and slave test verification layers through the UVM's config_db mechanism.

[0052] The test case module is used to establish each test case required for the host and the slave during the verification phase. The test case is used to instantiate various instructions required for the verification phase. In the test case module, the test cases are divided into two types: basic test cases and extended test cases. The basic test cases respectively need to instantiate the verification environment, set the default sequence, set the timeout exit time of the entire system, and set the values of some parameters in the verification environment. The extended test cases are combined based on the basic test cases, and then multiple test cases for completing verification tasks such as data reading, writing, and erasing are extended.

[0053] The stimulus sequence library module contains a large number of stimulus sequences generated according to each test case. Each stimulus sequence contains all the information to be transmitted during the communication between the host and the slave. The stimulus sequence library module uses a series of stimulus sequences to form a sequence library required for verifying different register functions. In the stimulus sequence library module, when the slave or the test case is adjusted, the sequence library needs to be changed; at this time, only new stimulus sequences need to be generated, and the original stimulus sequences can be added, deleted, or modified.

[0054] The verification layer is an execution unit that instantiates and executes various verification instruction operations in a reusable register performance interaction verification system based on UVM. It is composed of a series of functional modules that execute verification tasks. The test layer includes components such as an agent, a register model, a self - comparator, and a first - in - first - out queue, etc.

[0055] Among them, the agent contains a sequence generator, a driver, and a monitor. The sequence generator is responsible for data transmission, and then sequentially sends the sequence information in the stimulus sequence library module to the driver according to the requirements of the slave. The driver defines functions under different commands, drives the sequence information to the interface between the host and the slave, and then realizes the bidirectional transmission of signals between the agent and the slave through the virtual interface. The monitor is connected to the interface between the host and the slave, collects the information on the signal line between the interfaces, and verifies the function and timing of the signals sent by the driver during the verification phase.

[0056] The register model is used to simulate the actual registers in the design under test. Specifically, while simulating the functional characteristics of the real registers in the RTL design solution and reflecting the current register status, the register model realizes virtual operations for the full-functional verification process of the registers under test in the host through operations such as reading, writing, and mirroring. In this embodiment, the register model adopts the backdoor access method as described in Figure 3 to perform two-level checks to improve the efficiency of quickly locating problems during the verification process.

[0057] In Figure 3 , taking the backdoor access as an example, the read and write operation processes of the register model are explained. For example, the host sends a write command to the slave, and the slave gives feedback indicating that it has received this command. Then the host sends the write address, and the slave gives feedback indicating that it has received this address. Then the host sends the write data, and the slave gives feedback indicating that it has received this data and written it into the internal register. The host sends a read command to the slave, and the slave gives feedback indicating that it has received this command. Then the host sends the read address, and the slave gives feedback indicating that it has received this address. Then the slave sends the data of the register corresponding to this address to the host.

[0058] The driver is also connected to the automatic comparator through a first-in-first-out queue, so that the driver can send the transmission information to be verified to the automatic comparator in sequence while sending signals to the slave. In this embodiment, the communication connection status between different functional modules instantiated in the verification layer through the transaction-level modeling communication unit is specifically realized, including establishing communication connections inside the agent and the driver, between the agent and the first-in-first-out queue, and between the first-in-first-out queue and the automatic comparator; and finally ensuring that a stable information communication connection can be established between the driver and the automatic comparator.

[0059] The automatic comparator is the place where the entire verification system compares the feedback content of the RTL design solution. It receives the information sent from the driver at one end and the data of the register model at the other end (in the embodiment, taking the backdoor access method of the register model as an example), and compares these two sets of data. If the two are equal, it means that this verification is correct; if not, it means that this verification fails.

[0060] For example, when the host wants to write something into the slave, the sequence generated by the sequence generator will contain write information such as the write address and the write data. This sequence is then sent to the driver. While driving this sequence to the slave, the driver also sends this information to the automatic comparator. The automatic comparator then receives a correct address and correct write data. Subsequently, the register model retrieves the actual data in the slave corresponding to this address through backdoor access and passes it to the automatic comparator. At this time, the automatic comparator has two sets of data. One set is the correct data that should be written, and the other set is the data actually written to the register. If they are equal, the verification is correct; if not, the verification is incorrect.

[0061] In the solution of this embodiment, the verification layer needs to be recreated before each IP in each design solution performs various verification tasks. The agent is the execution module of the verification task and uses the driver, monitor, and sequence generator to complete the task. For different verification tasks in the same IP, only some parts in the agent need to be adaptively modified; for some general IPs, dedicated agents are selected for configuration to be directly replaced during the creation of the verification layer.

[0062] In addition, in the verification tasks of some RTL designs with more complex functions, verification components need to be further added to the verification layer. The verification components are communicatively connected to the monitor. The verification components are used to statistically analyze all the monitoring information collected by the monitor, and then determine whether the excitation signals sent by the driver have included the verification of all functions of the slave, and finally output a coverage metric representing the completion degree of the verification function. In the reusable register performance interaction verification system based on UVM, the verification components are selected to be integrators or coverage collectors.

[0063] Embodiment 2

[0064] This embodiment provides an application of a reusable register performance interaction verification system based on UVM. In this application, the reusable register performance interaction verification system based on UVM provided in Embodiment 1 is used as the host, and the RTL design solution written in Verilog or SystemVerilog language is used as the slave, and the interface between the host and the slave is instantiated through the top-level module; thus, a virtual verification device for verifying the register performance of the RTL design solution can be built.

[0065] This virtual verification device is mainly used to complete the verification tasks related to data reading, writing, and erasing of registers in the RTL design solution. Such as Figure 4As shown in the figure, the top layer of the verification device in this embodiment contains a top-level module. The top-level module defines clock and reset variables and generates clock and reset signals. The top-level module instantiates the interface between the host and the slave; the top-level module also instantiates the slave and connects the signals on the slave to the interface signals.

[0066] In a traditional verification platform, a dedicated verification platform needs to be built separately for each different slave for functional verification. In the solution of this embodiment, the verification personnel only need to first modify the interface between the slave and the host, then update the information in the information library file according to the communication requirements between the host and the slave, and finally perform some simple configurations on the proxy to verify different slaves. Therefore, the solution provided in this embodiment can greatly improve the verification efficiency of complex RTL design solutions while ensuring the verification quality.

[0067] In the solution of this embodiment, any complex verification task can be decomposed into different test cases for implementation. Therefore, the verification processes of all RTL design solutions can adopt roughly the same processing logic; mainly including five stages: "verification system configuration - sequence library instantiation - test case writing and stimulus sequence generation - register simulation - verification data sampling and analysis".

[0068] For example, in the virtualized verification device constructed in this embodiment, the verification process of the data write function is roughly as Figure 5 shown, including the following steps:

[0069] S1: In the register performance interaction verification system of the host, configure the write information of the information library file and the definition library file. The write information includes the host's write command, the slave's write feedback, the host's write address, the slave's address feedback, the host's write data, the slave's write data feedback, etc.

[0070] S2: Instantiate and start the corresponding sequence in the sequence library in the virtual sequence according to the scenario requirements. The verification tasks started and executed by the sequence include multiple write operations, and the addresses and data of the multiple write operations are allocated in two ways: specified and random.

[0071] S3: Write the test case corresponding to the write operation verification scheme. The test case inherits from the test layer, and finally mounts the virtual sequence to the sequence sender in the way of default_sequence to start the corresponding sequence.

[0072] S4: Pass a string to run_test() to create an instance of the class represented by this string, and then automatically start the register performance interaction verification system, and execute the phase mechanism of each component in turn. After all phases are executed, the simulation ends.

[0073] S5: The automatic comparator generates verification data for each verification. Then, an external script is run to directly summarize and analyze the relevant data of multiple verifications, and a final verification result is given.

[0074] In summary, the system provided in this embodiment uses the most mainstream UVM verification methodology to build a verification environment. The system has high versatility and is suitable for reasonable reuse. This can not only ensure the correctness of the code but also avoid the repeated development of verification components. Technical personnel only need to make very few code modifications for a specific project of the design and then can be put into the verification process of other projects. In addition, this system is not limited to the IP module-level verification platform and can also be reused in the system-level chip verification platform. It can arbitrarily configure multiple groups of signals, making it more convenient to apply in some complex IPs and system levels.

[0075] This system has strong scalability, supports communication between hosts and slaves with various configurations, the interface supports two-way signals shared by the host and the slave, the register model supports front-door access and back-door access, supports different bus widths, and supports modification to other bus protocols. At the same time, by flexibly constructing various required test cases and adding constrained random stimuli, the convergence of verification completeness can be accelerated. Therefore, the verification efficiency of the test cases of the verification system in this embodiment is high, it can simulate more comprehensive scenarios, and greatly shortens the R & D cycle of IC design.

[0076] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, and improvements made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A reusable register performance interaction verification system based on UVM, characterized in that: It is applied to a verification device including a host and a slave; the reusable register performance interaction verification system based on UVM is written in the systemverilog language, created based on the UVM library, and runs in the host of the verification device; the slave is communicatively connected to the host through an interface; the slave is an RTL design solution written in verilog or system verilog language; The reusable register performance interaction verification system based on UVM includes: A configuration module, which is used to create a corresponding configuration file according to the currently connected slave and the corresponding verification task, and then declare the information library file and the definition library file in the configuration file; the configuration module is also used to instantiate the virtual interface between the host and the slave; A test case module, which is used to establish each test case required for the host and the slave during the verification phase, and the test case is used to instantiate each instruction required for the verification phase; An excitation sequence library module, which contains a large number of excitation sequences generated according to each test case, and each excitation sequence contains all the information to be transmitted during the communication between the host and the slave; the excitation sequence library module uses a series of excitation sequences to form a sequence library required for verifying different register functions; A verification layer, which contains all functional modules for performing verification tasks, including an agent, a register model, a self-comparator, and a first-in first-out queue; among them, the agent contains a sequence generator, a driver, and a monitor; the sequence generator is responsible for data transmission, and then sequentially sends the sequence information in the excitation sequence library module to the driver according to the requirements of the slave; the driver defines functions under different commands, drives the sequence information to the interface between the host and the slave, and then realizes the bidirectional transmission of signals between the agent and the slave through the virtual interface; the monitor is connected to the interface between the host and the slave, and collects the information on the signal line between the interfaces, and verifies the function and timing of the signals sent by the driver during the verification phase; the register model is used to simulate the actual registers in the design under test; and then, according to the signals fed back from the slave to the host during the verification phase, a virtual operation of the full-function verification process of the register under test is realized in the host; the driver is also connected to the automatic comparator through the first-in first-out queue to enable the driver to send the information to be verified to the automatic comparator in sequence while sending signals to the slave; the automatic comparator also receives the feedback information from the register module, and compares the received transmission signal with the feedback information. If the two are the same, the verification is correct, otherwise the verification is incorrect; and A transaction-level modeling communication unit, which is used to establish communication connections between the agent and the driver instantiated in the verification layer, between the agent and the first-in first-out queue, and between the first-in first-out queue and the automatic comparator; to ensure the information communication between the driver and the automatic comparator.

2. The reusable register performance interaction verification system based on UVM according to claim 1, wherein: The information library file is derived from the object class, and all the fixed information required by the entire register performance interaction verification system is defined in the information library file, including: the length of the read / write data, the number of read / write data, and the formats of the commands and feedbacks during the master-slave interaction. The information library file defines the fixed information as local variables and uses the automatic domain mechanism to register these variables into the entire register performance interaction verification system for use by all components.

3. The reusable register performance interaction verification system based on UVM according to claim 1, wherein: The definition library file is written to more conveniently observe the verification results. The definition library file defines the sampling rules for the feedback signals on the signal lines and defines each state in the verification stage using an enumeration type. The definition library file contains the various command states sent by the host, the various command states feedback by the slave, and the address states of the various commands sent by the host, so that all the interacting signals in the debug waveform of the verification process correspond to the different progress of each command.

4. The reusable register performance interaction verification system based on UVM according to claim 1, wherein: The interface between the host and the slave contains the definitions of all the slave interface signals required to implement the data communication between the host and the slave. The virtual interface is used to instantiate the communication link between the host and the slave during the verification process of each register chip, so as to ensure that when the slave changes, only the virtual interface needs to be modified, and the signals can be transmitted between the components in the host and slave test verification layers through the UVM's config_db mechanism.

5. The reusable register performance interaction verification system based on UVM according to claim 1, characterized in that: In the test case module, the test cases are divided into two types: basic test cases and extended test cases. The basic test cases respectively need to instantiate the verification environment, set the default sequence, set the timeout exit time of the entire system, and set the values of some parameters in the verification environment. The extended test cases are combined based on the basic test cases to further expand test cases for verifying tasks such as data reading, writing, and erasing.

6. The reusable register performance interaction verification system based on UVM according to claim 1, wherein: In the excitation sequence library module, when the slave or the test case is adjusted, the sequence library needs to be changed. At this time, only a new excitation sequence needs to be generated to add, delete, or modify the original excitation sequence.

7. The reusable register performance interaction verification system based on UVM according to claim 1, characterized in that: The verification layer is recreated before the execution of multiple verification tasks for each IP. The agent is the execution module of the verification task and uses the driver, monitor, and sequence generator to complete the task. For different verification tasks in the same IP, only some parts of the agent need to be adaptively modified. For some general IPs, a dedicated agent is selected and configured to be directly replaced during the creation of the verification layer.

8. The reusable register performance interaction verification system based on UVM according to claim 1, characterized in that: The verification layer also includes a verification component, which is communicatively connected to the monitor. The verification component is used to count all the monitoring information collected by the monitor, and then determine whether the excitation signals sent by the driver have included the verification of all the functions of the slave, and finally output a coverage metric representing the degree of completion of the verification function. In the reusable register performance interaction verification system based on UVM, the verification component selects an integrator or a coverage collector.

9. The reusable register performance interaction verification system based on UVM according to claim 1, characterized in that: A top-level module is included in the top layer of the verification device; the top-level module defines clock and reset variables and generates clock and reset signals; the top-level module instantiates the interface between the host and the slave. The top-level module also instantiates the slave and connects the signals on the slave to the interface signals.

10. A reusable register performance interaction verification system application based on UVM, characterized in that, Using the UVM-based reusable register performance interaction verification system described in any one of claims 1-9 as the host, and using the RTL design solution written in Verilog or SystemVerilog language as the slave, and instantiating the interface between the host and the slave through the top-level module; thus, a virtual verification device for verifying the register performance of the RTL design solution can be built; the virtual verification device is used to complete the verification tasks related to data reading, writing, and erasing of registers in the RTL design solution. Among them, the verification process of the data write function in the virtual verification device includes the following steps: S1: In the register performance interaction verification system of the host, configure the write information of the information library file and the definition library file; the write information includes the write command of the host, the write feedback of the slave, the write address of the host, the address feedback of the slave, the write data of the host, and the write data feedback of the slave. S2: Instantiate and start the corresponding sequence in the sequence library according to the scenario requirements in the virtual sequence. The verification tasks started and executed by the sequence include multiple write operations. The addresses and data of the multiple write operations are allocated in two ways: specified and random. S3: Write a test case corresponding to the write operation verification scheme. The test case inherits from the test layer, and finally mounts the virtual sequence to the sequence sender in the way of default_sequence to start the corresponding sequence. S4: Pass a string to run_test() to create an instance of the class represented by this string, and then automatically start the register performance interaction verification system, and execute the phase mechanism of each component in turn. After all phases are executed, the simulation ends. S5: The automatic comparator will generate the verification data for each verification, and then run an external script to directly summarize and analyze the relevant data of multiple verifications, and give the final verification result.

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