A design space exploration method for RISC-V processors

Abstract

This invention discloses a design space exploration method for a RISC-V processor. Based on the optimization of the design space search algorithm, this method adds an autonomous learning algorithm to provide key information for the search algorithm. This method analyzes the sensitivity of each layer in the CNN network in advance, reducing the processor's computing resources and storage space, improving search efficiency, and achieving better optimization results. The method utilizes a sparrow search algorithm to optimize convolutional neural networks, significantly improving the accuracy of the prediction model and shortening the simulation calculation time. The method optimizes the processor's convolution operations on the convolutional neural network, reduces the resource requirements of the DSP unit, and increases the parallelism of the processor's pipeline instructions. This significantly reduces the cycle time of the processor chip design and optimizes the processor's performance.

Description

Technical Field

[0001] The present invention relates to the technical field of processor chips, and in particular to a design space exploration method for a RISC-V processor. Background Art

[0002] As an open source and free instruction set, the RI SC-V instruction set has received widespread attention in the industry. It is an open instruction set architecture based on the reduced instruction set principle. It has the characteristics of simple architecture, modular instruction set, and extensible instructions. It can realize the design of customized function chips and improve the flexibility and high efficiency of the processor.

[0003] With the advancement of integrated circuit technology, the increasing complexity of system structure design, and the rapid development of artificial intelligence, the requirements for processor performance are constantly increasing. There are more and more parameters related to processor design, which makes the processor design space grow exponentially. The processor design space consists of all parameters that affect the response of the processor benchmark program. However, when using different benchmarks to verify an architecture, it takes a lot of time to obtain indicators. Software simulation technology is extremely time-consuming, which brings us huge computing energy consumption and investment costs. Therefore, it is impractical to traverse and evaluate each microarchitecture to explore the optimal architecture. Architectural design is a key link in chip design and directly affects the cost-effectiveness of the chip. In response to the above problems, researchers have proposed many accelerated design space exploration technologies to improve the efficiency of design space exploration, such as:

[0004] (1) Shorten the time it takes for the simulator to simulate a single configuration

[0005] Fast simulation techniques primarily accelerate simulation by reducing the number of simulated instructions. Well-known methods include SimPoint and SMARTS. These techniques extract representative instruction traces from a test program. The test program is then rapidly simulated, and the execution counts of basic blocks within the program are combined into basic block vectors. Based on the similarity of these vector blocks, a clustering algorithm is used to classify the test program into clusters. Within each cluster, a representative sample is selected. Finally, representative simulation points within the test program are used as the resulting representative samples. The weight of each sample reflects the behavioral characteristics of the entire test program. This can significantly accelerate individual simulations. These methods significantly reduce the simulation cost of design space exploration.

[0006] (2) Using search algorithms

[0007] In order to find the optimal parameter combination that meets the constraints from the huge design space, researchers heuristically accelerate the processor based on traditional design space exploration algorithms such as random traversal, simulated annealing, ant colony algorithm, genetic algorithm, and taboo search algorithm, and solve problems in specific application scenarios by combining efficient search algorithms.

[0008] In addition, Joseph et al. proposed a nonlinear regression model based on radial basis functions (RBFs) to predict processor performance. To reduce simulation time, Khan and Dubach proposed a reaction-based prediction model. This approach involves accurately simulating the execution of a new program on a small number of processor configurations and obtaining performance metrics as input to the prediction model. Considering the shortcomings of random sampling of training samples, Li et al. proposed a design space exploration method based on active learning sampling.

[0009] (3) Improve the parallelism of pipeline instructions in the processor

[0010] Key technologies for processor development and instruction-level parallelism include pipelining, out-of-order execution, multi-issue, superscalar, and prediction techniques. To improve instruction-level parallelism, modern microprocessors are generally moving towards superscalar and deeply pipelined architectures. However, the numerous conditional branch instructions in a program disrupt the normal instruction fetch and execution process, causing pipeline interruptions and severely impacting pipeline efficiency. To reduce the control flow overhead caused by branch instructions and increase pipeline throughput, advanced branch predictors with high prediction accuracy and low misprediction penalty latency are required. Although branch prediction is a relatively traditional performance-enhancing technique, even a mere 0.01% improvement in prediction accuracy, when considered against a large instruction base, can yield significant performance gains from reducing the total branch misprediction penalty and energy savings from reducing the number of instructions executed on the wrong path.

[0011] Although the above method reduces the simulation cost of the design space to a certain extent, the number of configurations in the design space is too large. Simply reducing the simulation time of a single configuration is very limited. In addition, there are still problems such as large computing power and insufficient accuracy of the prediction model. Summary of the Invention

[0012] The purpose of the present invention is to overcome the shortcomings of the existing technology and provide a design space exploration method for RISC-V processors. The method uses the better convergence performance and search ability of the sparrow search algorithm to optimize the convolutional neural network. By optimizing the network structure, the resource requirements of the DSP unit are reduced, and the parallelism of the pipeline instructions in the processor is improved. The method can find the optimal solution set in the design space in the shortest possible time, greatly reducing the computational effort and investment cost, while improving the performance of the processor.

[0013] To achieve the above objectives, the technical solutions provided by the present invention are:

[0014] A design space exploration method for a RISC-V processor, comprising:

[0015] Using a pruning method based on an autonomous learning algorithm, the weights and parameter sensitivities of critical paths are analyzed to determine the network model with the most sensitive parameters.

[0016] Perform search optimization in the network model with large parameter sensitivity, and optimize the convolutional neural network with the sparrow search algorithm to obtain the training set;

[0017] The obtained training set is used as the input of the fitness function. After multiple iterations, the maximum value of the fitness function is the optimal solution, that is, the design space.

[0018] Furthermore, the method specifically includes the following steps:

[0019] S1, initialization phase:

[0020] Using an autonomous learning algorithm, unimportant connections and weights in a pre-trained model are selected. Based on the sensitivity of the parameters, the neural network structure is simplified to a certain extent, reducing the computational effort of the design search algorithm on the network model. The design parameters in the sparrow search algorithm are initialized, and the network topology is determined based on the network scale parameters.

[0021] S2, sampling stage:

[0022] Using random sampling method, N sample values ​​are randomly selected from the design space obtained in the initialization phase as the input of the CNN network model in the training phase;

[0023] S3, training phase:

[0024] The sampled values ​​are put into the CNN network model optimized by the sparrow search algorithm for training to obtain a training set;

[0025] S4, prediction stage:

[0026] The training set is then loaded into the fitness function of the sparrow search algorithm to obtain a set of fitness function values ​​and sort them;

[0027] S5, iterative process:

[0028] Determine whether the end condition is met. If not, select the point with the largest fitness function value and repeat steps S2 to S4 until the iteration is completed;

[0029] S6. Output the maximum value of the fitness function as the optimal solution set.

[0030] Furthermore, a pruning method based on an autonomous learning algorithm is used to analyze the weights and parameter sensitivities of the critical paths and determine the network model, including:

[0031] (1 Initialize the autonomous learning algorithm and obtain the CNN pre-training model according to the predetermined parameters;

[0032] (2 After obtaining the CNN pre-training model, analyze the sensitivity of each layer of the CNN network and determine the pruning order according to the sensitivity from large to small; divide the convolution layer into two independent groups, and use the parameter group definition to control the weight grouping of the convolution kernel channel direction;

[0033] (3) Calculate the group weight values ​​within each group, select the largest weight value, retain the connection, and define the rest as redundant connections and perform intra-group weight pruning on them;

[0034] (4) Determine whether each layer of the CNN network has been pruned. If it is completed, the optimized CNN network is obtained. If not, continue to execute step (2).

[0035] Furthermore, search optimization is performed in network models with large parameter sensitivity values, and the convolutional neural network is optimized with the sparrow search algorithm to obtain a training set. The obtained training set is used as the input of the fitness function. After multiple iterations, the maximum value of the fitness function is obtained, which is the optimal solution. Specifically, the following steps are performed:

[0036] 1) Obtain the performance of the processor under different design parameter configurations, compare their performance, and use the optimal parameter configuration as the benchmark design point in the search process;

[0037] 2) Initialize the initial population PO, the number of iterations N, the number of discoverers SD, the safety value ST, the warning value R2 in the sparrow search algorithm, set the fitness function and the convolutional neural network topology;

[0038] 3) Bring the benchmark design point into the fitness function calculation, update the position of the discoverer, the position of the follower, and update the optimal value;

[0039] 4) Determine whether the conditions are met. If so, use the optimal value to train the CNN network model and calculate the error between the predicted value and the true value. If not, continue to step 3). When the maximum number of iterations is reached, end the loop.

[0040] 5) Output the optimal solution set.

[0041] Further, in step 3),

[0042] The formula for updating the discoverer's position is as follows:

[0043]

[0044] Where Q is a random number that obeys the normal distribution, L is a unit row vector, and a is a random number in [0, 1].

[0045] The formula for updating the follower position is as follows:

[0046]

[0047] Among them, x worst is the position with the lowest fitness, and B is a row vector containing only two random elements, 1 and -1;

[0048] Fitness function model:

[0049] S=max(MSE trs，tes )

[0050] Among them, trs is the training set, tes is the test set, and MSE is the mean square error.

[0051] The existing search algorithms have the following defects:

[0052] (1) The design can only be evaluated based on a certain target response and the next design parameter configuration can be found based on its own search principle. However, this principle is usually blind and cannot effectively guide the selection of design points, resulting in excessive search iterations.

[0053] (2) Traditional technologies such as greedy search algorithms have search results that are greatly affected by the starting design. Once the starting design is determined, its greedy search characteristics can easily lead to falling into a local optimal solution and making it impossible to have an overview of the overall situation. For example, simulated annealing algorithms, although they can be applied to global optimization, are only applicable to continuous search spaces.

[0054] Compared with the existing technology, the principles and advantages of this solution are as follows:

[0055] This solution is based on search algorithm optimization and adds the use of autonomous learning algorithms to provide key information for the search algorithm and analyze parameter sensitivity in advance, making the search more efficient and the optimization effect better.

[0056] This solution uses the better convergence and search capabilities of the sparrow search algorithm to optimize the CNN structure, greatly improving the accuracy of the prediction model, shortening the simulation calculation time, reducing the cycle time of processor chip design, and optimizing the performance of the processor. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the services required for use in the embodiments or the prior art descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0058] Figure 1 Schematic diagram of the basic principles of a design space exploration method for a RI SC-V processor according to an embodiment of the present invention.

[0059] Figure 2 This is a flow chart of an autonomous learning algorithm for a design space exploration method for a RI SC-V processor according to an embodiment of the present invention.

[0060] Figure 3 This is a design space exploration flow chart of a design space exploration method for a RI SC-V processor according to an embodiment of the present invention. DETAILED DESCRIPTION

[0061] The present invention will be further described below in conjunction with specific embodiments:

[0062] like Figure 1 As shown, the design space exploration method of a RI SC-V processor described in this embodiment includes:

[0063] Using a pruning method based on an autonomous learning algorithm, the weights and parameter sensitivities of the critical paths are analyzed to obtain a network model.

[0064] Perform search optimization in the network model with large parameter sensitivity, and optimize the convolutional neural network with the sparrow search algorithm to obtain the training set;

[0065] The obtained training set is used as the input of the fitness function. After multiple iterations, the maximum value of the fitness function is the optimal solution.

[0066] Specifically, this embodiment includes the following steps:

[0067] S1, initialization phase:

[0068] Using an autonomous learning algorithm, unimportant connections and weights in a pre-trained model are selected, and an optimized network model is obtained based on the sensitivity of the parameters. This simplifies the neural network structure to a certain extent and reduces the computational effort of the design search algorithm on the network model. The design parameters in the sparrow search algorithm are initialized, and the network topology is determined based on the network scale parameters.

[0069] S2, sampling stage:

[0070] Using random sampling method, N sample values ​​are randomly selected from the design space obtained in the initialization phase as the input of the CNN network model in the training phase;

[0071] S3, training phase:

[0072] The sampled values ​​are put into the CNN network model optimized by the sparrow search algorithm for training to obtain a training set;

[0073] S4, prediction stage:

[0074] The training set is then loaded into the fitness function of the sparrow search algorithm to obtain a set of fitness function values ​​and sort them;

[0075] S5, iterative process:

[0076] Determine whether the end condition is met. If not, select the point with the largest fitness function value and repeat steps S2 to S4 until the iteration is completed;

[0077] S6. Output the maximum value of the fitness function as the optimal solution set, that is, the design space.

[0078] like Figure 2 As shown in the figure, the pruning method based on the autonomous learning algorithm is used to analyze the weights and parameter sensitivities of the critical paths and determine the network model, including:

[0079] (1 Initialize the autonomous learning algorithm and obtain the CNN pre-training model according to the predetermined parameters;

[0080] (2 After obtaining the CNN pre-training model, analyze the sensitivity of each layer of the CNN network and determine the pruning order according to the sensitivity from large to small; divide the convolution layer into two independent groups, and use the parameter group definition to control the weight grouping of the convolution kernel channel direction;

[0081] (3) Calculate the group weight values ​​within each group, select the largest weight value, retain the connection, and define the rest as redundant connections and perform intra-group weight pruning on them;

[0082] (4) Determine whether each layer of the CNN network has been pruned. If it is completed, the optimized CNN network is obtained. If not, continue to execute step (2);

[0083] like Figure 3 As shown in the figure, search optimization is performed on the optimized network model, and the convolutional neural network is optimized by combining the sparrow search algorithm to obtain a training set. The obtained training set is used as the input of the fitness function. After multiple iterations, the maximum value of the fitness function is obtained, which is the optimal solution. Specifically, it includes:

[0084] 1) Obtain the performance of the processor under different design parameter configurations, compare their performance, and use the optimal parameter configuration as the benchmark design point in the search process;

[0085] 2) Initialize the initial population PO, the number of iterations N, the number of discoverers SD, the safety value ST, the warning value R2 in the sparrow search algorithm, set the fitness function and the convolutional neural network topology;

[0086] 3) Bring the benchmark design point into the fitness function calculation, update the position of the discoverer, the position of the follower, and update the optimal value;

[0087] 4) Determine whether the conditions are met. If so, use the optimal value to train the CNN network model and calculate the error between the predicted value and the true value. If not, continue to step 3). When the maximum number of iterations is reached, end the loop.

[0088] 5) Output the optimal solution set.

[0089] Specifically, in the above step 3),

[0090] The formula for updating the discoverer's position is as follows:

[0091]

[0092] Where Q is a random number that obeys the normal distribution, L is a unit row vector, and a is a random number in [0, 1].

[0093] The formula for updating the follower position is as follows:

[0094]

[0095] Among them, x worst is the position with the lowest fitness, and B is a row vector containing only two random elements, 1 and -1;

[0096] Fitness function model:

[0097] S=max(MSE trs，tes )

[0098] Among them, trs is the training set, tes is the test set, and MSE is the mean square error.

[0099] The embodiments described above are only preferred embodiments of the present invention and are not intended to limit the scope of implementation of the present invention. Therefore, any changes made based on the shape and principle of the present invention should be included in the scope of protection of the present invention.

Claims

1. A design space exploration method for a RISC-V processor, characterized in that: The specific steps include: S1, initialization phase: Using the autonomous learning algorithm, the CNN network is pruned according to the sensitivity of the parameters, simplifying the neural network structure and reducing the computational effort of the design search algorithm on the network model; the design parameters in the sparrow search algorithm are initialized and the network topology is determined based on the network scale parameters; S2, sampling stage: Using random sampling method, N sample values ​​are randomly selected from the design space obtained in the initialization phase as the input of the CNN network model in the training phase; S3, training phase: The sampled values ​​are put into the CNN network model optimized by the sparrow search algorithm for training to obtain a training set; S4, prediction stage: The training set is then loaded into the fitness function of the sparrow search algorithm to obtain a set of fitness function values ​​and sort them; S5, iterative process: Determine whether the end condition is met. If not, select the point with the largest fitness function value and repeat steps S2 to S4 until the iteration is completed; S6. Output the maximum value of the fitness function as the optimal solution set; Using a pruning method based on an autonomous learning algorithm, the weights and parameter sensitivities of critical paths are analyzed to determine the network model, including: (1 Initialize the autonomous learning algorithm and obtain the CNN pre-training model according to the predetermined parameters; (2 After obtaining the CNN pre-training model, analyze the sensitivity of each layer of the CNN network and determine the pruning order according to the sensitivity from large to small; divide the convolution layer into two independent groups, and use the parameter group definition to control the weight grouping of the convolution kernel channel direction; (3) Calculate the group weight values ​​within each group, select the largest weight value, retain the connection, and define the rest as redundant connections and perform intra-group weight pruning on them; (4) Determine whether each layer of the CNN network has been pruned. If it is completed, the optimized CNN network is obtained. If not, continue to execute step (2); Search and optimize the network structure with high parameter sensitivity, and optimize the convolutional neural network with the sparrow search algorithm to obtain a training set. The obtained training set is used as the input of the fitness function. After multiple iterations, the maximum value of the fitness function is obtained, which is the optimal solution. Specifically, the following steps are performed: 1) Obtain the performance of the processor under different design parameter configurations, compare their performance, and use the optimal parameter configuration as the benchmark design point in the search process; 2) Initialize the initial population PO, the number of iterations N, the number of discoverers SD, the safety value ST, the warning value R2 in the sparrow search algorithm, set the fitness function and the convolutional neural network topology; 3) Bring the benchmark design point into the fitness function calculation, update the position of the discoverer, the position of the follower, and update the optimal value; 4) Determine whether the conditions are met. If so, use the optimal value to train the CNN network model and calculate the error between the predicted value and the true value. If not, continue to step 3). When the maximum number of iterations is reached, end the loop. 5) Output the optimal solution set.

2. The design space exploration method for a RISC-V processor according to claim 1, characterized in that: In step 3), The formula for updating the discoverer's position is as follows: Where Q is a random number that obeys the normal distribution, L is a unit row vector, and a is a random number in [0, 1]. The formula for updating the follower position is as follows: Among them, x worst is the position with the lowest fitness, and B is a row vector containing only two random elements, 1 and -1; Fitness function model: S=max(MSE trs，tes ) Among them, trs is the training set, tes is the test set, and MSE is the mean square error.

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