Pixel circuit, driving method thereof, and display panel

Abstract

The present invention discloses a pixel circuit, a driving method thereof, and a display panel. The pixel circuit includes: a data writing module, a main driving module, an auxiliary driving module, an access control module, and a light-emitting module; the data writing module is electrically connected to the main driving module; the access control module is electrically connected to the main driving module and the auxiliary driving module; the control end of the main driving module is electrically connected to the control end of the auxiliary driving module. The access control module is used to be turned on during the data writing phase, so that the data writing module transmits the data voltage to the control end of the main driving module through the multi-path parallel path formed by the main driving module and the auxiliary driving module; and is turned off during the light-emitting phase, so that the auxiliary driving module is disconnected from the path where the light-emitting module is located. The pixel circuit forms multiple data writing paths, so that the data voltage can be written more fully. And only the driving current generated by the main driving module is transmitted to the light-emitting module, so as to realize the driving of low-current devices.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a pixel circuit, a driving method thereof, and a display panel. Background Art

[0002] With the further development of organic light emitting diode (OLED) display devices, the iteration of OLED materials and the application of new OLED stacked devices, the power consumption of OLED display devices has been greatly reduced, and the current of OLED has become smaller and smaller.

[0003] OLED display devices include multiple driving modules, each containing a driving transistor that generates a driving current to drive the OLED to emit light. Reducing OLED power consumption and current consumption poses further challenges to the current control capabilities of the driving transistor.

[0004] In the prior art, precise control of current by the driving transistor is achieved by reducing the width-to-length ratio of the driving transistor. However, this results in poor display uniformity. Summary of the Invention

[0005] The present invention provides a pixel circuit, a driving method thereof, and a display panel, which can improve display uniformity while reducing the width-to-length ratio of a driving transistor to reduce driving current.

[0006] According to one aspect of the present invention, a pixel circuit is provided, comprising: a data writing module, a main driving module, an auxiliary driving module, an access control module and a light emitting module;

[0007] The data writing module is electrically connected to the main driving module; the access control module is electrically connected to the main driving module and the auxiliary driving module; the control end of the main driving module is electrically connected to the control end of the auxiliary driving module;

[0008] The access control module is used to be turned on during the data writing phase so that the data writing module transmits the data voltage to the control end of the main driving module through the multi-way parallel path formed by the main driving module and the auxiliary driving module; it is turned off during the light-emitting phase so that the auxiliary driving module is disconnected from the path where the light-emitting module is located; the main driving module is used to output a driving current according to the voltage of its own control end during the light-emitting phase to drive the light-emitting module to emit light.

[0009] Optionally, the data writing module includes a writing unit and a compensation unit, wherein the writing unit is connected between the data line and the first end of the main driving module, and the compensation unit is connected between the second end of the main driving module and the control end of the main driving module;

[0010] The access control module includes one or more access control units; at least one access control unit is connected between the data line and the first end of the auxiliary driving module, or at least one access control unit is connected between the first end of the main driving module and the first end of the auxiliary driving module, or at least one access control unit is connected between the writing unit and the first end of the main driving module, and the first end of the auxiliary driving module is connected to the first end of the main driving module via the access control unit connected to the writing unit;

[0011] And / or, at least one access control unit is connected between the second end of the auxiliary driving module and the control end of the main driving module, or, at least one access control unit is connected between the second end of the main driving module and the second end of the auxiliary driving module; or, at least one access control unit is connected between the compensation unit and the second end of the main driving module, and the second end of the auxiliary driving module is connected to the control end of the main driving module via the compensation unit;

[0012] Optionally, the control end of the access control unit, the control end of the writing unit, and the control end of the compensation unit are all electrically connected to the first scan line.

[0013] Optionally, the access control module includes an access control unit;

[0014] The access control unit is connected between the data line and the first end of the auxiliary driving module, or the access control unit is connected between the first end of the main driving module and the first end of the auxiliary driving module, or the access control unit is connected between the writing unit and the first end of the main driving module, and the first end of the auxiliary driving module is connected to the first end of the main driving module via the access control unit;

[0015] The second end of the auxiliary driving module is electrically connected to the second end or the control end of the main driving module;

[0016] Alternatively, the first end of the auxiliary driving module is electrically connected to the first end of the main driving module or the data line;

[0017] The access control unit is connected between the second end of the auxiliary driving module and the control end of the main driving module, or the access control unit is connected between the second end of the main driving module and the second end of the auxiliary driving module; or the access control unit is connected between the compensation unit and the second end of the main driving module, and the second end of the auxiliary driving module is connected to the control end of the main driving module via the compensation unit.

[0018] Optionally, the access control module includes a first access control unit and a second access control unit;

[0019] The first access control unit is connected between the data line and the first end of the auxiliary driving module, or the first access control unit is connected between the first end of the main driving module and the first end of the auxiliary driving module, or the first access control unit is connected between the writing unit and the first end of the main driving module, and the first end of the auxiliary driving module is connected to the first end of the main driving module via the first access control unit;

[0020] The second access control unit is connected between the second end of the auxiliary driving module and the control end of the main driving module, or the second access control unit is connected between the second end of the main driving module and the second end of the auxiliary driving module; or the second access control unit is connected between the compensation unit and the second end of the main driving module, and the second end of the auxiliary driving module is connected to the control end of the main driving module via the compensation unit.

[0021] Optionally, the main driving module includes a first transistor, the auxiliary driving module includes a second transistor, and the threshold voltage of the first transistor is the same as the threshold voltage of the second transistor.

[0022] Optionally, the pixel circuit further includes a storage module and a light emitting control module, wherein the storage module is connected to the control terminal of the main driving module and is used to store the voltage of the control terminal of the main driving module;

[0023] The light control module, the main driving module and the light emitting module are connected between the first power line and the second power line. The light control module is used to control the light emitting module to emit light according to the driving current output by the main driving module according to the signal on the light control signal line during the light control stage.

[0024] Optionally, the pixel circuit also includes an initialization module, which is used to write the initialization voltage provided by the initialization signal line into the control end of the main driving module and / or the first end of the light-emitting module according to the signal on the second scanning line during the initialization stage, and the second end of the light-emitting module is electrically connected to the second power line.

[0025] According to another aspect of the present invention, a driving method for a pixel circuit is provided, wherein the pixel circuit includes a data writing module, a main driving module, an auxiliary driving module, an access control module, and a light emitting module;

[0026] The data writing module is electrically connected to the main driving module; the access control module is electrically connected to the main driving module and the auxiliary driving module; the control end of the main driving module is electrically connected to the control end of the auxiliary driving module;

[0027] The driving method of the pixel circuit includes:

[0028] During the data writing phase, the access control module is controlled to be turned on so that the data writing module transmits the data voltage to the control terminal of the main driving module through the multi-path parallel path formed by the main driving module and the auxiliary driving module;

[0029] In the light-emitting stage, the access control module is controlled to be turned off to disconnect the path where the auxiliary drive module is located from the light-emitting module. The main drive module outputs a drive current according to the voltage of its own control terminal to drive the light-emitting module to emit light.

[0030] According to another aspect of the present invention, a display panel is provided, comprising any one of the above pixel circuits.

[0031] Optionally, the data writing module includes a writing unit and a compensation unit, the access control module includes a first access control unit and a second access control unit, the display panel includes a substrate, and an active layer and a plurality of conductive layers stacked on one side of the substrate, the first scan line and the data line are located in the conductive layer, and the conductive layer also includes a driving unit;

[0032] The active layer includes a first connection portion and a second connection portion extending along a first direction, one end of the first connection portion is connected to the data line, and one end of the second connection portion is connected to the driving portion;

[0033] The active layer further includes a first active portion and a second active portion, wherein the first active portion and the second active portion are both disposed between the first connecting portion and the second connecting portion and are respectively connected to the first connecting portion and the second connecting portion; the first active portion and the driving portion form a main driving module, and the second active portion and the driving portion form an auxiliary driving module;

[0034] In the first direction, there is a gap between the first active portion and the second active portion; the first scanning line includes a main portion extending along the second direction, a partial orthographic projection of the main portion on the substrate is located within the gap, the main portion overlaps with the first connecting portion to form a first access control unit, and the main portion overlaps with the second connecting portion to form a second access control unit;

[0035] The first scan line further includes a branch portion, which is located at least on a side of the second active portion away from the main portion. The branch portion overlaps with the first connection portion to form a writing unit, and overlaps with the second connection portion to form a compensation unit.

[0036] Optionally, the data writing module includes a writing unit and a compensation unit, the access control module includes a first access control unit and a second access control unit, the display panel includes a substrate, and an active layer and a plurality of conductive layers stacked on one side of the substrate, the first scan line and the data line are located in the conductive layer, and the conductive layer also includes a driving unit;

[0037] The active layer includes a first connection portion and a second connection portion extending along a first direction, one end of the first connection portion is connected to the data line, and one end of the second connection portion is connected to the driving portion;

[0038] The active layer further includes a first active portion and a second active portion, wherein the first active portion and the second active portion are both disposed between the first connecting portion and the second connecting portion and are respectively connected to the first connecting portion and the second connecting portion; the second active portion includes a first sub-active portion, a second sub-active portion, and a third sub-active portion connected in sequence, wherein the first sub-active portion and the third sub-active portion extend along a first direction, and the second sub-active portion extends along a second direction; the first active portion and the driving portion form a main driving module, and the second active portion and the driving portion form an auxiliary driving module;

[0039] The first scan line includes a main body portion extending along the second direction, a partial orthographic projection of the main body portion on the substrate is located between the first active portion and the second sub-active portion, the main body portion overlaps with the first connecting portion to form a writing unit, the main body portion overlaps with the first sub-active portion to form a first access control unit, the main body portion overlaps with the second connecting portion to form a compensation unit, and the main body portion overlaps with the third sub-active portion to form a second access control unit.

[0040] Optionally, the multi-layer conductive layer includes a first metal layer, a second metal layer and a third metal layer that are stacked together, the first scanning line is located in the first metal layer, the driving part is located in the second metal layer, the data line is located in the third metal layer, and the third metal layer also includes a connecting structure, and the second connecting part is connected to the driving part through the connecting structure.

[0041] A pixel circuit provided by an embodiment of the present invention includes: a data writing module, a main driver module, an auxiliary driver module, an access control module, and a light-emitting module; the data writing module is electrically connected to the main driver module; the access control module is electrically connected to the main driver module and the auxiliary driver module; and the control terminal of the main driver module is electrically connected to the control terminal of the auxiliary driver module. The access control module is configured to be turned on during the data writing phase, so that the data writing module forms multiple parallel paths through the main driver module and the auxiliary driver module to transmit a data voltage to the control terminal of the main driver module; and to be turned off during the light-emitting phase, so that the auxiliary driver module is disconnected from the path of the light-emitting module. The main driver module is configured to output a driving current based on the voltage at its control terminal during the light-emitting phase to drive the light-emitting module to emit light. By simultaneously writing data voltages to the control terminal of the main driver module through multiple paths, the voltage at the control terminal of the main driver module can be fully written even after reducing the aspect ratio of the transistors included in the main driver module, thereby reducing the driving current. This improves display uniformity. Furthermore, during the light-emitting phase, only the driving current generated by the main driver module is transmitted to the light-emitting module, which can reduce the driving current and enable driving low-current devices, thereby reducing power consumption.

[0042] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present invention, nor is it intended to limit the scope of the present invention. Other features of the present invention will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0044] Figure 1 It is a structural diagram of a pixel circuit;

[0045] Figure 2 is a structural schematic diagram of a pixel circuit provided by an embodiment of the present invention;

[0046] Figure 3 is a structural diagram of another pixel circuit provided by an embodiment of the present invention;

[0047] Figure 4 is a structural diagram of another pixel circuit provided by an embodiment of the present invention;

[0048] Figure 5 This is a driving timing diagram of a pixel circuit provided by an embodiment of the present invention;

[0049] Figure 6 is a structural diagram of another pixel circuit provided by an embodiment of the present invention;

[0050] Figure 7 is a structural diagram of another pixel circuit provided by an embodiment of the present invention;

[0051] Figure 8 is a structural diagram of another pixel circuit provided by an embodiment of the present invention;

[0052] Figure 9 is a structural diagram of another pixel circuit provided by an embodiment of the present invention;

[0053] Figure 10 is a structural diagram of another pixel circuit provided by an embodiment of the present invention;

[0054] Figure 11 is a structural diagram of another pixel circuit provided by an embodiment of the present invention;

[0055] Figure 12 is a structural diagram of another pixel circuit provided by an embodiment of the present invention;

[0056] Figure 13 is a structural diagram of another pixel circuit provided by an embodiment of the present invention;

[0057] Figure 14 is a structural diagram of another pixel circuit provided by an embodiment of the present invention;

[0058] Figure 15 is a structural diagram of another pixel circuit provided by an embodiment of the present invention;

[0059] Figure 16 is a structural diagram of another pixel circuit provided by an embodiment of the present invention;

[0060] Figure 17 is a structural diagram of another pixel circuit provided by an embodiment of the present invention;

[0061] Figure 18 is a structural diagram of another pixel circuit provided by an embodiment of the present invention;

[0062] Figure 19 is a structural diagram of another pixel circuit provided by an embodiment of the present invention;

[0063] Figure 20 is a structural diagram of another pixel circuit provided by an embodiment of the present invention;

[0064] Figure 21 is a structural diagram of another pixel circuit provided by an embodiment of the present invention;

[0065] Figure 22 is a structural diagram of another pixel circuit provided by an embodiment of the present invention;

[0066] Figure 23 is a structural diagram of another pixel circuit provided by an embodiment of the present invention;

[0067] Figure 24 is a structural diagram of another pixel circuit provided by an embodiment of the present invention;

[0068] Figure 25 1 is a schematic diagram of a layout of a pixel circuit provided by an embodiment of the present invention;

[0069] Figure 26 1 is a schematic structural diagram of an active layer of a pixel circuit provided by an embodiment of the present invention;

[0070] Figure 27 is a schematic diagram of a layout of another pixel circuit provided by an embodiment of the present invention;

[0071] Figure 28 This is a schematic structural diagram of an active layer and a first scanning line of a pixel circuit provided by an embodiment of the present invention;

[0072] Figure 29 is a structural schematic diagram of a display device provided by an embodiment of the present invention;

[0073] Figure 30This is a flowchart of a driving method for a pixel circuit provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0074] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0075] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0076] As described in the background art, in order to adapt to the low current drive of OLED display devices, the aspect ratio of the transistors included in the driving module, namely the driving transistors, is reduced, resulting in poor display uniformity. The inventors have found that the reason for the above problem is that as the driving transistors are used for a longer time, the threshold voltage of the driving transistors changes. The threshold voltage of the driving transistors needs to be compensated to avoid the display unevenness caused by different driving currents generated by different driving transistors at the same grayscale due to the change in threshold voltage. Figure 1The pixel circuit includes a storage capacitor Cst, a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a light-emitting module 5. The second transistor T2 is electrically connected to the data line Vdata. The fifth transistor T5, the first transistor T1, the sixth transistor T6, and the light-emitting module 5 are connected between a first power line Vdd and a second power line Vss. The fourth transistor T4 and the seventh transistor T7 are respectively electrically connected to an initialization signal line Vref. The gates of the second transistor T2 and the third transistor T3 are both connected to the first scan line Scan1. The gates of the fourth transistor T4 and the seventh transistor T7 are electrically connected to the second scan line Scan2. The gates of the fifth transistor T5 and the sixth transistor T6 are electrically connected to the emission control signal line EM. In the data writing phase, the second transistor T2 and the third transistor T3 are turned on in response to the signal on the first scan line Scan1. The first transistor T1 is also in the on state in the data writing phase. The turned-on second transistor T2 transmits the data voltage to the first electrode of the first transistor T1. The third transistor T3 transmits the voltage of the second electrode of the first transistor T1 to the gate of the first transistor T1, so that the voltage of the gate of the first transistor T1 is raised until it is raised to Vd-|Vth| (taking the first transistor T1 as a P-type transistor as an example). The compensation of the threshold voltage is completed, where Vd is the data voltage provided by the data line Vdata and Vth is the threshold voltage of the first transistor T1. The first transistor T1 generates a driving current based on its gate and the first electrode. μ is the electron mobility, Cox is the gate oxide capacitance per unit area, is the width-to-length ratio of the first transistor T1, V gs is the voltage difference between the gate and the first electrode of the first transistor T1, and V1 is the first power supply voltage provided by the first power line. As can be seen from the above formula, when the compensation is sufficient, the magnitude of the driving current is independent of the threshold voltage, thereby ensuring the consistency of the driving current. In order to reduce the magnitude of the driving current, the aspect ratio of the first transistor T1 can be reduced. However, when the aspect ratio of the first transistor T1 is reduced, the driving current decreases. Therefore, the charge flowing from the first electrode of the first transistor T1 to its second electrode per unit time decreases, and the compensation capability of the pixel circuit is reduced. As a result, during the data writing phase, the voltage of the gate of the first transistor T1 is insufficient to be raised to Vd-|Vth|. As a result, when the input data voltage is the same, different first transistors generate different driving currents and different luminous brightness, resulting in poor display uniformity.

[0077] In view of the above technical problems, the embodiment of the present invention provides a new pixel circuit. Figure 2, the pixel circuit includes: a data writing module 1, a main driving module 2, an auxiliary driving module 3, an access control module 4 and a light emitting module 5;

[0078] The data writing module 1 is electrically connected to the main driving module 2; the access control module 4 is electrically connected to the main driving module 2 and the auxiliary driving module 3, and the control terminal G1 of the main driving module 2 is electrically connected to the control terminal G2 of the auxiliary driving module 3;

[0079] The access control module 4 is used to be turned on during the data writing phase, so that the data writing module 1 transmits the data voltage to the control terminal of the main driving module 2 through the multi-path parallel path formed by the main driving module 2 and the auxiliary driving module 3; and turned off during the light-emitting phase, so that the auxiliary driving module 3 is disconnected from the path where the light-emitting module 5 is located;

[0080] The main driving module 2 is used to output a driving current according to the voltage of its own control terminal G in the light-emitting stage to drive the light-emitting module 5 to emit light.

[0081] The light-emitting module 5 can be a light-emitting diode, for example, an organic light-emitting diode (OLED), which emits light under the drive of a driving current. The data writing module 1 is also connected to the data line Vdata, which is used to provide a data voltage. Optionally, the pixel circuit also includes a light-emitting control module 6, and the light-emitting control module 6, the main driving module 2 and the light-emitting module 5 are connected between the first power line Vdd and the second power line Vss. The light-emitting control module 6 is used to control the light-emitting module 5 to emit light according to the drive current output by the main driving module 2 according to the signal on the light-emitting control signal line EM during the light-emitting phase. In this embodiment, the main driving module 2 and the auxiliary driving module 3 both include transistors, and the transistors included are all driving tubes. The access control module 4 and the data writing module 1 both act as switches. The light-emitting control module 6 acts as a switch. The access control module 4 is turned off during the light-emitting stage, and the path where the auxiliary driving module 3 and the light-emitting module 5 are located is disconnected. This can be: disconnecting the connection path between the auxiliary driving module 3 and the light-emitting module 5, and / or disconnecting the connection path between the auxiliary driving module 3 and the first power line Vdd, so that the auxiliary driving module 3 does not work, the auxiliary driving module 3 cannot generate a driving current, or even if a driving current is generated, it cannot be transmitted to the light-emitting module 5.

[0082] By controlling the on / off switching of the access control module 4, the auxiliary driver module 3 is controlled to function. By controlling the on / off switching of the access control module 4 to activate the auxiliary driver module 3, the pixel circuit can form multiple parallel pathways from the data line Vdata to the control terminal G1 of the main driver module 2 during the data write phase, thereby simultaneously writing the data voltage provided by the data line Vdata to the control terminal G1 of the main driver module 2. For example, one pathway can include the data line Vdata, the data write module 1, the access control module 4, and the main driver module 2 (note that in other embodiments, the access control module 4 is not required for this transmission path), and the other pathway can include the data line Vdata, the data write module 1, the auxiliary driver module 3, the access control module 4, and the control terminal G1 of the main driver module 2. Through these two parallel pathways, the data voltage is simultaneously written to the control terminal G1 of the main driver module 2 during the data write phase, ensuring that the voltage at the control terminal G1 of the main driver module 2 is fully written. During the light-emitting stage, the access control module 4 is controlled to be turned off so that the auxiliary driving module 3 will not work. The auxiliary driving module 3 cannot generate a driving current, or even if it generates a driving current, it cannot be transmitted to the light-emitting module, ensuring that only the driving current generated by the main driving module 2 is transmitted to the light-emitting module 5 to control the light-emitting module 5 to emit light.

[0083] In this embodiment, by controlling the access control module to be turned on, multiple data voltage writing paths are formed. Data voltages are simultaneously written to the control terminal of the main driver module through these multiple paths. This ensures that even after reducing the aspect ratio of the transistors included in the main driver module, which results in a reduction in drive current, sufficient voltage can still be written to the control terminal of the main driver module, thereby improving display uniformity. Furthermore, during the light-emitting phase, the access control module is controlled to be turned off, preventing the auxiliary driver module from generating drive current. Even if drive current is generated, it cannot be transmitted to the light-emitting module. Only the drive current generated by the main driver module is transmitted to the light-emitting module. This reduces the drive current, enables driving low-current devices, and reduces power consumption.

[0084] refer to Figure 3 Optionally, the data writing module includes a writing unit 11 and a compensation unit 12, wherein the writing unit 11 is connected between the data line Vdata and the first end S1 of the main driving module 2, and the compensation unit 12 is connected between the second end D1 of the main driving module 2 and the control end G1 of the main driving module 2.

[0085] The writing unit 11 and the compensation unit 12 function as switches. The control terminals of the writing unit 11 and the compensation unit 12 can be connected to the same scan line or different scan lines. During the data writing phase, the writing unit 11 and the compensation unit 12 can be turned on. During the light-emitting phase, the writing unit 11 and the compensation unit 12 can be turned off.

[0086] Optionally, the access control module includes one or more access control units 41; at least one access control unit 41 is connected between the data line and the first end S2 of the auxiliary driving module 3, or at least one access control unit 41 is connected between the first end S1 of the main driving module 2 and the first end S1 of the auxiliary driving module 2, or at least one access control unit 41 is connected between the writing unit 11 and the first end S1 of the main driving module 2, and the first end S2 of the auxiliary driving module 3 is connected to the first end S1 of the main driving module 2 via the access control unit 41 connected to the writing unit 11;

[0087] And / or, at least one access control unit 41 is connected between the second end D2 of the auxiliary driving module 3 and the control end G1 of the main driving module 2, or, at least one access control unit 41 is connected between the second end D1 of the main driving module 2 and the second end D2 of the auxiliary driving module 3; or, at least one access control unit 41 is connected between the compensation unit 12 and the second end D1 of the main driving module 2, and the second end D2 of the auxiliary driving module 3 is connected to the control end G1 of the main driving module 2 via the compensation unit 12.

[0088] The auxiliary driver module 3 and the main driver module 2 include transistors, each of which functions as a driver transistor. That is, the first terminal of the driver module charges its control terminal via its second terminal, causing the voltage at the control terminal to continuously change. For example, if the transistor included in the main driver module 2 is a P-type transistor, the voltage at the first terminal S1 of the main driver module 2 charges its control terminal G1 via its second terminal D1, raising the voltage at the control terminal G1 until the voltage difference between the control terminal G1 and the first terminal S1 of the main driver module 2 equals the threshold voltage of the main driver module 2, at which point the main driver module 2 is turned off. The access control unit 41 functions as a switch, directly connecting its two terminals (i.e., the first terminal and the second terminal of the access control unit 41) when turned on.

[0089] Optionally, at least one access control unit 41 is connected between the data line and the first terminal S2 of the auxiliary driver module 2. During the data writing phase, the access control unit 41 can be controlled to be turned on to transmit the data voltage to the first terminal S2 of the auxiliary driver module 3. During the light-emitting phase, the access control unit 41 can be controlled to be turned off to disconnect the path between the first terminal S2 of the auxiliary driver module 3 and the first power line Vdd, preventing the auxiliary driver module 3 from generating a driving current. In this connection scenario, for example, one data voltage writing path can be through the writing unit 11, the main driver module 2, and the compensation unit 12. That is, the data voltage is sequentially transmitted to the control terminal G1 of the main driver module 2 through the writing unit 11, the main driver module 2, and the compensation unit 12. Another data voltage writing path can be formed through the auxiliary driver module 3. Through one or more access control units 41 and the auxiliary driver module 3, another data voltage transmission path to the control terminal G1 of the main driver module 2 can be formed.

[0090] Optionally, at least one access control unit 41 is connected between the first terminal S1 of the main driver module 2 and the first terminal S2 of the auxiliary driver module 3. During the data writing phase, the access control unit 41 can be controlled to be turned on, so that the data voltage is transmitted to the first terminal S2 of the auxiliary driver module 3 via the write unit 11 and the access control unit 41. During the light-emitting phase, the access control unit 41 can be controlled to be turned off, disconnecting the path between the first terminal S2 of the auxiliary driver module 3 and the first power line Vdd, preventing the auxiliary driver module 3 from generating a driving current. In this connection scenario, one data voltage writing path can, for example, be through the write unit 11, the main driver module 2, and the compensation unit 12. That is, the data voltage is sequentially transmitted to the control terminal G1 of the main driver module 2 via the write unit 11, the main driver module 2, and the compensation unit 12. Another data voltage writing path can be formed through the auxiliary driver module 3. This path can be formed by the write unit 11, one or more access control units 41, and the auxiliary driver module 3 to transmit the data voltage to the control terminal of the main driver module 2.

[0091] Optionally, at least one access control unit 41 is connected between the write unit 11 and the first terminal S1 of the main driver module 2. The first terminal S2 of the auxiliary driver module 3 is connected to the first terminal S1 of the main driver module 2 via the access control unit 41 connected to the write unit 11. During the data writing phase, the access control unit 41 can be controlled to be on, so that the data voltage is transmitted to the first terminal S2 of the auxiliary driver module 3 via the write unit 11. During the light-emitting phase, the access control unit 41 can be controlled to be off, disconnecting the path between the first terminal S2 of the auxiliary driver module 3 and the first power line Vdd, preventing the auxiliary driver module 3 from generating a driving current. In this connection scenario, one data voltage transmission path can exemplarily be: the write unit 11, the access control unit 41, the main driver module 2, and the compensation unit 12. Another data voltage writing path can be formed through the auxiliary driver module 3. The data voltage is transmitted to the first terminal S2 of the auxiliary driver module 3 via the write unit 11. Another data voltage transmission path to the control terminal of the main driver module 2 can be formed through the write unit 11 and the auxiliary driver module 3.

[0092] Optionally, at least one access control unit 41 is connected between the second terminal D2 of the auxiliary driver module 3 and the control terminal G1 of the main driver module 2. During the data writing phase, the access control unit 41 is controlled to be on. After the data voltage is transmitted to the first terminal S2 of the auxiliary driver module 3, the data voltage at the first terminal S2 of the auxiliary driver module 3 charges its own second terminal, thereby transmitting the data voltage transmitted to the auxiliary driver module 3 to the control terminal G1 of the main driver module 2 via the access control unit 41. During the light-emitting phase, the access control unit 41 is controlled to be off, which can disconnect the path between the second terminal D2 of the auxiliary driver module 3 and the light-emitting module 5, preventing the auxiliary driver module from generating a driving current to transmit to the light-emitting module. In this connection scenario, one data voltage transmission path can be, for example, through the writing unit 11, the main driver module 2, and the compensation unit 12. Another data voltage writing path can be formed through the auxiliary driver module 3. The data voltage is transmitted to the first terminal S2 of the auxiliary driver module 3 via the writing unit 11. Another data voltage transmission path to the control terminal G1 of the main driver module 2 is formed through the writing unit 11, the auxiliary driver module 3, and the access control unit 41.

[0093] Optionally, at least one access control unit 41 is connected between the second terminal D1 of the main driver module 2 and the second terminal D2 of the auxiliary driver module 3. During the data writing phase, the access control unit 41 is controlled to be on. After the data voltage is transmitted to the first terminal S2 of the auxiliary driver module 3, the voltage at the first terminal S2 of the auxiliary driver module 3 charges its own second terminal. Furthermore, the access control unit 41 connected between the second terminal D1 of the main driver module 2 and the second terminal D2 of the auxiliary driver module 3 transmits the voltage at the second terminal D2 of the auxiliary driver module 3 to the control terminal G1 of the main driver module 2 via the compensation unit 12. During the light-emitting phase, the access control unit 41 is controlled to be off, which disconnects the path between the second terminal D2 of the auxiliary driver module 3 and the light-emitting module 5, preventing the drive current generated by the auxiliary driver module 3 from being transmitted to the light-emitting module 5. In this connection case, illustratively, a data voltage transmission path may be: the writing unit 11, the main driving module 2 and the compensation unit 12, and another data voltage writing path may be formed by the auxiliary driving module 3. The data voltage is transmitted to the first end S2 of the auxiliary driving module 3 through the writing unit 11, and another path for transmitting the data voltage to the control end G1 of the main driving module 2 may be formed through the writing unit 11, the auxiliary driving module 3, the access control unit 41 and the compensation unit 12.

[0094] Optionally, at least one access control unit 41 is connected between the compensation unit 12 and the second terminal D1 of the main driver module 2, and the second terminal D2 of the auxiliary driver module 3 is connected to the control terminal G1 of the main driver module 2 via the compensation unit 12. This is equivalent to at least one access control unit 41 being connected between the compensation unit 12 and the control terminal G1 of the main driver module 2, and the second terminal D2 of the auxiliary driver module 3 being connected to the control terminal G1 of the main driver module 2 via the access control unit 41 connected to the compensation unit 12. The circuit structure and operating principle are identical, and the only difference is the module name, and both are within the scope of protection of the present invention. During the data writing phase, the access control unit 41 is controlled to be turned on, and the data voltage transmitted to the first terminal of the main driver module G1 is sequentially written to the control terminal G1 of the main driver module 2 via the access control unit 41 and the compensation unit 12. At the same time, the data voltage at the first terminal S2 of the auxiliary driver module 3 is charged to its own second terminal, and the data voltage transmitted to the auxiliary driver module 3 is then transmitted to the control terminal G1 of the main driver module 2 via the access control unit 41 connected to the compensation unit 12. During the light-emitting phase, the access control unit 41 is controlled to be turned off, disconnecting the path between the second terminal D2 of the auxiliary driver module 2 and the light-emitting module 5, preventing the drive current generated by the auxiliary driver module from being transmitted to the light-emitting module. In this connection scenario, for example, one data voltage transmission path can be formed through the writing unit 11, the main driver module 2, the access control unit 41, and the compensation unit 12. Another data voltage writing path can be formed through the auxiliary driver module 3. The data voltage is transmitted to the first terminal S2 of the auxiliary driver module 3 through the writing unit 11. Another data voltage transmission path is formed through the auxiliary driver module 3 and the access control unit 41 to transmit the data voltage to the control terminal of the main driver module 2.

[0095] Figure 3 The figure is only an exemplary connection relationship of the pixel circuit, and Figure 3 The pixel circuit exemplarily includes two access control units 41 , one connected between the first end S1 of the main driving module 2 and the first end S2 of the auxiliary driving module 3 , and the other connected between the second end D2 of the auxiliary driving module 3 and the second end D1 of the main driving module 2 .

[0096] Continue to refer Figure 3 Optionally, the control end of the access control unit 41, the control end of the write unit 11, and the control end of the compensation unit 12 are all electrically connected to the first scan line Scan1. This reduces wiring complexity compared to when at least two of the control ends of the access control unit 41, the write unit 11, and the compensation unit 12 are connected to different scan lines. The access control unit 41, the write unit 11, and the compensation unit 12 can be turned on and off simultaneously. The access control unit 41, the write unit 11, and the compensation unit 12 can be turned on during the data writing phase and turned off during the light emitting phase.

[0097] Optionally, at least two of the control end of the access control unit 41, the control end of the write unit 11, and the control end of the compensation unit 12 are connected to the same scan line. Optionally, the control end of the access control unit 41, the control end of the write unit 11, and the control end of the compensation unit 12 are connected to three different scan lines.

[0098] Continue to refer Figure 3 Optionally, the pixel circuit further includes a storage module 7 , which is connected to the control terminal G1 of the main driving module 2 and is used to store the voltage of the control terminal G1 of the main driving module 2 .

[0099] Continue to refer Figure 3 Optionally, the pixel circuit further includes an initialization module 8, which is configured to write an initialization voltage provided by the initialization signal line Vref to the control terminal G1 of the main driving module 2 and / or the first terminal of the light-emitting module 5 according to the signal on the second scan line Scan2 during the initialization phase. The second terminal of the light-emitting module 5 is electrically connected to the second power line Vdd.

[0100] The initialization module 8 may initialize only the control terminal G1 of the main driver module 2, or may initialize only the first terminal of the light-emitting module 5, or may initialize both the control terminal G1 of the main driver module 2 and the first terminal of the light-emitting module 5. In this embodiment, the initialization module 8 initializes both the control terminal G1 of the main driver module 2 and the first terminal of the light-emitting module 5.

[0101] Exemplarily, the light control module includes a first light control unit 61 and a second light control unit 62, the first light control unit 61 is connected between the first power line Vdd and the first end S1 of the main driving module 2, and the second light control unit 62 is connected between the second end D1 of the main driving module 2 and the first end of the light emitting module 5.

[0102] The pixel circuit's operating process also includes an initialization phase before the data writing phase. During the initialization phase, the data writing module 1, access control module (i.e., one or more access control units 41), and light control module (i.e., first light control unit 61 and second light control unit 62) are all turned off, while the initialization module 8 is turned on. The turned-on initialization module 8 transmits an initialization voltage to the control terminal G1 of the main driver module 2 and the first terminal of the light-emitting module 5, completing the initialization of the main driver module 2 and the light-emitting module 5. This prevents any residual charge at the control terminal G1 of the main driver module 2 and the first terminal of the light-emitting module 5 from affecting the current frame.

[0103] Optionally, the access control module includes a first access control unit 401 and a second access control unit 402; the first access control unit 401 is connected between the data line Vdata and the first terminal S2 of the auxiliary driver module 3, or the first access control unit 401 is connected between the first terminal S1 of the main driver module 2 and the first terminal S2 of the auxiliary driver module 3, or the first access control unit 401 is connected between the write unit 11 and the first terminal S1 of the main driver module 2, with the first terminal S2 of the auxiliary driver module 3 connected to the first terminal S1 of the main driver module 2 via the first access control unit 401. The second access control unit 402 is connected between the second terminal D2 of the auxiliary driver module 3 and the control terminal G1 of the main driver module 2, or the second access control unit 402 is connected between the second terminal D1 of the main driver module 2 and the second terminal D2 of the auxiliary driver module 3; or the second access control unit 402 is connected between the compensation unit 12 and the control terminal G1 of the main driver module 2, with the second terminal D2 of the auxiliary driver module 3 connected to the control terminal G1 of the main driver module 2 via the second access control unit 402.

[0104] refer to Figure 4 Optionally, the access control module includes a first access control unit 401 and a second access control unit 402, the first access control unit 401 is connected between the data line Vdata and the first end S2 of the auxiliary driving module 3, and the second access control unit 402 is connected between the second end D1 of the main driving module 2 and the second end D2 of the auxiliary driving module 3. Figure 5 The timing diagram shown applies to Figure 4 The pixel circuit shown in FIG. 1 includes an initialization phase t1 , a data writing phase t2 and a light emitting phase t3 .

[0105] During initialization phase t1, the signals on the first scan line Scan1 and the light-emission control signal line EM are both off signals, for example, at a high level. The signal on the second scan line Scan2 is on signals, for example, at a low level. The signal on the first scan line Scan1 controls the write unit 11, the first access control unit 401, the second access control unit 402, and the compensation unit 12 to be off. The signal on the light-emission control signal line EM controls the first light-emission control unit 61 and the second light-emission control unit 62 to be off. The signal on the second scan line Scan2 controls the initialization module 8 to be on. The on-state initialization module 8 transmits the initialization voltage provided by the initialization signal line Vref to the first terminal of the light-emitting module 5 and the control terminal G1 of the main driver module 2, thereby initializing the first terminal of the light-emitting module 5 and the control terminal G1 of the main driver module 2. Because the control terminal G2 of the auxiliary driver module 3 is electrically connected to the control terminal G1 of the main driver module 2, the initialization voltage is also written to the control terminal G2 of the auxiliary driver module 3 during initialization phase t1.

[0106] During the data writing phase t2, the signals on the second scan line Scan2 and the light-emission control signal line EM are both off signals, for example, at a high level, while the signal on the first scan line Scan1 is on signals, for example, at a low level. The signal on the light-emission control signal line EM turns off the first and second light-emission control units 61 and 62. The signal on the second scan line Scan2 turns off the initialization module 8. The signal on the first scan line Scan1 turns on the first access control unit 401, the second access control unit 402, the write unit 11, and the compensation unit 12. The enabled write unit 11 transmits the data voltage to the first terminal S1 of the main driver module 2. The first terminal S1 of the main driver module 2 charges its second terminal D1 based on the data voltage transmitted by the write unit 11. The compensation unit 12 transmits the voltage at the second terminal D1 of the main driver module 2 to the control terminal G1 of the main driver module 2. Simultaneously, the enabled first access control unit 401 transmits the data voltage to the first terminal S2 of the auxiliary driver module 3. The first terminal S2 of the auxiliary driver module 3 charges its second terminal D2, causing the voltage at its second terminal D2 to continuously change. The turned-on second access control unit 402 transmits the voltage at the second terminal D2 of the auxiliary driver module 3 to the control terminal G1 of the main driver module 2 via the compensation unit 12. During the data writing phase t2, two paths exist for writing the data voltage to the control terminal G1 of the main driver module 2: one path involves the writing unit 11, the first terminal S1 of the main driver module 2, the second terminal D1 of the main driver module 2, the compensation unit 12, and the control terminal G1 of the main driver module 2; the other path involves the writing unit 11, the first access control unit 401, the auxiliary driver module 3, the second access control unit 402, the compensation unit 12, and the control terminal G1 of the main driver module 2. Both paths simultaneously write the data voltage and compensate for the threshold voltage during the data writing phase t2, ensuring more complete data voltage writing and threshold compensation.

[0107] During the light-emitting phase t3, the signals on the first scan line Scan1 and the second scan line Scan2 are both off signals, for example, at a high level, while the signal on the light-emitting control signal line EM is on signal, for example, at a low level. The signal on the first scan line Scan1 controls the first access control unit 401, the second access control unit 402, the writing unit 11, and the compensation unit 12 to be off. The signal on the second scan line Scan2 controls the initialization module 8 to be off. The signal on the light-emitting control signal line EM controls the first light-emitting control unit 61 and the second light-emitting control unit 62 to be on. The on-state first light-emitting control unit 61 transmits the first power supply voltage provided by the first power supply line Vdd to the first terminal S1 of the main driver module 2. The main driver module 2 generates a driving current based on the voltages at its first terminal S1 and the control terminal G1, and transmits the driving current to the light-emitting module 5, thereby driving the light-emitting module 5 to emit light. During the light-emitting phase t3, because the first access control unit 401, the second access control unit 402, and the writing unit 11 are turned off, the first power supply voltage on the first power line Vdd cannot be transmitted to the first terminal S2 of the auxiliary driving module 3. Therefore, the auxiliary driving module 3 cannot generate a driving current to transmit to the light-emitting module 5. In this embodiment, the pixel circuit drives the light-emitting module 5 only through the main driving module 2. The single driving module can reduce the driving current, facilitate the control of low-current devices, and reduce power consumption.

[0108] Figure 6 Corresponding to Figure 4 A specific circuit structure, refer to Figure 4 and Figure 6 Optionally, the main driving module 2 includes a first transistor T1, the auxiliary driving module 3 includes a second transistor T2, and the threshold voltage of the first transistor is the same as the threshold voltage of the second transistor.

[0109] The writing unit 11 includes a third transistor T3, the compensation unit 12 includes a fourth transistor T4, the first access control unit 401 includes a fifth transistor T5, and the second access control unit 402 includes a sixth transistor T6; the storage module 7 includes a storage capacitor Cst, the first light-emitting control unit 61 includes a seventh transistor T7, the second light-emitting control unit 62 includes an eighth transistor T8, and the initialization module 8 includes a ninth transistor T9 and a tenth transistor T10;

[0110] The first electrode of the first transistor T1 serves as the first terminal S1 of the main driving module 2, the second electrode of the first transistor T1 serves as the second terminal D1 of the main driving module 2, and the gate of the first transistor T1 serves as the control terminal G1 of the main driving module 2; the first electrode of the second transistor T2 serves as the first terminal S2 of the auxiliary driving module 3, the second electrode of the second transistor T2 serves as the second terminal D2 of the auxiliary driving module 3, and the gate of the second transistor T2 serves as the control terminal G2 of the auxiliary driving module 3; the first electrode of the third transistor T3 is electrically connected to the data line Vdata, the second electrode of the third transistor T3 is electrically connected to the first electrode of the first transistor T1, and the fourth transistor T3 is electrically connected to the data line Vdata. A first electrode of the transistor T4 is electrically connected to the second electrode of the first transistor T1, a second electrode of the fourth transistor T4 is electrically connected to the gate of the first transistor T1, a first electrode of the fifth transistor T5 is electrically connected to the data line Vdata, a second electrode of the fifth transistor T5 is electrically connected to the first electrode of the second transistor T2, a first electrode of the sixth transistor T6 is electrically connected to the second electrode of the second transistor T2, a second electrode of the sixth transistor T6 is electrically connected to the second electrode of the first transistor T1, and a gate of the third transistor T3, a gate of the fourth transistor T4, a gate of the fifth transistor T5, and a gate of the sixth transistor T6 are all electrically connected to the first scan line Scan1. A first electrode of the seventh transistor T7 is electrically connected to the first power supply line Vdd, a second electrode of the seventh transistor T7 is electrically connected to the first electrode of the first transistor T1, a first electrode of the eighth transistor T8 is electrically connected to the second electrode of the first transistor T1, a second electrode of the eighth transistor T8 is electrically connected to the first end of the light-emitting module 5, a gate of the seventh transistor T7 and a gate of the eighth transistor T8 are both electrically connected to the light-emitting control signal line EM, a first electrode of the ninth transistor T9 is electrically connected to the initialization signal line Vref, a second electrode of the ninth transistor T9 is electrically connected to the first end of the light-emitting module 5, a first electrode of the tenth transistor T10 is electrically connected to the initialization signal line Vref, a second electrode of the tenth transistor T10 is electrically connected to the gate of the first transistor T1, and a gate of the ninth transistor T9 and a gate of the tenth transistor T10 are both electrically connected to the second scan line Scan2.

[0111] In this embodiment, all transistors are P-type transistors. When the gate of the P-type transistor is at a high level, it is turned off, and when the gate is at a low level, it is turned on. Figure 5 The drive timing shown also applies to Figure 6 The pixel circuit shown in FIG. Figure 4The working process of the pixel circuit shown is the same or similar and will not be described in detail here. It is worth noting that in the data writing stage, when the gate potential of the first transistor T1 is raised to Vd-|Vth|, the compensation process ends, and the writing of the data voltage and the compensation of the threshold voltage are completed. Wherein, Vd is the data voltage and Vth is the threshold voltage of the first transistor T1. Optionally, all transistors may be N-type transistors. Optionally, some of the transistors are P-type transistors and the other part of the transistors are N-type transistors.

[0112] Figure 4 or Figure 6 In the pixel circuit shown, the first access control unit 401 (for example, may include a fifth transistor T5), the auxiliary driving module 3 (for example, may include a second transistor T2), and the second access control unit 402 (for example, may include a sixth transistor T6) are connected in series in sequence, so that the gate of the first transistor T1 has fewer leakage paths, which is conducive to maintaining the stability of the gate potential of the first transistor T1.

[0113] refer to Figure 7 Optionally, the first access control unit 401 (for example, may include a fifth transistor T5) may also be connected between the first terminal S1 of the main driving module 2 (for example, may include the first transistor T1) and the first terminal S2 of the auxiliary driving module 3 (for example, may include the second transistor T2), and the second access control unit 402 (for example, may include the sixth transistor T6) is connected between the second terminal D1 of the main driving module 2 and the second terminal D2 of the auxiliary driving module 3. Other structures and connection relationships are the same as Figure 6 Same or similar. Figure 7 The pixel circuit shown is Figure 6 The difference is that Figure 7 In the data writing phase of the pixel circuit, the data voltage is directly transmitted to the first terminal of the first access control unit 401 via the writing unit 11 (the third transistor T3). The other working processes are the same as those of the first access control unit 401. Figure 6 The operation process of the pixel circuit in FIG1 is the same or similar and will not be further described here. One data voltage transmission path can be formed through the writing unit 11, the main driving module 2, and the compensation unit 12. Another data voltage writing path can be formed through the auxiliary driving module 3. The writing unit 11, the first access control unit 401, the auxiliary driving module 3, the second access control unit 402, and the compensation unit 12 form another data voltage transmission path to the control terminal G1 of the main driving module 2. During the light-emitting phase, the first access control unit 401 and the second access control unit 402 are controlled to be turned off, thereby disconnecting the path between the first terminal S2 of the auxiliary driving module 3 and the first power line Vdd, and disconnecting the path between the second terminal D2 of the auxiliary driving module 3 and the light-emitting module 5.

[0114] Figure 7In the pixel circuit shown, the first access control unit 401 (fifth transistor T5), the auxiliary driving module 3 (for example, which may include the second transistor T2), and the second access control unit 402 (for example, which may include the sixth transistor T6) are connected in series in sequence, so that the gate of the first transistor T1 has fewer leakage paths, which is conducive to maintaining the stability of the gate potential of the first transistor T1.

[0115] refer to Figure 8 Optionally, the first access control unit 401 (for example, it may include a fifth transistor T5) may also be connected between the data line Vdata and the first end S2 of the auxiliary driving module 3 (for example, it may include a second transistor T2), and the second access control unit 402 (for example, it may include a sixth transistor T6) is connected between the control end G1 of the main driving module 2 and the second end D2 of the auxiliary driving module 2. Other structures and connection relationships are the same as Figure 6 The pixel circuits shown are the same or similar. Figure 8 The pixel circuit shown is Figure 6 The difference between the working process of the pixel circuit shown is that, in the data writing phase, the first access control unit 401 and the second access control unit 402 are controlled to be turned on, and the path formed through the auxiliary driving module 3 is: the data line Vdata, the first access control unit 401 (for example, may include a fifth transistor T5), the auxiliary driving module 3 (for example, may include a second transistor T2), the second access control unit 402 (for example, may include a sixth transistor T6), and the control terminal G1 of the main driving module 2 (for example, may include the first transistor T1). That is, the data voltage is sequentially transmitted to the control terminal G1 of the main driving module 2 (for example, may include the first transistor T1) through the first access control unit 401 (for example, may include a fifth transistor T5), the auxiliary driving module 3 (for example, may include a second transistor T2), and the second access control unit 402 (for example, may include a sixth transistor T6). The rest of the working process is the same as the above. Figure 6 The operation process of the pixel circuit in FIG. 1 is the same or similar and will not be described in detail here. During the light-emitting phase, the first access control unit 401 and the second access control unit 402 are controlled to be turned off, thereby disconnecting the path between the first terminal S2 of the auxiliary driver module 2 and the first power line Vdd, and disconnecting the path between the second terminal D2 of the auxiliary driver module 2 and the light-emitting module 5.

[0116] refer to Figure 9 Optionally, the first access control unit 401 (for example, may include a fifth transistor T5) may also be connected between the first terminal S1 of the main driving module 2 (for example, may include the first transistor T1) and the first terminal S2 of the auxiliary driving module 3 (for example, may include the second transistor T2), and the second access control unit 402 (for example, may include the sixth transistor T6) is connected between the second terminal D2 of the auxiliary driving module 3 and the control terminal G1 of the main driving module 2. Other structures and connection relationships are the same as those in FIG. Figure 6 The pixel circuits shown are the same or similar. Figure 9 The pixel circuit shown is Figure 6 The difference in the working process of the pixel circuit shown is that, in the data writing phase, the path formed by the auxiliary driving module 3 (for example, which may include the second transistor T2) is: the data line Vdata, the writing unit 11 (for example, which may include the third transistor), the first access control unit 401 (for example, which may include the fifth transistor T5), the auxiliary driving module 3 (for example, which may include the second transistor T2), the second access control unit 402 (for example, which may include the sixth transistor T6), and the control end of the main driving module 2 (for example, which may include the first transistor T1). That is, the data voltage is sequentially transmitted to the control end G1 of the main driving module 2 (for example, which may include the first transistor T1) through the writing unit 11 (for example, which may include the third transistor T3), the first access control unit 401 (for example, which may include the fifth transistor T5), the auxiliary driving module 3 (for example, which may include the second transistor T2), and the second access control unit 402 (for example, which may include the sixth transistor T6). The rest of the working process is the same as that of the embodiment. Figure 6 The working process of the pixel circuit in is the same or similar and will not be repeated here.

[0117] refer to Figure 10 Optionally, the first access control unit 401 (for example, may include a fifth transistor T5) is connected between the write unit 11 (for example, may include a third transistor T3) and the first end S1 of the main driving module 2 (for example, may include a first transistor T1), and the first end of the auxiliary driving module 3 (for example, may include a second transistor T2) is connected to the first end S1 of the main driving module 2 (for example, may include a first transistor T1) via the first access control unit 401. This is equivalent to the first access control unit 401 (for example, may include a fifth transistor T5) being connected between the data line Vdata and the first end of the auxiliary driving module 3 (for example, may include a second transistor T2), and the write unit 11 (for example, may include a third transistor T3) being connected between the first end S1 of the main driving module 2 (for example, may include a first transistor T1) and the first end of the auxiliary driving module 3 (for example, may include a second transistor T2). The circuit structure and working principle are the same, and the only difference is the module name. Both are within the scope of protection of the present invention, which is equivalent to converting Figure 10 The first access control unit 401 and the writing unit 11 in the embodiment are swapped. Figure 10The first end of the writing unit 11 is electrically connected to the data line Vdata, the second end of the writing unit 11 is electrically connected to the first end of the first access control unit 401, the first end of the first access control unit 401 is electrically connected to the first end S1 of the main driving module 2, the auxiliary driving module 3 and the second access control unit 402 are connected in series between the second end of the writing unit 11 and the control end G1 of the main driving module 2, the compensation unit 12 is connected between the second end D1 of the main driving module 2 and the control end G1, and the other structures and connection relationships are the same as those of the embodiment. Figure 6 The pixel circuits shown are the same or similar. Figure 10 The pixel circuit shown is Figure 6 The difference in the operation process of the pixel circuit shown is that, in the data writing phase, the path formed by the main driving module 2 (the first transistor T1) is: the data line Vdata, the writing unit 11 (for example, which may include the third transistor T3), the first access control unit 401 (for example, which may include the fifth transistor T5), the main driving module 2 (for example, which may include the first transistor T1), and the compensation unit 12 (for example, which may include the fourth transistor T4). That is, the data voltage is sequentially transmitted to the control terminal G1 of the main driving module 2 (the first transistor T1) through the writing unit 11 (for example, which may include the third transistor T3), the first access control unit 401 (for example, which may include the fifth transistor T5), the main driving module 2 (for example, which may include the first transistor T1), and the compensation unit 12 (for example, which may include the fourth transistor T4). At the same time, the path formed by the auxiliary driving module 3 (for example, including the second transistor T2) is: the data line Vdata, the write unit 11 (for example, including the third transistor T3), the auxiliary driving module 3 (for example, including the second transistor T2), the second access control unit 402 (for example, including the sixth transistor), and the control end of the main driving module 2 (for example, including the first transistor T1). That is, the data voltage is sequentially transmitted through the write unit 11 (for example, including the third transistor T3), the auxiliary driving module 3 (for example, including the second transistor T2), and the second access control unit 402 (for example, including the sixth transistor) to the control end G1 of the main driving module 2 (for example, including the first transistor T1). Other working processes are similar to Figure 6 The working process of the pixel circuit in is the same or similar and will not be repeated here.

[0118] refer to Figure 11Optionally, a first access control unit 401 (e.g., may include a fifth transistor T5) is connected between the write unit 11 (e.g., may include a third transistor T3) and the first terminal S1 of the main drive module 2 (e.g., may include a first transistor T1). The first terminal S2 of the auxiliary drive module 3 (e.g., may include a second transistor T2) is connected to the first terminal S1 of the main drive module 2 via the first access control unit 401 (e.g., may include a fifth transistor T5). A second access control unit 402 (e.g., may include a sixth transistor T6) is connected between the compensation unit 12 and the second terminal D1 of the main drive module 2. The second terminal D2 of the auxiliary drive module 3 is connected to the control terminal G1 of the main drive module 2 via the compensation unit 12. This is equivalent to the second access control unit 402 being connected between the compensation unit 12 and the control terminal G1 of the main drive module 2, and the second terminal D2 of the auxiliary drive module 3 being connected to the control terminal G1 of the main drive module 2 via the second access control unit 402. The circuit structure and operating principle are the same, and the only difference is the module name. Both fall within the scope of protection of the present invention, which is equivalent to replacing the second access control unit 402 with the compensation unit 12. Figure 11 The second access control unit 402 and the compensation unit 12 in the embodiment are swapped. Exemplarily, a first end of the write unit 11 is electrically connected to the data line Vdata, a second end of the write unit 11 is electrically connected to a first end of the first access control unit 401, a second end of the first access control unit 401 is electrically connected to a first end S1 of the main driving module 2, a first end of the auxiliary driving module 3 is electrically connected to a second end of the write unit 11, a second end of the auxiliary driving module 3 is electrically connected to a first end of the second access control unit 402, a second end of the second access control unit 402 is electrically connected to a second end D1 of the main driving module 2, a first end of the compensation unit 12 is electrically connected to a first end of the second access control unit 402, a second end of the compensation unit 12 is electrically connected to a second end D1 of the main driving module 2, and other structures and connection relationships are the same as those in FIG. Figure 6 The pixel circuits shown are the same or similar. Figure 11 The pixel circuit shown is Figure 6The difference in the operation process of the pixel circuit shown is that, in the data writing phase, the path formed by the main driving module 2 (first transistor T1) is: data line Vdata, writing unit 11 (third transistor T3), first access control unit 401 (fifth transistor T5), main driving module 2 (first transistor T1), second access control unit 402 (sixth transistor), and compensation unit 12 (fourth transistor T4). That is, the data voltage is sequentially transmitted to the control terminal G1 of the main driving module 2 (first transistor T1) via the writing unit 11 (third transistor T3), first access control unit 401 (fifth transistor T5), main driving module 2 (first transistor T1), second access control unit 402 (sixth transistor T6), and compensation unit 12 (fourth transistor T4). At the same time, the path formed by the auxiliary driving module 3 (second transistor T2) is: data line Vdata, writing unit 11 (third transistor T3), auxiliary driving module 3 (second transistor T2), compensation unit 12 (fourth transistor T4), that is, the data voltage is sequentially transmitted through the writing unit 11 (third transistor T3), auxiliary driving module 3 (second transistor T2), compensation unit 12 (fourth transistor T4) to the control terminal G1 of the main driving module 2 (first transistor T1). The rest of the working process is the same as Figure 6 The working process of the pixel circuit in is the same or similar and will not be repeated here.

[0119] refer to Figure 12 Optionally, the first access control unit 401 (for example, may include a fifth transistor T5) is connected between the writing unit 11 (for example, may include a third transistor T3) and the first terminal S1 of the main driving module 2 (for example, may include a first transistor T1). The first terminal of the auxiliary driving module 3 (for example, may include a second transistor T2) is connected to the first terminal S1 of the main driving module 2 (for example, may include a first transistor T1) via the first access control unit 401 (for example, may include a fifth transistor T5). The second access control unit 402 (sixth transistor T6) is connected between the second terminal D2 of the auxiliary driving module 3 and the second terminal D1 of the main driving module 2. Other structures and connection relationships are the same as those in FIG. Figure 6 The pixel circuits shown are the same or similar. Figure 12 The pixel circuit shown is Figure 6The difference in the operation process of the pixel circuit shown is that, during the data writing phase, the path formed by the main driving module 2 (for example, which may include the first transistor T1) is: the data line Vdata, the writing unit 11 (for example, which may include the third transistor T3), the first access control unit 401 (for example, which may include the fifth transistor T5), the main driving module 2 (for example, which may include the first transistor T1), and the compensation unit 12 (for example, which may include the fourth transistor T4). That is, the data voltage is sequentially transmitted to the control terminal G1 of the main driving module 2 (for example, which may include the first transistor T1) through the writing unit 11 (for example, which may include the third transistor T3), the first access control unit 401 (for example, which may include the fifth transistor T5), the main driving module 2 (for example, which may include the first transistor T1), and the compensation unit 12 (for example, which may include the fourth transistor T4). At the same time, the path formed by the auxiliary driving module 3 (for example, which may include the second transistor T2) is: data line Vdata, writing unit 11 (for example, which may include the third transistor T3), auxiliary driving module 3 (for example, which may include the second transistor T2), second access control unit 402 (for example, which may include the sixth transistor) and compensation unit 12 (for example, which may include the fourth transistor T4). That is, the data voltage is sequentially transmitted to the control terminal G1 of the main driving module 2 (for example, which may include the first transistor T1) through the writing unit 11 (for example, which may include the third transistor T3), auxiliary driving module 3 (for example, which may include the second transistor T2), second access control unit 402 (for example, which may include the sixth transistor) and compensation unit 12 (for example, which may include the fourth transistor T4). Other working processes are similar to Figure 6 The working process of the pixel circuit in is the same or similar and will not be repeated here.

[0120] Figures 6 to 12 This example illustrates a pixel circuit's access control module comprising a first access control unit and a second access control unit. It's worth noting that any combination of the first access control unit and the second access control unit, as long as they form a path from two data lines to the control terminal of the main driver module during the data writing phase, is encompassed by the present invention. During the data writing phase, the first access control unit 401 and the second access control unit 402 are controlled to conduct, forming a path from multiple data lines to the control terminal of the main driver module. During the light-emitting phase, the first access control unit 401 and the second access control unit 402 are controlled to shut down, disconnecting the path between the first terminal S2 of the auxiliary driver module 2 and the first power line Vdd, and disconnecting the path between the second terminal D2 of the auxiliary driver module 2 and the light-emitting module 5.

[0121] Optionally, there can be one or more auxiliary drive modules 2, and any auxiliary drive module 2 can be provided with a corresponding access control module. Multiple auxiliary drive modules 2 can form more data lines to the charging path of the control terminal of the main drive module during the data writing phase.

[0122] Optionally, the access control module includes an access control unit; the access control unit is connected between the data line and the first end of the auxiliary driver module, or between the first end of the main driver module and the first end of the auxiliary driver module, or between the write unit and the first end of the main driver module, with the first end of the auxiliary driver module connected to the first end of the main driver module via the access control unit; and the second end of the auxiliary driver module is electrically connected to the second end or control end of the main driver module. During the data writing phase, the access control unit is controlled to conduct, forming a path from the multiple data lines to the control end of the main driver module. During the light-emitting phase, the access control unit is controlled to shut down, disconnecting the path between the first end of the auxiliary driver module and the first power line.

[0123] Optionally, the access control module includes an access control unit; the first end of the auxiliary driver module is electrically connected to the first end or data line of the main driver module; the access control unit is connected between the second end of the auxiliary driver module and the control end of the main driver module, or the access control unit is connected between the second end of the main driver module and the second end of the auxiliary driver module; or the access control unit is connected between the compensation unit and the control end of the main driver module, with the second end of the auxiliary driver module connected to the control end of the main driver module via the access control unit. During the data writing phase, the access control unit is controlled to be turned on, forming a path from the multiple data lines to the control end of the main driver module. During the light-emitting phase, the access control unit is controlled to be turned off, which can disconnect the path between the second end of the auxiliary driver module and the light-emitting module.

[0124] refer to Figure 13 Optionally, the access control module includes an access control unit 403, which is connected between the data line Vdata and the first terminal S2 of the auxiliary driving module 3. The second terminal D2 of the auxiliary driving module 3 is electrically connected to the second terminal D1 of the main driving module 2. The access control unit 403 includes an eleventh transistor T11, wherein a first electrode of the eleventh transistor T11 is electrically connected to the data line Vdata, a second electrode of the eleventh transistor T11 is electrically connected to the first terminal S2 of the auxiliary driving module 3, and a gate of the eleventh transistor T11 is electrically connected to the first scan line Scan1. Figure 13 The structure and connection relationship of other modules in the pixel circuit shown are similar to Figure 6 The pixel circuits shown are the same or similar and will not be described again here. Figure 13 The working process of the pixel circuit shown is similar to Figure 6The difference in the working process of the pixel circuit shown is that: in the data writing stage, the data voltage is written into the control terminal G1 of the main driving module 2 (for example, including the first transistor T1) via the auxiliary driving module 3 (for example, including the second transistor T2). The transmission path is: the access control unit 403 (for example, including the eleventh transistor T11), the auxiliary driving module 3 (for example, including the second transistor T2), and the compensation unit 12 (for example, including the fourth transistor). That is, the data voltage is sequentially transmitted to the control terminal G1 of the main driving module 2 (for example, including the first transistor T1) via the access control unit 403 (for example, including the eleventh transistor T11), the auxiliary driving module 3 (for example, including the second transistor T2), and the compensation unit 12 (for example, including the fourth transistor T4). The other working processes are the same as those of FIG. Figure 6 The working process of the pixel circuit in is the same or similar and will not be repeated here.

[0125] refer to Figure 14 Optionally, the access control unit 403 is connected between the first terminal S1 of the main driving module 2 and the first terminal S2 of the auxiliary driving module 3 . The second terminal D2 of the auxiliary driving module 3 is electrically connected to the second terminal D1 of the main driving module 2 . Figure 14 The working process of the pixel circuit shown is similar to Figure 6 The difference in the working process of the pixel circuit shown is that: in the data writing stage, the data voltage is written to the control terminal G1 of the main driving module 2 (for example, including the first transistor T1) via the auxiliary driving module 3 (for example, including the second transistor T2). The transmission path is: the writing unit 111 (for example, including the third transistor T3), the access control unit 403 (for example, including the eleventh transistor T11), the auxiliary driving module 3 (for example, including the second transistor T2), and the compensation unit 12 (for example, including the fourth transistor T4). That is, the data voltage is sequentially transmitted to the control terminal G1 of the main driving module 2 (for example, including the first transistor T1) via the writing unit 111 (for example, including the third transistor T3), the access control unit 403 (for example, including the eleventh transistor T11), the auxiliary driving module 3 (for example, including the second transistor T2), and the compensation unit 12 (for example, including the fourth transistor T4). The other working processes are the same. Figure 6 The working process of the pixel circuit in is the same or similar and will not be repeated here.

[0126] refer to Figure 15 Optionally, the access control unit 403 is connected between the data line Vdata and the first terminal S2 of the auxiliary driving module 3. The second terminal D2 of the auxiliary driving module 3 is electrically connected to the control terminal G1 of the main driving module 2. Figure 15 The working process of the pixel circuit shown is similar to Figure 6The difference in the working process of the pixel circuit shown is that: in the data writing stage, the data voltage is written into the control terminal G1 of the main driving module 2 (for example, including the first transistor T1) via the auxiliary driving module 3 (for example, including the second transistor T2). The transmission path is: access control unit 403, (for example, including the eleventh transistor T11), auxiliary driving module 3 (for example, including the second transistor T2), that is, the data voltage is sequentially transmitted to the control terminal G1 of the main driving module 2 (for example, including the first transistor T1) via the access control unit 403 (for example, including the eleventh transistor T11) and the auxiliary driving module 3 (for example, including the second transistor T2). The other working processes are the same as those of FIG. Figure 6 The working process of the pixel circuit in is the same or similar and will not be repeated here.

[0127] refer to Figure 16 Optionally, the access control unit 403 is connected between the first terminal S1 of the main driving module 2 and the first terminal S2 of the auxiliary driving module 3. The second terminal D2 of the auxiliary driving module 3 is electrically connected to the control terminal G1 of the main driving module 2. Figure 16 The working process of the pixel circuit shown is similar to Figure 6 The difference in the working process of the pixel circuit shown is that: in the data writing stage, the data voltage is written to the control terminal G1 of the main driving module 2 (for example, including the first transistor T1) via the auxiliary driving module 3 (for example, including the second transistor T2). The transmission path is: the writing unit 11 (for example, including the third transistor T3), the access control unit 403 (for example, including the eleventh transistor T11), and the auxiliary driving module 3 (for example, including the second transistor T2). That is, the data voltage is sequentially transmitted to the control terminal G1 of the main driving module 2 (for example, including the first transistor T1) via the writing unit 11 (for example, including the third transistor T3), the access control unit 403 (for example, including the eleventh transistor T11), and the auxiliary driving module 3 (for example, including the second transistor T2). The other working processes are the same. Figure 6 The working process of the pixel circuit in is the same or similar and will not be repeated here.

[0128] refer to Figure 17Optionally, the access control unit 403 (for example, may include an eleventh transistor T11) is connected between the write unit 11 (for example, may include a third transistor T3) and the first end S1 of the main driving module 2 (for example, may include the first transistor T1), and the first end S2 of the auxiliary driving module 3 is connected to the first end S1 of the main driving module 2 via the access control unit 403 (the eleventh transistor T11). This is equivalent to the access control unit 403 (for example, may include the eleventh transistor T11) being connected between the data line Vdata and the first end of the auxiliary driving module 3 (for example, may include the second transistor T2), and the write unit 11 (for example, may include the third transistor T3) being connected between the first end S1 of the main driving module 2 (for example, may include the first transistor T1) and the first end of the auxiliary driving module 3 (for example, may include the second transistor T2). The circuit structure and working principle are the same, and the only difference is the module name. Both are within the scope of protection of the present invention, which is equivalent to the access control unit 403 (for example, may include the eleventh transistor T11) being connected between the data line Vdata and the first end of the auxiliary driving module 3 (for example, may include the second transistor T2). Figure 17 The access control unit 403 and the writing unit 11 are swapped. The second terminal D2 of the auxiliary driving module 3 is electrically connected to the control terminal G1 of the main driving module 2. Figure 17 The working process of the pixel circuit shown is similar to Figure 6 The difference between the working process of the pixel circuit shown is that: in the data writing stage, the transmission path of the data voltage written to the control terminal G1 of the main driving module 2 via the auxiliary driving module 3 is: writing unit 11, auxiliary driving module 3, that is, the data voltage is transmitted to the control terminal G1 of the main driving module 2 via the writing unit 111 and the auxiliary driving module 3 in sequence. The transmission path of the data voltage written to the control terminal G1 of the main driving module 2 via the main driving module 2 is: writing unit 11, access control unit 403 main driving module 2 and compensation unit 12, that is, the data voltage is transmitted to the control terminal G1 of the main driving module 2 via the writing unit 11, access control unit 403, main driving module 2 and compensation unit 12 in sequence. The other working processes are the same as Figure 6 The working process of the pixel circuit in is the same or similar and will not be repeated here.

[0129] refer to Figure 18 Optionally, the access control unit 403 (for example, may include an eleventh transistor T11) is connected between the writing unit 11 (for example, may include a third transistor T3) and the first end S1 of the main driving module 2 (for example, may include the first transistor T1), the first end S2 of the auxiliary driving module 3 is connected to the first end S1 of the main driving module 2 via the access control unit 403 (for example, may include the eleventh transistor T11), and the second end D2 of the auxiliary driving module 3 is electrically connected to the second end D1 of the main driving module 2. Figure 18 The working process of the pixel circuit shown is similar to Figure 6The difference in the working process of the pixel circuit shown is that: in the data writing stage, the data voltage is written to the control terminal G1 of the main driving module 2 (first transistor T1) via the auxiliary driving module 3 (second transistor T2) through the transmission path: the writing unit 11 (third transistor), the auxiliary driving module 3 (second transistor T2) and the compensation unit 12 (fourth transistor T4), that is, the data voltage is transmitted to the control terminal G1 of the main driving module 2 (first transistor T1) in sequence via the writing unit 111 (third transistor), the auxiliary driving module 3 (second transistor T2) and the compensation unit 12 (fourth transistor T4). The data voltage is written to the control terminal G1 of the main driving module 2 (first transistor T1) via the main driving module 2 (first transistor T1) via the transmission path: the writing unit 11 (third transistor), the access control unit 403 (eleventh transistor T11), the main driving module 2 (first transistor T1) and the compensation unit 12 (fourth transistor T4). That is, the data voltage is sequentially transmitted to the control terminal G1 of the main driving module 2 (first transistor T1) via the writing unit 11 (third transistor), the access control unit 403 (eleventh transistor T11), the main driving module 2 (first transistor T1) and the compensation unit 12 (fourth transistor T4). The rest of the working process is the same as Figure 6 The working process of the pixel circuit in is the same or similar and will not be repeated here.

[0130] refer to Figure 19 Optionally, the first terminal S2 of the auxiliary driving module 3 (the second transistor T2) is electrically connected to the first terminal S1 of the main driving module 2 (the first transistor T1). The access control unit 403 (the eleventh transistor T11) is connected between the compensation unit 12 (the fourth transistor T4) and the second terminal D1 of the main driving module 2 (the first transistor T1). The second terminal D2 of the auxiliary driving module 3 (the second transistor T2) is connected to the control terminal G1 of the main driving module 2 (the first transistor T1) via the compensation unit 12 (the fourth transistor T4). This is equivalent to the access control unit 403 being connected between the compensation unit 12 (the fourth transistor T4) and the control terminal G1 of the main driving module 2 (the first transistor T1). The second terminal D2 of the auxiliary driving module 3 (the second transistor T2) is connected to the control terminal of the main driving module 2 (the first transistor T1) via the access control unit 403 (the eleventh transistor T11). The circuit structure and working principle are the same, and the only difference is the module name. Both are within the scope of protection of the present invention, which is equivalent to the access control unit 403 being connected between the compensation unit 12 (the fourth transistor T4) and the control terminal G1 of the main driving module 2 (the first transistor T1). Figure 19 The access control unit 403 and the compensation unit 12 in the embodiment are swapped. Figure 19 The working process of the pixel circuit shown is similar to Figure 6The difference in the working process of the pixel circuit shown is that: in the data writing stage, the data voltage is written to the control terminal G1 of the main driving module 2 (first transistor T1) via the auxiliary driving module 3 (second transistor T2) through the transmission path: the writing unit 11 (third transistor T3), the auxiliary driving module 3 (second transistor T2) and the compensation unit 12 (fourth transistor T4), that is, the data voltage is transmitted to the control terminal G1 of the main driving module 2 (first transistor T1) in sequence via the writing unit 111 (third transistor T3), the auxiliary driving module 3 (second transistor T2) and the compensation unit 12 (fourth transistor T4). The data voltage is written to the control terminal G1 of the main driving module 2 (first transistor T1) via the main driving module 2 (first transistor T1) through the transmission path: the writing unit 11 (third transistor T3), the main driving module 2 (first transistor T1), the access control unit 403 (eleventh transistor T11) and the compensation unit 12 (fourth transistor T4). That is, the data voltage is sequentially transmitted to the control terminal G1 of the main driving module 2 (first transistor T1) via the writing unit 11 (third transistor T3), the main driving module 2 (first transistor T1), the access control unit 403 (eleventh transistor T11) and the compensation unit 12 (fourth transistor T4). The rest of the working process is the same as Figure 6 The working process of the pixel circuit in is the same or similar and will not be repeated here.

[0131] refer to Figure 20 Optionally, the first terminal S2 of the auxiliary driving module 3 (for example, including the second transistor T2) is electrically connected to the data line Vdata. The access control unit 403 (for example, including the eleventh transistor T11) is connected between the compensation unit 12 (for example, including the fourth transistor T4) and the second terminal D1 of the main driving module 2 (for example, including the first transistor T1). The second terminal D2 of the auxiliary driving module 3 (the second transistor T2) is connected to the control terminal G1 of the main driving module 2 (for example, including the first transistor T1) via the compensation unit 12 (for example, including the fourth transistor T4). This is equivalent to the access control unit 403 (for example, including the eleventh transistor T11) being connected between the compensation unit 12 (for example, including the fourth transistor T4) and the control terminal G1 of the main driving module 2 (for example, including the first transistor T1), and the second terminal D2 of the auxiliary driving module 3 (the second transistor T2) is connected to the control terminal G1 of the main driving module 2 (the first transistor T1) via the access control unit 403 (the eleventh transistor T11). The circuit structure and working principle are the same, and the only difference is the module name. Both are within the scope of protection of the present invention, which is equivalent to the access control unit 403 (for example, including the eleventh transistor T11) being connected between the compensation unit 12 (for example, including the fourth transistor T4) and the control terminal G1 of the main driving module 2 (for example, including the first transistor T1). Figure 20 The access control unit 403 and the compensation unit 12 in the embodiment are swapped. Figure 20 The working process of the pixel circuit shown is similar to Figure 6The difference in the working process of the pixel circuit shown is that: in the data writing stage, the data voltage is written into the control terminal G1 of the main driving module 2 (first transistor T1) via the auxiliary driving module 3 (second transistor T2) through the transmission path: the auxiliary driving module 3 (second transistor T2) and the access control unit 403 (eleventh transistor T11), that is, the data voltage is sequentially transmitted to the control terminal G1 of the main driving module 2 (first transistor T1) via the auxiliary driving module 3 (second transistor T2) and the access control unit 403 (eleventh transistor T11). The transmission path for the data voltage to be written to the control terminal G1 of the main driving module 2 (first transistor T1) via the main driving module 2 (first transistor T1) is: the writing unit 11 (for example, including the third transistor T3), the main driving module 2 (first transistor T1), the access control unit 403 (the eleventh transistor T11), and the compensation unit 12 (for example, including the fourth transistor T4). That is, the data voltage is sequentially transmitted to the control terminal G1 of the main driving module 2 (first transistor T1) via the writing unit 11 (the third transistor T3), the main driving module 2 (first transistor T1), the access control unit 403 (the eleventh transistor T11), and the compensation unit 12 (the fourth transistor T4). The rest of the working process is the same as Figure 6 The working process of the pixel circuit in is the same or similar and will not be repeated here.

[0132] refer to Figure 21 Optionally, the first end S2 of the auxiliary driving module 3 (for example, may include the second transistor T2) is electrically connected to the first end of the main driving module 2 (for example, may include the first transistor T1), and the access control unit 403 (for example, may include the eleventh transistor T11) is connected between the second end D1 of the main driving module 2 (for example, may include the first transistor T1) and the second end D2 of the auxiliary driving module (for example, may include the second transistor T2). Figure 21 The working process of the pixel circuit shown is similar to Figure 6The difference in the working process of the pixel circuit shown is that: in the data writing stage, the data voltage is written to the control terminal G1 of the main driving module 2 (for example, including the first transistor T1) via the auxiliary driving module 3 (the second transistor T2) through the transmission path: the writing unit 11 (for example, including the third transistor T3), the auxiliary driving module 3 (for example, including the second transistor T2), the access control unit 403 (for example, including the eleventh transistor T11), and the compensation unit 12 (for example, including the fourth transistor T4). That is, the data voltage is sequentially transmitted to the control terminal G1 of the main driving module 2 (for example, including the first transistor T1) through the writing unit 11 (for example, including the third transistor T3), the auxiliary driving module 3 (for example, including the second transistor T2), the access control unit 403 (for example, including the eleventh transistor T11), and the compensation unit 12 (for example, including the fourth transistor T4). The transmission path of the data voltage written to the control terminal G1 of the main driving module 2 (for example, including the first transistor T1) via the main driving module 2 (for example, including the first transistor T1) is the same as that of FIG. Figure 6 Same or similar, other work processes Figure 6 The working process of the pixel circuit in is the same or similar and will not be repeated here.

[0133] refer to Figure 22 Optionally, the first end S2 of the auxiliary driving module 3 (for example, may include the second transistor T2) is electrically connected to the data line Vdata, and the access control unit 403 (for example, may include the eleventh transistor T11) is connected between the second end D1 of the main driving module 2 (for example, may include the first transistor T1) and the second end D2 of the auxiliary driving module (for example, may include the second transistor T2). Figure 22 The working process of the pixel circuit shown is similar to Figure 6 The difference in the working process of the pixel circuit shown is that: in the data writing stage, the transmission path of the data voltage written to the control terminal G1 of the main driving module 2 via the auxiliary driving module 3 is: the auxiliary driving module 3, the access control unit 403 and the compensation unit 12, that is, the data voltage is transmitted to the control terminal G1 of the main driving module 2 via the auxiliary driving module 3, the access control unit 403 and the compensation unit 12 in sequence. The transmission path of the data voltage written to the control terminal G1 of the main driving module 2 via the main driving module 2 is the same as Figure 6 Same or similar, other work processes Figure 6 The working process of the pixel circuit in is the same or similar and will not be repeated here.

[0134] refer to Figure 23Optionally, the first end S2 of the auxiliary driving module 3 (for example, may include the second transistor T2) is electrically connected to the first end S1 of the main driving module 2 (for example, may include the first transistor T1), and the access control unit 403 (for example, may include the eleventh transistor T11) is connected between the second end D2 of the auxiliary driving module 3 (for example, may include the second transistor T2) and the control end G1 of the main driving module 2 (for example, may include the first transistor T1). Figure 23 The working process of the pixel circuit shown is similar to Figure 6 The difference in the working process of the pixel circuit shown is that: in the data writing stage, the transmission path of the data voltage written to the control terminal G1 of the main driving module 2 via the auxiliary driving module 3 is: the writing unit 11, the auxiliary driving module 3 and the access control unit 403, that is, the data voltage is transmitted to the control terminal G1 of the main driving module 2 via the writing unit 11, the auxiliary driving module 3 and the access control unit 403 in sequence. The transmission path of the data voltage written to the control terminal G1 of the main driving module 2 via the main driving module 2 is the same as Figure 6 Same or similar, other work processes are also Figure 6 The working process of the pixel circuit in is the same or similar and will not be repeated here.

[0135] refer to Figure 24 Optionally, the first end S2 of the auxiliary driving module 3 (for example, may include the second transistor T2) is electrically connected to the data line Vdata, and the access control unit 403 (for example, may include the eleventh transistor T11) is connected between the second end D2 of the auxiliary driving module (for example, may include the second transistor T2) and the control end G1 of the main driving module 2 (for example, may include the first transistor T1). Figure 24 The working process of the pixel circuit shown is similar to Figure 6 The difference in the working process of the pixel circuit shown is that: in the data writing stage, the transmission path of the data voltage written to the control terminal G1 of the main driving module 2 via the auxiliary driving module 3 is: data line Vdata, auxiliary driving module 3 and access control unit 403, that is, the data voltage is transmitted to the control terminal G1 of the main driving module 2 via the auxiliary driving module 3 and access control unit 403 in sequence. The transmission path of the data voltage written to the control terminal G1 of the main driving module 2 via the main driving module 2 is the same as Figure 6 Same or similar, other work processes are also Figure 6 The working process of the pixel circuit in is the same or similar and will not be repeated here.

[0136] Figures 13 to 24The exemplary embodiment of the pixel circuit's access control module includes an access control unit. It is worth noting that any combination of the access control unit connection method and the auxiliary driver module connection method is encompassed by the present invention, as long as the solution forms a path from at least two data lines to the control terminal of the main driver module during the data writing phase. During the light-emitting phase, the access control unit 403 is controlled to shut down, disconnecting the path between the first terminal S2 of the auxiliary driver module 2 and the first power line Vdd, or disconnecting the path between the second terminal D2 of the auxiliary driver module 2 and the light-emitting module 5.

[0137] An embodiment of the present invention further provides a display panel, comprising the pixel circuit in the above embodiment. The display panel has the same beneficial effects as the pixel circuit, which will not be described in detail herein.

[0138] Figure 26 The active layer shown corresponds to Figure 25 The active layer in Figure 25 The layout shown (equivalent to the schematic diagram of the orthographic projection of each film layer on the substrate) is suitable for Figure 7 The pixel circuit shown, refer to Figure 7 、 Figure 25 and Figure 26 Optionally, the data writing module includes a writing unit 11 and a compensation unit 12, the access control module includes a first access control unit 401 and a second access control unit 402, the display panel includes a substrate, and a stacked active layer 01 and a plurality of conductive layers located on one side of the substrate, the first scan line Scan1, the data line Vdata, the first power line Vdd and the second power line Vss are located in the conductive layer, and the conductive layer also includes a driving unit 02;

[0139] The active layer 01 includes a first connection portion 011 and a second connection portion 012 extending along a first direction X. One end of the first connection portion 011 is connected to the data line Vdata, one end of the second connection portion 012 is connected to the driving portion 02, the other end of the first connection portion 011 is connected to the first power line Vdd, and the other end of the second connection portion 012 is connected to the second power line Vss.

[0140] Active layer 01 also includes a first active portion 013 and a second active portion 014. Both first active portion 013 and second active portion 014 are disposed between and respectively connect first connecting portion 011 and second connecting portion 012. Second active portion 014 includes a first sub-active portion 0141, a second sub-active portion 0142, and a third sub-active portion 0143, which are sequentially connected. The first sub-active portion 0141 and the third sub-active portion 0143 extend along a first direction X, while the second sub-active portion 0142 extends along a second direction Y. The first active portion 013 and the driver portion 02 form a main driver module 2, while the second active portion 014 and the driver portion 02 form an auxiliary driver module 3. The first direction X intersects the second direction Y, and optionally, the first direction X is perpendicular to the second direction Y. Active layer 01 and the multiple conductive layers are stacked along a third direction (i.e., the thickness direction of the substrate). Optionally, the first direction X is perpendicular to the third direction. Optionally, the second direction Y is perpendicular to the third direction. An insulating layer may be provided between the conductive layers, and an insulating layer may be provided between the conductive layer and the active layer.

[0141] The first scan line Scan1 includes a main body extending along the second direction Y, and a partial orthographic projection of the main body on the substrate is located between the first active portion 013 and the second sub-active portion 0142. The main body overlaps with the first connecting portion 011 to form a writing unit 11, the main body overlaps with the first sub-active portion 0141 to form a first access control unit 401, the main body overlaps with the second connecting portion 012 to form a compensation unit 12, and the main body overlaps with the third sub-active portion 0143 to form a second access control unit 402.

[0142] Continue to refer Figure 7 、 Figure 25 and Figure 26The first active portion 013 includes a fourth sub-active portion 0131, a fifth sub-active portion 0132, a sixth sub-active portion 0133, a seventh sub-active portion 0134, and an eighth sub-active portion 0135, which are connected in sequence. The fourth sub-active portion 0131, the sixth sub-active portion 0133, and the eighth sub-active portion 0135 extend along the second direction Y, while the fifth sub-active portion 0132 and the seventh sub-active portion 0134 extend along the first direction X. The fourth sub-active portion 0131 is connected to the first connecting portion 011, and the eighth sub-active portion 0135 is connected to the second connecting portion 012. The first active portion 013 and the driving portion 02 form the main driving module 2, that is, the first transistor T1. The second active portion 014 and the driving portion 02 form the auxiliary driving module 3, that is, the second transistor T2. The main body overlaps with the first connecting portion 011 to form the writing unit 11, namely the third transistor T3. The main body overlaps with the first sub-active portion 0141 to form the first access control unit 401, namely the fifth transistor T5. The main body overlaps with the third sub-active portion 0143 to form the second access control unit 402, namely the sixth transistor T6. The main body overlaps with the second connecting portion 012 to form the compensation unit 12, namely the fourth transistor T4.

[0143] Continue to refer Figure 7 、 Figure 25 and Figure 26 The multi-layer conductive layer includes a first metal layer, a second metal layer and a third metal layer which are stacked together. The first scan line Scan1 is located in the first metal layer, the driving unit 02 is located in the second metal layer, and the data line Vdata is located in the third metal layer. The third metal layer also includes a connecting structure 05, and the second connecting unit 012 is connected to the driving unit 02 through the connecting structure.

[0144] In addition to the data line Vdata, the first power line Vdd and the second power line Vss are also located in the third metal layer. The driver unit 02 serves as one plate of the storage capacitor Cst. The other plate of the storage capacitor Cst is located in the third metal layer and is connected to the first power line Vdd. The connection structure 05 includes a first substructure extending along the first direction X and a second substructure extending along the second direction Y. The first substructure and the second substructure are connected, and the second substructure is connected to the second connection portion 012. The first substructure is connected to the driver unit 02. The connection structure 05 and the driver unit 02 are located in different metal layers. The connection can be achieved by punching. In this embodiment, the light control signal line EM connected to the control terminals of the first and second light control units 61 and 62 is also located in the first metal layer. The light control signal line EM overlaps with the first connection portion 011 to form the first light control unit 61, which is also the seventh transistor T7. The light control signal line EM overlaps with the second connection portion 012 to form the second light control unit 62, which is also the eighth transistor T8.

[0145] Figure 28 Corresponding to Figure 27 The active layer and the first scan line Scan1, Figure 27 The layout shown (equivalent to the schematic diagram of the orthographic projection of each film layer on the substrate) is suitable for Figure 11 The pixel circuit shown, refer to Figure 11 、 Figure 27 and Figure 28 Optionally, the data writing module includes a writing unit 11 and a compensation unit 12, the access control module includes a first access control unit 401 and a second access control unit 402, the display panel includes a substrate, and an active layer 01 and a plurality of conductive layers located on one side of the substrate and stacked along the thickness direction of the substrate, the first scan line Scan1 and the data line Vdata are located in the conductive layer, and the conductive layer also includes a driving unit 02;

[0146] The active layer 01 includes a first connection portion 011 and a second connection portion 012 extending along a first direction X. One end of the first connection portion 011 is connected to the data line Vdata, one end of the second connection portion 012 is connected to the driving portion 02, the other end of the first connection portion 011 is connected to the first power line Vdd, and the other end of the second connection portion 012 is connected to the second power line Vss.

[0147] The active layer 01 further includes a first active portion 013 and a second active portion 014. The first active portion 013 and the second active portion 014 are both disposed between the first connecting portion 011 and the second connecting portion 012 and are respectively connected to the first connecting portion 011 and the second connecting portion 012. The first active portion 013 and the driving portion 02 form a main driving module 2, and the second active portion 014 and the driving portion 02 form an auxiliary driving module 3.

[0148] In the first direction X, there is a distance between the first active portion 013 and the second active portion 014; the main portion 03 may be located between the first active portion 013 and the second active portion 014; the first scan line Scan1 includes the main portion 03 extending along the second direction Y; a partial orthographic projection of the main portion 03 on the substrate is located within the distance (or gap) between the first active portion 013 and the second active portion 014; the main portion 03 overlaps with the first connecting portion 011 to form a first access control unit 401; and the main portion 03 overlaps with the second connecting portion 012 to form a second access control unit 402;

[0149] The first scan line Scan1 further includes a branch portion 04 , which is at least located on a side of the second active portion 014 away from the main portion 03 . The branch portion 04 overlaps with the first connection portion 011 to form a writing unit 11 , and overlaps with the second connection portion 012 to form a compensation unit 12 .

[0150] Optionally, the middle portion of the first active portion 013 may be arched, with both ends of the first active portion 013 extending along the second direction Y. Optionally, the first active portion 013 includes a fourth sub-active portion 0131, a fifth sub-active portion 0132, a sixth sub-active portion 0133, a seventh sub-active portion 0134, and an eighth sub-active portion 0135, which are sequentially connected. The fourth sub-active portion 0131, the sixth sub-active portion 0133, and the eighth sub-active portion 0135 extend along the second direction Y, and the fifth sub-active portion 0132 and the seventh sub-active portion 0134 extend along the first direction X. The fourth sub-active portion 0131 is connected to the first connecting portion 011, and the eighth sub-active portion 0135 is connected to the second connecting portion 012. The second active portion 014 extends along the second direction Y. The first active portion 013 and the driver portion 02 form the main driver module 2, which also forms the first transistor T1. The driver portion 02 is equivalent to the gate of the first transistor T1. The second active portion 014 and the driver portion 02 form the auxiliary driver module 3, which is also the second transistor T2. The main portion 03 overlaps with the first connecting portion 011 to form the first access control unit 401, which is also the fifth transistor T5. The main portion 03 overlaps with the second connecting portion 012 to form the second access control unit 402, which is also the sixth transistor T6. The branch portion 04 overlaps with the first connecting portion 011 to form the write unit 11, which is also the third transistor T3. The branch portion 04 overlaps with the second connecting portion 012 to form the compensation unit 12, which is also the fourth transistor T4. The branch portion 04 includes a first sub-branch 041, a second sub-branch 042 and a third sub-branch 043 connected in sequence. The first sub-branch 041 and the third sub-branch 043 extend along the first direction X, and the second sub-branch 042 extends along the second direction Y. The first sub-branch 041 is connected to the main body portion 03, the third sub-branch 043 is connected to the main body portion 03, and the second sub-branch 042 is located on the side of the second active portion 014 away from the main body portion 03.

[0151] Continue to refer Figure 11 、 Figure 27 and Figure 28 Optionally, the multi-layer conductive layer includes a first metal layer, a second metal layer and a third metal layer that are stacked together, the first scan line Scan1 is located in the first metal layer, the driving unit 02 is located in the second metal layer, the data line Vdata is located in the third metal layer, and the third metal layer also includes a connecting structure 05, and the second connecting unit 012 is connected to the driving unit 02 through the connecting structure.

[0152] In addition to the data line Vdata, the first power line Vdd and the second power line Vss are also located in the third metal layer. The driver unit 02 can be reused as one plate of the storage capacitor Cst. The other plate of the storage capacitor Cst is located in the third metal layer and is connected to the first power line Vdd. The connection structure 05 includes a first substructure extending along the first direction X and a second substructure extending along the second direction Y. The first substructure and the second substructure are connected, and the second substructure is connected to the second connection unit 012. The second end of the second access control unit 402 is connected to the control terminal G1 of the main driver module 02 through the connection structure 05. The connection structure 05 and the driver unit 02 belong to different metal layers, and the connection can be achieved by punching. In this embodiment, the light-emitting control signal line EM connected to the control ends of the first light-emitting control unit 61 and the second light-emitting control unit 62 is also located in the first metal layer, and the light-emitting control signal line EM overlaps with the first connection portion 011 to form the first light-emitting control unit 61, that is, the seventh transistor T7, and the light-emitting control signal line EM overlaps with the second connection portion 012 to form the second light-emitting control unit 62, that is, the eighth transistor T8.

[0153] The present invention also provides a display device, referring to Figure 29 The display device 06 includes the display panel 07 in the above embodiment. The display device 06 can be Figure 29 The mobile phone shown may also be a computer, a television, a smart wearable display device, etc., and the embodiment of the present invention does not specifically limit this. The beneficial effects of the display device are the same as those of the display panel, and will not be repeated here.

[0154] The embodiment of the present invention further provides a driving method of a pixel circuit, referring to Figure 30 The pixel circuit includes a data writing module 1, a main driving module 2, an auxiliary driving module 3, an access control module 4 and a light emitting module 5; the data writing module 1 is electrically connected to the main driving module 2; the access control module 4 is electrically connected to the main driving module 2 and the auxiliary driving module 3; the control end of the main driving module 2 is electrically connected to the control end of the auxiliary driving module 3; the driving method of the pixel circuit includes:

[0155] S10: In the data writing phase, the access control module is controlled to be turned on, so that the data writing module transmits the data voltage to the control terminal of the main driving module through the multi-path parallel path formed by the main driving module and the auxiliary driving module.

[0156] During the data writing phase, access control module 4 forms multiple data voltage writing paths, including at least one path formed through main driver module 2 and at least one path formed through auxiliary driver module 3. Data voltages are simultaneously transmitted to the control terminal of main driver module 2 via multiple paths, enabling more complete data voltage writing. During the data writing phase, data writing module 1 can be turned on.

[0157] S20: During the light-emitting phase, the access control module is controlled to shut down, disconnecting the path between the auxiliary driver module and the light-emitting module. The main driver module then outputs a driving current based on the voltage at its control terminal, driving the light-emitting module to emit light. Specifically, during the light-emitting phase, by shutting down access control module 4, only the driving current generated by main driver module 2 is transmitted to light-emitting module 5. This single driver module reduces the driving current, facilitating the control of low-current devices. During the light-emitting phase, data writing module 1 may be shut down.

[0158] The driving method of the pixel circuit provided in the embodiment of the present invention is used to drive the pixel circuit provided in the above embodiment. The driving method of the pixel circuit provided in the embodiment of the present invention has the same beneficial effects as the pixel circuit, which will not be described in detail here.

[0159] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit them here. The above specific implementation methods do not constitute limitations on the scope of protection of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A pixel circuit, characterized in that: include: Data writing module, main driving module, auxiliary driving module, access control module and light emitting module; The data writing module is electrically connected to the main driving module; the access control module is electrically connected to the main driving module and the auxiliary driving module; the control end of the main driving module is electrically connected to the control end of the auxiliary driving module; The access control module is configured to be turned on during a data writing phase so that the data writing module transmits a data voltage to the control terminal of the main driving module through a multi-path parallel path formed by the main driving module and the auxiliary driving module; and turned off during a light-emitting phase so that the auxiliary driving module is disconnected from the path where the light-emitting module is located; The main driving module is used to output a driving current according to the voltage of its own control terminal in the light-emitting stage to drive the light-emitting module to emit light.

2. The pixel circuit according to claim 1, wherein: The data writing module includes a writing unit and a compensation unit, wherein the writing unit is connected between the data line and the first end of the main driving module, and the compensation unit is connected between the second end of the main driving module and the control end of the main driving module; The access control module includes one or more access control units; at least one of the access control units is connected between the data line and the first end of the auxiliary driving module, or at least one of the access control units is connected between the first end of the main driving module and the first end of the auxiliary driving module, or at least one of the access control units is connected between the writing unit and the first end of the main driving module, and the first end of the auxiliary driving module is connected to the first end of the main driving module via the access control unit connected to the writing unit; And / or, at least one of the access control units is connected between the second end of the auxiliary driving module and the control end of the main driving module, or, at least one of the access control units is connected between the second end of the main driving module and the second end of the auxiliary driving module; or, at least one of the access control units is connected between the compensation unit and the second end of the main driving module, and the second end of the auxiliary driving module is connected to the control end of the main driving module via the compensation unit.

3. The pixel circuit according to claim 2, wherein: The control end of the access control unit, the control end of the writing unit, and the control end of the compensation unit are all electrically connected to the first scan line.

4. The pixel circuit according to claim 2, wherein: The access control module includes an access control unit; The access control unit is connected between the data line and the first end of the auxiliary driving module, or the access control unit is connected between the first end of the main driving module and the first end of the auxiliary driving module, or the access control unit is connected between the writing unit and the first end of the main driving module, and the first end of the auxiliary driving module is connected to the first end of the main driving module via the access control unit; The second end of the auxiliary driving module is electrically connected to the second end or the control end of the main driving module; Alternatively, the first end of the auxiliary driving module is electrically connected to the first end of the main driving module or the data line; The access control unit is connected between the second end of the auxiliary driving module and the control end of the main driving module, or the access control unit is connected between the second end of the main driving module and the second end of the auxiliary driving module; or the access control unit is connected between the compensation unit and the second end of the main driving module, and the second end of the auxiliary driving module is connected to the control end of the main driving module via the compensation unit.

5. The pixel circuit according to claim 2, wherein: The access control module includes a first access control unit and a second access control unit; The first access control unit is connected between the data line and the first end of the auxiliary driving module, or the first access control unit is connected between the first end of the main driving module and the first end of the auxiliary driving module, or the first access control unit is connected between the writing unit and the first end of the main driving module, and the first end of the auxiliary driving module is connected to the first end of the main driving module via the first access control unit; The second access control unit is connected between the second end of the auxiliary driving module and the control end of the main driving module, or the second access control unit is connected between the second end of the main driving module and the second end of the auxiliary driving module; or the second access control unit is connected between the compensation unit and the second end of the main driving module, and the second end of the auxiliary driving module is connected to the control end of the main driving module via the compensation unit.

6. The pixel circuit according to any one of claims 1 to 5, characterized in that: The main driving module includes a first transistor, and the auxiliary driving module includes a second transistor. The threshold voltage of the first transistor is the same as the threshold voltage of the second transistor.

7. The pixel circuit according to claim 6, wherein: The pixel circuit further includes a storage module and a light emitting control module, wherein the storage module is connected to the control terminal of the main driving module and is used to store the voltage of the control terminal of the main driving module; The light-emitting control module, the main driving module and the light-emitting module are connected between a first power line and a second power line. The light-emitting control module is used to control the light-emitting module to emit light according to the driving current output by the main driving module according to the signal on the light-emitting control signal line during the light-emitting control stage.

8. The pixel circuit according to claim 7, wherein: The pixel circuit also includes an initialization module, which is used to write the initialization voltage provided by the initialization signal line into the control end of the main driving module and / or the first end of the light-emitting module according to the signal on the second scanning line during the initialization stage, and the second end of the light-emitting module is electrically connected to the second power line.

9. A method for driving a pixel circuit, characterized in that: The pixel circuit includes a data writing module, a main driving module, an auxiliary driving module, an access control module and a light emitting module; The data writing module is electrically connected to the main driving module; the access control module is electrically connected to the main driving module and the auxiliary driving module; The control end of the main driving module is electrically connected to the control end of the auxiliary driving module; The driving method of the pixel circuit includes: During the data writing phase, the access control module is controlled to be turned on so that the data writing module transmits a data voltage to the control terminal of the main driving module through the multi-path parallel path formed by the main driving module and the auxiliary driving module; In the light-emitting stage, the access control module is controlled to be turned off to disconnect the auxiliary driving module from the path where the light-emitting module is located, and the main driving module outputs a driving current according to the voltage of its own control terminal to drive the light-emitting module to emit light.

10. A display panel, characterized in that: The pixel circuit comprises the pixel circuit according to any one of claims 1 to 8.

11. The display panel according to claim 10, wherein: The data writing module includes a writing unit and a compensation unit, the access control module includes a first access control unit and a second access control unit, the display panel includes a substrate, and an active layer and a plurality of conductive layers stacked on one side of the substrate, the first scan line and the data line are located in the conductive layer, and the conductive layer also includes a driving unit; The active layer includes a first connection portion and a second connection portion extending along a first direction, one end of the first connection portion is connected to the data line, and one end of the second connection portion is connected to the driving portion; The active layer further includes a first active portion and a second active portion, wherein the first active portion and the second active portion are both disposed between the first connecting portion and the second connecting portion and are respectively connected to the first connecting portion and the second connecting portion; the first active portion and the driving portion form the main driving module, and the second active portion and the driving portion form the auxiliary driving module; In the first direction, there is a distance between the first active portion and the second active portion; the first scan line includes a main portion extending along the second direction, a partial orthographic projection of the main portion on the substrate is located within the distance, the main portion overlaps with the first connecting portion to form the first access control unit, and the main portion overlaps with the second connecting portion to form the second access control unit; The first scan line further includes a branch portion, which is located at least on a side of the second active portion away from the main portion. The branch portion overlaps with the first connecting portion to form the writing unit, and the branch portion overlaps with the second connecting portion to form the compensation unit.

12. The display panel according to claim 10, wherein: The data writing module includes a writing unit and a compensation unit, the access control module includes a first access control unit and a second access control unit, the display panel includes a substrate, and an active layer and a plurality of conductive layers stacked on one side of the substrate, the first scan line and the data line are located in the conductive layer, and the conductive layer also includes a driving unit; The active layer includes a first connection portion and a second connection portion extending along a first direction, one end of the first connection portion is connected to the data line, and one end of the second connection portion is connected to the driving portion; The active layer further includes a first active portion and a second active portion, wherein the first active portion and the second active portion are both disposed between the first connecting portion and the second connecting portion and are respectively connected to the first connecting portion and the second connecting portion; the second active portion includes a first sub-active portion, a second sub-active portion, and a third sub-active portion connected in sequence, wherein the first sub-active portion and the third sub-active portion extend along the first direction, and the second sub-active portion extends along the second direction; the first active portion and the driving portion form the main driving module, and the second active portion and the driving portion form the auxiliary driving module; The first scan line includes a main body portion extending along the second direction, a partial orthographic projection of the main body portion on the substrate is located between the first active portion and the second sub-active portion, the main body portion overlaps with the first connecting portion to form the writing unit, the main body portion overlaps with the first sub-active portion to form the first access control unit, the main body portion overlaps with the second connecting portion to form the compensation unit, and the main body portion overlaps with the third sub-active portion to form the second access control unit.

13. The display panel according to claim 11 or 12, wherein: The multi-layer conductive layer includes a first metal layer, a second metal layer and a third metal layer which are stacked together. The first scanning line is located in the first metal layer, the driving part is located in the second metal layer, and the data line is located in the third metal layer. The third metal layer also includes a connecting structure, and the second connecting part is connected to the driving part through the connecting structure.

Images