Display device, backlight module driving circuit and driving method thereof

Abstract

The present disclosure relates to a display device and a backlight module driving circuit and method thereof. A driving circuit includes first to seventh transistors, a first capacitor and a second capacitor. The first transistor is coupled to a first node and receives a data voltage. The second transistor receives an initial voltage and is coupled to a second node. The third transistor is coupled to the first node and a third node. The fourth transistor is coupled to the second node and a fourth node. The fifth transistor receives a reference voltage and is coupled to the third node. The sixth transistor receives a ground voltage and is coupled to the fourth node. The seventh transistor is coupled to the third node, the fourth node and the second node. The first capacitor is coupled between the first node and the second node. The second capacitor is coupled between the initial voltage and the first node.

Description

Technical Field

[0001] This disclosure relates to a driving circuit and driving method, and more particularly to a driving circuit and driving method for a backlight module in a display device. Background Technology

[0002] In LCD displays using micro-LED backlight modules, multiple light-emitting areas are typically distributed across the backlight module. During the driving of the backlight module, each light-emitting area receives a corresponding driving voltage from the scanning circuit in a time-sharing manner. Whenever the scanning circuit provides a driving voltage to the light-emitting area, the data circuit provides corresponding data to the light-emitting area that received the driving voltage, causing the light-emitting area to emit light at a preset brightness.

[0003] However, the aforementioned backlight module driving method requires a large number of integrated circuits, and the number of integrated circuits increases with the number of light-emitting areas. Furthermore, with a large number of light-emitting areas, the duty ratio of each area is low, resulting in a need to provide a larger driving current to the backlight module to maintain the preset brightness. All of these factors further increase the cost of the LCD display. Summary of the Invention

[0004] One embodiment of this disclosure is a driving circuit. The driving circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, a first capacitor, and a second capacitor. A first terminal of the first transistor is coupled to a first node, and a second terminal of the first transistor receives a data voltage. A first terminal of the second transistor receives an initial voltage, and a second terminal of the second transistor is coupled to a second node. A first terminal of the third transistor is coupled to a third node, and a second terminal of the third transistor is coupled to the first node. A first terminal of the fourth transistor is coupled to the second node, and a second terminal of the fourth transistor is coupled to a fourth node. A first terminal of the fifth transistor receives a reference voltage, and a second terminal of the fifth transistor is coupled to the third node. A first terminal of the sixth transistor receives a ground voltage, and a second terminal of the sixth transistor is coupled to the fourth node. A first terminal of the seventh transistor is coupled to the third node, a second terminal of the seventh transistor is coupled to the fourth node, and a control terminal of the seventh transistor is coupled to the second node. The first capacitor is coupled between the first node and the second node. The second capacitor is coupled between the initial voltage and the first node.

[0005] Another embodiment of this disclosure is a display device. The display device includes a backlight module, a liquid crystal panel, and the aforementioned driving circuit. The liquid crystal panel is located on one side of the backlight module. The driving circuit is coupled to the backlight module at the third node and is used to drive the backlight module to emit light, causing the liquid crystal panel to display an image.

[0006] Another aspect of this disclosure is a driving method for a backlight module. This driving method includes: in a first period, writing a data voltage to a first node coupled between the data writing circuit and a light-emitting control circuit via a data writing circuit, and resetting a second node coupled between the reset circuit and a current-generating circuit to an initial voltage via a reset circuit; in a second period, compensating the second node from the initial voltage to a compensated voltage by turning on a compensation circuit; and in a third period, coupling the data voltage to the second node by turning on the light-emitting control circuit, so that the current-generating circuit generates a driving current to a light-emitting element of the backlight module according to an operating voltage.

[0007] In summary, by designing the driving circuit on the glass substrate, the driving circuit and driving method disclosed herein do not require the use of a large number of integrated circuits to drive the backlight module. This makes it suitable for backlight modules with high current requirements and allows for flexible adjustment of the duty cycle of the light-emitting area in the backlight module, thereby further enabling the display device to have the advantages of reduced cost and power consumption. Attached Figure Description

[0008] Figure 1 A block diagram illustrating a display device according to some embodiments of the present disclosure is provided.

[0009] Figure 2 A block diagram of a backlight module and driving circuit is shown for some embodiments according to the present disclosure.

[0010] Figure 3 A circuit diagram of a backlight module and a driving circuit is shown for some embodiments according to this disclosure.

[0011] Figure 4 A signal timing diagram of a display device in gating mode is illustrated according to some embodiments of the present disclosure.

[0012] Figures 5A to 5D The following diagram illustrates the operation of a drive circuit during different periods according to some embodiments of the present disclosure.

[0013] Figure 6 A block diagram of a backlight module and driving circuit is shown for some other embodiments according to this disclosure.

[0014] Figure 7A circuit diagram of a backlight module and driving circuit is shown for some other embodiments according to this disclosure.

[0015] Figure 8 A signal timing diagram of a display device in scanning mode is illustrated according to some embodiments of the present disclosure.

[0016] Figures 9A to 9C The following diagram illustrates the operation of a drive circuit during different periods according to some embodiments of the present disclosure.

[0017] The reference numerals in the attached figures are explained as follows:

[0018] 10: Drive circuit

[0019] 20: Backlight Module

[0020] 30: LCD panel

[0021] 40: Glass substrate

[0022] 50: Flexible connector

[0023] 100: Display device

[0024] 101, 103: Sub-circuits

[0025] 110: Data writing circuit

[0026] 112: Reset Circuit

[0027] 114: Light-emitting control circuit

[0028] 116: Compensation Circuit

[0029] 118: Current generating circuit

[0030] 120: Holding circuit

[0031] 201[1], 201[2], 201

[12] , 201

[13] , 201

[24] : Light-emitting element

[0032] 203: Circuit board

[0033] T1, T2, T3, T4, T5, T6, T7, T8: Transistors

[0034] C1, C2: Capacitors

[0035] A, B, C, D: Nodes

[0036] SW[1], SW[2]: Switching elements

[0037] Mst: Gantt Mode

[0038] Msc: Scan Mode

[0039] TMst, TMsc: Signal timing diagrams

[0040] TIst, TIsc: Data write time

[0041] TRst, TRsc: Liquid crystal response time

[0042] S1[n-1]: First control signal

[0043] S1[n]: Second control signal

[0044] S1[n+1]: Third control signal

[0045] S2[n]: Fourth control signal

[0046] EM, EM[n]: Light emission control signals

[0047] VCC1, VCC2, VCC12, VCC13, VCC23, VCC24: Drive voltage

[0048] R1, R2, R12, R13, R23, R24: Driving regions

[0049] VDATA: Data voltage

[0050] VINI: Initial voltage

[0051] VREF: Reference Voltage

[0052] VCP: Compensation Voltage

[0053] VW: Operating voltage

[0054] VLED: Voltage Difference

[0055] Vth: Critical Voltage

[0056] GND: Grounding voltage

[0057] Id: Drive current

[0058] F[n-1], F[n], F[n+1]: Frame time

[0059] P1, P2, P3, P4: Period Detailed Implementation

[0060] The following is a detailed description of the embodiments in conjunction with the accompanying drawings. However, the specific embodiments described are only for explaining this case and are not intended to limit this case. The description of the structural operations is not intended to limit the order of their execution. Any structure that is recombined with elements and produces a device with equivalent function is within the scope of this disclosure.

[0061] Unless otherwise specified, the terms used throughout the specification and claims generally have their ordinary meaning in the context of the art, the content disclosed herein, and the specific content.

[0062] The terms "coupled" or "connected" as used in this article can refer to two or more components making direct physical or electrical contact with each other, or making indirect physical or electrical contact with each other, or to two or more components operating or moving together.

[0063] Please see Figure 1 , Figure 1 A block diagram illustrating a display device 100 according to some embodiments of the present disclosure is provided. In some embodiments, the display device 100 includes a driving circuit 10, a backlight module 20, and a liquid crystal panel 30. Figure 1 As shown, the LCD panel 30 is located on one side of the backlight module 20. The driving circuit 10 is electrically coupled to the backlight module 20 and is used to drive the backlight module 20 to emit light, so that the LCD panel 30 displays an image (not shown) for the user to view.

[0064] In some embodiments, the display device 100 is implemented by a liquid crystal display (LCD), but this disclosure is not limited thereto. Furthermore, the structure of the liquid crystal panel 30 is well known to those skilled in the art to which this disclosure pertains, and therefore will not be described in detail here.

[0065] Please see Figure 2 , Figure 2 A block diagram illustrating a backlight module 20 and a driving circuit 10 according to some embodiments of the present disclosure is provided. In some embodiments, the display device 100 further includes a glass substrate 40. The backlight module 20 includes a plurality of light-emitting elements 201 and a circuit board 203. Figure 2 As shown, the driving circuit 10 is configured to be formed on the glass substrate 40, and a plurality of light-emitting elements 201 are configured to be arranged in an array on the circuit board 203. Furthermore, the driving circuit 10 on the glass substrate 40 is electrically coupled to the plurality of light-emitting elements 201 on the circuit board 203 via a flexible connector 50.

[0066] In some embodiments, the glass substrate 40 is implemented using a low-temperature polycrystalline silicon (LTPS) glass substrate, the circuit board 203 is implemented using an FR-4 substrate, the light-emitting element 201 is implemented using a micro LED, and the flexible connector 50 is implemented using a flexible printed circuit (FPC). It should be understood that this disclosure is not limited thereto.

[0067] At Figure 2 In this embodiment, half of the light-emitting elements 201[1] in the backlight module 20 are allocated in a driving region R1, while the other half of the light-emitting elements 201[2] in the backlight module 20 are allocated in another driving region R2, which is different from the driving region R1. The multiple light-emitting elements 201[1] in the driving region R1 are driven by a driving voltage VCC1, while the multiple light-emitting elements 201[2] in the driving region R2 are driven by another driving voltage VCC2.

[0068] Please see Figure 3 , Figure 3 A circuit diagram of a backlight module 20 and a driving circuit 10 is shown for some embodiments according to this disclosure. In some embodiments, the driving circuit 10 includes a plurality of sub-circuits 101, wherein the plurality of sub-circuits 101 are configured and arranged in an array on a glass substrate 40. Figure 3 As shown, the anode of each light-emitting element 201[1] in the driving region R1 receives the driving voltage VCC1 through a switching element SW[1], while the cathode of each light-emitting element 201[1] in the driving region R1 is electrically coupled to the corresponding sub-circuit 101. The anode of each light-emitting element 201[2] in the driving region R2 receives the driving voltage VCC2 through another switching element SW[2], while the cathode of each light-emitting element 201[2] in the driving region R2 is electrically coupled to the corresponding sub-circuit 101.

[0069] In some practical applications, the multiple light-emitting elements 201[1] in the driving region R1, the multiple light-emitting elements 201[2] in the driving region R2, and the multiple sub-circuits 101 are all arranged in an array of 12 rows and 24 columns, that is, the three have the same arrangement. In this case, the light-emitting elements 201[1] and 201[2] in the first row of the first column are coupled to the sub-circuit 101 in the first row of the first column (which is the aforementioned corresponding sub-circuit 101). The configuration of the remaining light-emitting elements 201[1] and 201[2] in the array can be deduced in the same way, so it will not be described in detail here.

[0070] At Figure 3In some embodiments, each sub-circuit 101 includes a data writing circuit 110, a reset circuit 112, a light-emitting control circuit 114, a compensation circuit 116, a current generating circuit 118, a holding circuit 120, and two capacitors C1 and C2. In some embodiments, such as Figure 3 As shown, the data writing circuit 110 includes two transistors T1 and T4, the reset circuit 112 includes one transistor T2, the light emission control circuit 114 includes two transistors T3 and T6, the compensation circuit 116 includes one transistor T5, the current generation circuit 118 includes one transistor T7, and the holding circuit 120 includes one transistor T8.

[0071] Structurally, transistor T1 has its first terminal coupled to node A, and its second terminal receiving a data voltage VDATA. Transistor T2 has its first terminal receiving an initial voltage VINI, and its second terminal coupled to node B. Transistor T3 has its first terminal coupled to node C, and its second terminal coupled to node A. Transistor T4 has its first terminal coupled to node B, and its second terminal coupled to node D. Transistor T5 has its first terminal receiving a reference voltage VREF, and its second terminal coupled to node C. Transistor T6 has its first terminal receiving a ground voltage GND, and its second terminal coupled to node D. Transistor T7 has its first terminal coupled to node C, its second terminal coupled to node D, and its control terminal coupled to node B. Transistor T8 has its first terminal receiving a reference voltage VREF, and its second terminal coupled to node C. Capacitor C1 is coupled between nodes A and B. Capacitor C2 is coupled between the initial voltage VINI and node A. Furthermore, the sub-circuit 101 in the driving circuit 10 is coupled to the cathode end of the corresponding light-emitting element 201 in the backlight module 20 at node C.

[0072] For example Figure 3 As shown, transistor T2 is turned on or off according to the voltage level of a first control signal S1[n-1]. Transistors T1 and T4 are turned on or off according to the voltage level of a second control signal S1[n]. Transistor T5 is turned on or off according to the voltage level of a third control signal S1[n+1]. Transistor T8 is turned on or off according to the voltage level of a fourth control signal S2[n]. Furthermore, transistors T3 and T6 are turned on or off according to the voltage level of a light emission control signal EM.

[0073] In the foregoing embodiments, the data voltage VDATA is 0–6 volts, the initial voltage VINI is approximately -3 volts, the reference voltage VREF is approximately 0.5 volts, and the driving voltages VCC1 and VCC2 are each approximately -12–8 volts. The equivalent lengths and widths of transistors T1–T5 are approximately 6 and 30 micrometers (μm), respectively; the equivalent length and width of transistor T6 are approximately 2160 and 7200 micrometers, respectively; and the equivalent length and width of transistor T7 are approximately 2880 and 9600 micrometers, respectively. The capacitance of capacitor C1 is approximately 30 pF, and the capacitance of capacitor C2 is approximately 5 pF. It should be understood that this disclosure is not limited thereto. It is worth noting that the above-described transistor and voltage configuration is designed to enable the driving circuit 10 to generate a larger driving current to the backlight module 20, allowing the backlight module 20 to emit sufficiently bright light to the liquid crystal panel 30. Therefore, it differs from the transistor and voltage configuration in a typical pixel circuit.

[0074] In the foregoing embodiments, transistors T1 to T8 are all P-type thin-film transistors, but this disclosure is not limited thereto. In other embodiments, those skilled in the art to which this disclosure pertains may also implement transistors T1 to T8 using N-type thin-film transistors.

[0075] Please see Figure 4 , Figure 4 The following diagram illustrates a signal timing diagram of a display device 100 in a strobe mode (Mst) according to some embodiments of the present disclosure. In some embodiments, the display device 100 operates in strobe mode (Mst) to time-division multiplex the signal. Figure 2 The driving regions R1 and R2 in the code are used for driving. For example... Figure 4 As shown, in the strobe mode Mst, the driving voltages VCC1 and VCC2 are provided alternately during the continuous frame time F[n-1] to F[n+1]. Furthermore, Figure 4 A signal timing diagram TMst is shown corresponding to the light-emitting element 201[1] in the first column of the driving region R1. The operation of the sub-circuit 101 will be described in detail with reference to the signal timing diagram TMst. As shown in the signal timing diagram TMst, the frame time F[n] in the gating mode Mst includes the periods P1 to P4.

[0076] Please refer to the following: Figure 4 and Figure 5A , Figure 5AA schematic diagram illustrating the operation of a driving circuit 10 during period P1 is provided for some embodiments of this disclosure. During period P1, transistor T2 is turned on according to the first control signal S1[n-1], transistors T1 and T4 are turned on according to the second control signal S1[n], transistor T5 is turned off according to the third control signal S1[n+1], transistor T8 is turned off according to the fourth control signal S2[n], and transistors T3 and T6 are turned off according to the light emission control signal EM. Accordingly, as Figure 5A As shown, the data voltage VDATA is provided to node A through transistor T1, the initial voltage VINI is provided to nodes B and D through transistors T2 and T4, and the voltage value of node C is equivalent to the initial voltage VINI minus the absolute value of the threshold voltage Vth of transistor T7.

[0077] As can be seen from the above description, during period P1, the data voltage VDATA is written to node A, which is coupled between the data writing circuit 110 and the light emission control circuit 114, by means of the data writing circuit 110, and the node B, which is coupled between the reset circuit 112 and the current generation circuit 118, is reset to the initial voltage VINI by means of the reset circuit 112.

[0078] Please refer to the following: Figure 4 and Figure 5B , Figure 5B A schematic diagram illustrating the operation of a drive circuit 10 during period P2 is provided according to some embodiments of this disclosure. During period P2, transistor T2 changes from on to off according to a first control signal S1[n-1], transistors T1 and T4 remain on according to a second control signal S1[n], transistor T5 changes from off to on according to a third control signal S1[n+1], transistor T8 changes from off to on according to a fourth control signal S2[n], and transistors T3 and T6 remain off according to a light emission control signal EM. Accordingly, a reference voltage VREF is provided to node C through transistors T5 and T8. At the beginning of period P2, the voltage difference between the first terminal and the control terminal of transistor T7 is approximately the reference voltage VREF minus the initial voltage VINI. Since this voltage difference is greater than the critical voltage Vth of transistor T7, transistor T7 turns on, and further charges node B with reference voltage VREF through multiple conducting transistors T4, T5, T7 and T8 until the voltage difference between the first terminal and the control terminal of transistor T7 is reduced to the critical voltage Vth of transistor T7.

[0079] As explained above, during period P2, the compensation circuit 116 compensates node B from the initial voltage VINI to a compensation voltage VCP. This compensation voltage VCP is approximately the reference voltage VREF minus the absolute value of the threshold voltage Vth of transistor T7.

[0080] Please refer to the following: Figure 4 and Figure 5C , Figure 5C A schematic diagram illustrating the operation of a drive circuit 10 during period P3 is provided according to some embodiments of this disclosure. During period P3, transistor T2 remains off according to a first control signal S1[n-1], transistors T1 and T4 change from on to off according to a second control signal S1[n], transistor T5 initially remains on and then changes from on to off according to a third control signal S1[n+1], transistor T8 remains on according to a fourth control signal S2[n], and transistors T3 and T6 remain off according to a light emission control signal EM. Accordingly, node A is held at the data voltage VDATA, nodes B and D are held at the compensation voltage VCP, and node C is held at the reference voltage VREF.

[0081] As can be seen from the above description, during period P3, node A and node B are held at the data voltage VDATA and compensation voltage VCP respectively by the on-hold circuit 120.

[0082] Depend on Figure 4 As can be seen from the description of periods P2 and P3, the compensation circuit 116 and the holding circuit 120 change from off to on together during period P2, and remain on together during the initial period of period P3. Thereafter, only the holding circuit 120 remains on to maintain the voltage values ​​of nodes A to D. It is worth noting that this configuration is to wait for the sub-circuits 101 corresponding to the light-emitting elements 201[1] of other columns in the driving region R1 to complete the reset, data writing and compensation operations (that is, the operations of periods P1 and P2). In other words, in the gating mode Mst, the sub-circuit 101 of each column will maintain the voltage values ​​of nodes A to D after completing the reset, data writing and compensation operations until the sub-circuits 101 of the remaining columns also complete the reset, data writing and compensation operations.

[0083] As explained above, Figure 4 It also shows a data write time TIst and a liquid crystal response time TRst corresponding to the light-emitting element 201[1] in the first column of the driving region R1, after which the driving voltage VCC1 is provided. Figure 4 It can also be seen that the light-emitting elements 201[1] in the other columns of the driving area R1 also have corresponding data writing times and liquid crystal response times, but they are not shown for the sake of keeping the diagram simple. It is worth noting that in the gating mode Mst, each column of light-emitting elements 201[1] corresponds to a different liquid crystal response time TRst, which also reflects that the time for each column of sub-circuits 101 corresponding to the driving area R1 to maintain the voltage values ​​of nodes A to D is different.

[0084] After each column of sub-circuit 101 has completed the reset, data writing, and compensation operations, the operation of each column of sub-circuit 101 corresponding to the driving area R1 simultaneously enters period P4. Please refer to the following: Figure 4 and Figure 5D , Figure 5D A schematic diagram illustrating the operation of a drive circuit 10 during period P4 is provided for some embodiments of this disclosure. During period P4, transistor T2 remains off according to the first control signal S1[n-1], transistors T1 and T4 remain off according to the second control signal S1[n], transistor T5 remains off according to the third control signal S1[n+1], transistor T8 changes from on to off according to the fourth control signal S2[n], and transistors T3 and T6 change from off to on according to the light emission control signal EM. Furthermore, as... Figure 4 and Figure 5D As shown, after transistors T3 and T6 are turned on, the switching element SW[1] is then turned on so that all the light-emitting elements 201[1] in the driving region R1 receive the driving voltage VCC1.

[0085] Under the aforementioned configuration, the voltage value of node C becomes an output voltage of the backlight module 20. This output voltage is approximately the driving voltage VCC1 minus the voltage difference VLED across the light-emitting element 201 [1]. The voltage value of node A also becomes the output voltage of the backlight module 20 due to the conduction of transistor T3. Since the voltage difference across capacitor C1 remains constant, the voltage value of node B also changes from the compensation voltage VCP to a working voltage VW. This working voltage VW is approximately the compensation voltage VCP (i.e., the absolute value of the reference voltage VREF minus the threshold voltage Vth of transistor T7) plus the voltage difference changed at node A (i.e., the driving voltage VCC1 minus the voltage difference VLED across the light-emitting element 201 [1] and the data voltage VDATA). In other words, during period P4, the data voltage VDATA is coupled from node A to node B through capacitor C1. In addition, the driving voltage VCC1 is also coupled to node B.

[0086] Next, transistor T7 generates a driving current Id based on the voltage value at its first terminal (i.e., the driving voltage VCC1 minus the voltage difference VLED across the light-emitting element 201[1]) and the voltage value at its control terminal (i.e., the operating voltage VW). Specifically, the driving current Id passes through the light-emitting element 201[1], transistor T7, and transistor T6, causing the light-emitting element 201[1] to emit light. The driving current Id can be expressed by formula (1):

[0087]

[0088] Where K is the conductivity parameter.

[0089] It is worth noting that, due to the structure of sub-circuit 101 and the operation of P1 to P4 during this period, the magnitude of the drive current Id will not be affected by the variation of the critical voltage Vth of transistor T7 and / or the voltage rise / fall of drive voltage VCC1 due to parasitic elements. That is, drive circuit 10 can provide a relatively stable drive current Id to light-emitting element 201 [1], so as to increase brightness uniformity. In addition, as Figure 5D As shown, there are only two transistors T6 and T7 in the path of the drive current Id, which can reduce the voltage applied to the sub-circuit 101 and further reduce the power consumption of the display device 100.

[0090] Please refer to it again. Figure 2 and Figure 4 The operation of the driving circuit 10 in the selection mode Mst to drive all the light-emitting elements 201[2] in the driving area R2 can be deduced in the same way, so it will not be described in detail here.

[0091] Please see Figure 6 , Figure 6 A block diagram illustrating a backlight module 20 and a driving circuit 10 according to some embodiments of this disclosure is provided. Figure 6 In this embodiment, the light-emitting elements 201 in each column of the backlight module 20 are assigned to a corresponding driving region. For example, the light-emitting elements 201[1] in the first column are assigned to driving region R1, the light-emitting elements 201[2] in the second column are assigned to driving region R2, the light-emitting elements 201

[12] in the 12th column are assigned to driving region R12, the light-emitting elements 201

[13] in the 13th column are assigned to driving region R13, and the light-emitting elements 201

[24] in the 24th column are assigned to driving region R24. The configuration of the light-emitting elements 201 in the remaining columns can be deduced in the same way, and will not be described in detail here. In addition, the light-emitting elements 201 in each driving region are driven by a corresponding driving voltage. For example, the light-emitting element 201[1] in driving region R1 is driven by driving voltage VCC1, the light-emitting element 201[2] in driving region R2 is driven by driving voltage VCC2, the light-emitting element 201

[12] in driving region R12 is driven by driving voltage VCC12, the light-emitting element 201

[13] in driving region R13 is driven by driving voltage VCC13, and the light-emitting element 201

[24] in driving region R24 is driven by driving voltage VCC24. The configuration of the light-emitting elements 201 in the other driving regions can be deduced in the same way, so it will not be described in detail here.

[0092] Please see Figure 7 , Figure 7A circuit diagram of a backlight module 20 and a driving circuit 10 is shown for some embodiments according to this disclosure. In some embodiments, in order to drive such... Figure 6 The backlight module 20 shown has a driving circuit 10 that includes multiple sub-circuits 103. Compared to... Figure 3 Sub-circuit 101, Figure 7 Sub-circuit 103 does not include holding circuit 120. That is, as... Figure 7 As shown, sub-circuit 103 includes transistors T1 to T7 and capacitors C1 to C2, and does not receive the fourth control signal S2[n]. It should be understood that the remaining settings and operations of sub-circuit 103 are similar to those of sub-circuit 101, and therefore will not be described in detail here.

[0093] Please see Figure 8 , Figure 8 The following diagram illustrates a signal timing diagram of a display device 100 in a scanning mode MSc, according to some embodiments of the present disclosure. In some embodiments, the display device 100 operates in scanning mode MSc to time-division multiplex the signal. Figure 6 Multiple drive regions R1 to R24 in the code are driven. For example... Figure 8 As shown, in scan mode MSc, multiple drive voltages VCC1 to VCC24 are sequentially provided during continuous frame times F[n] to F[n+1]. Furthermore, Figure 8 A signal timing diagram TMsc corresponding to the light-emitting element 201[1] in the driving region R1 is shown. The operation of the sub-circuit 103 will then be explained in conjunction with the signal timing diagram TMsc. As shown in the signal timing diagram TMsc, the frame time F[n] in the scan mode Msc includes periods P1 to P2 and P4.

[0094] At Figure 8 In the embodiments, the descriptions of periods P1 to P2 and P4 are consistent with... Figure 4 The embodiments are described in the same or similar manner, and will therefore be briefly described here only. Please refer to [the relevant documents / references]. Figure 8 and Figure 9A , Figure 9A A schematic diagram illustrating the operation of a drive circuit 10 during period P1 is provided according to some embodiments of this disclosure. During period P1, transistors T1, T2, and T4 are turned on, while transistors T3, T5, and T6 are turned off. Accordingly, the data voltage VDATA is provided to node A through transistor T1, the initial voltage VINI is provided to nodes B and D through transistors T2 and T4, and the voltage value at node C is equivalent to the initial voltage VINI minus the absolute value of the threshold voltage Vth of transistor T7.

[0095] Please refer to the following: Figure 8 and Figure 9B , Figure 9BA schematic diagram illustrating the operation of a drive circuit 10 during period P2 is provided according to some embodiments of this disclosure. During period P2, transistors T1, T4, and T5 are turned on, while transistors T2, T3, and T6 are turned off. Accordingly, a reference voltage VREF is provided to node C through transistor T5, which causes transistor T7 to turn on, further charging node B to the compensation voltage VCP.

[0096] Please refer to the following: Figure 8 and Figure 9C , Figure 9C A schematic diagram of the operation of a drive circuit 10 during period P4 is shown for some embodiments of the present disclosure. During period P4, transistors T3 and T6 are turned on, and transistors T1, T2, T4 and T5 are turned off. Also, switching element SW[1] is turned on so that all light-emitting elements 201[1] in the drive region R1 receive the drive voltage VCC1. Accordingly, the voltage values ​​of nodes C and A become the output voltage of the backlight module 20 due to the turn-on of transistor T3 (i.e., the drive voltage VCC1 minus the voltage difference VLED across the light-emitting element 201[1]). The data voltage VDATA is coupled from node A to node B through capacitor C1, which further changes the voltage value of node B from the compensation voltage VCP to the operating voltage VW. Then, transistor T7 generates a drive current Id based on the voltage difference between its first terminal (i.e., node C) and the control terminal (i.e., node B), causing the light-emitting element 201[1] to emit light.

[0097] Please refer to it again. Figure 6 and Figure 8 The operation of the driving circuit 10 in driving multiple light-emitting elements 201[2] to 201

[24] in the remaining driving area R2 to R24 under scanning mode MSc can be deduced by analogy, so it will not be described in detail here.

[0098] As explained above, in scan mode MSc, after completing the reset, data writing, and compensation operations, each column's sub-circuit 103 will drive the corresponding column's light-emitting element 201 to emit light within a short period. In other words, unlike sub-circuit 101, sub-circuit 103 does not wait for the remaining columns' sub-circuit 101 to complete the reset, data writing, and compensation operations. Therefore, with... Figure 2 and Figure 6 In other words, Figure 2 The light-emitting element 201 in the upper middle part (that is, the light-emitting element 201[1] in the driving region R1) will emit light synchronously, but Figure 6 The light-emitting elements 201 in the upper middle part (that is, the light-emitting elements 201[1] to 201

[12] in the driving area R1 to R12) emit light sequentially from top to bottom.

[0099] To further explain, such as Figure 8As shown, since the third control signal S1[n+1] has a conduction voltage level between period P2 and period P4, only transistor T5 remains on in sub-circuit 103 between period P2 and period P4. Therefore, between period P2 and period P4, the voltage value of node A remains at the data voltage VDATA, the voltage values ​​of nodes B and D remain at the compensation voltage VCP, and the voltage value of node C remains at the reference voltage VREF. That is, in some embodiments, sub-circuit 103, in addition to the operations during periods P1 to P2 and P4, also includes the operation of maintaining the voltage values ​​of nodes A to D between period P2 and period P4 during frame time F[n]. It should be understood that the operation of sub-circuit 103 between period P2 and period P4 corresponds to the operation of sub-circuit 101 during period P3, except that the time for sub-circuit 103 to maintain the voltage values ​​of nodes A to D is determined by transistor T5, while the time for sub-circuit 101 to maintain the voltage values ​​of nodes A to D is determined by transistor T8.

[0100] As explained above, Figure 8 It also shows a data write time TIsc and a liquid crystal response time TRsc corresponding to the light-emitting element 201[1] in the first column of the driving region R1, and the time for providing the driving voltage VCC1 is followed by the liquid crystal response time TRsc. Figure 8 It can also be seen that the other columns of light-emitting elements 201 also have corresponding data writing times and liquid crystal response times, but these are not shown for the sake of simplicity. It is worth noting that in scan mode MSc, each column of light-emitting elements 201 corresponds to the same liquid crystal response time TRsc, which reflects the difference between scan mode MSc and gating mode Mst. For example, compared to gating mode Mst, the light-emitting element 201 has a longer emission time in scan mode MSc, resulting in higher brightness for the backlight module 20 in scan mode MSc.

[0101] It is worth noting that, in the foregoing embodiments, by designing the driving circuit 10 on the glass substrate 40, the driving circuit 10 of the present disclosure can store voltage and convert it into driving current in a timely manner through the glass substrate 40, so that the output of the driving circuit 10 is not limited by factors such as the physical characteristics or number of integrated circuits used, as in related technologies.

[0102] In addition, such as Figure 2 and Figure 3As explained, one of the sub-circuits 101 in the driving circuit 10 drives one of the light-emitting elements 201[1] in the driving region R1 and one of the light-emitting elements 201[2] in the driving region R2. It can be seen that the duty ratio of each of the driving regions R1 and R2 is about 50%. However, the present disclosure is not limited to this. By designing the driving circuit 10 on the glass substrate 40, in other embodiments, one sub-circuit 101 can drive three light-emitting elements 201 located in different driving regions respectively, so that the duty ratio of each driving region becomes about 33%. That is to say, by designing the driving circuit 10 on the glass substrate 40, the driving circuit 10 of the present disclosure can also flexibly adjust the duty ratio of the light-emitting regions in the backlight module 20.

[0103] As can be seen from the above-described embodiments of the present disclosure, by designing the driving circuit 10 on the glass substrate 40, the driving circuit 10 and driving method of the present disclosure (that is, the operation of P1 to P4 during this period) do not need to use a large number of integrated circuits to drive the backlight module, which is suitable for backlight modules with high current requirements, and the duty cycle of the light-emitting area in the backlight module can be flexibly adjusted, so as to further enable the display device 100 to have the advantages of reducing cost and power consumption.

[0104] Although the present disclosure has been described above with reference to embodiments, it is not intended to limit the present disclosure. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the present disclosure. Therefore, the scope of protection of the present disclosure shall be determined by the appended claims.

Claims

1. A driving circuit, comprising: a first transistor, wherein a first terminal of the first transistor is coupled to a first node, and a second terminal of the first transistor receives a data voltage, and a control terminal of the first transistor receives a second control signal; a second transistor, wherein a first terminal of the second transistor receives an initial voltage, and a second terminal of the second transistor is coupled to a second node, and a control terminal of the second transistor receives a first control signal; a third transistor, wherein a first terminal of the third transistor is coupled to a third node, and a second terminal of the third transistor is coupled to the first node, and a control terminal of the third transistor receives a light emitting control signal; a fourth transistor, wherein a first terminal of the fourth transistor is coupled to the second node, and a second terminal of the fourth transistor is coupled to a fourth node, and a control terminal of the fourth transistor receives the second control signal; a fifth transistor, wherein a first terminal of the fifth transistor receives a reference voltage, and a second terminal of the fifth transistor is coupled to the third node, and a control terminal of the fifth transistor receives a third control signal; a sixth transistor, wherein a first terminal of the sixth transistor receives a ground voltage, and a second terminal of the sixth transistor is coupled to the fourth node, and a control terminal of the sixth transistor receives the light emitting control signal; a seventh transistor, wherein a first terminal of the seventh transistor is coupled to the third node, and a second terminal of the seventh transistor is coupled to the fourth node, and a control terminal of the seventh transistor is coupled to the second node; a first capacitor coupled between the first node and the second node; and a second capacitor coupled between the initial voltage and the first node.

2. The driving circuit of claim 1, wherein during a first period, the second transistor is turned on according to a first control signal, the first transistor and the fourth transistor are turned on according to a second control signal, the fifth transistor is turned off according to a third control signal, and the third transistor and the sixth transistor are turned off according to a light emitting control signal; during a second period after the first period, the second transistor is turned off from on according to the first control signal, and the fifth transistor is turned on from off according to the third control signal; during a third period after the second period, the first transistor and the fourth transistor are turned off from on according to the second control signal, the fifth transistor is turned off from on according to the third control signal, and the third transistor and the sixth transistor are turned on from off according to the light emitting control signal.

3. The driving circuit of claim 1, further comprising: an eighth transistor, wherein a first terminal of the eighth transistor receives the reference voltage, and a second terminal of the eighth transistor is coupled to the third node. ​ 4. The driving circuit of claim 3, wherein during a first period, the second transistor is turned on according to a first control signal, the first transistor and the fourth transistor are turned on according to a second control signal, the fifth transistor is turned off according to a third control signal, the eighth transistor is turned off according to a fourth control signal, and the third transistor and the sixth transistor are turned off according to a light emitting control signal; during a second period after the first period, the second transistor is turned off according to the first control signal, the fifth transistor is turned on according to the third control signal, and the eighth transistor is turned on according to the fourth control signal; during a third period after the second period, the first transistor and the fourth transistor are turned off according to the second control signal; during a fourth period after the second period, the fifth transistor is turned off according to the third control signal, the eighth transistor is turned off according to the fourth control signal, and the third transistor and the sixth transistor are turned on according to the light emitting control signal.

5. A display device, comprising: a backlight module; a liquid crystal panel located at a side of the backlight module; and the driving circuit of claim 1, wherein the driving circuit is coupled to the third node and used to drive the backlight module to emit light so that the liquid crystal panel displays an image.

6. The display device of claim 5, further comprising a glass substrate, wherein the driving circuit is disposed on the glass substrate.

7. A driving method of a backlight module, comprising: In a first period, a data voltage is written to a first node coupled between a data write circuit and a light emission control circuit by the data write circuit, and a second node coupled between a reset circuit and a current generation circuit is reset to an initial voltage by the reset circuit, wherein the data writing circuit comprises the first transistor and the fourth transistor according to any one of claims 1-4, the light emitting control circuit comprises the third transistor and the sixth transistor according to any one of claims 1-4, the reset circuit comprises the second transistor according to any one of claims 1-4, and the current generating circuit comprises the seventh transistor according to any one of claims 1-4; during a second period, the second node is compensated from the initial voltage to a compensation voltage by turning on a compensation circuit, wherein the compensation circuit comprises the fifth transistor according to any one of claims 1-4; and during a third period, the data voltage is coupled to the second node by turning on the light emitting control circuit, so that the current generating circuit generates a driving current to a light emitting element of the backlight module according to an operating voltage.

8. The driving method of claim 7, further comprising: during a fourth period between the second period and the third period, the first node and the second node are respectively maintained at the data voltage and the compensation voltage by turning on a maintaining circuit, wherein the maintaining circuit comprises an eighth transistor, a first end of the eighth transistor receives a reference voltage, a second end of the eighth transistor is coupled to a third node, and a control end of the eighth transistor receives a fourth control signal.

9. The driving method of claim 7, further comprising: In the second period, a reference voltage is provided to a third node coupled between the compensation circuit and the current generating circuit by the compensation circuit; wherein the compensation voltage is the reference voltage minus a threshold voltage of a transistor in the current generating circuit.

10. The driving method of claim 7, further comprising: In the third period, an output voltage of the backlight module is provided to the first node by the light emitting control circuit; wherein the operating voltage is the compensation voltage plus the output voltage minus the data voltage.

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