A storage block and a memory

Abstract

The present invention relates to a storage block and a memory. The storage block includes a plurality of storage arrays arranged along a first direction, and each of the storage arrays is divided into at least two array units along a second direction, where the first direction is perpendicular to the second direction; a plurality of read / write control circuits, which are arranged between two adjacent storage arrays; and a plurality of data signal lines for electrically connecting the read / write control circuits and the array units. Among them, different array units of each storage array are electrically connected to different read / write control circuits through different data signal lines. The storage block according to the embodiment of the present invention has the advantage of low power consumption.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a memory block and a memory. Background Art

[0002] A Dynamic Random Access Memory (DRAM) is a commonly used semiconductor memory component in a computer and is composed of many repeated memory cells. Each memory cell generally includes a capacitor and a transistor. The gate of the transistor is connected to a word line, the drain is connected to a bit line, and the source is connected to the capacitor. The voltage signal on the word line can control the opening or closing of the transistor, and then the data information stored in the capacitor can be read through the bit line, or the data information can be written into the capacitor through the bit line for storage.

[0003] DRAM can be divided into Double Data Rate (DDR) dynamic random access memory, Graphics Double Data Rate (GDDR) dynamic random access memory, and Low Power Double Data Rate (LPDDR) dynamic random access memory. As DRAM is applied in more and more fields, such as more and more applications in the mobile field, users have higher and higher requirements for the power consumption index of DRAM.

[0004] However, the current power consumption of DRAM is still relatively high and it is difficult to meet the low-power requirements. Summary of the Invention

[0005] Embodiments of the present invention provide a memory block and a memory to solve the problem of high power consumption of the memory block.

[0006] To solve the above problems, an embodiment of the present invention provides a memory block, including:

[0007] A plurality of memory arrays arranged along a first direction, each of the memory arrays being divided into at least two array units along a second direction, the first direction being perpendicular to the second direction;

[0008] A read / write control circuit disposed between two adjacent memory arrays;

[0009] Data signal lines for electrically connecting the read / write control circuit and the array units;

[0010] Wherein, different array units of each memory array are electrically connected to different read / write control circuits through different data signal lines.

[0011] In addition, the plurality of storage arrays are used for storing data and parity codes; the storage block further includes: a plurality of error detection and correction units, which are arranged between two adjacent ones of the storage arrays and are electrically connected to the plurality of read / write control circuits, and are used for performing error detection and / or error correction on the data according to the parity codes.

[0012] In addition, the plurality of error detection and correction units at least include: a first error detection and correction unit, which is connected to each of the array units through the read / write control circuit and is used for performing error detection and correction on a part of the output data of the array units; a second error detection and correction unit, which is connected to each of the array units through the read / write control circuit and is used for performing error detection and correction on the remaining output data of the array units.

[0013] In addition, the data signal lines corresponding to each of the array units include an even number of block data buses. The block data buses are numbered sequentially from zero according to natural numbers. The block data buses O with odd numbers are connected to the first error detection and correction unit, and the block data buses E with even numbers are connected to the second error detection and correction unit.

[0014] In addition, each of the array units includes a local conversion circuit and an even number of local data buses. The local data buses are divided into local data buses O and local data buses E. The local data buses O are connected to the block data buses O through the local conversion circuit, and the local data buses E are connected to the block data buses E through the local conversion circuit.

[0015] In addition, each of the local data buses is connected to a plurality of sense amplifiers through a selection switch, and the sense amplifiers are arranged in one-to-one correspondence with the bit lines in the storage array.

[0016] In addition, the output data on two adjacent bit lines respectively enter the local data buses O and the local data buses E through the sense amplifiers and the selection switches.

[0017] In addition, the number of the block data buses is 2 * 4 * (16 * N), and the number of the local data buses is 2 * 4 * M * (16 * N); the number of the block data buses O is 4 * (16 * N), and the number of the block data buses E is 4 * (16 * N); the number of the local data buses O is 4 * M * (16 * N), and the number of the local data buses E is 4 * M * (16 * N); one block data bus O corresponds to M local data buses O, and one block data bus E corresponds to M local data buses E; the local data buses are divided into M * (16 * N) groups of local data buses O and M * (16 * N) groups of local data buses E with 4 adjacent ones as a group.

[0018] In addition, there are multiple read / write control circuits, which are divided into a first type of read / write control circuit and a second type of read / write control circuit;

[0019] Each of the first type of read / write control circuits corresponds to two of the array units. The first type of read / write control circuit includes: a first read / write control unit and a second read / write control unit; the first read / write control unit is connected between the odd block data bus O of the corresponding array unit and the first error detection and correction unit, and the second read / write control unit is connected between the even block data bus E of the corresponding array unit and the second error detection and correction unit;

[0020] Each of the second type of read / write control circuits corresponds to one of the array units. The second type of read / write control circuit is used to be integrally connected between all the block data buses of the corresponding array unit and the first error detection and correction unit and the second error detection and correction unit.

[0021] In addition, the plurality of memory arrays include a memory array U, a memory array V, and a memory array W arranged in sequence along the first direction; each memory array is divided into two array units along the second direction; two array units on the same side in the second direction of the memory array U and the memory array V share the same word line address;

[0022] The read / write control circuits corresponding to the memory array U and the memory array V are associated and configured to simultaneously access the memory cells with the same word line address in the two array units on the same side in the memory array U and the memory array V.

[0023] In addition, two array units on the first side of the memory array U and the memory array V share the same word line address; the read / write control circuits corresponding to the memory array U and the memory array V are associated and configured to simultaneously access the memory cells with the same word line address in the two array units on the first side of the memory array U and the memory array V; or,

[0024] Two array units on the second side of the memory array U and the memory array V share the same word line address, and the first side and the second side are opposite sides in the second direction; the read / write control circuits corresponding to the memory array U and the memory array V are associated and configured to simultaneously access the memory cells with the same word line address in the two array units on the second side of the memory array U and the memory array V.

[0025] In addition, when two array units on the first side of the memory array U and the memory array V share the same word line address, two array units on the second side of the memory array U and the memory array V share the same word line address;

[0026] The read / write control circuits corresponding to the storage array U and the storage array V are associated and configured to simultaneously access two array units on the second side in the storage array U and the storage array V;

[0027] When two array units on the second side in the storage array U and the storage array V share the same word line address, two array units on the first side in the storage array U and the storage array V share the same word line address;

[0028] The read / write control circuits corresponding to the storage array U and the storage array V are associated and configured to simultaneously access two array units on the first side in the storage array U and the storage array V.

[0029] In addition, when two array units on the first side in the storage array U and the storage array V share the same word line address and / or two array units on the second side share the same word line address, two array units on the first side and the second side in the storage array W share the same word line address;

[0030] The read / write control circuit corresponding to the storage array W is associated and configured to simultaneously access the array units on the first side and the second side in the storage array W.

[0031] In addition, it further includes: a row decoding circuit, configured to issue a row decoding signal to locate the word lines in different selected array units.

[0032] Correspondingly, an embodiment of the present invention further provides a memory, including the storage block in the above embodiment.

[0033] Compared with the prior art, the technical solution provided by the present invention has the following advantages:

[0034] An embodiment of the present invention provides a storage block with superior structural performance, including a storage array divided into at least two array units, a read / write control circuit, and a data signal line for electrically connecting the read / write control circuit and the array unit. During a single read operation, each read / write control circuit only needs to access one array unit in the corresponding storage array, and the read / write control circuit and each array unit in the storage array are connected through different data signal lines. Since each data signal line is only electrically connected to one array unit, that is, has an electrical contact point, during a single read / write operation, the number of electrical contact points is reduced, and the parasitic resistance and parasitic capacitance of this storage block are also reduced, which is beneficial to reducing the power consumption of the storage block. At the same time, since the read / write control circuit is arranged between two adjacent storage arrays, the distance from the read / write control circuit to the corresponding array unit can be greatly shortened, thereby reducing the length of the data signal line and improving the data transmission efficiency.

[0035] In addition, the storage array is used to store data and parity codes; the storage block further includes an error detection and correction unit for detecting and / or correcting errors in the data according to the parity codes. Since the error detection and correction unit is arranged between two adjacent storage arrays where the read / write control circuit is located, it can make the layout between the read / write control circuit and the error detection and correction unit compact, reducing the layout area; at the same time, it can also shorten the distance between the read / write control circuit and the error detection and correction unit, thereby reducing the length of the data signal lines between the two and improving the data transmission efficiency.

[0036] In addition, the output data on two adjacent bit lines enter the local data bus O and the local data bus E respectively through sense amplifiers and strobe switches, so that the data corresponding to the physically adjacent local data buses enter the first error detection and correction unit and the second error detection and correction unit respectively. Therefore, when the data corresponding to the bit lines at adjacent positions are simultaneously in error, the error can also be corrected, further improving the error detection and correction ability of the memory.

[0037] In addition, a plurality of storage arrays include a storage array U, a storage array V, and a storage array W, and each storage array is divided into two array units; by setting the two array units on at least one same side in the storage array U and the storage array V to share the same word line address, and the read / write control circuits corresponding to the storage array U and the storage array V are configured to be associated to simultaneously access the two array units on the same side in the storage array U and the storage array V, the two storage arrays can be simultaneously accessed through the shared word line address, reducing the word line overhead and lowering the power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 It is a schematic structural diagram of a DARM;

[0039] Figure 2 It is a schematic structural diagram of a storage block provided by an embodiment of the present invention;

[0040] Figure 3 It is a schematic top view structural diagram of a memory layout;

[0041] Figure 4 It is a schematic structural diagram of a memory;

[0042] Figure 5 It is a schematic structural diagram of a storage block provided by another embodiment of the present invention;

[0043] Figure 6 It is a schematic structural diagram of a storage block provided by still another embodiment of the present invention;

[0044] Figure 7 For Figure 6 the schematic connection diagram of signal lines in a local area of the memory in

[0045] Figure 8A structural schematic diagram of a memory block provided by another embodiment of the present invention. Detailed implementation manners

[0046] As can be seen from the background art, the power consumption of current DRAMs needs to be further reduced.

[0047] Now, an analysis is made in conjunction with a structural schematic diagram of a DRAM. Figure 1 It is a structural schematic diagram of a DARM. Refer to Figure 1 , a DRAM is composed of multiple memory blocks (banks, also known as memory banks), each memory block includes several memory arrays, and each memory array includes a memory array (array) and a sense amplifier array. For DRAMs, whether it is the DDR (2 / 3 / 4, etc.) series or the LPDDR (2 / 3 / 4 / 5) series, the memory blocks are divided into a high-bit group and a low-bit group according to the output pins (DQ). That is to say, each bank can also be correspondingly divided into 2 half banks, one of the half banks serves as the first module M1, the first module M1 provides low-bit output pins, and the other half bank serves as the second module M2, and the second module M2 provides high-bit output pins.

[0048] The data signal line YIO is used to transmit data between the selected memory array and the read / write control circuit. Whether it is the half bank of the low-bit group or the half bank of the high-bit group, in order to successfully complete the read and write operations, the data signal line YIO has electrical contact points with each memory array in the half bank, generating parasitic capacitance; the data signal line YIO is very long, resulting in a large parasitic resistance, which will bring the problem of large power consumption for each read and write, resulting in high power consumption of the DRAM.

[0049] Further analysis reveals that parasitic resistance and parasitic capacitance are also one of the main reasons for the high power consumption of DARMs. For the data signal line YIO, during each read operation or write operation, there are parasitic capacitance and parasitic resistance at the electrical contact points between each group of data signal lines YIO and each memory array. Due to the large number of electrical contact points, the corresponding parasitic resistance and parasitic resistance are large, resulting in high power consumption of the DRAM.

[0050] To solve the above problems, the embodiments of the present invention provide a memory block with excellent structural performance. Through the design of a special structure, the parasitic resistance and parasitic capacitance of the memory block are reduced, thereby reducing the power consumption of the memory block.

[0051] To make the objectives, technical solutions, and advantages of the present invention clearer, the embodiments of the present invention will be described in detail below with reference to the accompanying drawings. However, those of ordinary skill in the art can understand that in the embodiments of the present invention, many technical details are provided to help readers better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the present application can still be implemented.

[0052] Figure 2 FIG. is a schematic structural diagram of a storage block provided by an embodiment of the present invention.

[0053] Referring to Figure 2 , in this embodiment, the storage block includes a plurality of memory arrays 101 arranged along the first direction (X), and each memory array 101 is divided into at least two array units (such as array unit 1101 and array unit 1102) along the second direction (Y). The first direction X and the second direction Y are perpendicular to each other; a plurality of read / write control circuits 102 are provided between adjacent two memory arrays 101 (such as Figure 2 memory array V and memory array W in ); a plurality of data signal lines YIO (such as YIO1 and YIO2) are used to electrically connect the read / write control circuit 102 and the array unit; wherein, different array units of each memory array 101 are electrically connected to different read / write control circuits 102 through different data signal lines YIO. It can be known that the above-mentioned first direction X is the direction in which the word line WL extends, and the second direction Y is the direction in which the bit line BL extends.

[0054] The embodiment of the present invention provides a storage block with excellent structural performance, including a memory array divided into at least two array units, a read / write control circuit, and a data signal line for electrically connecting the read / write control circuit and the array unit. In a single read operation, each read / write control circuit only needs to access one array unit in the corresponding memory array, and the read / write control circuit and each array unit in the memory array are connected through different data signal lines. Since each data signal line is only electrically connected to one array unit, that is, there is an electrical contact point, during a single read / write operation, the number of electrical contact points is reduced, and the parasitic resistance and parasitic capacitance of this storage block are also reduced, which is beneficial to reducing the power consumption of the storage block. At the same time, since the read / write control circuit is provided between adjacent two memory arrays, the distance from the read / write control circuit to the corresponding array unit can be greatly shortened, thereby reducing the length of the data signal line and improving the data transmission efficiency.

[0055] The following will describe this embodiment in detail with reference to the accompanying drawings. It should be noted that for ease of explanation, the following embodiment takes the storage block including 3 storage arrays 101 and 4 read / write control circuits 102 as an example. It can be known that in the embodiments of the present application, the numbers of the storage arrays 101 and the read / write control circuits 102 can also be other numbers and can be set according to actual needs. At the same time, for ease of illustration, Figure 2 and Figure 5 both the thick solid line symbols and the thick dashed line symbols marked in the figure indicate electrical connections, that is, having electrical contact points. The difference between the thick solid line and the thick dashed line is only the sorting position of the connected memory arrays. Among them, the thick solid line is connected to the memory arrays with odd sorting, and the thick dashed line is connected to the memory arrays with even sorting.

[0056] As Figure 2 shown, in this embodiment, the storage block may include 3 storage arrays U, V, and W. Each storage array 101 is divided into two array units (such as array unit 1101 and array unit 1102) along the second direction Y; 4 read / write control circuits 102 are located between any two storage arrays 101. Each read / write control circuit 102 can be electrically connected to any one or more array units in the 3 storage arrays 101, but it is necessary to satisfy that different array units of each storage array 101 are electrically connected to different read / write control circuits 102 through different data signal lines YIO.

[0057] For example, four read / write control circuits 102 are located between the memory array V and the memory array W. Each of the two read / write control circuits 102 close to the memory array V is connected to an array unit in the memory array U and an array unit in the memory array V. Among them, one read / write control circuit 102 is connected to the array units 1101 in the memory arrays V and U, and this read / write control circuit 102 is connected to the memory array with an odd number in the sorting of the two array units 1101 through the data signal line YIO1, and is connected to the memory array with an even number in the sorting of the two array units 1101 through the data signal line YIO2; similarly, the other read / write control circuit 102 is connected to the two array units 1102 in the memory arrays V and U, and this read / write control circuit 102 is connected to the memory array with an odd number in the sorting of the two array units 1102 through the data signal line YIO1, and is connected to the memory array with an even number in the sorting of the two array units 1102 through the data signal line YIO2. Each of the two read / write control circuits 102 close to the memory array W is connected to an array unit in the memory array W. Among them, one read / write control circuit 102 is connected to the array unit 1101 in the memory array W; this read / write control circuit 102 is simultaneously connected to the memory arrays with odd and even numbers in the sorting of the array unit 1101 through the data signal line YIO1 and the data signal line YIO2; similarly, the other read / write control circuit 102 is connected to the array unit 1102 in the memory array W; this read / write control circuit 102 is simultaneously connected to the memory arrays with odd and even numbers in the sorting of the array unit 1102 through the data signal line YIO1 and the data signal line YIO2.

[0058] In actual wiring design, the array units with relatively close distances can be designed to be connected to the read / write control circuit 102 to reduce the wiring cost. It should be noted that an array unit is not only connected to one YIO. The data signal lines YIO1 and YIO2 are only general references to one of the data signal lines connected to a memory array in the array unit.

[0059] Each memory array 101 includes a memory array (such as Figure 2 the numbers 0, 1, 2,... shown therein) and a sense amplifier array (Sense Amplifier, SA) ( Figure 2 not shown in the figure, please refer to Figure 1 ). The memory array includes a plurality of memory cells for storing data; the sense amplifier array is used to amplify the output signal of the memory array. The number of memory arrays and sense amplifier arrays included in each array unit can be the same or different.

[0060] Compared with the solution where all memory arrays in a storage array 101 are electrically connected to data signal lines and electrically connected to a read / write control circuit through the data signal lines, in this embodiment, in a single read operation or write operation, the data signal line is only connected to one array unit in the storage array 101, that is, the data signal line is only electrically connected to a part of the memory arrays, so that the number of electrical contact points is reduced. Thus, not only can the parasitic circuits and parasitic capacitances in the storage block be reduced, but also the load on the data signal line is significantly reduced, and therefore the power consumption of the storage block can be significantly reduced.

[0061] In addition, since different data signal lines are connected to different array units, the length of the data signal line can be reduced. For example Figure 2 in, among the two array units of each storage array 101, the array unit 1101 and the array unit 1102 adopt two mutually disconnected data signal lines (the data signal line YIO1 and the data signal line YIO2 are also divided into two segments respectively). That is: the data signal line on the side of the array unit 1101 in the storage array is only electrically connected to the array unit 1101 and does not need to extend to the side of the array unit 1102; similarly, the data signal line on the side of the array unit 1102 in the storage array is only electrically connected to the array unit 1102 and does not need to extend to the side of the array unit 1101, thereby reducing the length of the data signal line, which is beneficial to further reducing the resistance of the data signal line and the consumed power, and thus further reducing the power consumption of the storage block.

[0062] In summary, the storage block provided in this embodiment consumes less power each time, and correspondingly, the storage block has the advantage of low power consumption.

[0063] In the related art, for DRAM, data often appears incorrect during the data storage process. Therefore, ECC (Error Checking and Correcting) technology is required to ensure the correctness of data storage. The related art usually uses adding parity bits on the basis of a certain length of valid data bits to detect and correct the incorrect data. The ECC technology in the related art still has deficiencies.

[0064] Analysis shows that if there is one bit error in the data, the ECC check technology can not only detect it but also correct it. The ECC check can also detect 2 - 4 bit errors. However, it is difficult for the ECC check to correct errors of 2 bits and above. That is to say, although the ECC check technology can simultaneously detect and correct single-bit errors, if two or more bits of data are detected as having errors at the same time, the current ECC check technology is powerless. In addition, further analysis shows that the probability of two adjacent data appearing incorrect at the same time is relatively high currently. Further analysis shows that the main reasons for this problem are as follows:

[0065] Figure 3 It is a schematic top view layout of a memory. The memory includes: a plurality of active regions 10 arranged in an array; word lines 12, bit lines 11, and capacitors 13 electrically connected to the active regions. There are defects of adjacent cell to cell bridge in the memory, or called adjacent two-bit errors. For example, there is a bridge between capacitors 91 and 92 corresponding to adjacent active regions 10, as shown by the dashed box in Figure 3 . Capacitor 91 is connected to bit line BL3 through a transistor, and capacitor 92 is connected to bit line BL2 through a transistor. As the process size of the memory gets smaller and smaller, the occurrence probability of this kind of defect is also getting larger and larger.

[0066] Figure 4 It is a schematic diagram of the structure of a memory. The memory includes: a memory array composed of memory cells 14, each memory cell 14 is connected to a bit line BL and a word line WL; a column selection signal unit, marked as CSL in Figure 4 <n-1>, CSL <n>and CSL<n+1>. Each column selection signal unit includes multiple column selection signal lines. Each column selection signal line is connected to the corresponding bit line BL in the memory array and the local data bus through a switch. The control signal of the switch comes from a column decoding circuit (not shown in Figure 4 ), which is used to determine whether the data on the bit line BL is transmitted to the local data bus. For example, the column selection signal unit CSL <n>Including 8 column selection signal lines, and the 8 column selection signal lines are connected to the local data bus through the bit lines BL in the storage array controlled by switches; the local data bus is labeled as LIO in Figure 4 , where LIO:O<3:0> labels the local data buses with odd numbers, and LIO:E<3:0> labels the local data buses with even numbers; the block data bus is labeled as YIO in Figure 4 , where YIO:O<3:0> labels the block data buses with odd numbers, and YIO:E<3:0> labels the block data buses with even numbers. The local data bus is connected to the block data bus through a local conversion circuit (such as a local sense amplifier circuit, Figure 4 not shown in the figure). Figure 4 The interaction between YIO:E<3:0> and LIO:E<3:0>, and the interaction between YIO:O<3:0> and LIO:O<3:0> are schematically shown by arc curves in

[0067] Combined with Figure 3 and Figure 4 , the block data buses YIO:E<3:0> and YIO:O<3:0> are connected to the same error detection and correction unit 15. If the two bit lines BL corresponding to two storage units 14 are exactly connected to the same column decoding circuit, then two errors occur simultaneously at the same read time point. For example, Figure 3 the storage unit 91 and the storage unit 92 in Figure 3 (91 and 92 represent capacitors in Figure 4 , while 91 and 92 represent storage units in Figure 3 and Figure 4 . Here, they are labeled the same to illustrate adjacent two-bit errors in combination with <n>Transfer its data to local data lines LIO:O<3:0> and local data lines LIO:E<3:0>, and then transfer the data to YIO:E<3:0> and YIO:O<3:0> through the local conversion circuit. Then, two-bit errors enter the error detection and correction unit 15 simultaneously. The currently used ECC (for example, for ECC of 128 bits (data bits) + 8 bits (parity bits), it can only correct one bit) cannot correct the above two-bit errors.

[0068] To solve the above problems, another embodiment of the present invention further provides a storage block, which is substantially the same as the storage block provided in the previous embodiment. The difference is that a plurality of memory arrays 101 are used to store data and parity codes; the storage block further includes: a plurality of error detection and correction units, which are arranged between two adjacent memory arrays 101 and are electrically connected to a plurality of read / write control circuits 102, and are used to detect and / or correct data according to the parity codes; wherein, during a read operation, the data and parity codes read out by the read / write control circuit 102 are divided into at least two parts, and the read / write control circuit 102 is configured to transmit each part to a different error detection and correction unit. Since the read / write control circuit 102 divides the output data of the array unit into at least two parts during each read operation, and the read / write control circuit 102 transmits each part to a different error detection and correction unit, when more than one error appears in the output data of the array unit simultaneously, different errors can be corrected by different error detection and correction units, so that the storage block can correct more than one error and improve the error detection and correction ability of the storage block. The storage block provided in this embodiment will be described below with reference to the accompanying drawings. It should be noted that for the same or corresponding parts as those in the previous embodiment, please refer to the detailed description of the previous embodiment, and the following will not be elaborated in detail.

[0069] As Figure 5 shown, the number of a plurality of error detection and correction units 103 in the storage block can be two, and they are arranged close to the read / write control circuit 102 and are respectively electrically connected to the above 4 read / write control circuits 102, and are used to detect and / or correct the read data according to the parity codes read from the array unit each time. Wherein, during a read operation, the data and parity codes read out by the read / write control circuit 102 from the array unit are divided into at least two parts (such as randomly distributed, or distributed according to the parity of the serial number of the memory array where the data is located), and the read / write control circuit 102 is configured to transmit one part to one error detection and correction unit and the remaining part to another error detection and correction unit.

[0070] For example Figure 5 In this case, each read / write control circuit 102 divides all the parity codes and data read from the array cells into two parts. Among these two parts, one part is transmitted by the read / write control circuit 102 to the error detection and correction unit 103 near the array cell 1101, and the remaining part is transmitted by the read / write control circuit 102 to the error detection and correction unit 1032 near the array cell 1102.

[0071] Since the write control circuit 102 divides the output data of the array cell into at least two parts during each read operation, and the read / write control circuit 102 transmits each part to a different error detection and correction unit, when more than one error occurs simultaneously in the output data of the array cell, different errors can be corrected by different error detection and correction units, so that the memory block can correct more than one error, improving the error detection and correction ability of the memory block and the read / write performance of the memory.

[0072] The memory block of this embodiment further includes: a row decoding circuit (not shown in the figure), which is used to issue a row decoding signal to locate the word lines in different selected array cells.

[0073] For example, when the row decoding signal locates and selects the array cells 1101 in the memory arrays U and V, the data signal lines YIO1 or YIO2 on one side of the array cells 1101 in the memory arrays U and V will read the data in the corresponding array cells 1101.

[0074] Figure 6 A memory block provided for another embodiment of the present invention. On the basis of any of the foregoing memory block structures, the number of several error detection and correction units 103 is two, and they can be respectively:

[0075] The first error detection and correction unit 1031 is connected to each array cell through the read / write control circuit 102 and is used to perform error detection and correction on a part of the output data of the array cell; the second error detection and correction unit 1032 is connected to each array cell through the read / write control circuit 102 and is used to perform error detection and correction on the remaining output data part of the array cell.

[0076] In this example, the layout of the memory arrays can refer to Figure 3 and Figure 4 . In this embodiment, taking the output data of the memory array U as 136 bits as an example, among them, 128 bits of data are valid data (data that the memory needs to interact with the external controller through the memory interface), and 8 bits of data are parity codes generated after being processed by the first error detection and correction unit 1031 and the second error detection and correction unit 1032. It should be noted that the memory includes a write data operation and a read data operation. When performing a write data operation on the memory array in the memory, the data received by the memory interface passes through the ECC module (such as Figure 6 The first error detection and correction unit 1031 and the second error detection and correction unit 1032) in it are processed. For example, when entering the ECC module, the data is 128 bits. This 128-bit data is also called valid data. The data output by the ECC module is 136 bits (128 bits of valid data + 8 bits of parity code). Among them, 128 bits of data are valid data, and 8 bits are the parity code generated by the ECC module. These 136 bits will be stored in the storage array of the storage array U. It can be said that the ECC module is in the encoding process for the write data operation; when reading data from the storage array in the memory, 136 bits (128 bits of valid data + 8 bits of parity code) of data are also output from the storage array U. These 136 bits enter the ECC module at the same time. At this time, the ECC module executes an algorithm opposite to the writing algorithm. It can be said that the ECC module is in the decoding process for the read data operation. The ECC module decodes the 128 bits of valid data and compares the result of the decoding operation with the 8-bit parity code to determine whether there is an error in the output 128 bits of valid data. If there is only 1 bit error in every 64 bits (one-bit error), the ECC module can also correct the one-bit error.

[0077] Continue to refer to Figure 6 , in this embodiment, for example, taking the case of reading out 272 bits of data (256 bits of stored data + 16 bits of check code) from storage array U and storage array V as an example, the output data of 136 bits (128 bits of stored data + 8 bits of check code) read out from storage array U are respectively output to the first error detection and correction unit 1031 and the second error detection and correction unit 1032, and the output data of 136 bits (128 bits of stored data + 8 bits of check code) read out from storage array V are respectively output to the first error detection and correction unit 1031 and the second error detection and correction unit 1032. A comparative embodiment is provided. Storage array U outputs the output data of 138 bits (128 bits of stored data + 8 bits of check code) to the first error detection and correction unit 1031, and storage array V outputs the output data of 136 bits (128 bits of stored data + 8 bits of check code) to the second error detection and correction unit 1032. In comparison, since part of the output data of storage array U (or storage array V) is input to the first error detection and correction unit 1031 for error detection and correction, and the remaining output data is input to the second error detection and correction unit 1032 for error detection and correction, when more than one error occurs simultaneously in the output data of storage array U (or storage array V) (for example, two-bit error), different errors can be corrected by the first error detection and correction unit 1031 or the second error detection and correction unit 1032, so that the memory can correct more than one error, improving the error detection and correction ability of the memory.

[0078] In this embodiment, the number of bits of data received by the first error detection and correction unit 1031 is the same as the number of bits of data received by the second error detection and correction unit 1032. In an example, the number of bits of data received by the first error detection and correction unit 1031 and the number of bits of data received by the second error detection and correction unit 1032 are both 128 bits + 8 bits. Among them, 128 bits are the valid data written or read by storage array U and storage array V, and 8 bits are the check code generated by the first error detection and correction unit 1031 or the second error detection and correction unit 1032..

[0079] In addition, the internal error detection algorithm of the first error detection and correction unit 1031 is the same as the internal error detection algorithm of the second error detection and correction unit 1032. In this way, it is beneficial to reduce the design difficulty of the memory.

[0080] Taking the first error detection and correction unit 1031 as an example, each time data is written, the first error detection and correction unit 1031 uses an internal error detection algorithm to calculate the valid data (128 bits), and obtains a check bit (8 bits), denoted as the first check bit. Then, the valid data (128 bits) and the check bit (8 bits) are written into the storage array 101 at the same time. When these data are read out from the storage array 101, the valid data (128 bits) is calculated again using the same algorithm to obtain a check bit (8 bits), denoted as the second check bit. The second check bit is compared with the directly read first check bit. If the results are the same, it means the data is correct; otherwise, it means there is an error. The first error detection and correction unit 1031 can logically detect the error. When only one-bit error occurs, the first error detection and correction unit 1031 can correct the error without affecting the memory read operation. For example, when the "0" at the 3rd bit of 128 bits is the error bit, the first error detection and correction unit 1031 corrects the "0" at the 3rd bit to "1".

[0081] Regarding the working principle of the second error detection and correction unit 1032, reference can be made to the first error detection and correction unit 1031, which will not be elaborated below.

[0082] Specifically, part of the output data in the storage array U is input to the first error detection and correction unit 1031 for error detection and correction, and the rest of the output data is input to the second error detection and correction unit 1032 for error detection and correction. In this way, two adjacent bit errors that may occur in the same storage array U are placed in different ECC units respectively. Since these two error data are processed by the first error detection and correction unit 1031 and the second error detection and correction unit 1032 respectively, that is, each of the first error detection and correction unit 1031 and the second error detection and correction unit 1032 only processes one error. Therefore, from the perspective of the memory, this memory can correct these two errors simultaneously.

[0083] Regarding the error detection and correction mechanism when errors occur in the storage array V and the storage array W, reference can be made to the corresponding description of the storage array U, which will not be elaborated here.

[0084] In this embodiment, the storage capacities of the storage arrays U and V and the storage capacity of W are the same. In other embodiments, the storage capacities of the storage arrays U, V, and W may not be exactly the same.

[0085] Combined with reference Figure 6 and Figure 7 , Figure 7 For Figure 6 Schematic diagram of signal line connection of a partial area represented by a thick line in a checkerboard of the storage array 101 (shown schematically with the storage array U expanded, the thick solid line is only connected to odd checkerboards, the thick dashed line is only connected to even checkerboards, and the storage arrays V and W are the same as the storage array U). The local data bus LIO is connected to a plurality of sense amplifiers (not shown) through the column selection signal unit 109, and the sense amplifiers are arranged in one-to-one correspondence with the bit lines BL of the storage unit 105. The column selection signal unit 109 includes a strobe switch, and the column select signal controls the conduction or cut-off of the strobe switch. When the strobe switch is conductive, the sense amplifier exchanges data with the local data bus LIO. When the strobe switch is cut off, the sense amplifier no longer exchanges data with the local data bus LIO. In addition, the output data on adjacent bit lines BL enter the local data bus O and the local data bus E through the sense amplifier and the column selection signal unit 109 respectively. For the sake of distinction, Figure 7 in LIO:E indicates the local data bus E, and LIO:O indicates the local data bus O, with CSL <n-1>, CSL <n>And CSL<n+1> shows a column selection signal unit, where a strobe switch is located in the column selection signal unit (not shown), and sense amplifiers are located on both sides of the bit line BL (not shown). The local data bus E also exchanges data with the block data bus E through a local conversion circuit (not shown), and the local data bus O also exchanges data with the block data bus O through a local conversion circuit (not shown). In Figure 7 the block data bus E is schematically shown by a solid line YIO:E with an arrow, and the block data bus O is schematically shown by a dashed line YIO:O with an arrow.

[0086] Continuing to refer to Figure 6 one of the block data buses O is denoted by YIO1_O, and one of the block data buses E is denoted by YIO1_E. In one embodiment, Figure 7 YIO:E in Figure 7 can be understood as one of the YIO1_E, and YIO:O in

[0087] Continuing to refer to Figure 6 the data of YIO_O enters the first error detection and correction unit 1031, and the data of YIO_E enters the second error detection and correction unit 1032. In this embodiment, the storage arrays U, V, and W each include a local conversion circuit (LocalSA, not shown) and an even number of local data buses. The local data buses are divided into local data bus O and local data bus E. The local data bus O is connected to the block data bus O through a local conversion circuit, and the local data bus E is connected to the block data bus E through a local conversion circuit.

[0088] It should be noted that the local data buses are numbered in sequence from zero as natural numbers. The local data buses with odd numbers are defined as local data bus O, and the local data buses with even numbers are defined as local data bus E; or rather, among the local data buses corresponding to physically adjacent storage arrays, the local data buses in odd positions are defined as local data bus O, and the local data buses in even positions are defined as local data bus E.

[0089] Since physically adjacent data is placed in different error detection and correction units, that is, it enters the first error detection and correction unit 1031 and the second error detection and correction unit 1032 respectively. When two adjacent bit errors occur, since these two bit errors are corrected in different error detection and correction units respectively, these two bit errors can be processed simultaneously. It can be understood that even if the process size is continuously reduced and the risk of bridging between adjacent capacitors increases, since the data corresponding to adjacent capacitors enters different error detection and correction units for error correction, even if the process size is continuously reduced, the errors of two physically adjacent bits of data can still be corrected.

[0090] Continue to refer to Figure 6 , the arrangement of the memory arrays in the memory array U is numbered starting from 0 according to natural numbers. The block data bus is electrically connected to the memory arrays with even numbers. More specifically, the memory array includes memory cells, a local data bus E, a local data bus O, and a local conversion circuit. The block data bus is connected to the local data bus E through the local conversion circuit; the block data bus is connected to the local data bus O through the local conversion circuit. Figure 6 The connection relationship between the block data bus and the memory array is marked with thick line symbols in

[0091] It can be understood that in one example, the block data bus is 2 * 4 * (16 * N) strips, and the local data bus is 2 * 4 * M * (16 * N) strips; the block data bus O is 4 * (16 * N) strips, and the block data bus E is 4 * (16 * N) strips; the local data bus O is 4 * M * (16 * N) strips, and the local data bus E is 4 * M * (16 * N) strips; 1 strip of block data bus O corresponds to M strips of local data bus O, and 1 strip of block data bus E corresponds to M strips of local data bus E; the local data bus is divided into M * (16 * N) groups of local data bus O and M * (16 * N) groups of local data bus E with 4 adjacent strips as a group. Among them, M and N are natural numbers greater than or equal to 1. Taking M and N both being 1 as an example, the block data bus is 2 * 4 * 16 strips, the local data bus is 2 * 4 * 16 strips, the block data bus O is 4 * 16 strips, the block data bus E is 4 * 16 strips, the local data bus O is 4 * 16 strips, the local data bus E is 4 * 16 strips, and there are 16 groups of local data bus O and 16 groups of local data bus E in total.

[0092] In one example, such as Figure 6 As shown, the data signal lines corresponding to each array unit include an even number of block data buses. The block data buses are numbered in sequence from zero as natural numbers. The block data buses with odd numbers O (denoted as YIO_O) are connected to the first error detection and correction unit 1031 through the read / write control circuit 102, and the block data buses with even numbers E (denoted as YIO_E) are connected to the second error detection and correction unit 1032 through the read / write control circuit 102; each array unit in the storage array U includes an even number of block data buses. The block data buses are numbered in sequence from zero as natural numbers. The block data buses with odd numbers O (denoted as YIO_O) are connected to the first error detection and correction unit 1031 through the read / write control circuit 102, and the block data buses with even numbers E (denoted as YIO_E) are connected to the second error detection and correction unit 1032 through the read / write control circuit 102; each array unit in the storage array V includes an even number of block data buses. The block data buses are numbered in sequence from zero as natural numbers. The block data buses with odd numbers O (denoted as YIO_O) are connected to the first error detection and correction unit 1031 through the read / write control circuit 102, and the block data buses with even numbers E (denoted as YIO_E) are connected to the second error detection and correction unit 1032 through the read / write control circuit 102; each array unit in the storage array W includes an even number of block data buses. The block data buses are numbered in sequence from zero as natural numbers. The block data buses with odd numbers O (denoted as YIO_O) are connected to the first error detection and correction unit 1031 through the read / write control circuit 102, and the block data buses with even numbers E (denoted as YIO_E) are connected to the second error detection and correction unit 1032 through the read / write control circuit 102.

[0093] In this way, the data of the block data buses O (YIO_O) of the storage arrays U, V, and W enter the first error detection and correction unit 1031 through the read / write control circuit 102 for error detection and correction; the data of the block data buses E (YIO_E) of the storage arrays U, V, and W enter the second error detection and correction unit 1032 through the read / write control circuit 102 for error detection and correction.

[0094] In another example, the data signal lines corresponding to each array unit include an even number of block data buses. The block data buses are numbered in sequence from zero according to natural numbers. The block data buses with odd numbers (denoted as YIO_O) are connected to the second error detection and correction unit 1032, and the block data buses with even numbers (denoted as YIO_E) are connected to the first error detection and correction unit 1031. Each array unit in the storage array U includes an even number of block data buses. The block data buses are numbered in sequence from zero according to natural numbers. The block data buses with odd numbers (denoted as YIO_O) are connected to the second error detection and correction unit 1032, and the block data buses with even numbers (denoted as YIO_E) are connected to the first error detection and correction unit 1031; each array unit in the storage array V includes an even number of block data buses. The block data buses are numbered in sequence from zero according to natural numbers. The block data buses with odd numbers (denoted as YIO_O) are connected to the second error detection and correction unit 1032, and the block data buses with even numbers (denoted as YIO_E) are connected to the first error detection and correction unit 1031; each array unit in the storage array W includes an even number of block data buses. The block data buses are numbered in sequence from zero according to natural numbers. The block data buses with odd numbers (denoted as YIO_O) are connected to the second error detection and correction unit 1032, and the block data buses with even numbers (denoted as YIO_E) are connected to the first error detection and correction unit 1031.

[0095] In this way, the data on the block data buses O (YIO_O) of the storage arrays U, V, and W enter the second error detection and correction unit 1032 for error detection and correction; the data on the block data buses E (YIO_E) of the storage arrays U, V, and W enter the first error detection and correction unit 1031 for error detection and correction.

[0096] For the storage block provided in this embodiment, since the output data of the same array unit are respectively input into different error detection and correction units, that is, part of the output data is input into the first error detection and correction unit 1031 for error detection and correction, and the rest of the output data is input into the second error detection and correction unit 1032 for error detection and correction. In this way, if two-bit data errors occur simultaneously, the first error detection and correction unit 1031 and the second error detection and correction unit 1032 can respectively correct one bit of the two bits of data, thereby improving the error detection and correction ability of the memory.

[0097] Continuing to refer to Figure 6 , in this embodiment, there are multiple read / write control circuits 102, and they are divided into a first type of read / write control circuit 102 and a second type of read / write control circuit 102;

[0098] Each first - type read - write control circuit 102 corresponds to two array units. The first - type read - write control circuit 102 includes: a first read - write control unit 1021 and a second read - write control unit 1022; the first read - write control unit 1021 is connected between the odd - numbered block data bus O of the corresponding array unit and the first error detection and correction unit 1031, and the second read - write control unit 1022 is connected between the even - numbered block data bus E of the corresponding array unit and the second error detection and correction unit 1032;

[0099] Each second - type read - write control circuit 102 corresponds to one array unit. The second - type read - write control circuit 102 is used to be integrally connected between all the block data buses (odd - numbered block data bus O+even - numbered block data bus E) of the corresponding array unit and the first error detection and correction unit 1031 and the second error detection and correction unit 1032.

[0100] Reference Figure 6 , in this embodiment, while retaining part of the read - write control circuits 102 that integrally receive the data transmitted by the odd - numbered block data bus O and the even - numbered block data bus E of the array unit ( Figure 6 the two read - write control circuits 102 close to the array unit W in

[0101] ), two read - write control units are designed by splitting one read - write control circuit 102. One read - write control unit 1021 is responsible for specifically receiving the data transmitted by the odd - numbered block data bus O of the array unit, and the other read - write control unit 1022 is responsible for specifically receiving the data transmitted by the even - numbered block data bus E of the same array unit. By specifically setting two read - write control units that respectively receive the data transmitted by the odd - numbered block data bus O and the even - numbered block data bus E of the array unit, the differential management of data can be improved and the design cost can be saved.

[0102] Figure 8 This is a schematic structural diagram of a storage block provided by another embodiment of the present invention.

[0103] In some embodiments of the present application, the output data of two array units of the storage array U, the storage array V, and the storage array W respectively correspond to high-order data and low-order data. For example, in the storage array U, the array unit 1101 stores high-order data, and the array unit 1102 stores low-order data; in the storage array V, the array unit 1101 on the side with a smaller memory array sorting number stores low-order data, and the array unit 1102 stores high-order data; in the storage array W, the array unit 1101 stores high-order data, and the array unit 1102 stores low-order data. In this way, since the data output by the two array units of the storage array U, the storage array V, and the storage array W includes low-order data and high-order data, only one array unit storing high-order data and another array unit storing low-order data located in a different storage array 101 in the storage array U, the storage array V, or the storage array W will be accessed in a single access, thereby reducing the power consumption of the memory.

[0104] Reference Figure 8 , the above-mentioned several storage arrays 101 (the remaining structures other than the storage array 101 can be referred to the descriptions in the foregoing embodiments and will not be elaborated here) include a storage array U, a storage array V, and a storage array W arranged in sequence along the first direction; each storage array is divided into two array units along the second direction; two array units on the same side in the second direction in the storage array U and the storage array V share the same word line address; the read / write control circuits corresponding to the storage array U and the storage array V are associated and configured to simultaneously access the storage units with the same word line address in the two array units on the same side in the storage array U and the storage array V.

[0105] Specifically, it can be that two array units on the first side in the storage array U and the storage array V share the same word line address; the read / write control circuits corresponding to the storage array U and the storage array V are associated and configured to simultaneously access the storage units with the same word line address in the two array units on the first side in the storage array U and the storage array V; or, two array units on the second side in the storage array U and the storage array V share the same word line address, and the first side and the second side are opposite sides in the second direction; the read / write control circuits corresponding to the storage array U and the storage array V are associated and configured to simultaneously access the storage units with the same word line address in the two array units on the second side in the storage array U and the storage array V.

[0106] For example, reference Figure 8 , taking the side where the array unit 1101 in the storage array U and the storage array V is located as the first side, the side where the array unit 1102 is located as the second side, and the two array units on the first side in the storage array U and the storage array V sharing the same word line address as an example. At this time, the two array units 1101 in the storage arrays U and V can share the same word line address, that is, the same word line address can access the storage arrays with the same word line address. For example, accessing the word line address corresponding to 1 can simultaneously access the data in the memory array numbered 3 in the storage arrays U and V.

[0107] Continue to refer to Figure 8 , when the two array units on the first side in the storage array U and the storage array V share the same word line, the two array units on the second side in the storage array U and the storage array V share the same word line address; the read / write control circuits 102 corresponding to the storage arrays U and V are associated and configured to simultaneously access the two array units on the second side in the storage arrays U and V; when the two array units on the second side in the storage array U and the storage array V share the same word line address, the two array units on the first side in the storage array U and the storage array V share the same word line address; the read / write control circuits 102 corresponding to the storage arrays U and V are associated and configured to simultaneously access the two array units on the first side in the storage arrays U and V.

[0108] Specifically, refer to Figure 8 , taking the side where the array unit 1101 in the storage array U and the storage array V is located as the first side, the side where the array unit 1102 is located as the second side, and the two array units on the first side in the storage array U and the storage array V sharing the same word line address as an example. When the two array units 1101 in the storage arrays U and V share the same word line address, the two array units 1102 in the storage arrays U and V can also share the same word line address, that is, the same word line can access the memory arrays with the same word line address. For example, accessing the word line address corresponding to 2 can simultaneously access the data in the memory array numbered 20 in the storage arrays U and V.

[0109] Continue to refer to Figure 8 , when the two array units on the first side in the storage array U and the storage array V share the same word line address and / or the two array units on the second side share the same word line address, the two array units on the first side and the second side in the storage array W share the same word line address; the read / write control circuit corresponding to the storage array W is associated and configured to simultaneously access the array units on the first side and the second side in the storage array W.

[0110] Specifically, refer to Figure 8 , taking the side where the array unit 1101 is located in the storage array U and the storage array V as the first side, the side where the array unit 1102 is located as the second side, and taking the example that two array units on the first side in the storage array U and the storage array V share the same word line address. When two array units 1101 in the storage array U and the storage array V share the same word line address, two array units (array unit 1101 and array unit 1102) in the storage array W can also share the same word line address, that is, the same word line can access memory arrays with the same word line address. For example, accessing the word line address corresponding to 3 can simultaneously access the data in the array unit 1101 in the storage array W and the data in the memory array numbered 38 in the array unit 1102.

[0111] Compared with the foregoing embodiments, the storage block provided in this embodiment can realize that the data in two array units can be accessed simultaneously because the word line addresses are the same by configuring the access states of the read / write control circuits corresponding to each storage array, and can realize flexible access data combinations.

[0112] Based on the storage blocks in the above embodiments, this embodiment further provides a memory, and this memory includes the storage blocks in any one or at least two combined embodiments of the above.

[0113] Those of ordinary skill in the art can understand that the above embodiments are specific embodiments for implementing the present invention, and in practical applications, various changes can be made in form and details without departing from the spirit and scope of the present invention. Any person skilled in the art can make their own changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.< / n> < / n> < / n> < / n> ​

Claims

1. A storage block, characterized in that, Including: A plurality of memory arrays arranged along a first direction, each of the memory arrays being divided into at least two array units along a second direction, the first direction being perpendicular to the second direction; A read / write control circuit disposed between two adjacent memory arrays; Data signal lines for electrically connecting the read / write control circuit and the array units; Wherein different array units of each memory array are electrically connected to different read / write control circuits through different data signal lines; The plurality of memory arrays are used for storing data and parity codes; The memory block further includes: A plurality of error detection and correction units disposed between two adjacent memory arrays and electrically connected to the plurality of read / write control circuits for detecting and / or correcting errors in the data according to the parity codes; The plurality of error detection and correction units at least include: A first error detection and correction unit connected to each array unit through the read / write control circuit for detecting and correcting errors in a part of the output data of the array unit; A second error detection and correction unit connected to each array unit through the read / write control circuit for detecting and correcting errors in the remaining output data of the array unit; Each data signal line corresponding to an array unit includes an even number of block data buses. The block data buses are numbered in natural numbers starting from zero. The block data buses numbered odd are connected to the first error detection and correction unit, and the block data buses numbered even are connected to the second error detection and correction unit.

2. The memory block according to claim 1, wherein Each array unit includes a local conversion circuit and an even number of local data buses. The local data buses are divided into local data bus O and local data bus E. The local data bus O is connected to the block data bus O through the local conversion circuit, and the local data bus E is connected to the block data bus E through the local conversion circuit.

3. The memory block according to claim 2, characterized in that Each local data bus is connected to a plurality of sense amplifiers through a selection switch, and the sense amplifiers are arranged in one-to-one correspondence with bit lines in the memory array.

4. The memory block according to claim 3, wherein The output data on two adjacent bit lines enter the local data bus O and the local data bus E respectively through the sense amplifier and the selection switch.

5. The memory block according to claim 4, wherein, The block data buses are 2*4*(16*N) in number, and the local data buses are 2*4*M*(16*N) in number; The block data bus O is 4*(16*N) in number, and the block data bus E is 4*(16*N) in number; The local data bus O is 4*M*(16*N) in number, and the local data bus E is 4*M*(16*N) in number; 1 block data bus O corresponds to M local data buses O, and 1 block data bus E corresponds to M local data buses E; The local data buses are divided into M*(16*N) groups of local data buses O and M*(16*N) groups of local data buses E in groups of 4 adjacent ones.

6. The memory block according to any one of claims 1-5, characterized in that, There are a plurality of the read / write control circuits, which are divided into a first type of read / write control circuit and a second type of read / write control circuit; Each of the first - type read - write control circuits corresponds to two of the array units. The first - type read - write control circuit includes: a first read - write control unit and a second read - write control unit. The first read - write control unit is connected between the odd - numbered block data bus O of the corresponding array unit and the first error detection and correction unit, and the second read - write control unit is connected between the even - numbered block data bus E of the corresponding array unit and the second error detection and correction unit. Each of the second - type read - write control circuits corresponds to one of the array units. The second - type read - write control circuit is used to be integrally connected between all the block data buses of the corresponding array unit and the first error detection and correction unit and the second error detection and correction unit.

7. A storage block, characterized in that, Comprising: A plurality of memory arrays arranged along a first direction. Each memory array is divided into at least two array units along a second direction, and the first direction is perpendicular to the second direction. A read - write control circuit, which is arranged between two adjacent memory arrays. Data signal lines for electrically connecting the read - write control circuit and the array units. Wherein, different array units of each memory array are electrically connected to different read - write control circuits through different data signal lines. The plurality of memory arrays include memory array U, memory array V, and memory array W arranged in sequence along the first direction. Each memory array is divided into two array units along the second direction. Two array units on the same side in the second direction of memory array U and memory array V share the same word - line address. The read - write control circuits corresponding to memory array U and memory array V are associated and configured to simultaneously access the memory cells with the same word - line address in the two array units on the same side in memory array U and memory array V.

8. The storage block according to claim 7, wherein Two array units on the first side of memory array U and memory array V share the same word - line address. The read - write control circuits corresponding to memory array U and memory array V are associated and configured to simultaneously access the memory cells with the same word - line address in the two array units on the first side of memory array U and memory array V; or, Two array units on the second side of memory array U and memory array V share the same word - line address. The first side and the second side are opposite sides in the second direction. The read - write control circuits corresponding to memory array U and memory array V are associated and configured to simultaneously access the memory cells with the same word - line address in the two array units on the second side of memory array U and memory array V.

9. The storage block according to claim 8, wherein When two array units on the first side of memory array U and memory array V share the same word - line address, two array units on the second side of memory array U and memory array V share the same word - line address. The read - write control circuits corresponding to memory array U and memory array V are associated and configured to simultaneously access the two array units on the second side of memory array U and memory array V. When two array cells on the second side in the storage array U and the storage array V share the same word line address, two array cells on the first side in the storage array U and the storage array V share the same word line address; The read / write control circuits corresponding to the storage array U and the storage array V are associated and configured to simultaneously access two array cells on the first side in the storage array U and the storage array V.

10. The storage block according to claim 9, wherein When two array cells on the first side in the storage array U and the storage array V share the same word line address and / or two array cells on the second side in the storage array U and the storage array V share the same word line address, two array cells on the first side and the second side in the storage array W share the same word line address; The read / write control circuit corresponding to the storage array W is associated and configured to simultaneously access the array cells on the first side and the second side in the storage array W.

11. The storage block according to claim 1, characterized in that, Further comprising: A row decoding circuit for generating a row decoding signal to locate the word lines in different selected array cells.

12. A memory, characterized in that, Including the storage block according to any one of claims 1-11.

Images