Erasing Method and Apparatus for Non-Volatile Memory

Abstract

The present invention discloses an erasing method for a non-volatile memory, comprising: Step 1, performing pre-verification and pre-programming on a selected erasing block. Step 2, recording the first process time for completing Step 1. Step 3, completing the erasing process step. Step 4, dynamically setting a repair interval according to the first process time, the longer the first process time, the smaller the repair interval, and vice versa. Step 5, repairing each storage unit in the erasing interference area within the repair interval, the time for completing the repair operation is the second repair time, and the sum of the first process time and the second repair time is the third time. Step 6, the erasing process ends, and the time for completing the erasing process is the fourth process time. The dynamic setting of the repair interval reduces the variation range of the third time and thus reduces the variation range of the fourth process time. The present invention also provides an erasing device for a non-volatile memory. The present invention can reduce the variation range of the erasing time and improve the reliability of the storage unit.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor integrated circuits, and particularly to an erasing method for a nonvolatile memory. The present invention also relates to an erasing device for a nonvolatile memory. Background Art

[0002] For a floating gate (FG) flash memory, since charges are stored in the floating gate, when there are more charges in the floating gate, the threshold voltage (Vt) of the memory cell is high; when there are fewer charges in the floating gate, the threshold voltage of the memory cell is low. In this way, it is possible to distinguish whether the stored data is "0" or "1" according to the amount of stored charges. Generally defined as: during programming, charges are attracted to the floating gate, there are more charges in the floating gate, the threshold voltage of the memory cell is high, and the stored data is "0"; on the contrary, during erasing, charges are attracted to the floating gate, there are fewer charges in the floating gate, the threshold voltage of the memory cell is low, and the stored data is "1".

[0003] Due to the existence of the floating gate, the voltages of the word line (WL) and the bit line (BL) on a memory cell both affect the floating gate, and the final voltage on the floating gate is jointly determined by the voltages of the word line and the bit line. During a read operation, a word line read voltage (VREAD), such as 5V, is applied to the selected cell word line, a bit line read voltage (VRBL), such as 1V, is applied to the bit line, and a selection voltage (VDSEL), such as 0V, is applied to the unselected cell word lines. However, due to the compactness characteristics of the memory cells, some cell word lines are shared in the row direction, and some cell bit lines are shared in the column direction.

[0004] Due to the compactness characteristics, the shared word lines, bit lines, and the common P-well of the memory cells all affect the characteristics of the memory cells.

[0005] When the flash memory is erased, in the same area, for the selected memory cells, the gate is connected to a negative high voltage, the P-well is connected to a positive high voltage, the source is connected to a positive high voltage or floating, and the drain is floating; for the unselected memory cells, the gate is connected to a positive low voltage or 0V, and the others are the same; at this time, the unselected memory cells will still be interfered by the positive high voltage of the P-well, and there is a weak erasing phenomenon; therefore, it is necessary to verify and repair both "0" and "1" of the unselected memory cells in the same area.

[0006] However, due to the long repair time, for the unselected memory cells in the same area, generally within the number of times that the memory cells can withstand a certain amount of erase interference, only some rather than all of them are repaired; but the fewer the repair frequency, the worse the reliability of the memory cells. This phenomenon is more obvious at high temperatures or after the memory cells have undergone a certain number of erase / write cycles, especially after process scaling.

[0007] In the erase process, in order to keep the distribution during the erase process relatively uniform, the threshold voltage distribution of the memory cells is raised to a relatively high level, and usually pre-programming is performed before each erase. However, in one erase, the number of memory cells to be erased is relatively large, such as 64K bytes. Pre-programming, like programming, is to inject stored charges such as stored electrons into the floating gate. If the floating gate of the memory cell already stores charges, that is, it has been programmed, then the threshold voltage of the memory cell itself is relatively high. At this time, pre-programming is not required for this memory cell or the required pre-programming time is less. However, among these 64K bytes, there may be a relatively large number of programmed bytes or a relatively small number of programmed bytes. When there are a relatively large number of programmed bytes, the required pre-programming time is less; when there are a relatively small number of programmed bytes, the required pre-programming time is more. Therefore, the pre-programming time has a relatively large impact on the erase time, and with different stored data in the erase block, the erase time has a relatively large variation range. The extension of the erase time will ultimately affect the performance of the flash memory.

[0008] The following further explains the existing erase methods as follows:

[0009] As Figure 1 shown, it is a schematic structural diagram of a storage block of an existing non-volatile memory; the storage block is simply referred to as block 100, and block 100 includes multiple erase blocks 101. Figure 1 Figure shows n erase blocks 101, which are respectively marked with numbers from 0, 1 to n - 1; each erase block 101 is formed on the same P-type semiconductor substrate 102. Each erase block 101 is provided with a word line drive circuit 103, and the word line drive circuit 103 provides a drive signal for each word line 104 in the erase block 101. The erase blocks 101 of the entire block 100 include multiple aligned columns of memory cells, and the memory cells in the same column share the same bit line 105. Figure 1 In the figure, the bit line is represented by BL, and there are j bit lines in total, which are respectively marked with numbers from 0, 1 to j - 1. After an erase operation is performed on a certain erase block 101, generally, over-erase repair or erase interference repair is performed on the non-erased area of the same block, that is, the memory cells outside the selected erase block 101. Over-erase repair is the repair of memory cells storing "1", and erase interference repair is the repair of memory cells storing "0".

[0010] AsFigure 2 As shown, it is a flowchart of the erasing method for an existing non-volatile memory; the erasing method for the existing non-volatile memory includes the following steps:

[0011] Step S101: Start to accept an erasing instruction.

[0012] Step S102: Perform erasing initialization, that is, internal initialization of the chip, and set all the erasing block addresses to zero.

[0013] Step S103: Perform erasing block pre-verification and pre-programming operations. Pre-programming is similar to programming, which is also to write charges into the floating gate to ensure that the threshold voltage of the storage units in the erasing block is in a high state before erasing.

[0014] Step S104: Perform erasing of the erasing block. After the pre-programming ends, start the erasing operation, that is, perform the erasing operation on the selected erasing block.

[0015] Step S105: Perform erasing block erasing verification, that is, after each erasing ends, perform erasing verification on the erasing block.

[0016] Step S106: Judge the result of the erasing verification, that is, judge whether "the erasing is passed?".

[0017] If the judgment result of Step S106 is no, then perform:

[0018] Step S107: Judge whether the maximum number of erasings is reached, that is, Figure 2 "Is the maximum number of erasings reached?" shown in. If the judgment result is no, that is, the maximum number is not reached, then go to Step S104.

[0019] If the judgment result of Step S106 is yes or the judgment result of Step S107 is yes, then perform the subsequent Step S108.

[0020] As can be seen from the above, the process in the dotted box 201 corresponds to the whole erasing process steps. The erasing process steps include more than one erasing loop steps. The erasing loop steps are composed of Step S104 to Step S107. Therefore, if the erasing verification is successful within the limited number of times, no more erasing is performed; if the erasing verification fails after exceeding the limited number of times, no more erasing actions are performed.

[0021] Step S108: Perform an over-erasure operation after the erasure of the erasure block is completed. That is, after the process in the dashed box 201 is completed, it indicates that the erasure process of the erasure block is ended, and then the over-erasure operation is performed. The over-erasure operation is used to correct the over-erasure generated during the erasure process. The over-erasure operation includes over-erasure verification and over-erasure programming. The over-erasure verification will detect whether there is over-erasure; the over-erasure programming will perform a certain programming on the floating gate, so that a certain amount of charge is injected into the floating gate, causing a certain change in the threshold voltage of the memory cell.

[0022] After that, perform:

[0023] Step S109: Load a random address in the disturbed area of the same block.

[0024] Step S110: Repair the area in the same block that is disturbed by erasure; that is, when the over-erasure operation after the erasure of the erasure block is completed, then perform other operations, such as anti-interference repair operations, etc.

[0025] When the repair operation is completed, the result of the entire erasure process, that is, Step S111: The erasure of the erasure block is completed. Summary of the Invention

[0026] The technical problem to be solved by the present invention is to provide an erasure method for a non-volatile memory, which can improve the influence of different data stored in the blocks of the memory array on the erasure time, so as to reduce the variation range of the erasure time and thus improve the reliability of the memory cells. For this purpose, the present invention also provides an erasure device for a non-volatile memory.

[0027] To solve the above technical problem, in the erasure method for a non-volatile memory provided by the present invention, the memory array of the non-volatile memory includes a plurality of blocks, and each of the blocks includes a plurality of erasure blocks. The erasure process of a selected erasure block in a selected block includes the following steps:

[0028] Step 1: Perform pre-verification and pre-programming on the selected erasure block.

[0029] Step 2: Record the first process time after completing Step 1. The first process time is determined by the original data stored in the selected erasure block.

[0030] Step 3: Complete the erasure process steps. The erasure process steps include more than one erasure cycle step, and each erasure cycle step realizes an erasure operation on the selected erasure block.

[0031] Step 4: Dynamically set a repair interval in the selected block according to the first process time. The longer the first process time, the smaller the repair interval; the shorter the first process time, the larger the repair interval.

[0032] Step Five: Perform a repair operation to repair each storage unit in the erased interference area within the repair interval. The time taken to complete the repair operation is the second repair time. The smaller the repair interval, the longer the second repair time; the larger the repair interval, the shorter the second repair time. The sum of the first process time and the second repair time is the third time.

[0033] Step Six: The erasure process ends, and the time taken to complete the entire erasure process is the fourth process time.

[0034] When the original data stored in the selected erasure block is different, the fourth process time is different, and the variation range of the fourth process time is determined by the third time. When the original data stored in the selected erasure block is different, the repair interval dynamically set in Step Four reduces the variation range of the third time and thus reduces the variation range of the fourth process time.

[0035] A further improvement is that Step Two includes the following sub-steps:

[0036] Step 21: Start a first time counter before Step One.

[0037] Step 22: After Step One is completed, record the value of the first time counter as the first process time.

[0038] A further improvement is that the original data consists of the data stored in each storage unit, and the data of the storage unit includes "1" and "0". The more the number of "0"s in the data of the storage unit, the shorter the first process time; conversely, the fewer the number of "0"s in the data of the storage unit, the longer the first process time.

[0039] A further improvement is that the selected erasure block includes N bytes, where N is greater than or equal to 1.

[0040] When the data of each storage unit in each byte is "0", the data of the byte is "0". The more the number of "0"s in the data of the byte, the shorter the first process time; conversely, the fewer the number of "0"s in the data of the byte, the longer the first process time.

[0041] A further improvement is that Step Five includes the following sub-steps:

[0042] Step 51: Load a random address in the erased interference area within the repair interval.

[0043] Step 52: Starting from the random address, repair each storage unit in the erased interference area within the repair interval.

[0044] A further improvement is that after step three and before step six, it further includes:

[0045] Step seven, perform an over-erasure operation on the selected erasure block.

[0046] A further improvement is that step four and step five are performed at a selected time point after step three is completed and before step six is completed; or, step four and step five are performed at a selected time point in each of the erasure cycle steps of step three.

[0047] A further improvement is that in step five, the repair operation repairs the "1" storage units and omits the repair of the "0" storage units.

[0048] Or, the repair operation repairs the "0" storage units and omits the repair of the "1" storage units;

[0049] Or, the repair operation repairs the "1" storage units and simultaneously repairs the "0" storage units.

[0050] A further improvement is that each of the storage units of the non-volatile memory is formed in a corresponding P-well;

[0051] All of the blocks of the non-volatile memory are formed in the same respective P-well;

[0052] Or, the non-volatile memory is divided into multiple parts, and multiple blocks in each part share the same P-well;

[0053] Or, each block is independently formed in a P-well;

[0054] Or, each block includes multiple P-wells, and each storage unit is independently formed in the corresponding P-well or multiple storage units share the same corresponding P-well.

[0055] To solve the above technical problems, the erasure device of the non-volatile memory provided by the present invention includes: a process control module, a storage array.

[0056] The storage array includes multiple blocks, and each block includes multiple erasure blocks.

[0057] The process control module controls the erasure process.

[0058] The erasure process for the selected erasure block in a selected block includes the following steps:

[0059] Step one, perform pre-verification and pre-programming on the selected erasure block.

[0060] Step 2. Record the first process time after completing Step 1, where the first process time is determined by the original data stored in the selected erasure block.

[0061] Step 3. Complete the erasure process steps, where the erasure process steps include more than one erasure cycle step, and one erasure operation on the selected erasure block is implemented in each erasure cycle step.

[0062] Step 4. Dynamically set a repair range in the selected block according to the first process time. The longer the first process time, the smaller the repair range; the shorter the first process time, the larger the repair range.

[0063] Step 5. Perform a repair operation to repair each storage unit in the area affected by erasure interference within the repair range. The time to complete the repair operation is the second repair time. The smaller the repair range, the longer the second repair time; the larger the repair range, the shorter the second repair time. The sum of the first process time and the second repair time is the third time.

[0064] Step 6. The erasure process ends, and the time to complete the entire erasure process is the fourth process time.

[0065] When the original data stored in the selected erasure block is different, the fourth process time is different, and the variation range of the fourth process time is determined by the third time. When the original data stored in the selected erasure block is different, the repair range dynamically set in Step 4 reduces the variation range of the third time and thus reduces the variation range of the fourth process time.

[0066] A further improvement is that Step 2 includes the following sub-steps:

[0067] Step 21. Start the first time counter before Step 1;

[0068] Step 22. After completing Step 1, record the value of the first time counter as the first process time.

[0069] A further improvement is that the original data consists of the data stored in each storage unit, the data of the storage unit includes "1" and "0", and the more the number of "0" in the data of the storage unit, the shorter the first process time; conversely, the fewer the number of "0" in the data of the storage unit, the longer the first process time.

[0070] A further improvement is that the selected erasure block includes N bytes, where N is greater than or equal to 1;

[0071] When the data of the storage units in each of the bytes is "0", the data of the byte is "0". The more the number of "0"s in the data of the byte, the shorter the first process time; conversely, the fewer the number of "0"s in the data of the byte, the longer the first process time.

[0072] A further improvement is that step five includes the following sub-steps:

[0073] Step 51: Load the random address of the erased interference area in the repair range.

[0074] Step 52: Starting from the random address, repair each storage unit in the erased interference area in the repair range.

[0075] The erasing device further includes: a random address generation module. In step 51, the random address is formed by the random address generation module.

[0076] A further improvement is that the erasing device further includes: a detection module, a repair module, and a voltage control module;

[0077] During the repair operation:

[0078] The detection module is used to verify "1" or "0" for each storage unit in the erased interference area in the repair range;

[0079] When the verification result of the detection module determines that "1" or "0" repair is required, the repair module issues an instruction to configure the repair parameters and process parameters of the repair operation;

[0080] After receiving the instruction from the detection module or the repair module, the voltage control module generates and controls the voltage and configures the voltage to the corresponding storage unit.

[0081] In view of the defect that when the data stored in the blocks of the storage array of the non-volatile memory in the existing method is different, the erasure time, that is, the time required for the entire erasure process, namely the fourth process time, will change greatly, the present invention records the pre-programming time, that is, the first process time, which has a great influence on the erasure time, and dynamically adjusts the repair interval according to the recorded first process time, and thus realizes the dynamic adjustment of the second repair time. In this way, when the first process time is long, the second repair time can be reduced by narrowing the repair interval, and vice versa. In this way, the third time formed by the sum of the first process time and the second repair time can be dynamically adjusted. When the data stored in the blocks of the storage array changes, the change of the third time can finally be reduced by the change of the second repair time, so that the change range of the fourth process time can be reduced. Therefore, the present invention can improve the influence of the data stored in the blocks of the storage array on the erasure time, thereby reducing the change range of the erasure time and improving the reliability of the storage unit. BRIEF DESCRIPTION OF THE DRAWINGS

[0082] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:

[0083] Figure 1 is a schematic structural diagram of a storage block of an existing non-volatile memory;

[0084] Figure 2 is a flowchart of an erasure method of an existing non-volatile memory;

[0085] Figure 3 is a flowchart of an erasure method of a non-volatile memory according to an embodiment of the present invention;

[0086] Figure 4 is a flowchart of an erasure method of a non-volatile memory according to a preferred embodiment of the present invention;

[0087] Figure 5A is a graph showing the change of the erasure time of the same erasure block with the stored data in the erasure method of an existing non-volatile memory;

[0088] Figure 5B is a graph showing the change of the erasure time of the same erasure block with the stored data in the erasure method of a non-volatile memory according to a preferred embodiment of the present invention;

[0089] Figure 6 is a schematic structural diagram of an erasure device of a non-volatile memory according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0090] As Figure 3 shown, it is a flowchart of an erasure method of a non-volatile memory according to an embodiment of the present invention; As Figure 4As shown, it is a flowchart of the erasing method of the non-volatile memory in a preferred embodiment of the present invention; in the erasing method of the non-volatile memory in an embodiment of the present invention, the storage array of the non-volatile memory includes a plurality of blocks, and each of the blocks includes a plurality of erasing blocks. For the block structure of the storage array of the non-volatile memory, please also refer to Figure 1 as shown, Figure 1 in which block 100 includes a plurality of erasing blocks 101, Figure 1 which shows n erasing blocks 101, and are numbered respectively with 0, 1 to n - 1; each erasing block 101 is formed on the same P-type semiconductor substrate 102. Each erasing block 101 is provided with a word line driving circuit 103, and the word line driving circuit 103 provides a driving signal for each word line 104 in the erasing block 101. The erasing blocks 101 of the entire block 100 include aligned multiple columns of storage units, and the storage units in the same column share the same bit line 105, Figure 1 in which the bit lines are represented by BL, and there are j bit lines in total, which are numbered respectively with 0, 1 to j - 1.

[0091] Each of the storage units of the non-volatile memory is formed in a corresponding P-well.

[0092] In some embodiments, all of the blocks 100 of the non-volatile memory are formed in the same respective P-well.

[0093] In some embodiments, the non-volatile memory is divided into multiple parts, and the multiple blocks 100 in each part share the same respective P-well.

[0094] In some embodiments, each of the blocks 100 is independently formed in a respective P-well.

[0095] In some embodiments, each of the blocks 100 includes a plurality of the P-wells, and each of the storage units is independently formed in the corresponding P-well or multiple storage units share the same corresponding P-well.

[0096] In the erasing method of the non-volatile memory in an embodiment of the present invention, the erasing process of a selected erasing block in a selected block includes the following steps:

[0097] Step 1: Perform pre-verification and pre-programming on the selected erasing block.

[0098] In some preferred embodiments, as Figure 4 shown, Step 1 corresponds to Step S203, erasing block pre-verification and programming. Pre-programming is similar to programming, and also writes charges into the floating gate to ensure that the threshold voltage of the erasing block storage unit is in a higher state before erasing.

[0099] Before Step S203, it also includes:

[0100] Step S201: Start to receive an erasure instruction.

[0101] Step S202: Perform erasure initialization, i.e., internal chip initialization, and set all erasure block addresses to zero.

[0102] Step Two: Record the first process time for completing Step One, where the first process time is determined by the original data stored in the selected erasure block.

[0103] In a preferred embodiment of the present invention, Step Two includes the following sub-steps:

[0104] Step 21: Start a first time counter before Step One.

[0105] Step 22: After Step One is completed, record the value of the first time counter as the first process time.

[0106] Figure 4 In [the relevant content], Step Two corresponds to Step S301, Step 21 corresponds to Step S301a: Start a pre-programming time counter, and the first time counter is the pre-programming time counter.

[0107] Step 22 corresponds to Step S301b: Record the pre-programming process time. Step S301a is before Step 203, and Step S301b is after Step S203. Therefore, the value of the first time counter is the first process time.

[0108] In some embodiments, the original data is composed of the data stored in each storage unit. The data of the storage unit includes "1" and "0". The more the number of "0"s in the data of the storage unit, the shorter the first process time. Conversely, the fewer the number of "0"s in the data of the storage unit, the longer the first process time. Further, the selected erasure block includes N bytes, where N is greater than or equal to 1.

[0109] When the data of the storage units in each byte is all "0", the data of the byte is "0". The more the number of "0"s in the data of the byte, the shorter the first process time. Conversely, the fewer the number of "0"s in the data of the byte, the longer the first process time.

[0110] Step Three: Complete the erasure process steps, where the erasure process steps include more than one erasure cycle step, and each erasure cycle step implements an erasure operation on the selected erasure block.

[0111] In some preferred embodiments, as Figure 4 shown, the erasure process steps include:

[0112] Step S204: Perform an erase block erase. After the pre-programming is completed, the erase operation will start, that is, perform an erase operation on the selected erase block.

[0113] Step S205: Perform an erase block erase verification, that is, after each erase is completed, perform an erase verification on the erase block.

[0114] The erase block erase verification is mainly used to compare the high boundary point of the threshold voltage distribution of the selected erase block with EV. EV represents the boundary point of the erase verification. If the high boundary point is greater than EV, the verification fails; if the high boundary point is less than or equal to EV, the verification passes.

[0115] Step S206: Judge the result of the erase verification, that is, judge whether "the erase is passed?".

[0116] If the judgment result of step S206 is no, that is, the high boundary point of the threshold voltage distribution of the selected erase block is greater than EV, then perform:

[0117] Step S207: Judge whether the maximum number of erases is reached, that is, Figure 4 "Has the maximum number of erases been reached?" shown in. If the judgment result is no, that is, the maximum number has not been reached, then go to step S204. The erase operation in step S204 will further erase the charges in the floating gate, so that the high boundary point of the threshold voltage distribution of the selected erase block will be further reduced.

[0118] If the judgment result of step S206 is yes, that is, the high boundary point of the threshold voltage distribution of the selected erase block is less than or equal to EV, or the judgment result of step S207 is yes, then perform the subsequent step S208.

[0119] The process in the dashed box 301 corresponds to the entire erase process steps. The erase process steps include more than one erase cycle step. The erase cycle step consists of steps S204 to S207. Among them, steps S204 and S205 are the main bodies of the erase cycle step, and steps S206 and S207 are used to control the cycle. If the erase verification is successful within the limited number of times, no further erasure will be performed; if the limited number of times is exceeded and the erase verification fails, no further erase action will be performed either.

[0120] In the embodiment of the present invention, after step three is completed and before the subsequent step six, it further includes:

[0121] Step seven: Perform an over-erase operation on the selected erase block.

[0122] In the embodiment of the present invention, step seven is further placed before the subsequent step four.

[0123] All over-erasure operations include over-erasure verification and over-erasure programming. Over-erasure verification detects whether over-erasure exists; over-erasure programming programs the floating gate to a certain extent, so that a certain amount of charge is injected into the floating gate, causing a certain change in the threshold voltage of the memory cell, so as to realize the adjustment of the lower boundary point. The over-erasure operation makes the lower boundary point of the threshold voltage distribution of the selected erasure block greater than or equal to B1, where B1 is the boundary point that needs to be repaired for the final over-erasure.

[0124] In Figure 4 In the preferred embodiment shown, step two corresponds to step S208. In step S208, an over-erasure operation is performed after the erasure of the erasure block ends. That is, after the process in the dashed box 301 is completed, it indicates that the erasure process of the erasure block ends, and then the over-erasure operation is performed. The over-erasure operation is used to repair the over-erasure generated during the erasure process.

[0125] Step four: Dynamically set a repair interval in the selected block according to the first process time. The longer the first process time, the smaller the repair interval; the shorter the first process time, the larger the repair interval.

[0126] In Figure 4 In the preferred embodiment shown, step four corresponds to step S302. In step S302, a repair interval is set according to the pre-programming time.

[0127] Step five: Perform a repair operation to repair each memory cell in the erased interference area in the repair interval. The time to complete the repair operation is the second repair time. The smaller the repair interval, the longer the second repair time; the larger the repair interval, the shorter the second repair time. The sum of the first process time and the second repair time is the third time.

[0128] In the preferred embodiment of the present invention, step five includes the following sub-steps:

[0129] Step 51: Load the random addresses in the erased interference area of the repair interval.

[0130] Step 52: Repair each memory cell in the erased interference area of the repair interval with the random address as the starting address.

[0131] In some embodiments, the repair operation only repairs the "1" memory cells and omits the repair of the "0" memory cells.

[0132] In some embodiments, the repair operation only repairs the "0" memory cells and omits the repair of the "1" memory cells.

[0133] In some embodiments, the repair operation only repairs the "1" memory cells and repairs the "0" memory cells at the same time.

[0134] In Figure 4 In the preferred embodiment shown, step 51 corresponds to step S209, loading the random address of the disturbed area in the same block.

[0135] Step 52 corresponds to the repair operation of the erased and disturbed area within the same block in S210; that is, after the erasure of the erasure block is completed or the over-erasure operation is completed, other operations are performed, such as anti-interference repair operations, etc.

[0136] Step Six: The erasure process ends, and the time taken to complete the entire erasure process is the fourth process time.

[0137] When the original data stored in the selected erasure block is different, the fourth process time is different, and the variation range of the fourth process time is determined by the third time; when the original data stored in the selected erasure block is different, the repair interval dynamically set in step four reduces the variation range of the third time and thus reduces the variation range of the fourth process time.

[0138] In Figure 4 In the preferred embodiment shown, step Six corresponds to step S211, the erasure of the erasure block ends, that is, the entire erasure process ends.

[0139] In the embodiment of the present invention, step four and step five are performed after step seven is completed.

[0140] In some embodiments, it can also be: step four and step five are set to be performed at a selected time point after step three is completed and before step six is completed.

[0141] In some embodiments, it can also be: step four and step five are set to be performed at a selected time point in each erasure cycle step of step three.

[0142] In view of the defect that when the data stored in the blocks of the storage array of the non-volatile memory in the existing method is different, the erasure time, that is, the time required for the entire erasure process, namely the fourth process time, will vary greatly, the embodiments of the present invention record the pre-programming time, that is, the first process time, which has a great influence on the erasure time, and dynamically adjust the repair interval according to the recorded first process time, and thus dynamically adjust the second repair time. In this way, when the first process time is long, the second repair time can be reduced by narrowing the repair interval, and vice versa, so that the third time formed by the sum of the first process time and the second repair time can be dynamically adjusted. When the data stored in the blocks of the storage array changes, finally, by changing the second repair time, the change of the third time can be reduced, so that the change range of the fourth process time can be reduced. Therefore, the embodiments of the present invention can improve the influence of the data stored in the blocks of the storage array on the erasure time, thereby reducing the change range of the erasure time and improving the reliability of the storage unit.

[0143] As Figure 5A shown, it is a graph of the erasure time of the same erasure block varying with the stored data in the erasure method of the existing non-volatile memory; when erasing the same erasure block, when the original data is in different states of "0" or "1", the erasure time, that is, the fourth process time, will change, and this change in erasure time is as follows:

[0144] An erasure block has N bytes. When there is only one byte with "0" data in the erasure block, the entire erasure time is T2; when all bytes are "0" data, the erasure time is T1. Since the number of bytes containing "0" in the erasure block is different, the pre-programming time is different, so the final erasure time varies greatly. As Figure 5A shown, as the original data in the N bytes of the erasure block changes, the change range of the final erasure time is from T1 to T2.

[0145] As Figure 5B shown, it is a graph of the erasure time of the same erasure block varying with the stored data in the erasure method of the non-volatile memory in the preferred embodiment of the present invention; similarly, when erasing the same erasure block, when the original data is in different states of "0" or "1", the erasure time will change, and this change in erasure time is as follows:

[0146] An erasure block has N bytes. When there is only one byte with "0" data, the entire erasure time is T4, and when all bytes are "0" data, the erasure time is T3.

[0147] In a preferred embodiment of the present invention, due to the adoption of a pre-programming time monitoring mechanism, the pre-programming time is different because the number of original data "0"s before erasure is different. According to the length of the pre-programming time before erasure, the size of the area to be repaired in the same block is dynamically adjusted to adjust the final programming time. Therefore, the shortest erasure time T3 and the longest erasure time T4 after improvement. Finally, T2≥T4>T3≥T1, and the erasure time boundary after improvement is included in the erasure time boundary before improvement, which improves the erasure time and increases the reliability of the storage unit.

[0148] As Figure 6 shown, it is a schematic structural diagram of an erasure device of a non-volatile memory according to an embodiment of the present invention; the erasure device of the non-volatile memory according to the embodiment of the present invention includes: a process control module 401 and a storage array 406.

[0149] The storage array 406 includes a plurality of blocks, and each of the blocks includes a plurality of erasure blocks.

[0150] The process control module 401 controls the erasure process.

[0151] The erasure process for a selected erasure block in a selected block includes the following steps:

[0152] Step 1: Perform pre-verification and pre-programming on the selected erasure block.

[0153] Step 2: Record the first process time for completing Step 1, and the first process time is determined by the original data stored in the selected erasure block.

[0154] In the device according to the embodiment of the present invention, Step 2 includes the following sub-steps:

[0155] Step 21: Start a first time counter before Step 1;

[0156] Step 22: After Step 1 is completed, record the value of the first time counter as the first process time.

[0157] The original data is composed of the data stored in each storage unit, and the data of the storage unit includes "1" and "0". The more the number of "0"s in the data of the storage unit, the shorter the first process time. Conversely, the fewer the number of "0"s in the data of the storage unit, the longer the first process time. Further, the selected erasure block includes N bytes, and N is greater than or equal to 1;

[0158] When the data of each storage unit in each byte is "0", the data of the byte is "0". The more the number of "0"s in the data of the byte, the shorter the first process time. Conversely, the fewer the number of "0"s in the data of the byte, the longer the first process time.

[0159] Step 3: Complete the erasure process steps, where the erasure process steps include more than one erasure cycle step, and in each erasure cycle step, one erasure operation on the selected erasure block is implemented.

[0160] Step 4: Dynamically set a repair range in the selected block according to the first process time. The longer the first process time, the smaller the repair range; the shorter the first process time, the larger the repair range.

[0161] Step 5: Perform a repair operation to repair each storage unit in the erased interference area within the repair range. The time taken to complete the repair operation is the second repair time. The smaller the repair range, the longer the second repair time; the larger the repair range, the shorter the second repair time. The sum of the first process time and the second repair time is the third time.

[0162] Step 5 includes the following sub-steps:

[0163] Step 51: Load the random addresses of the erased interference area within the repair range.

[0164] Step 52: Starting from the random address, repair each storage unit in the erased interference area within the repair range.

[0165] Step 6: The erasure process ends, and the time taken to complete the entire erasure process is the fourth process time.

[0166] When the original data stored in the selected erasure block is different, the fourth process time is different, and the variation range of the fourth process time is determined by the third time. When the original data stored in the selected erasure block is different, the repair range dynamically set in Step 4 reduces the variation range of the third time and thus reduces the variation range of the fourth process time.

[0167] The erasure device of the non-volatile memory according to the embodiment of the present invention further includes: a detection module 402, a repair module 403, and a voltage control module 405;

[0168] During the repair operation:

[0169] The detection module 402 is used to verify whether the storage units in the repair range are "1" or "0".

[0170] When the verification result of the detection module 402 determines that a "1" or "0" repair is required, the repair module 403 issues an instruction to configure the repair parameters and process parameters of the repair operation.

[0171] After receiving instructions from the detection module 402 or the repair module 403, the voltage control module 405 generates and controls voltage and configures the voltage to the corresponding storage unit.

[0172] The erasing device further includes: a random address generation module 404. In step 51, the random address generation module 404 generates a random address.

[0173] The detection module 402, the repair module 403, and the voltage control module 405 also implement the over-erasure operation simultaneously. The process control module 401 controls the progress of the entire erasing process, including the erasing process steps, the over-erasure operation, and the repair operation.

[0174] The present invention has been described in detail through specific embodiments, but these do not constitute a limitation to the present invention. Without departing from the principle of the present invention, those skilled in the art can also make many deformations and improvements, which should also be regarded as the protection scope of the present invention.

Claims

1. A method for erasing a non-volatile memory, characterized in that, The storage array of the non-volatile memory includes multiple blocks, and each of the blocks includes multiple erase blocks. The erasure process for a selected erase block in a selected block includes the following steps: Step 1: Perform pre-verification and pre-programming on the selected erase block; Step 2: Record the first process time for completing Step 1, and the first process time is determined by the original data stored in the selected erase block; Step 3: Complete the erasure process steps, and the erasure process steps include more than one erasure cycle step. In each of the erasure cycle steps, one erasure operation on the selected erase block is implemented; Step 4: Dynamically set a repair interval in the selected block according to the first process time. The longer the first process time, the smaller the repair interval, and the shorter the first process time, the larger the repair interval; Step 5: Perform a repair operation to repair each storage unit in the erased interference area within the repair interval. The time for completing the repair operation is the second repair time. The smaller the repair interval, the longer the second repair time, and the larger the repair interval, the shorter the second repair time; The sum of the first process time and the second repair time is the third time; Step 6: The erasure process ends, and the time for completing the entire erasure process is the fourth process time; When the original data stored in the selected erase block is different, the fourth process time is different, and the variation range of the fourth process time is determined by the third time; when the original data stored in the selected erase block is different, the repair interval dynamically set in Step 4 reduces the variation range of the third time and thus reduces the variation range of the fourth process time.

2. The erasing method of the non-volatile memory according to claim 1, characterized in that, Step 2 includes the following sub-steps: Step 21: Start a first time counter before Step 1; Step 22: After Step 1 is completed, record the value of the first time counter as the first process time.

3. The erasing method of the non-volatile memory according to claim 1, characterized in that: The original data is composed of the data stored in each storage unit. The data of the storage unit includes "1" and "0". The more the number of "0"s in the data of the storage unit, the shorter the first process time, and vice versa, the fewer the number of "0"s in the data of the storage unit, the longer the first process time.

4. The erasing method of the non-volatile memory according to claim 3, characterized in that: The selected erase block includes N bytes, and N is greater than or equal to 1; When the data of each storage unit in the byte is "0", the data of the byte is "0". The more the number of "0"s in the data of the byte, the shorter the first process time, and vice versa, the fewer the number of "0"s in the data of the byte, the longer the first process time.

5. The erasing method of the non-volatile memory according to claim 1, characterized in that, Step 5 includes the following sub-steps: Step 51: Load a random address in the erased interference area within the repair interval; Step 52: Repair each storage unit in the erased interference area within the repair interval starting from the random address.

6. The erasing method of the non-volatile memory according to claim 1, wherein: After Step 3 is completed and before Step 6, it also includes: Step 7: Perform an over-erasure operation on the selected erase block.

7. The erasing method of the non-volatile memory according to claim 6, characterized in that: Step 4 and Step 5 are set to be carried out at a selected time point after Step 3 is completed and before Step 6 is completed; or, Step 4 and Step 5 are set to be carried out at a selected time point in each of the erasure cycle steps of Step 3.

8. The erasing method of the non-volatile memory according to claim 1, characterized in that: In Step 5, the repair operation repairs the "1" storage cells and omits the repair of the "0" storage cells; Or, the repair operation repairs the "0" storage cells and omits the repair of the "1" storage cells; Or, the repair operation repairs the "1" storage cells and simultaneously repairs the "0" storage cells.

9. The erasing method of the non-volatile memory according to claim 1, characterized in that: Each of the storage cells of the non-volatile memory is formed in a corresponding P-well; All of the blocks of the non-volatile memory are formed in the same respective P-well; Or, the non-volatile memory is divided into multiple parts, and multiple blocks in each part share the same P-well; Or, each block is independently formed in a P-well; Or, each block includes multiple P-wells, and each storage cell is independently formed in a corresponding P-well or multiple storage cells share the same corresponding P-well.

10. An erasing device for a non-volatile memory, characterized in that, Including: A process control module, a storage array; The storage array includes multiple blocks, and each block includes multiple erase blocks; The process control module controls the erasure process; The erasure process for a selected erase block in a selected block includes the following steps: Step 1, perform pre-verification and pre-programming on the selected erase block; Step 2, record the first process time for completing Step 1, and the first process time is determined by the original data stored in the selected erase block; Step 3, complete the erasure process step, and the erasure process step includes more than one erasure cycle step, and each erasure cycle step implements an erasure operation on the selected erase block; Step 4, dynamically set a repair interval in the selected block according to the first process time, the longer the first process time, the smaller the repair interval, and the shorter the first process time, the larger the repair interval; Step 5, perform a repair operation to repair each storage cell in the erased interference area within the repair interval, and the time for completing the repair operation is the second repair time, the smaller the repair interval, the longer the second repair time, and the larger the repair interval, the shorter the second repair time; The sum of the first process time and the second repair time is the third time; Step 6, the erasure process ends, and the time for completing the entire erasure process is the fourth process time; When the original data stored in the selected erase block is different, the fourth process time is different, and the change range of the fourth process time is determined by the third time; when the original data stored in the selected erase block is different, the repair interval dynamically set in Step 4 reduces the change range of the third time and thus reduces the change range of the fourth process time.

11. The erasing device of the non-volatile memory according to claim 10, wherein, Step 2 includes the following sub-steps: Step 21, start a first time counter before Step 1; Step 22: After step one is completed, record the value of the first time counter as the first process time.

12. The erasing device of the non-volatile memory according to claim 10, characterized in that: The original data consists of the data stored in each storage unit. The data in the storage unit includes "1" and "0". The more the number of "0"s in the data of the storage unit, the shorter the first process time. Conversely, the fewer the number of "0"s in the data of the storage unit, the longer the first process time.

13. The erasing device of the non-volatile memory according to claim 12, characterized in that: The selected erasure block includes N bytes, where N is greater than or equal to 1; When the data of the storage units in each byte is all "0", the data of the byte is "0". The more the number of "0"s in the data of the byte, the shorter the first process time. Conversely, the fewer the number of "0"s in the data of the byte, the longer the first process time.

14. The erasing device of the non-volatile memory according to claim 10, wherein Step five includes the following sub-steps: Step 51: Load the random address of the erased interference area in the repair interval; Step 52: Repair each storage unit in the erased interference area in the repair interval with the random address as the starting address; The erasure device further includes: a random address generation module. In step 51, the random address is formed by the random address generation module.

15. The erasing device of the non-volatile memory according to claim 10, characterized in that, The erasure device further includes: a detection module, a repair module, and a voltage control module; During the repair operation: The detection module is used to verify whether each storage unit in the erased interference area in the repair interval is "1" or "0"; When the verification result of the detection module determines that "1" or "0" repair is required, the repair module issues instructions to configure the repair parameters and process parameters of the repair operation; After receiving the instructions from the detection module or the repair module, the voltage control module generates and controls the voltage and configures the voltage to the corresponding storage unit.

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