Storage block and memory

Abstract

The present invention relates to a storage block and a memory. The storage block includes a plurality of storage arrays arranged along a first direction, which are used to store data and parity codes. Each storage array is divided into at least two array units; a plurality of read / write control circuits, which are respectively in one-to-one correspondence with the storage arrays, and are used to write or read data and parity codes to / from the corresponding storage arrays; the read / write control circuits are electrically connected to each array unit through different data signal lines, and are configured to be able to access only one array unit in the corresponding storage array each time; a plurality of error detection and correction units, which are electrically connected to the plurality of read / write control circuits, and are used to perform error detection and / or correction on the data according to the parity codes; wherein, during a read operation, the data and parity codes read out by each read / write control circuit are divided into at least two parts, and the read / write control circuits are configured to transmit each part to different error detection and correction units. The storage block according to the embodiment of the present invention has the advantages of low power consumption and accurate parity check.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a memory block and a memory. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a commonly used semiconductor memory device in a computer and consists of many repeated memory cells. Each memory cell generally includes a capacitor and a transistor. The gate of the transistor is connected to a word line, the drain is connected to a bit line, and the source is connected to the capacitor. The voltage signal on the word line can control the opening or closing of the transistor, and then the data information stored in the capacitor can be read through the bit line, or the data information can be written into the capacitor through the bit line for storage.

[0003] DRAM can be divided into Double Data Rate (DDR) dynamic random access memory, GDDR (Graphics Double Data Rate) dynamic random access memory, and Low Power Double Data Rate (LPDDR) dynamic random access memory. As DRAM is applied in more and more fields, such as being more and more applied in the mobile field, users' requirements for the power consumption index of DRAM are getting higher and higher.

[0004] For DRAM, data often goes wrong during the data storage process. Therefore, ECC (Error Checking and Correcting) technology is required to ensure the correctness of data storage. Usually, parity bits are added based on a certain length of valid data bits to detect and correct the wrong data.

[0005] However, the current ECC technology still has deficiencies. Summary of the Invention

[0006] Embodiments of the present invention provide a memory block and a memory to solve the problem of high power consumption of the memory.

[0007] To solve the above problems, an embodiment of the present invention provides a memory block, including: a plurality of memory arrays arranged along a first direction for storing data and parity bits, and each of the memory arrays is divided into at least two array units;

[0008] A plurality of read / write control circuits, each corresponding to one of the memory arrays respectively, for writing or reading the data and the parity code to / from the corresponding memory array; the read / write control circuit is electrically connected to each of the array units through different data signal lines, and the read / write control circuit is configured to access only one array unit in the corresponding memory array each time;

[0009] A plurality of error detection and correction units, electrically connected to the plurality of read / write control circuits, for detecting errors and / or correcting errors in the data according to the parity code;

[0010] Wherein, during a read operation, the data and the parity code read out by each read / write control circuit are divided into at least two parts, and the read / write control circuit is configured to transmit each part to a different error detection and correction unit.

[0011] In addition, it further includes: a plurality of switching switch modules, each corresponding to one of the memory arrays respectively, for switching one of the array units to be electrically connected to the read / write control circuit through the data signal line.

[0012] In addition, the switching switch module includes: a control unit and a switch unit; the control unit generates a control signal based on the received row decoding signal; the switch unit is configured to connect the read / write control circuit to one of the array units through the data signal line based on the control signal.

[0013] In addition, the switch unit includes a plurality of switches, and each data signal line is connected to the read / write control circuit through one of the switches.

[0014] In addition, the plurality of error detection and correction units at least includes: a first error detection and correction unit, connected to each of the array units through the read / write control circuit, for detecting and correcting errors in a part of the output data of the array unit; a second error detection and correction unit, connected to each of the array units through the read / write control circuit, for detecting and correcting errors in the remaining output data part of the array unit.

[0015] In addition, the data signal lines corresponding to each array unit include an even number of block data buses, number the block data buses in natural numbers starting from zero in sequence, the block data buses with odd numbers O are connected to the first error detection and correction unit, and the block data buses with even numbers E are connected to the second error detection and correction unit.

[0016] In addition, each of the array units includes a local conversion circuit and an even number of local data buses. The local data buses are divided into local data bus O and local data bus E. The local data bus O is connected to the block data bus O through the local conversion circuit, and the local data bus E is connected to the block data bus E through the local conversion circuit.

[0017] In addition, each of the local data buses is connected to an even number of sense amplifiers through a strobe switch, and the sense amplifiers are arranged in one-to-one correspondence with the bit lines in the memory array.

[0018] In addition, the output data on two adjacent bit lines enter the local data bus O and the local data bus E respectively through the sense amplifiers and the strobe switches.

[0019] In addition, the number of the block data buses is 2 * 4 * (16 * N), and the number of the local data buses is 2 * 4 * M * (16 * N); the number of the block data bus O is 4 * (16 * N), and the number of the block data bus E is 4 * (16 * N); the number of the local data bus O is 4 * M * (16 * N), and the number of the local data bus E is 4 * M * (16 * N); one block data bus O corresponds to M local data buses O, and one block data bus E corresponds to M local data buses E; the local data buses are divided into M * (16 * N) groups of local data buses O and M * (16 * N) groups of local data buses E in groups of 4 adjacent ones.

[0020] In addition, the several memory arrays include a memory array U, a memory array V, and a memory array W arranged in sequence along the first direction; each memory array is divided into two array units along the second direction; two array units on the same side in the second direction in the memory array U and the memory array V share the same word line address;

[0021] Two read / write control circuits corresponding to the two array units on the same side in the memory array U and the memory array V are associated and configured to simultaneously access the memory cells with the same word line address in the two array units on the same side in the memory array U and the memory array V.

[0022] In addition, two array units on the first side in the memory array U and the memory array V share the same word line address; two read / write control circuits corresponding to the memory array U and the memory array V are associated and configured to respectively and simultaneously access the memory cells with the same word line address in the two array units on the first side in the memory array U and the memory array V; or,

[0023] The two array units on the second side in the storage array U and the storage array V share the same word line address, and the first side and the second side are different sides in the second direction; the two read / write control circuits corresponding to the storage array U and the storage array V are associated and configured to simultaneously access the storage units with the same word line address in the two array units on the second side in the storage array U and the storage array V respectively.

[0024] In addition, when the two array units on the first side in the storage array U and the storage array V share the same word line address, the two array units on the second side in the storage array V and the storage array W share the same word line address. The two read / write control circuits corresponding to the storage array V and the storage array W are associated and configured to simultaneously access the two array units on the second side in the storage array V and the storage array W respectively. The two read / write control circuits corresponding to the storage array U and the storage array W are associated and configured to simultaneously access the array unit on the second side in the storage array U and the array unit on the first side in the storage array W respectively.

[0025] In addition, when the two array units on the first side in the storage array U and the storage array V share the same word line address, the two array units on the first side in the storage array V and the storage array W share the same word line address. The two read / write control circuits corresponding to the storage array V and the storage array W are associated and configured to simultaneously access the two array units on the first side in the storage array V and the storage array W respectively. The two read / write control circuits corresponding to the storage array U and the storage array W are associated and configured to simultaneously access the array unit on the first side in the storage array U and the array unit on the second side in the storage array W respectively.

[0026] In addition, it further includes: a row decoding circuit for generating a row decoding signal to locate and select the word line in the array unit.

[0027] Correspondingly, an embodiment of the present invention further provides a memory including the storage block in the above embodiment.

[0028] Compared with the prior art, the technical solution provided by the present invention has the following advantages:

[0029] An embodiment of the present invention provides a storage block with excellent structural performance, including a storage array divided into at least two array units; several read / write control circuits corresponding to the storage array one by one, used to write or read data and parity codes to / from the corresponding storage array, and each read / write control circuit is electrically connected to each array unit through different data signal lines; several error detection and correction units used to detect and / or correct errors in the data according to the parity codes. During a single read operation, each read / write control circuit only needs to access one array unit in the corresponding storage array, and the read / write control circuit and each array unit in the storage array are connected through different data signal lines. Since each data signal line is only electrically connected to one array unit, that is, there is an electrical contact point, during a single read / write operation, the number of electrical contact points is reduced, and the parasitic resistance and parasitic capacitance of this storage block are also reduced, which is beneficial to reducing the power consumption of the storage block. At the same time, since the output data of the array unit is divided into at least two parts during each read operation, and the read / write control circuit transmits each part to different error detection and correction units, when more than one error appears in the output data of the array unit at the same time, different errors can be corrected by different error detection and correction units, so that the storage block can correct more than one error, improving the error detection and correction ability of the storage block.

[0030] In addition, the storage block further includes a switching switch module, and the switching switch module is used to connect the read / write control circuit to an array unit through a data signal line. In this way, when a data signal line corresponding to an array unit in the storage array transmits a data signal, the data signal lines of other array units in the storage array are completely disconnected from the circuit, thus avoiding the heat loss problem caused by other data signal lines and further reducing the power consumption of the storage block.

[0031] In addition, the output data on two adjacent bit lines enter the local data bus O and the local data bus E through a sense amplifier and a strobe switch respectively, so that the data corresponding to the physically adjacent local data buses enter the first error detection and correction unit and the second error detection and correction unit respectively. Therefore, when the data corresponding to the bit lines at adjacent positions are in error at the same time, this error can also be corrected, further improving the error detection and correction ability of the memory.

[0032] In addition, several storage arrays include a storage array U, a storage array V, and a storage array W, and each storage array is divided into two array units; by setting two array units on the same side in the storage array U and the storage array V to share the same word line address, and the two read / write control circuits corresponding to the storage array U and the storage array V are associated and configured to simultaneously access the two array units on the same side in the storage array U and the storage array V, two storage arrays can be simultaneously accessed through sharing the same word line address, reducing the word line overhead and lowering the energy consumption. Description of the Drawings

[0033] One or more embodiments are illustrated by way of example in the accompanying drawings, which do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are represented as similar elements, and unless otherwise stated, the drawings in the figures do not constitute a scale limitation.

[0034] Figure 1 It is a schematic structural diagram of a DARM;

[0035] Figure 2 It is a schematic top view of the layout of a memory;

[0036] Figure 3 It is a schematic structural diagram of a memory;

[0037] Figure 4 It is a schematic structural diagram of a storage block provided by an embodiment of the present invention;

[0038] Figure 5 It is a schematic structural diagram of a storage block provided by another embodiment of the present invention;

[0039] Figure 6 It is a schematic structural diagram of a storage block provided by yet another embodiment of the present invention;

[0040] Figure 7 It is Figure 6 a schematic diagram of the signal line connection of the local area of the memory in;

[0041] Figure 8 It is a schematic structural diagram of a storage block provided by yet another embodiment of the present invention. Detailed implementation manners

[0042] As can be seen from the background art, the power consumption of current DRAM needs to be further reduced.

[0043] Now, it is analyzed in combination with a schematic structural diagram of a DRAM. Figure 1 It is a schematic structural diagram of a DARM. Referring to Figure 1 , a DRAM is composed of multiple storage blocks (banks, also known as memory banks), each storage block includes several memory arrays, and each memory array includes a memory array (array) and a sense amplifier array. For DRAM, whether it is the DDR (2 / 3 / 4, etc.) series or the LPDDR (2 / 3 / 4 / 5) series, the storage blocks are divided into a high-bit group and a low-bit group according to the output pins (DQ). That is to say, each bank can also be correspondingly divided into 2 half banks, one of which is used as the first module M1, and the first module M1 provides low-bit output pins, and the other half bank is used as the second module M2, and the second module M2 provides high-bit output pins.

[0044] The data signal line YIO is used to transfer data between the selected memory array and the read / write control circuit. Whether it is the lower half bank or the upper half bank, in order to successfully complete the read and write operations, the data signal line YIO has electrical contact points with each memory array in the half bank, generating parasitic capacitance. The data signal line YIO is very long, resulting in a relatively large parasitic resistance, which will cause a large amount of power consumption for each read and write operation, leading to high power consumption of the DRAM.

[0045] Further analysis reveals that parasitic resistance and parasitic capacitance are also one of the main reasons for the high power consumption of DARM. For the data signal line YIO, during each read operation or write operation, there are parasitic capacitance and parasitic resistance at the electrical contact points between each group of data signal lines YIO and each memory array. Due to the large number of electrical contact points, the corresponding parasitic resistance and parasitic resistance are large, resulting in high power consumption of the DRAM.

[0046] At the same time, as can be seen from the background technology, the existing ECC technology still has deficiencies.

[0047] Analysis shows that if there is one bit error in the data, the ECC check technology can not only detect it but also correct it. The ECC check can also detect 2 - 4 bit errors. However, it is difficult for the ECC check to correct errors of 2 bits and above. That is to say, although the ECC check technology can detect and correct single-bit errors simultaneously, if two or more bits of data are detected to have errors at the same time, the current ECC check technology is powerless. In addition, further analysis reveals that the probability of two adjacent data having errors at the same time is relatively high currently. Further analysis shows that the main reasons for this problem are as follows:

[0048] Figure 2 It is a schematic top view structure diagram of a memory. The memory includes: multiple active regions 10 arranged in an array; word lines 12, bit lines 11, and capacitors 13 electrically connected to the active regions. There are defects of adjacent cell to cell bridge in the memory, or called adjacent two-bit errors. For example, there is a bridge between capacitors 91 and 92 corresponding to adjacent active regions 10, as shown by the dotted line box in Figure 1 Capacitor 91 is connected to bit line BL3 through a transistor, and capacitor 92 is connected to bit line BL2 through a transistor. As the process size of the memory becomes smaller and smaller, the probability of this kind of defect occurring is also getting larger and larger.

[0049] Figure 3 It is a schematic structure diagram of a memory. The memory includes: a memory array composed of memory cells 14, each memory cell 14 is connected to a bit line BL and a word line WL; a column selection signal unit, atFigure 2 labeled as CSL <n-1>, CSL <n>and CSL<n+1>. Each column selection signal unit includes multiple column selection signal lines. Each column selection signal line is connected to the corresponding bit line BL in the memory array and the local data bus through a switch. The control signal of the switch comes from the column decoding circuit (not shown in Figure 3 ), and is used to determine whether the data on the bit line BL is transmitted to the local data bus. For example, the column selection signal unit CSL <n>It includes 8 column selection signal lines. The 8 column selection signal lines are connected to the local data bus through the bit lines BL in the memory array controlled by switches; the local data bus, which is labeled as LIO in Figure 3 . Among them, LIO:O<3:0> indicates the local data buses with odd numbers, and LIO:E<3:0> indicates the local data buses with even numbers; the block data bus, which is labeled as YIO in Figure 3 . Among them, YIO:O<3:0> indicates the block data buses with odd numbers, and YIO:E<3:0> indicates the block data buses with even numbers. The local data bus is connected to the block data bus through a local conversion circuit (such as a local sense amplifier circuit, Figure 3 not shown in the figure). Figure 2 shows the interaction between YIO:E<3:0> and LIO:E<3:0>, and the interaction between YIO:O<3:0> and LIO:O<3:0> in an arc curve.

[0050] Combined with Figure 2 and Figure 3 , the block data buses YIO:E<3:0> and YIO:O<3:0> are connected to the same error detection and correction unit 15. If the two bit lines BL corresponding to two memory cells 14 are exactly connected to the same column decoding circuit, then two errors occur simultaneously at the same read time point. For example, Figure 2 the memory cell 91 and the memory cell 92 in Figure 2 (91 and 92 represent capacitors in Figure 3 , while 91 and 92 represent memory cells in Figure 2 and Figure 3 . Here, they are labeled the same to illustrate adjacent two-bit errors in combination with <n>Its data is transmitted to the local data lines LIO:O<3:0> and the local data lines LIO:E<3:0>, and then the data is transmitted to YIO:E<3:0> and YIO:O<3:0> through the local conversion circuit. Then, two-bit errors enter the error detection and correction unit 15 simultaneously. The currently used ECC (for example, for ECC of 128 bits (data bits) + 8 bits (check code), it can only correct one bit) cannot correct the above two-bit errors.

[0051] To solve the above problems, an embodiment of the present invention provides a storage block with excellent structural performance. Through the design of a special structure, the parasitic resistance and parasitic capacitance of the storage block are reduced, thereby reducing the power consumption of the storage block. At the same time, the storage block includes several error detection and / or correction units, so that when two data outputs of the storage array are in error at the same time, they can be corrected, thereby improving the error detection and correction ability of the memory and improving the read and write performance of the memory.

[0052] To make the objectives, technical solutions, and advantages of the present invention clearer, the embodiments of the present invention will be described in detail below with reference to the accompanying drawings. However, those of ordinary skill in the art can understand that in the embodiments of the present invention, many technical details are proposed to help readers better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the present application can still be implemented.

[0053] Figure 4 It is a schematic diagram of the structure of the storage block provided by an embodiment of the present invention.

[0054] Referring to Figure 4 , in this embodiment, the storage block includes several storage arrays 101 arranged along the first direction (X) for storing data and check codes. Each storage array 101 is divided into at least two array units 110 along the second direction (Y); several read / write control circuits 102, which are respectively corresponding to the storage arrays 101 one by one, for writing or reading data and check codes to / from the corresponding storage arrays 101; the read / write control circuits 102 are electrically connected to the respective array units 110 through different data signal lines, and the read / write control circuits 102 are configured to be able to access only one array unit 110 in the corresponding storage array 101 each time; several error detection and correction units 103, which are electrically connected to the several read / write control circuits 102, for detecting and / or correcting data according to the check codes; wherein, during a read operation, the data and check codes read by each read / write control circuit 102 are divided into at least two parts, and the read / write control circuits 102 are configured to transmit each part to different error detection and correction units 103. It can be known that the above first direction X is the direction in which the word line WL extends, and the second direction Y is the direction in which the bit line BL extends.

[0055] An embodiment of the present invention provides a storage block with superior structural performance, including a storage array divided into at least two array units; a plurality of read / write control circuits corresponding to the storage array one by one, for writing or reading data and check codes to / from the corresponding storage array, and each read / write control circuit is electrically connected to each array unit through different data signal lines; and a plurality of error detection and correction units for detecting and / or correcting data according to the check codes. During a single read operation, each read / write control circuit only needs to access one array unit in the corresponding storage array, and the read / write control circuit and each array unit in the storage array are connected through different data signal lines. Since each data signal line is only electrically connected to one array unit, that is, has an electrical contact point, during a single read / write operation, the number of electrical contact points is reduced, and the parasitic resistance and parasitic capacitance of this storage block are also reduced, which is beneficial to reducing the power consumption of the storage block. Since the output data of the array unit is divided into at least two parts during each read operation, and the read / write control circuit transmits each part to different error detection and correction units, when more than one error appears simultaneously in the output data of the array unit, different errors can be corrected by different error detection and correction units, so that the storage block can correct more than one error, improving the error detection and correction ability of the storage block.

[0056] The following will describe this embodiment in detail with reference to the drawings. It should be noted that for the convenience of illustration, Figure 4 and Figure 5 the thick solid line symbols marked in indicate electrical connection, that is, having electrical contact points, and the unmarked thick solid line symbols indicate non-electrical connection, that is, not having electrical contact points.

[0057] In this embodiment, the storage block may include 3 storage arrays 101, and each storage array 101 is divided into two array units 110 along the second direction Y; 3 read / write control circuits 102 correspond to the 3 storage arrays 101 one by one, and each read / write control circuit 102 is electrically connected to the two array units 110 through the data signal line YIO1 and the data signal line YIO2 respectively. Among them, the data signal line YIO1 is electrically connected to one array unit 110 in the storage array 101; the data signal line YIO2 is electrically connected to the other array unit 110 in the storage array 101. In some embodiments, the read / write control circuit 102 is located on one side of the storage array 101 in the second direction Y. Therefore, due to the existence of the array unit 110 on the side of the storage array 101 close to the read / write control circuit 102, the data signal line YIO2 needs to pass through the area of the array unit 110 on the side of the storage array 101 close to the read / write control circuit 102 to be electrically connected to the read / write control circuit 102. It should be noted that an array unit is not only connected to one YIO, and the data signal line YIO1 and the data signal line YIO2 are only general references to one of the data signal lines connected to different array units.

[0058] The read / write control circuit 102 is configured to access only one array cell 110 of the corresponding memory array 101 each time. For example Figure 4 in, one array cell 110 in the corresponding memory array 101 is accessed through the data signal line YIO1, and another array cell 110 in the corresponding memory array 101 is accessed through the data signal line YIO2.

[0059] Each memory array 101 includes a memory array (such as Figure 4 numbered 0, 1, 2,... as shown) and a sense amplifier array (Sense Amplifier, SA) ( Figure 4 not shown in the figure, please refer to Figure 1 ). The memory array includes a plurality of memory cells for storing data; the sense amplifier array is used to amplify the output signal of the memory array. The number of memory arrays and sense amplifier arrays included in each array cell 110 can be the same or different.

[0060] The number of several error detection and correction units 103 can be two, and they are arranged close to the read / write control circuit 102 and are electrically connected to the above three read / write control circuits 102 respectively, and are used to detect errors and / or correct the read data according to the check code read from the array cell 110 each time. Among them, during the read operation, the read data and the check code of each read / write control circuit 102 are divided into at least two parts (such as randomly allocated, or allocated according to the parity of the serial number of the memory array where the data is located), and the read / write control circuit 102 is configured to transmit one part to one error detection and correction unit 103 and the remaining part to another error detection and correction unit 103.

[0061] Compared with the scheme in which all the memory arrays in one memory array 101 are electrically connected to the data signal line and electrically connected to the read / write control circuit through the data signal line, in this embodiment, during a single read operation or write operation, only the data signal line is connected to one array cell in the memory array 101, that is, the data signal line is only electrically connected to a part of the memory arrays, so that the number of electrical contact points is reduced. In this way, not only can the parasitic circuit and parasitic capacitance in the memory block be reduced, but also the load on the data signal line is significantly reduced, so the power consumption of the memory block can be significantly reduced.

[0062] In addition, since different data signal lines are connected to different array cells, the length of the data signal line can be reduced. For example Figure 4 In the data signal line YIO1, it is only electrically connected to the array cells 110 on the side of the storage array 101 close to the read / write control circuit 102, so that the data signal line YIO1 does not need to extend to the array cells 110 on the side of the storage array 101 far from the read / write control circuit 102, thereby reducing the length of the data signal line YIO1, which is beneficial to further reducing the resistance of the data signal line YIO1 and the consumed power, and further reducing the power consumption of the storage block.

[0063] In summary, the power consumption of the storage block provided in this embodiment is small each time, and the corresponding storage block has the advantage of low power consumption.

[0064] Another embodiment of the present invention further provides a storage block, which is substantially the same as the storage block provided in the previous embodiment, except that it further includes a plurality of switching switch modules, which correspond to the storage arrays one by one and are used to switch one of the array cells in each array to be electrically connected to the read / write control circuit through the data signal line. The storage block provided in this embodiment will be described below with reference to the drawings. It should be noted that for the same or corresponding parts as those in the previous embodiment, please refer to the detailed description of the previous embodiment, and the following will not be elaborated in detail.

[0065] Figure 5 It is a schematic structural diagram of a storage block provided in another embodiment of the present invention.

[0066] Refer to Figure 5 In Figure 4 Based on the shown storage block structure, in this embodiment, a plurality of switching switch modules (not shown in the figure) correspond to the storage array 101 one by one and are used to switch one of the array cells 110 in the storage array 101 to be electrically connected to the read / write control circuit 102 through the data signal line.

[0067] Due to the setting of the switching switch module, in a single read operation or write operation, only the data signal line corresponding to one array cell 110 is electrically connected to the read / write control circuit 102, which is beneficial to further reducing the energy consumption of the data signal line and further reducing the power consumption of the storage block.

[0068] Specifically, the switching switch module includes: a control unit and a switch unit; the control unit generates a control signal based on the received row decoding signal; the switch unit is used to connect the read / write control circuit 102 to an array cell 110 through the data signal line based on the control signal.

[0069] The switch unit includes a plurality of switches, and the data signal lines electrically connected to the array cells 110 are respectively connected to the read / write control circuit 102 through different switches.

[0070] Specifically, as in Figure 5 In, the switch unit includes a plurality of switches (such as Figure 5 Exemplarily shown in the figure are switches S1 and S2), and data signal lines electrically connected to different array units 110 are respectively connected to the read / write control circuit 102 through different switches. For example, in each memory array 101, the array unit 110 on the side of the memory array 101 close to the read / write control circuit 102 can be connected to the read / write control circuit 102 through the data signal line YIO1 after connecting to the switch S1, and the array unit 110 on the side of the memory array 101 far from the read / write control circuit 102 can be connected to the read / write control circuit 102 through the data signal line YIO2 after connecting to the switch S2. The control unit controls the first switch S1 to be closed or opened and controls the second switch S2 to be closed or opened based on the row decoding signal.

[0071] It can be understood that the switch S1 or the switch S2 can be composed of at least one MOS transistor. When the switch S1 is closed, the data signal line YIO1 is electrically connected to the read / write control circuit 102; when the switch S1 is opened, the data signal line YIO1 is disconnected from the read / write control circuit 102; when the switch S2 is closed, the data signal line YIO2 is electrically connected to the read / write control circuit 102; when the switch S2 is opened, the data signal line YIO2 is disconnected from the read / write control circuit 102.

[0072] The memory block of this embodiment further includes: a row decoding circuit (not shown in the figure), which is used to issue a row decoding signal to locate the word line in the selected array unit 110.

[0073] For example, when the row decoding signal locates the array unit 110 on the side of the memory array U close to the read / write control circuit 102 and the array unit 110 on the side of the memory array V close to the read / write control circuit 102, in the switching switch module corresponding to the memory array U, the switch S1 is closed and the switch S2 is opened, and in the switching switch module corresponding to the memory array V, the switch S1 is closed and the switch S2 is opened, so as to enable the data signal line YIO1 to read the data in the array unit 110 on the side of the memory array U close to the read / write control circuit 102 and the array unit 110 on the side of the memory array V close to the read / write control circuit 102.

[0074] For the convenience of understanding, the working principle of the memory block provided in this embodiment will be described below with reference to the accompanying drawings:

[0075] As Figure 5 , in a single write operation, the array cells 110 on the side of the storage array U close to the read / write control circuit 102 and the array cells 110 on the side of the storage array V far from the read / write control circuit 102 are selected; for the storage array U, switch S1 is closed and switch S2 is opened, the data signal line YIO1 is connected to the circuit, and the data signal line YIO2 is disconnected from the circuit; for the storage array V, switch S1 is opened and switch S2 is closed, the data signal line YIO1 is disconnected from the circuit, and the data signal line YIO2 is connected to the circuit; for the storage array W, both switch S1 and switch S2 are opened, and the data signal lines YIO1 and YIO2 connected to the storage array W are disconnected from the circuit.

[0076] In the next write operation, the array cells 110 on the side of the storage array U far from the read / write control circuit 102 and the array cells 110 on the side of the storage array V close to the read / write control circuit 102 are selected; for the storage array U, switch S1 is opened and switch S2 is closed, the data signal line YIO2 is connected to the circuit, and the data signal line YIO1 is disconnected from the circuit; for the storage array V, switch S1 is closed and switch S2 is opened, the data signal line YIO2 is disconnected from the circuit, and the data signal line YIO1 is connected to the circuit; for the storage array W, the data signal lines YIO1 and YIO2 connected to the storage array W are disconnected from the circuit. It should be noted that the above two write operations are only one of many write operations, and the array cells 110 to be written can be selected according to specific needs, and are not limited to the above two methods.

[0077] Compared with the previous embodiment, in this embodiment, when the data signal line YIO1 or the data signal line YIO2 does not play the role of transmitting electrical signals, it will be completely disconnected from the circuit, which is beneficial to further reducing the power consumption of the storage block. It is found that when the number of storage arrays in several storage arrays is 145, the storage block can save 12 mA of current at a baud rate of 3733.

[0078] Figure 6 A storage block provided by another embodiment of the present invention, based on any of the above storage block structures, the number of several error detection and correction units 103 is two, and they can be respectively:

[0079] The first error detection and correction unit 1031 is connected to each array cell 110 through the read / write control circuit 102, and is used for error detection and correction of a part of the output data of the array cell 110; the second error detection and correction unit 1032 is connected to each array cell 110 through the read / write control circuit 102, and is used for error detection and correction of the remaining output data of the array cell 110.

[0080] In this example, the arrangement of the storage arrays can refer to Figure 2 and Figure 3 。In this embodiment, it is taken as an example that the data output by the storage array U is 136 bits. Among them, 128 bits of data are valid data (the data that the memory needs to interact with the external controller through the memory interface), and 8 bits of data are the parity codes generated after being processed by the first error detection and correction unit 1031 and the second error detection and correction unit 1032. It should be noted that the memory includes a write data operation and a read data operation. When a write data operation is performed on the storage array in the memory, the data received by the memory interface is processed by the ECC module (such as Figure 6 the first error detection and correction unit 1031 and the second error detection and correction unit 1032 in it). For example, when 128 bits of data enter the ECC module, these 128 bits of data are also called valid data, and the data output by the ECC module is 136 bits (128 bits of valid data + 8 bits of parity code). Among them, 128 bits of data are valid data, and 8 bits are the parity codes generated by the ECC module. These 136 bits will be stored in the storage array of the storage array U. It can be said that the ECC module is in the encoding process for the write data operation; when a read data operation is performed on the storage array in the memory, 136 bits (128 bits of valid data + 8 bits of parity code) of data are also output from the storage array U. These 136 bits enter the ECC module at the same time. At this time, the ECC module executes an algorithm opposite to the writing algorithm. It can be said that the ECC module is in the decoding process for the read data operation. The ECC module decodes the 128 bits of valid data and compares the result of the decoding operation with the 8 bits of parity code to determine whether there is an error in the output 128 bits of valid data. If there is only 1 bit error in every 64 bits (one-bit error), the ECC module can also correct the one-bit error.

[0081] Continue to refer to Figure 6 , in this embodiment, for example, taking the case of reading out 272 bits of data (256 bits of stored data + 16 bits of check code) from storage array U and storage array V as an example, the output data of 136 bits (128 bits of stored data + 8 bits of check code) read out from storage array U are respectively output to the first error detection and correction unit 1031 and the second error detection and correction unit 1032, and the output data of 136 bits (128 bits of stored data + 8 bits of check code) read out from storage array V are respectively output to the first error detection and correction unit 1031 and the second error detection and correction unit 1032. A comparative embodiment is provided. Storage array U outputs the output data of 138 bits (128 bits of stored data + 8 bits of check code) to the first error detection and correction unit 1031, and storage array V outputs the output data of 136 bits (128 bits of stored data + 8 bits of check code) to the second error detection and correction unit 1032. In comparison, since part of the output data of storage array U (or storage array V) is input to the first error detection and correction unit 1031 for error detection and correction, and the remaining output data is input to the second error detection and correction unit 1032 for error detection and correction, when more than one error occurs simultaneously in the output data of storage array U (or storage array V) (such as two-bit errors), different errors can be corrected by the first error detection and correction unit 1031 or the second error detection and correction unit 1032, so that the memory can correct more than one error, improving the error detection and correction ability of the memory.

[0082] In this embodiment, the number of bits of data received by the first error detection and correction unit 1031 is the same as the number of bits of data received by the second error detection and correction unit 1032. In one example, the number of bits of data received by the first error detection and correction unit 1031 and the number of bits of data received by the second error detection and correction unit 1032 are both 128 bits + 8 bits. Among them, 128 bits are the valid data written or read by storage array U and storage array V, and 8 bits are the check code generated by the first error detection and correction unit 1031 or the second error detection and correction unit 1032.

[0083] In addition, the internal error detection algorithm of the first error detection and correction unit 1031 is the same as the internal error detection algorithm of the second error detection and correction unit 1032. In this way, it is beneficial to reduce the design difficulty of the memory.

[0084] Taking the first error detection and correction unit 1031 as an example, each time data is written, the first error detection and correction unit 1031 uses an internal error detection algorithm to calculate the valid data (128 bits), and obtains a check code (8 bits), denoted as the first check code. Then, the valid data (128 bits) and the check code (8 bits) are written into the storage array 101 at the same time. When these data are read out from the storage array 101, the valid data (128 bits) are calculated again using the same algorithm to obtain a check code (8 bits), denoted as the second check code. The second check code is compared with the first check code directly read out. If the results are the same, it means the data is correct; otherwise, it means there is an error. The first error detection and correction unit 1031 can logically detect the error. When only one-bit error occurs, the first error detection and correction unit 1031 can correct the error without affecting the memory reading operation. For example, when the "0" at the 3rd bit of 128 bits is the error bit, the first error detection and correction unit 1031 corrects the "0" at the 3rd bit to "1".

[0085] Regarding the working principle of the second error detection and correction unit 1032, reference can be made to the first error detection and correction unit 1031, which will not be elaborated below.

[0086] Specifically, part of the output data in the storage array U is input to the first error detection and correction unit 1031 for error detection and correction, and the remaining part of the output data is input to the second error detection and correction unit 1032 for error detection and correction. In this way, two adjacent bit errors that may occur in the same storage array U are placed in different ECC units respectively. Since these two error data are processed by the first error detection and correction unit 1031 and the second error detection and correction unit 1032 respectively, that is, each of the first error detection and correction unit 1031 and the second error detection and correction unit 1032 only processes one error. Therefore, from the perspective of the memory, this memory can correct these two errors simultaneously.

[0087] Regarding the error detection and correction mechanism when errors occur in the storage array V and the storage array W, reference can be made to the corresponding description of the storage array U, which will not be elaborated here.

[0088] In this embodiment, the storage capacities of the storage arrays U and V and the storage capacity of W are the same. In other embodiments, the storage capacities of the storage arrays U, V, and W may not be exactly the same.

[0089] Combined with reference Figure 6 and Figure 7 , Figure 7 For Figure 6 Schematic diagram of signal line connection of the local area represented by the thick line in a grid of the storage array 101 (shown expanded with the storage array U, the thick solid line is only connected to odd grids, the thick dashed line is only connected to even grids, and the storage arrays V and W are the same as the storage array U). The local data bus LIO is connected to the bit line BL through the column selection signal unit 109, and the sense amplifier is provided in one-to-one correspondence with the bit line BL of the storage unit 105. The column selection signal unit 109 includes a strobe switch, and the column select signal controls the conduction or cut-off of the strobe switch. When the strobe switch is conductive, the bit line BL exchanges data with the local data bus LIO. When the strobe switch is cut off, the bit line BL no longer exchanges data with the local data bus LIO. In addition, the data on adjacent bit lines BL enter the local data bus O and the local data bus E respectively through the column selection signal unit 109. For the sake of distinction, Figure 7 in LIO:E indicates the local data bus E, and LIO:O indicates the local data bus O, with CSL <n-1>, CSL <n>And CSL<n+1> shows a column selection signal unit, where a strobe switch is located in the column selection signal unit (not shown), and sense amplifiers are located on both sides of the bit line BL (not shown). The local data bus E also exchanges data with the block data bus E through a local conversion circuit (not shown), and the local data bus O also exchanges data with the block data bus O through a local conversion circuit (not shown). In Figure 7 the block data bus E is schematically shown by the solid line YIO:E with an arrow, and the block data bus O is schematically shown by the dashed line YIO:O with an arrow.

[0090] Continuing to refer to Figure 6 , one of the block data buses O is denoted as YIO1_O, and one of the block data buses E is denoted as YIO1_E. In one embodiment, Figure 7 YIO:E in Figure 7 can be understood as one of the YIO1_E, and YIO:O in

[0091] Continuing to refer to Figure 6 , the data of YIO_O enters the first error detection and correction unit 1031, and the data of YIO_E enters the second error detection and correction unit 1032. In this embodiment, the storage arrays U, V, and W each include a local conversion circuit (LocalSA, not shown) and an even number of local data buses. The local data buses are divided into local data bus O and local data bus E. The local data bus O is connected to the block data bus O through a local conversion circuit, and the local data bus E is connected to the block data bus E through a local conversion circuit.

[0092] It should be noted that the local data buses are numbered in natural numbers starting from zero. The local data buses with odd numbers are defined as local data bus O, and the local data buses with even numbers are defined as local data bus E; or rather, among the local data buses corresponding to physically adjacent storage arrays, the local data buses in odd positions are defined as local data bus O, and the local data buses in even positions are defined as local data bus E.

[0093] Since physically adjacent data are placed in different error detection and correction units, that is, they enter the first error detection and correction unit 1031 and the second error detection and correction unit 1032 respectively. When two adjacent bit errors occur, since these two bit errors are corrected in different error detection and correction units respectively, these two bit errors can be processed simultaneously. It can be understood that even if the process size is continuously reduced and the risk of bridging between adjacent capacitors increases, since the data corresponding to adjacent capacitors enter different error detection and correction units for error correction, even if the process size is continuously reduced, the errors of two physically adjacent bits of data can still be corrected.

[0094] Continue to refer to Figure 6 , the arrangement of the memory arrays in the memory array U is numbered starting from 0 according to natural numbers. The block data bus is electrically connected to the memory arrays with even numbers. More specifically, the memory array includes memory cells, a local data bus E, a local data bus O, and a local conversion circuit. The block data bus is connected to the local data bus E through the local conversion circuit; the block data bus is connected to the local data bus O through the local conversion circuit. Figure 6 The connection relationship between the block data bus and the memory array is marked with thick line symbols in

[0095] It can be understood that in one example, the block data bus is 2 * 4 * (16 * N) strips, and the local data bus is 2 * 4 * M * (16 * N) strips; the block data bus O is 4 * (16 * N) strips, and the block data bus E is 4 * (16 * N) strips; the local data bus O is 4 * M * (16 * N) strips, and the local data bus E is 4 * M * (16 * N) strips; 1 strip of block data bus O corresponds to M strips of local data bus O, and 1 strip of block data bus E corresponds to M strips of local data bus E; the local data bus is divided into M * (16 * N) groups of local data bus O and M * (16 * N) groups of local data bus E with 4 adjacent strips as a group. Among them, M and N are natural numbers greater than or equal to 1. Taking M and N both being 1 as an example, the block data bus is 2 * 4 * 16 strips, the local data bus is 2 * 4 * 16 strips, the block data bus O is 4 * 16 strips, the block data bus E is 4 * 16 strips, the local data bus O is 4 * 16 strips, the local data bus E is 4 * 16 strips, and there are 16 groups of local data bus O and 16 groups of local data bus E in total.

[0096] In one example, such as Figure 6 As shown, the data signal lines corresponding to each array unit 110 include an even number of block data buses. The block data buses are numbered in sequence from zero according to natural numbers. The block data buses with odd numbers (denoted as YIO_O) are connected to the first error detection and correction unit 1031 through the read / write control circuit 102, and the block data buses with even numbers (denoted as YIO_E) are connected to the second error detection and correction unit 1032 through the read / write control circuit 102; each array unit 110 in the storage array U includes an even number of block data buses. The block data buses are numbered in sequence from zero according to natural numbers. The block data buses with odd numbers (denoted as YIO_O) are connected to the first error detection and correction unit 1031 through the read / write control circuit 102, and the block data buses with even numbers (denoted as YIO_E) are connected to the second error detection and correction unit 1032 through the read / write control circuit 102; each array unit 110 in the storage array V includes an even number of block data buses. The block data buses are numbered in sequence from zero according to natural numbers. The block data buses with odd numbers (denoted as YIO_O) are connected to the first error detection and correction unit 1031 through the read / write control circuit 102, and the block data buses with even numbers (denoted as YIO_E) are connected to the second error detection and correction unit 1032 through the read / write control circuit 102; each array unit 110 in the storage array W includes an even number of block data buses. The block data buses are numbered in sequence from zero according to natural numbers. The block data buses with odd numbers (denoted as YIO_O) are connected to the first error detection and correction unit 1031 through the read / write control circuit 102, and the block data buses with even numbers (denoted as YIO_E) are connected to the second error detection and correction unit 1032 through the read / write control circuit 102.

[0097] In this way, the data of the block data buses O (YIO_O) of the storage arrays U, V, and W enter the first error detection and correction unit 1031 through the read / write control circuit 102 for error detection and correction; the data of the block data buses E (YIO_E) of the storage arrays U, V, and W enter the second error detection and correction unit 1032 through the read / write control circuit 102 for error detection and correction.

[0098] In another example, the data signal lines corresponding to each array unit include an even number of block data buses. The block data buses are numbered in sequence from zero according to natural numbers. The block data buses with odd numbers (denoted as YIO_O) are connected to the second error detection and correction unit 1032, and the block data buses with even numbers (denoted as YIO_E) are connected to the first error detection and correction unit 1031. Each array unit 110 in the storage array U includes an even number of block data buses. The block data buses are numbered in sequence from zero according to natural numbers. The block data buses with odd numbers (denoted as YIO_O) are connected to the second error detection and correction unit 1032, and the block data buses with even numbers (denoted as YIO_E) are connected to the first error detection and correction unit 1031; each array unit 110 in the storage array V includes an even number of block data buses. The block data buses are numbered in sequence from zero according to natural numbers. The block data buses with odd numbers (denoted as YIO_O) are connected to the second error detection and correction unit 1032, and the block data buses with even numbers (denoted as YIO_E) are connected to the first error detection and correction unit 1031; each array unit 110 in the storage array W includes an even number of block data buses. The block data buses are numbered in sequence from zero according to natural numbers. The block data buses with odd numbers (denoted as YIO_O) are connected to the second error detection and correction unit 1032, and the block data buses with even numbers (denoted as YIO_E) are connected to the first error detection and correction unit 1031.

[0099] In this way, the data on the block data buses O (YIO_O) of the storage arrays U, V, and W enter the second error detection and correction unit 1032 for error detection and correction; the data on the block data buses E (YIO_E) of the storage arrays U, V, and W enter the first error detection and correction unit 1031 for error detection and correction.

[0100] For the storage block provided in this embodiment, since the output data of the same array unit 110 are respectively input into different error detection and correction units, that is, part of the output data is input into the first error detection and correction unit 1031 for error detection and correction, and the rest of the output data is input into the second error detection and correction unit 1032 for error detection and correction. In this way, if two-bit data errors occur simultaneously, the first error detection and correction unit 1031 and the second error detection and correction unit 1032 can respectively correct one bit of the two bits of data, thereby improving the error detection and correction ability of the memory.

[0101] Figure 8 It is a schematic structural diagram of a storage block provided in another embodiment of the present invention.

[0102] In some embodiments of the present application, the output data of two array units 110 of the storage array U, the storage array V, and the storage array W respectively correspond to high-order data and low-order data. For example, the array unit 110 on the side of the storage array U close to the read / write control circuit 102 stores high-order data, and the array unit 110 on the side of the storage array U far from the read / write control circuit 102 stores low-order data. The array unit 110 on the side of the storage array V close to the read / write control circuit 102 stores low-order data, and the array unit 110 on the side of the storage array V far from the read / write control circuit 102 stores high-order data. The array unit 110 on the side of the storage array W close to the read / write control circuit 102 stores high-order data, and the array unit 110 on the side of the storage array W far from the read / write control circuit 102 stores low-order data. In this way, since the data output by the two array units 110 of the storage array U, the storage array V, and the storage array W includes low-order data and high-order data, only one array unit 110 storing high-order data in the storage array U, the storage array V, or the storage array W and another array unit 110 storing low-order data in a different storage array 101 will be accessed in a single access, thereby reducing the power consumption of the memory.

[0103] Reference Figure 8 , the above-mentioned several storage arrays 101 (the remaining structures except the storage array 101 can refer to the descriptions in the foregoing embodiments and will not be elaborated here) include a storage array U, a storage array V, and a storage array W arranged in sequence along the first direction; each storage array is divided into two array units along the second direction; the first direction and the second direction are perpendicular to each other; two array units on the same side of the storage array U and the storage array V in the second direction Y share the same word line address; two read / write control circuits corresponding to the storage array U and the storage array V are associated and configured to simultaneously access the storage units at the same word line address in the two array units on the same side of the storage array U and the storage array V.

[0104] Specifically, it can be that two array units 110 on the first side of the storage array U and the storage array V share the same word line address; two read / write control circuits 102 corresponding to the storage array U and the storage array V are associated and configured to simultaneously access the storage units at the same word line address in the two array units on the first side of the storage array U and the storage array V; or, it can be that two array units on the second side of the storage array U and the storage array V share the same word line address, and the second side is the opposite side of the first side; two read / write control circuits corresponding to the storage array U and the storage array V are associated and configured to simultaneously access the storage units at the same word line address in the two array units on the second side of the storage array U and the storage array V. It should be noted that the first side mentioned in the embodiments of the present application can be one side of the storage array in the second direction Y, and the second side can be the other side of the storage array in the second direction Y.

[0105] For example, referring to Figure 8 , taking the case where two array units 110 on the first side in the storage array U and the storage array V share the same word line address as an example, two array units on the first side in the storage arrays U and V can share the same word line address. Two read / write control circuits 102 corresponding to the storage arrays U and V are associated and configured to simultaneously access the two array units 110 on the first side in the storage arrays U and V, that is, data with the same word line address in the memory array can be accessed. For example, accessing the word line address corresponding to 1 can simultaneously access data with the same word line address in the memory arrays numbered 3 in the storage arrays U and V.

[0106] Continuing to refer to Figure 8 , when two array units 110 on the first side in the storage arrays U and V share the same word line address, and two array units on the second side in the storage arrays V and W share the same word line address, two read / write control circuits 102 corresponding to the storage arrays V and W are associated and configured to simultaneously access the two array units 110 on the second side in the storage arrays V and W. That is, data with the same word line address in the storage arrays V and W can be accessed. For example, accessing the word line corresponding to 2 can simultaneously access data with the same word line address in the memory arrays numbered 38 in the storage arrays V and W.

[0107] Continuing to refer to Figure 8 , when two array units 110 on the first side in the storage arrays U and V share the same word line address, and two array units 110 on the second side in the storage arrays V and W share the same word line address, two read / write control circuits 102 corresponding to the storage arrays U and W are associated and configured to respectively and simultaneously access the array unit 110 on the second side in the storage array U and the array unit 110 on the first side in the storage array W. That is, the array unit 110 on the second side in the storage array U and the array unit 110 on the first side in the storage array W can also share the same word line address. In this way, accessing the word line corresponding to 3 can simultaneously access data with the same word line address in the array unit 110 on the second side in the storage array U and the array unit 110 on the first side in the storage array W in the memory array numbered 20.

[0108] In some embodiments of the present application, when two array units 110 on the second side in storage array U and storage array V share the same word line address, and two array units 110 on the first side in storage array V and storage array W share the same word line address, the two read / write control circuits 102 corresponding to storage array U and storage array V are associated and configured to simultaneously access the two array units 110 on the second side in storage array U and storage array V respectively, the two read / write control circuits 102 corresponding to storage array V and storage array W are associated and configured to simultaneously access the two array units 110 on the first side in storage array V and storage array W respectively, and the two read / write control circuits 102 corresponding to storage array U and storage array W are associated and configured to simultaneously access the array unit 110 on the first side in storage array U and the array unit 110 on the second side in storage array W.

[0109] Compared with the foregoing embodiments, the storage block provided in this embodiment can realize that the data in the two array units can be accessed simultaneously with the same word line by configuring the access states of the read / write control circuits corresponding to each storage array, and can realize flexible access data combinations.

[0110] Based on the storage blocks in the above embodiments, this embodiment further provides a memory, which includes the storage blocks in any one or at least two combined embodiments above.

[0111] Those of ordinary skill in the art can understand that the above embodiments are specific embodiments for implementing the present invention, and in practical applications, various changes can be made in form and details without departing from the spirit and scope of the present invention. Any person skilled in the art can make their own changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.< / n> < / n> < / n> < / n>

Claims

1. A storage block, characterized in that, Including: A plurality of memory arrays arranged in a first direction, configured to store data and parity codes, and each of the memory arrays is divided into at least two array units; A plurality of read / write control circuits, each corresponding to one of the memory arrays respectively, configured to write or read the data and the parity codes to / from the corresponding memory array; the read / write control circuits are electrically connected to the respective array units through different data signal lines, and the read / write control circuits are configured to access only one array unit in the corresponding memory array each time; A plurality of error detection and correction units, electrically connected to the plurality of read / write control circuits, configured to perform error detection and / or correction on the data according to the parity codes; Wherein, during a read operation, the data and the parity codes read out by each of the read / write control circuits are divided into at least two parts, and the read / write control circuits are configured to transmit each part to different error detection and correction units.

2. The storage block according to claim 1, characterized in that, Further including: A plurality of switch modules, each corresponding to one of the memory arrays respectively, configured to switch one of the array units to be electrically connected to the read / write control circuit through the data signal lines.

3. The storage block according to claim 2, characterized in that, The switch module includes: a control unit and a switch unit; the control unit generates a control signal based on a received row decoding signal; the switch unit is configured to connect the read / write control circuit to one of the array units through the data signal lines based on the control signal.

4. The storage block according to claim 3, characterized in that, The switch unit includes a plurality of switches, and each of the data signal lines is connected to the read / write control circuit through one of the switches.

5. The storage block according to claim 1, characterized in that, The plurality of error detection and correction units at least include: A first error detection and correction unit, connected to each of the array units through the read / write control circuit, configured to perform error detection and correction on a part of the output data of the array unit; a second error detection and correction unit, connected to each of the array units through the read / write control circuit, configured to perform error detection and correction on the remaining output data part of the array unit.

6. The storage block according to claim 5, characterized in that, The data signal lines corresponding to each of the array units include an even number of block data buses, numbering the block data buses in natural numbers starting from zero, the block data buses numbered with odd numbers O are connected to the first error detection and correction unit, and the block data buses numbered with even numbers E are connected to the second error detection and correction unit.

7. The storage block according to claim 6, characterized in that, Each of the array units includes a local conversion circuit and an even number of local data buses, the local data buses are divided into local data buses O and local data buses E, the local data buses O are connected to the block data buses O through the local conversion circuit, and the local data buses E are connected to the block data buses E through the local conversion circuit.

8. The storage block according to claim 7, characterized in that, Each of the local data buses is connected to an even number of sense amplifiers through a strobe switch, and the sense amplifiers are arranged in one-to-one correspondence with the bit lines in the memory array.

9. The storage block according to claim 8, characterized in that, The output data on two adjacent bit lines enter the local data buses O and the local data buses E respectively through the sense amplifiers and the strobe switches.

10. The storage block according to claim 9, characterized in that, The block data bus has 2 * 4 * (16 * N) lines, and the local data bus has 2 * 4 * M * (16 * N) lines; the block data bus O has 4 * (16 * N) lines, and the block data bus E has 4 * (16 * N) lines; the local data bus O has 4 * M * (16 * N) lines, and the local data bus E has 4 * M * (16 * N) lines; 1 line of the block data bus O corresponds to M lines of the local data bus O, and 1 line of the block data bus E corresponds to M lines of the local data bus E; the local data bus is divided into M * (16 * N) groups of the local data bus O and M * (16 * N) groups of the local data bus E with 4 adjacent lines as a group.

11. The storage block according to claim 1, characterized in that, The several memory arrays include a memory array U, a memory array V, and a memory array W arranged in sequence along the first direction; each memory array is divided into two array units along the second direction; two array units on the same side in the second direction of the memory array U and the memory array V share the same word line address; The two read / write control circuits corresponding to the memory array U and the memory array V are associated and configured to simultaneously access the memory cells with the same word line address in the two array units on the same side in the second direction of the memory array U and the memory array V.

12. The storage block according to claim 11, characterized in that, Two array units on the first side of the memory array U and the memory array V share the same word line address; the two read / write control circuits corresponding to the memory array U and the memory array V are associated and configured to respectively and simultaneously access the memory cells with the same word line address in the two array units on the first side of the memory array U and the memory array V; or, Two array units on the second side of the memory array U and the memory array V share the same word line address, and the first side and the second side are different sides in the second direction; the two read / write control circuits corresponding to the memory array U and the memory array V are associated and configured to respectively and simultaneously access the memory cells with the same word line address in the two array units on the second side of the memory array U and the memory array V.

13. The storage block according to claim 12, characterized in that, When two array units on the first side of the memory array U and the memory array V share the same word line address, two array units on the second side of the memory array V and the memory array W share the same word line address; the two read / write control circuits corresponding to the memory array V and the memory array W are associated and configured to respectively and simultaneously access the two array units on the second side of the memory array V and the memory array W, and the two read / write control circuits corresponding to the memory array U and the memory array W are associated and configured to respectively and simultaneously access the array unit on the second side of the memory array U and the array unit on the first side of the memory array W.

14. The storage block according to claim 12, characterized in that, When two array cells on the second side in the storage array U and the storage array V share the same word line address, two array cells on the first side in the storage array V and the storage array W share the same word line address; two read / write control circuits corresponding to the storage array V and the storage array W are associated and configured to respectively and simultaneously access the two array cells on the first side in the storage array V and the storage array W, and two read / write control circuits corresponding to the storage array U and the storage array W are associated and configured to respectively and simultaneously access the array cell on the first side in the storage array U and the array cell on the second side in the storage array W.

15. The storage block according to claim 1, characterized in that, It further includes: A row decoding circuit, configured to issue a row decoding signal to locate and select the word line in the array cell.

16. A memory, characterized in that, It includes the storage block according to any one of claims 1-15.

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