Semiconductor device

Abstract

A semiconductor device includes a substrate, a first conductive layer, a first insulating layer, a gate structure, a semiconductor layer, and a second insulating layer. The first conductive layer is disposed on the substrate. The first insulating layer is disposed on the first conductive layer. The gate structure is disposed on the first insulating layer. The semiconductor layer is disposed between the first insulating layer and the gate structure. The semiconductor layer includes a channel region, a first heavily doped region, a second heavily doped region, and at least one lightly doped region. The channel region overlaps the gate structure. The first heavily doped region and the second heavily doped region are respectively located on two sides of the channel region. The at least one lightly doped region is located between the first heavily doped region and the channel region or between the second heavily doped region and the channel region to form an asymmetric doping structure on two sides of the channel region. The second insulating layer is disposed between the semiconductor layer and the gate structure.

Description

Technical Field

[0001] This invention relates to an apparatus, and more particularly to a semiconductor apparatus. Background Technology

[0002] Semiconductor devices, such as thin-film transistors (TFTs), are widely used in electronic products for controlling current switching. With the increasing demand for thinner, lighter, and smaller electronic products, how to enable semiconductor devices to meet high-current or high-voltage applications within a small size or dimensions is a problem that needs to be improved. Summary of the Invention

[0003] The present invention provides a semiconductor device that is small in size and has improved carrier mobility and robustness.

[0004] The semiconductor device of the present invention includes a substrate, a gate structure, a semiconductor layer, and a second insulating layer. The gate structure is disposed on the substrate. The semiconductor layer is disposed between the substrate and the gate structure. The semiconductor layer includes a channel region, a first heavily doped region, a second heavily doped region, and at least one lightly doped region. The channel region overlaps the gate structure in the normal direction of the substrate. The first heavily doped region and the second heavily doped region are respectively located on opposite sides of the channel region. At least one lightly doped region is located between the first heavily doped region and the channel region or between the second heavily doped region and the channel region, to form an asymmetric doping structure on both sides of the channel region. The second insulating layer is disposed on the semiconductor layer and located between the semiconductor layer and the gate structure.

[0005] The semiconductor device of the present invention includes a substrate, a semiconductor layer, a gate structure, and an insulating layer. The semiconductor layer is disposed on the substrate and includes a channel region. The channel region includes a first undoped region, a second undoped region, and a channel-doped region. The channel-doped region is located between the first undoped region and the second undoped region. The gate structure is disposed on the semiconductor layer. The gate structure includes a first conductive portion, a second conductive portion, and a third conductive portion. The first conductive portion overlaps the first undoped region in the normal direction of the substrate. The second conductive portion overlaps the second undoped region in the normal direction of the substrate. The third conductive portion is disposed on the first and second conductive portions and partially overlaps the channel-doped region in the normal direction of the substrate. The first and second conductive portions are separated from each other, and the third conductive portion is electrically connected to the first and second conductive portions. The insulating layer is disposed on the semiconductor layer and located between the semiconductor layer and the gate structure.

[0006] Based on the above, the semiconductor device of the present invention has an asymmetric doping structure on both sides of the channel region. Compared with a semiconductor device of the same volume, the width of the second lightly doped region near the drain can be increased, so that the drain end has more buffer, thereby reducing the possible damage to the semiconductor device under the action of a high electric field, and thus enabling the semiconductor device to have improved carrier mobility and tolerance. Attached Figure Description

[0007] Figure 1 This is a top view schematic diagram of a semiconductor device according to an embodiment of the present invention;

[0008] Figure 2 It is along Figure 1 A cross-sectional schematic diagram of a semiconductor device according to an embodiment of the cross-section A-A';

[0009] Figure 3 It is along Figure 1 A cross-sectional schematic diagram of a semiconductor device according to another embodiment of the cross-section A-A';

[0010] Figure 4 It is along Figure 1 A cross-sectional schematic diagram of a semiconductor device according to another embodiment of the cross-section A-A';

[0011] Figure 5 This is a top view schematic diagram of a semiconductor device according to another embodiment of the present invention;

[0012] Figure 6 It is along Figure 5 A cross-sectional schematic diagram of a semiconductor device according to an embodiment of the cross-section B-B';

[0013] Figure 7 This is a top view schematic diagram of a semiconductor device according to another embodiment of the present invention;

[0014] Figure 8 It is along Figure 7 A cross-sectional schematic diagram of a semiconductor device according to an embodiment of the cross-section C-C';

[0015] Figure 9 This is a top view schematic diagram of a semiconductor device according to another embodiment of the present invention;

[0016] Figure 10 This is a top view schematic diagram of a semiconductor device according to another embodiment of the present invention;

[0017] Figure 11 It is along Figure 9 or Figure 10 A cross-sectional schematic diagram of a semiconductor device according to an embodiment of the cross-section D-D';

[0018] Figure 12 This is a top view schematic diagram of a semiconductor device according to another embodiment of the present invention;

[0019] Figure 13 It is along Figure 12 A cross-sectional schematic diagram of a semiconductor device according to an embodiment of the cross-section E-E';

[0020] Figure 14 This is a top view schematic diagram of a semiconductor device according to another embodiment of the present invention;

[0021] Figure 15 It is along Figure 14 A cross-sectional schematic diagram of a semiconductor device according to an embodiment of the cross-section F-F';

[0022] Figures 16A to 16D This is a cross-sectional schematic diagram of the manufacturing process of a semiconductor device according to an embodiment of the present invention;

[0023] Figures 17A to 17C This is a cross-sectional schematic diagram of the manufacturing process of a semiconductor device according to an embodiment of the present invention.

[0024] Symbol Explanation

[0025] 10, 10a, 10b, 20, 30, 40, 50, 60: Semiconductor device; 100: Substrate

[0026] 110: First conductive layer

[0027] 112: Fourth conductive part

[0028] 114: Fifth conductive part

[0029] 120: First insulating layer

[0030] 130: Semiconductor layer

[0031] 140: Second insulating layer

[0032] 152: First conductive part

[0033] 152': Initial first conductive portion

[0034] 152a, 154a: Inner wall

[0035] 152b, 154b: Outer wall

[0036] 152c, 154c: Top surface

[0037] 154: Second conductive part

[0038] 154': Initial second conductive portion

[0039] 156: Conductive extension portion

[0040] 160: Interlayer dielectric layer

[0041] 162: Third conductive part

[0042] 162a, 162b: Sidewall

[0043] A-A',B-B',C-C',D-D',E-E',F-F': hatching line

[0044] CH: Channel area

[0045] ch1: First undoped region

[0046] ch2: Second undoped region

[0047] ch3: Channel doped region

[0048] D: Drain electrode

[0049] G: Gate structure

[0050] H1: First doped region

[0051] H2: Second doped region

[0052] L1: First lightly doped region

[0053] L2: Second lightly doped region

[0054] N: Normal direction

[0055] PR: Patterned photoresist

[0056] P1, P2: Doping fabrication process

[0057] S: Source

[0058] W1: First width

[0059] W2: Second width

[0060] θ1, θ3: Inner angles

[0061] θ2, θ4: External angles Detailed Implementation

[0062] Figure 1 This is a top view schematic diagram of a semiconductor device according to an embodiment of the present invention. Figure 2 It is along Figure 1 A cross-sectional schematic diagram of a semiconductor device according to an embodiment of the cross-section A-A'. Figure 3 It is along Figure 1 A cross-sectional schematic diagram of a semiconductor device according to another embodiment of the section line A-A'. Figure 4 It is along Figure 1 A cross-sectional schematic diagram of a semiconductor device according to another embodiment of the section line A-A'.

[0063] Please refer to Figures 1 to 2The semiconductor device 10 includes a substrate 100, a first conductive layer 110, a first insulating layer 120, a semiconductor layer 130, a gate structure G, and a second insulating layer 140. In this embodiment, the semiconductor device 10 further includes an interlayer dielectric layer 160, a source electrode S, and a drain electrode D.

[0064] The substrate 100 may be made of glass, quartz, organic polymer, or opaque / reflective materials (e.g., conductive materials, metals, wafers, ceramics, or other suitable materials) or other suitable materials. If conductive materials or metals are used, an insulating layer (not shown) is applied to the substrate 100 to prevent short circuits. In some embodiments, the substrate 100 is a flexible substrate, and the material of the substrate 100 may be, for example, polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyester (PES), polymethyl methacrylate (PMMA), polycarbonate (PC), polyimide (PI), or metal foil or other flexible materials.

[0065] A first conductive layer 110 is disposed on a substrate 100, and a first insulating layer 120 is disposed on the first conductive layer 110. The material of the first conductive layer 110 may be a metal or an alloy, such as copper, aluminum, silver, gold, molybdenum, alloys of the above metals, or other suitable metals or alloys.

[0066] In some embodiments, the semiconductor device 10 may further include a buffer layer (not shown) disposed between the substrate 100 and the first conductive layer 110. The buffer layer may be made of silicon nitride, silicon oxide, silicon oxynitride, or other suitable materials or stacked layers of the above materials, and the present invention is not limited thereto.

[0067] A semiconductor layer 130 is disposed on a first insulating layer 120, a second insulating layer 140 is disposed on the semiconductor layer 130, and a gate structure G is disposed on the second insulating layer 140. That is, the semiconductor layer 130 is disposed between the first insulating layer 120 and the gate structure G, and the second insulating layer 140 is disposed between the semiconductor layer 130 and the gate structure G. The materials of the first insulating layer 120 and the second insulating layer 140 may include silicon nitride, silicon oxide, silicon oxynitride, or other suitable materials or stacked layers of the above materials; this invention is not limited thereto.

[0068] Semiconductor layer 130 includes a channel region CH, a first heavily doped region H1, a second heavily doped region H2, and at least one lightly doped region (e.g., a first lightly doped region L1 and a second lightly doped region L2). The channel region CH overlaps the gate structure G in the normal direction N of the substrate 100. The first heavily doped region H1 and the second heavily doped region H2 are located on opposite sides of the channel region CH. At least one lightly doped region is located between the first heavily doped region H1 and the channel region CH or between the second heavily doped region H2 and the channel region CH to form an asymmetric doping structure on both sides of the channel region CH. In this document, an asymmetric doping structure means that the semiconductor layer 130 has different ranges or degrees of doping on both sides of the channel region CH. For example, in this embodiment, such as Figure 2 As shown, the semiconductor layer 130 includes a first lightly doped region L1 with a first width W1 on one side of the channel region CH, and a second lightly doped region L2 with a second width W2 on the other side of the channel region CH, wherein the first width W1 is smaller than the second width W2, that is, the first lightly doped region L1 and the second lightly doped region L2 are asymmetrical. In other embodiments, the semiconductor layer 130 may include only a heavily doped region (e.g., a first heavily doped region H1) without a lightly doped region on one side of the channel region CH, while the semiconductor layer 130 may include a lightly doped region (e.g., a second lightly doped region L2) and a heavily doped region (e.g., a second heavily doped region H2) on the other side of the channel region CH, so that the two sides of the channel region CH have an asymmetrical doping structure.

[0069] In this embodiment, the semiconductor layer 130 may be made of polycrystalline silicon. In other embodiments, the semiconductor layer 130 may also be made of amorphous silicon, microcrystalline silicon, monocrystalline silicon, organic semiconductor materials, oxide semiconductor materials (e.g., indium zinc oxide, indium gallium zinc oxide, or other suitable materials) or combinations thereof, and the present invention is not limited thereto.

[0070] In some embodiments, the channel region CH includes a first undoped region ch1, a second undoped region ch2, and a channel doped region ch3, wherein the channel doped region ch3 is located between the first undoped region ch1 and the second undoped region ch2.

[0071] The first heavily doped region H1, the second heavily doped region H2, the first lightly doped region L1, the second lightly doped region L2, and the channel doped region ch3 of the semiconductor layer 130 can be doped semiconductors. For example, the dopant can be a group V element, such as phosphorus or arsenic, to form an N-type doped region, or the dopant can be a group III element, such as boron or aluminum, to form a P-type doped region. This invention does not limit the type of dopant; it can be adjusted according to actual needs.

[0072] In some embodiments, the first conductive layer 110 may overlap the channel region CH, the first lightly doped region L1, and the second lightly doped region L2 in the normal direction N of the substrate 100. In this way, the first conductive layer 110 can serve as a shielding layer to reduce optical leakage of the semiconductor device. Furthermore, since the first conductive layer 110 overlaps with the first lightly doped region L1 and the second lightly doped region L2 in the normal direction N of the substrate 100, the kink effect at the drain terminal can be reduced, thereby improving the reliability of the semiconductor device 10.

[0073] Figure 2 Although the diagram shows the first conductive layer 110 overlapping the first lightly doped region L1 and the second lightly doped region L2 in the normal direction N of the substrate 100, it is not intended to limit the present invention. The first conductive layer 110 can be selectively overlapped with the first lightly doped region L1 or the second lightly doped region L2 in the normal direction N of the substrate 100 based on actual needs.

[0074] In some embodiments, the projected area of ​​the first conductive layer 110 on the substrate 100 is greater than the projected area of ​​the gate structure G on the substrate 100.

[0075] The gate structure G includes a first conductive portion 152, a second conductive portion 154, and a third conductive portion 162. The first conductive portion 152 and the second conductive portion 154 are disposed on the second insulating layer 140 and are separated from each other. In some embodiments, the first conductive portion 152 and the second conductive portion 154 are parallel, that is, the first conductive portion 152 and the second conductive portion 154 have the same extending direction. In this embodiment, the width of the first conductive portion 152 is different from the width of the second conductive portion 154, but the invention is not limited thereto. In other embodiments, the width of the first conductive portion 152 and the width of the second conductive portion 154 may be the same. The third conductive portion 162 is disposed on the first conductive portion 152 and the second conductive portion 154 to electrically connect the first conductive portion 152 and the second conductive portion 154.

[0076] The gate structure G can be made of metal or alloy, such as copper, aluminum, silver, gold, molybdenum, alloys of the above metals, or other easily etchable metals or alloys. In some embodiments, the material of the third conductive portion 162 can be the same as or different from the materials of the first conductive portion 152 and the second conductive portion 154.

[0077] In some embodiments, the first conductive portion 152 overlaps with the first undoped region ch1 in the normal direction N of the substrate 100, and the second conductive portion 154 overlaps with the second undoped region ch2 in the normal direction N of the substrate 100. The third conductive portion 162 overlaps with the channel region CH in the normal direction N of the substrate 100, that is, the third conductive portion 162 overlaps with the first undoped region ch1, the second undoped region ch2, and the channel doped region ch3 in the normal direction N of the substrate 100. Therefore, the gate structure G does not overlap with the first heavily doped region H1, the second heavily doped region H2, the first lightly doped region L1, and the second lightly doped region L2 in the normal direction N of the substrate 100.

[0078] In some embodiments, the shortest distance between the first conductive portion 152 and the second conductive portion 154 may be less than 2 μm. On the other hand, the width of the channel doped region ch3 may be less than 2 μm.

[0079] In some embodiments, the first conductive portion 152 has an inner sidewall 152a, an outer sidewall 152b, and a top surface 152c connecting the inner sidewall 152a and the outer sidewall 152b. The second conductive portion 154 has an inner sidewall 154a, an outer sidewall 154b, and a top surface 154c connecting the inner sidewall 154a and the outer sidewall 154b. The third conductive portion 162 covers the top surface 152c and the inner sidewall 152a of the first conductive portion 152, and the top surface 154c and the inner sidewall 154a of the second conductive portion 154.

[0080] In some embodiments, the sidewall 162a of the third conductive portion 162 is flush with the outer sidewall 152b of the first conductive portion 152, and the sidewall 162b of the third conductive portion 162 is flush with the outer sidewall 154b of the second conductive portion 154, but the invention is not limited thereto. In other embodiments, the sidewall 162a or sidewall 162b of the third conductive portion 162 may be recessed within the outer sidewall 152b of the first conductive portion 152 or the outer sidewall 154b of the second conductive portion 154. In yet another embodiment, one sidewall 162a or sidewall 162b of the third conductive portion 162 may cover the outer sidewall 152b of the first conductive portion 152 or the outer sidewall 154b of the second conductive portion 154.

[0081] In some embodiments, the first conductive portion 152 and the second conductive portion 154 have an asymmetrical structure. For example, the angle θ1 between the inner sidewall 152a of the first conductive portion 152 and the second insulating layer 140 is different from the angle θ2 between the outer sidewall 152b of the first conductive portion 152 and the second insulating layer 140. Similarly, the angle θ3 between the inner sidewall 154a of the second conductive portion 154 and the second insulating layer 140 is different from the angle θ4 between the outer sidewall 154b of the second conductive portion 154 and the second insulating layer 140. In some embodiments, the angle θ1 between the inner sidewall 152 and the outer sidewall θ2 of the first conductive portion 152 is greater than the angle θ2 of the outer sidewall 152, for example, the angle θ1 between the inner sidewall 152 and the outer sidewall θ2 of the first conductive portion 152 is 10 degrees or more greater, but the present invention is not limited thereto. In some embodiments, the included inner angle θ3 of the second conductive portion 154 is greater than the included outer angle θ4 of the second conductive portion 154. For example, the included inner angle θ3 of the second conductive portion 154 is 10 degrees or more greater than the included outer angle θ4 of the second conductive portion 154, but the present invention is not limited thereto. However, in other embodiments, the first conductive portion 152 and the second conductive portion 154 can be symmetrical structures, that is, the included inner angle θ1 of the first conductive portion 152 is the same as the included outer angle θ2, and the included inner angle θ3 of the second conductive portion 154 is the same as the included outer angle θ4, and the present invention is not limited thereto.

[0082] In some embodiments, the outer included angle θ2 of the first conductive portion 152 may be substantially the same as the outer included angle θ4 of the second conductive portion 154, that is, the included angles between the opposite sidewalls of the gate structure G and the second insulating layer 140 are approximately the same, but the present invention is not limited thereto. In other embodiments, the outer included angle θ2 of the first conductive portion 152 may be different from the outer included angle θ4 of the second conductive portion 154. In some embodiments, the inner included angle θ1 of the first conductive portion 152 may be substantially the same as the inner included angle θ3 of the second conductive portion 154, but the present invention is not limited thereto. In other embodiments, the inner included angle θ1 of the first conductive portion 152 may be different from the inner included angle θ3 of the second conductive portion 154.

[0083] In some embodiments, the first conductive layer 110 may be electrically connected to the gate structure G or the semiconductor layer 130 via a via (not shown). That is, the first conductive layer 110 may serve as another gate to jointly control the semiconductor device 10, but the present invention is not limited thereto. In other embodiments, the first conductive layer 110 may be floating.

[0084] An interlayer dielectric layer 160 is disposed on the second insulating layer 140 and covers the gate structure G. The source electrode S and drain electrode D are disposed on the interlayer dielectric layer 160 and penetrate the interlayer dielectric layer 160 and the second insulating layer 140 to be electrically connected to the first heavily doped region H1 and the second heavily doped region H2, respectively. The material of the interlayer dielectric layer 160 may include acrylic, siloxane, polyimide, epoxy resin, or other suitable materials, and this invention is not limited thereto. The interlayer dielectric layer 160 may have a single-layer structure or a multi-layer structure, and this invention is not limited thereto. The materials of the source electrode S and the drain electrode D may be metals or alloys, such as copper, aluminum, silver, gold, molybdenum, alloys of the above metals, or other suitable metals or alloys, and this invention is not limited thereto.

[0085] In some embodiments, the second width W2 of the second lightly doped region L2 near the drain D is greater than the first width W1 of the first lightly doped region L1 near the source S. Because the semiconductor device 10 has an asymmetric doping structure, compared to a semiconductor device of the same volume, the width of the second lightly doped region L2 near the drain D can be increased, providing more buffer at the drain D end to reduce potential damage to the semiconductor device 10 under high electric fields.

[0086] Figure 3 It is along Figure 1 A cross-sectional schematic diagram of a semiconductor device according to another embodiment, shown by section line A-A'. It must be noted here that... Figure 3 The embodiments follow Figure 1 and Figure 2 The component reference numerals and partial contents of the embodiments are described below, wherein the same or similar reference numerals are used to represent the same or similar components, and descriptions of the same technical content are omitted. For explanations of the omitted parts, please refer to the foregoing embodiments, and will not be repeated here.

[0087] Please refer to Figure 3The main difference between semiconductor device 10a and semiconductor device 10 is that the third conductive portion 162 of the gate structure G of semiconductor device 10a covers the outer wall 152b of the first conductive portion 152, and there is no lightly doped region between the first heavily doped region H1 and the first undoped region ch1 of semiconductor layer 130. That is, the first heavily doped region H1 is adjacent to the first undoped region ch1. The third conductive portion 162 of the gate structure G partially overlaps the first heavily doped region H1 in the normal direction N of the substrate 100. Since semiconductor layer 130 includes only the first heavily doped region H1 and no lightly doped region on one side of the channel region CH, and includes a second lightly doped region L2 and a second heavily doped region H2 on the other side of the channel region CH, the two sides of the channel region CH have an asymmetrical doping structure. Compared with a semiconductor device of the same volume, the width of the second lightly doped region L2 near the drain D can be increased, so that the drain D end has more buffer, thereby reducing the possible damage to semiconductor device 10a under the action of high electric field.

[0088] Figure 3 The diagram schematically illustrates that the sidewall 162b of the third conductive portion 162 is flush with the outer sidewall 154b of the second conductive portion 154, but this is not intended to limit the invention. In other embodiments, the sidewall 162b of the third conductive portion 162 may be recessed within the outer sidewall 154b of the second conductive portion 154.

[0089] Figure 4 It is along Figure 1 A cross-sectional schematic diagram of a semiconductor device according to another embodiment, shown by section line A-A'. It must be noted here that... Figure 4 The embodiments follow Figure 1 and Figure 2 The component reference numerals and partial contents of the embodiments are described below, wherein the same or similar reference numerals are used to represent the same or similar components, and descriptions of the same technical content are omitted. For explanations of the omitted parts, please refer to the foregoing embodiments, and will not be repeated here.

[0090] Please refer to Figure 4 The main difference between semiconductor device 10b and semiconductor device 10 is that the sidewalls 162a and 162b of the third conductive portion 162 of the gate structure G of semiconductor device 10b are recessed inward compared to the outer sidewall 152b of the first conductive portion 152 and the outer sidewall 154b of the second conductive portion 154, respectively. In other words, the top surface 152c of a portion of the first conductive portion 152 is not covered by the third conductive portion 162, and the top surface 154c of a portion of the second conductive portion 154 is not covered by the third conductive portion 162. Figure 4The diagram schematically illustrates that the sidewalls 162a and 162b of the third conductive portion 162 are recessed within the outer sidewall 152b of the first conductive portion 152 and the outer sidewall 154b of the second conductive portion 154, respectively, but this is not intended to limit the invention. The third conductive portion 162 may have only one sidewall recessed, while the other sidewall is flush with or covers the corresponding outer sidewall of the first conductive portion 152 or the second conductive portion 154.

[0091] Figure 5 This is a top view schematic diagram of a semiconductor device according to another embodiment of the present invention. Figure 6 It is along Figure 5 A cross-sectional schematic diagram of a semiconductor device according to an embodiment, shown by section line B-B'. It must be noted here that... Figure 5 and Figure 6 The embodiments follow Figure 1 and Figure 2 The component reference numerals and partial contents of the embodiments are described below, wherein the same or similar reference numerals are used to represent the same or similar components, and descriptions of the same technical content are omitted. For explanations of the omitted parts, please refer to the foregoing embodiments, and will not be repeated here.

[0092] Please refer to Figure 5 and Figure 6 The main difference between semiconductor device 20 and semiconductor device 10 is that the first conductive layer 110 of semiconductor device 20 includes a fourth conductive portion 112 and a fifth conductive portion 114 that are separated from each other. The fourth conductive portion 112 corresponds to the first conductive portion 152, and the fifth conductive portion 114 corresponds to the second conductive portion 154. In this embodiment, the fourth conductive portion 112 overlaps with the first undoped region ch1 and the first lightly doped region L1 in the normal direction N of the substrate 100, and the fifth conductive portion 114 overlaps with the second undoped region ch2 and the second lightly doped region L2 in the normal direction N of the substrate 100. However, the present invention is not limited thereto, as long as the first conductive layer 110 overlaps with the first undoped region ch1 and the second undoped region ch2 in the normal direction N of the substrate 100 and overlaps with at least one of the first lightly doped region L1 and the second lightly doped region L2.

[0093] Figure 7 This is a top view schematic diagram of a semiconductor device according to another embodiment of the present invention. Figure 8 It is along Figure 7 A cross-sectional schematic diagram of a semiconductor device according to an embodiment of the cross-section C-C'. Figure 9 This is a top view schematic diagram of a semiconductor device according to another embodiment of the present invention, wherein along Figure 9 Schematic diagram of section line C-C' and Figure 8 Similar, can be used as a reference Figure 8 Please understand this. It must be noted here that... Figures 7 to 9 The embodiments follow Figure 1 and Figure 2 The component reference numerals and partial contents of the embodiments are described below, wherein the same or similar reference numerals are used to represent the same or similar components, and descriptions of the same technical content are omitted. For explanations of the omitted parts, please refer to the foregoing embodiments, and will not be repeated here.

[0094] Please refer to Figure 7 and Figure 8 The main difference between semiconductor device 30 and semiconductor device 10 is that the gate structure G of semiconductor device 30 includes a first conductive portion 152, a second conductive portion 154, and a conductive extension portion 156. The first conductive portion 152 and the second conductive portion 154 are disposed on the second insulating layer 140 and are separated from each other. The width of the first conductive portion 152 and the width of the second conductive portion 154 may be the same or different, and this invention is not limited thereto. The conductive extension portion 156 is disposed on the second insulating layer 140 and connects the first conductive portion 152 and the second conductive portion 154. The first conductive portion 152, the second conductive portion 154, and the conductive extension portion 156 are made of the same film layer, and the material of the conductive extension portion 156 may be the same as that of the first conductive portion 152 and the second conductive portion 154. Figure 7 In the design, the gate structure G is U-shaped. The conductive extension 156 does not overlap with the semiconductor layer 130 in the normal direction N of the substrate 100, and the gate structure G does not overlap with the channel doped region ch3 in the normal direction N of the substrate 100.

[0095] Figure 8 Although the diagram shows a first lightly doped region L1 and a second lightly doped region L2 on both sides of the channel region CH, it is not intended to limit the present invention. Figure 8 The two sides of the channel region CH can also be similar Figure 3 In one embodiment, only one side has a lightly doped region adjacent to the channel region, while the other side has a heavily doped region adjacent to the channel region.

[0096] Please refer to Figure 9 The main difference between semiconductor device 30a and semiconductor device 30 is that the gate structure G of semiconductor device 30a includes a first conductive portion 152 and a second conductive portion 154, but does not include a conductive extension portion. That is, the gate structure G of semiconductor device 30a has two separate and parallel first conductive portions 152 and second conductive portions 154.

[0097] Figure 10 This is a top view schematic diagram of a semiconductor device according to another embodiment of the present invention. Figure 11 It is along Figure 10 A cross-sectional schematic diagram of a semiconductor device according to an embodiment, with section line D-D'. It must be noted here that... Figures 10 to 11 The embodiments follow Figure 5 and Figure 7 The component reference numerals and partial contents of the embodiments are described below, wherein the same or similar reference numerals are used to represent the same or similar components, and descriptions of the same technical content are omitted. For explanations of the omitted parts, please refer to the foregoing embodiments, and will not be repeated here.

[0098] Please refer to Figure 10 and Figure 11 The main difference between semiconductor device 40 and semiconductor device 30 is that the first conductive layer 110 of semiconductor device 40 includes a fourth conductive portion 112 and a fifth conductive portion 114 that are separated from each other. The fourth conductive portion 112 corresponds to the first conductive portion 152, and the fifth conductive portion 114 corresponds to the second conductive portion 154. In this embodiment, the fourth conductive portion 112 overlaps with the first undoped region ch1 and the first lightly doped region L1 in the normal direction N of the substrate 100, and the fifth conductive portion 114 overlaps with the second undoped region ch2 and the second lightly doped region L2 in the normal direction N of the substrate 100. However, the present invention is not limited thereto, as long as the first conductive layer 110 overlaps with the first undoped region ch1 and the second undoped region ch2 in the normal direction N of the substrate 100 and overlaps with at least one of the first lightly doped region L1 and the second lightly doped region L2.

[0099] Figure 10 Although the diagram illustrates a gate structure G including a first conductive portion 152, a second conductive portion 154, and a conductive extension portion 156, it is not intended to limit the invention. The gate structure G may also be similar to... Figure 9 The embodiment includes only the first conductive portion 152 and the second conductive portion 154.

[0100] Figure 12 This is a top view schematic diagram of a semiconductor device according to another embodiment of the present invention. Figure 13 It is along Figure 12 A cross-sectional schematic diagram of a semiconductor device according to an embodiment, shown along section line E-E'. It must be noted here that... Figure 12 and Figure 13 The embodiments follow Figure 1 and Figure 2 The component reference numerals and partial contents of the embodiments are described below, wherein the same or similar reference numerals are used to represent the same or similar components, and descriptions of the same technical content are omitted. For explanations of the omitted parts, please refer to the foregoing embodiments, and will not be repeated here.

[0101] Please refer to Figure 12 and Figure 13The main difference between semiconductor device 50 and semiconductor device 10 is that semiconductor device 50 includes a substrate 100, a semiconductor layer 130, a gate structure G, a second insulating layer 140, an interlayer dielectric layer 160, a source electrode S, and a drain electrode D, but does not include... Figure 2 The first conductive layer 110 and the first insulating layer 120. Figure 13 The semiconductor device 50 is illustrated only schematically; its gate structure G and semiconductor layer 130 can be adjusted according to actual needs with reference to the foregoing embodiments. In some embodiments, the semiconductor device 50 may further include a buffer layer (not shown) disposed between the substrate 100 and the semiconductor layer 130. The material of the buffer layer may include silicon nitride, silicon oxide, silicon oxynitride, or other suitable materials or stacked layers of the above materials, and the present invention is not limited thereto.

[0102] Figure 14 This is a top view schematic diagram of a semiconductor device according to another embodiment of the present invention. Figure 15 It is along Figure 14 A cross-sectional schematic diagram of a semiconductor device according to an embodiment, shown by section line F-F'. It must be noted here that... Figure 14 and Figure 15 The embodiments follow Figure 7 and Figure 8 The component reference numerals and partial contents of the embodiments are described below, wherein the same or similar reference numerals are used to represent the same or similar components, and descriptions of the same technical content are omitted. For explanations of the omitted parts, please refer to the foregoing embodiments, and will not be repeated here.

[0103] Please refer to Figure 14 and Figure 15 The main difference between semiconductor device 60 and semiconductor device 30 is that semiconductor device 60 includes a substrate 100, a semiconductor layer 130, a gate structure G, a second insulating layer 140, an interlayer dielectric layer 160, a source electrode S, and a drain electrode D, but does not include... Figure 8 The first conductive layer 110 and the first insulating layer 120. Figure 15 The semiconductor device 60 is illustrated only schematically; its gate structure G and semiconductor layer 130 may be adjusted according to actual needs in the foregoing embodiments. In some embodiments, the semiconductor device 60 may further include a buffer layer (not shown) disposed between the substrate 100 and the semiconductor layer 130. The material of the buffer layer may include silicon nitride, silicon oxide, silicon oxynitride, or other suitable materials or stacked layers of the above materials, and the present invention is not limited thereto.

[0104] Figures 16A to 16D This is a cross-sectional schematic diagram of the manufacturing process of a semiconductor device according to an embodiment of the present invention. It should be noted that... Figure 16A and Figure 16D The embodiments follow Figure 2The component reference numerals and partial contents of the embodiments are described below, wherein the same or similar reference numerals are used to represent the same or similar components, and descriptions of the same technical content are omitted. For explanations of the omitted parts, please refer to the foregoing embodiments, and will not be repeated here.

[0105] Please refer to Figure 16A A substrate 100 is provided, a first conductive layer 110 is formed on the substrate 100, and then a first insulating layer 120 is formed on the substrate 100 and covers the first conductive layer 110. Subsequently, a semiconductor layer 130 and a second insulating layer 140 are sequentially formed on the first insulating layer 120. In some embodiments, a buffer layer (not shown) may be formed on the substrate 100 before forming the first conductive layer 110.

[0106] Please refer to Figure 16B An initial first conductive portion 152' and an initial second conductive portion 154' are formed on the second insulating layer 140. For example, the initial first conductive portion 152' and the initial second conductive portion 154' can be formed in the same process by photolithography etching. In this embodiment, the initial first conductive portion 152' and the initial second conductive portion 154' are not connected, and the shortest distance between them can be less than 2 μm. Then, using the initial first conductive portion 152' and the initial second conductive portion 154' as a mask, a doping process P1 is performed on the semiconductor layer 130 to form a first heavily doped region H1, a channel doped region ch3, and a second heavily doped region H2 in the portion of the substrate 100 that does not overlap with the initial first conductive portion 152' and the initial second conductive portion 154' in the normal direction N of the substrate 100.

[0107] Please refer to Figure 16C A gate structure G comprising a first conductive portion 152, a second conductive portion 154, and a third conductive portion 162 is formed. For example, a conductive material layer (not shown) can be first formed on the second insulating layer 140, the initial first conductive portion 152', and the initial second conductive portion 154'. Then, a patterned photoresist PR is formed on the conductive material layer, and then, using the patterned photoresist PR as a mask, the third conductive portion 162 is formed through a photolithography etching process. The patterned photoresist PR can define the position of the third conductive portion 162, thereby defining the range of the subsequently formed lightly doped region. In this embodiment, the patterned photoresist PR overlaps more with the first conductive portion 152 in the normal direction N of the substrate 100 than the second conductive portion 154, so as to subsequently form a first lightly doped region L1 and a second lightly doped region L2 (shown in the diagram) with different widths. Figure 16DHowever, this invention is not limited thereto, and the position of the patterned photoresist PR can be adjusted according to actual needs. In other embodiments, the patterned photoresist PR can completely overlap the initial first conductive portion 152' and partially overlap the initial second conductive portion 154' in the normal direction N of the substrate 100, so as to facilitate the subsequent formation of a structure similar to... Figure 3 The semiconductor layer 130 comprises only a lightly doped region. In some embodiments, during the etching of the conductive material layer to form the third conductive portion 162, the initial first conductive portion 152' and the initial second conductive portion 154' may be etched simultaneously to form the first conductive portion 152 and the second conductive portion 154, but this invention is not limited thereto. Since the first conductive portion 152 and the second conductive portion 154 are formed by two etching operations, the width of the gate structure G can be finely adjusted, and the angle of the inner included angle θ1 of the first conductive portion 152 can be different from the angle of the outer included angle θ2 of the first conductive portion 152, and the angle of the inner included angle θ3 of the second conductive portion 154 can be different from the angle of the outer included angle θ4 of the second conductive portion 154.

[0108] In other embodiments, the photoresist PR and the third conductive portion 162 can be patterned as a mask to etch the initial first conductive portion 152' and the initial second conductive portion 154' to form the first conductive portion 152 and the second conductive portion 154.

[0109] In some embodiments, after the first conductive portion 152 and the second conductive portion 154 are substantially formed, the patterned photoresist PR can be simultaneously etched with the first conductive portion 152, the second conductive portion 154 and the third conductive portion 162 using a suitable etching gas to adjust the morphology of the gate structure G.

[0110] Please refer to Figure 16D The patterned photoresist PR is removed, and then, using the gate structure G as a mask, a doping process P2 is performed on the semiconductor layer 130 to form a first lightly doped region L1 and a second lightly doped region L2 in the undoped portion of the substrate 100 that does not overlap with the gate structure G in the normal direction N. Since the portions of the semiconductor layer 130 that overlap with the first conductive portion 152 and the second conductive portion 154 in the normal direction N of the substrate 100 are not doped by doping processes P1 and P2, they constitute the first undoped region ch1 and the second undoped region ch2.

[0111] Afterwards, you can refer to Figure 2An interlayer dielectric layer 160 is formed on the second insulating layer 140 and covers the gate structure G. Subsequently, vias (not shown) are formed through the interlayer dielectric layer 160 and the second insulating layer 140 to expose portions of the surfaces of the first heavily doped region H1 and the second heavily doped region H2, respectively. Then, a conductive material layer (not shown) is formed on the interlayer dielectric layer 160 and in the vias, and the conductive material layer is patterned to form the source S and drain D.

[0112] Through the above manufacturing process, the semiconductor device 10 can be roughly manufactured.

[0113] Figures 17A to 17C This is a cross-sectional schematic diagram illustrating the manufacturing process of a semiconductor device according to an embodiment of the present invention. It should be noted that... Figure 17A and Figure 17C The embodiments follow Figure 8 , Figures 16A to 17C The component reference numerals and partial contents of the embodiments are described below, wherein the same or similar reference numerals are used to represent the same or similar components, and descriptions of the same technical content are omitted. For explanations of the omitted parts, please refer to the foregoing embodiments, and will not be repeated here.

[0114] Figure 17A It can be a continuation Figure 16B The manufacturing process. In some embodiments, during the formation of the initial first conductive portion 152' and the initial second conductive portion 154' on the second insulating layer 140, a conductive extension structure 156 (marked as shown in the figure) may be formed simultaneously. Figure 7 ).

[0115] Please refer to Figure 17A A patterned photoresist PR is formed on the second insulating layer 140, the initial first conductive portion 152', and the initial second conductive portion 154'. The patterned photoresist PR defines the positions of the subsequently formed first and second conductive portions, thereby determining the doping range of the subsequently formed first or second lightly doped regions. In this embodiment, the patterned photoresist PR overlaps more with the initial first conductive portion 152' in the normal direction N of the substrate 100 than the initial second conductive portion 154', so as to subsequently form first lightly doped regions L1 and second lightly doped regions L2 with different widths (illustrated in...). Figure 17C However, this invention is not limited thereto, and the position of the patterned photoresist PR can be adjusted according to actual needs. In other embodiments, the patterned photoresist PR can completely overlap the initial first conductive portion 152' and partially overlap the initial second conductive portion 154' in the normal direction N of the substrate 100, so as to facilitate the subsequent formation of a structure similar to... Figure 3 The semiconductor layer 130 consists of only a lightly doped region.

[0116] Please refer to Figure 17B Using a patterned photoresist PR as a mask, the initial first conductive portion 152' and the initial second conductive portion 154' are etched to form a gate structure G including the first conductive portion 152 and the second conductive portion 154. In some embodiments, after the first conductive portion 152 and the second conductive portion 154 are substantially formed, the patterned photoresist PR can be simultaneously etched with the first conductive portion 152 and the second conductive portion 154 using a suitable etching gas to adjust the morphology of the gate structure G.

[0117] Please refer to Figure 17C The patterned photoresist PR is removed, and then, using the first conductive portion 152 and the second conductive portion 154 as masks, a doping process P2 is performed on the semiconductor layer 130 to form a first lightly doped region L1 and a second lightly doped region L2 in the undoped portion that does not overlap with the first conductive portion 152 and the second conductive portion 154 in the normal direction N of the substrate 100. Since the portion of the semiconductor layer 130 that overlaps with the first conductive portion 152 and the second conductive portion 154 in the normal direction N of the substrate 100 is not doped by the doping processes P1 and P2, it constitutes the first undoped region ch1 and the second undoped region ch2.

[0118] Afterwards, you can refer to Figure 8 An interlayer dielectric layer 160 is formed on the second insulating layer 140, covering the first conductive portion 152 and the second conductive portion 154. Subsequently, vias (not shown) are formed through the interlayer dielectric layer 160 and the second insulating layer 140 to expose portions of the surfaces of the first heavily doped region H1 and the second heavily doped region H2, respectively. Afterward, a conductive material layer (not shown) is formed on the interlayer dielectric layer 160 and in the vias, and the conductive material layer is then patterned to form the source electrode S and the drain electrode D.

[0119] Through the above manufacturing process, the semiconductor device 30 can be roughly manufactured.

[0120] In summary, the semiconductor device of the present invention has an asymmetric doping structure on both sides of the channel region. Compared with a semiconductor device of the same volume, it can increase the width of the second lightly doped region near the drain, thereby providing more buffer at the drain end and reducing the possible damage to the semiconductor device under the action of a high electric field.

Claims

1. A semiconductor device, comprising: substrate; A gate structure is disposed on the substrate; A semiconductor layer is disposed between the substrate and the gate structure, wherein the semiconductor layer includes: The channel region overlaps the gate structure in the normal direction of the substrate; The first doped region and the second doped region are located on opposite sides of the channel region, respectively; and At least one lightly doped region is located between the first heavily doped region and the channel region or between the second heavily doped region and the channel region, to form an asymmetric doping structure on both sides of the channel region; and A second insulating layer is disposed on the semiconductor layer and located between the semiconductor layer and the gate structure. The gate structure includes: The first conductive portion and the second conductive portion are separated from each other, wherein the channel region includes a first undoped region overlapping the first conductive portion in the normal direction of the substrate, a second undoped region overlapping the second conductive portion in the normal direction of the substrate, and a channel doped region located between the first undoped region and the second undoped region, wherein the channel doped region is a heavily doped region. The width of the first conductive portion is greater than the width of the second conductive portion, such that the width of the first undoped region is greater than the width of the second undoped region.

2. The semiconductor device of claim 1, wherein the gate structure further comprises: A third conductive portion is disposed on the first conductive portion and the second conductive portion to electrically connect the first conductive portion and the second conductive portion.

3. The semiconductor device of claim 2, wherein the channel doped region and the third conductive portion partially overlap in the normal direction of the substrate.

4. The semiconductor device of claim 1, wherein the gate structure further comprises: A conductive extension portion is disposed on the second insulating layer and connects the first conductive portion and the second conductive portion, wherein the conductive extension portion does not overlap with the semiconductor layer in the normal direction of the substrate.

5. The semiconductor device of claim 1, further comprising: A first conductive layer is disposed on the substrate; as well as A first insulating layer is disposed on the first conductive layer. The projected area of ​​the first conductive layer on the substrate is larger than the projected area of ​​the gate structure on the substrate.

6. The semiconductor device of claim 5, wherein the first conductive layer partially overlaps the at least one lightly doped region in the normal direction of the substrate.

7. The semiconductor device of claim 5, wherein the at least one lightly doped region comprises: The first lightly doped region is located between the first heavily doped region and the channel region; as well as The second lightly doped region is located between the second heavily doped region and the channel region, wherein the width of the first lightly doped region is different from the width of the second lightly doped region.

8. The semiconductor device of claim 7, wherein the width of the first lightly doped region is smaller than the width of the second lightly doped region.

9. The semiconductor device of claim 7, further comprising: The source electrode is electrically connected to the first heavily doped region. as well as The drain is electrically connected to the second heavily doped region, wherein the width of the second lightly doped region is greater than the width of the first lightly doped region.

10. The semiconductor device of claim 7, wherein: The first conductive layer includes a fourth conductive portion and a fifth conductive portion that are separated from each other. The fourth conductive portion corresponds to the first conductive portion and overlaps with the first conductive portion and the first lightly doped region in the normal direction of the substrate. The fifth conductive portion corresponds to the second conductive portion and overlaps with the second conductive portion and the second lightly doped region in the normal direction of the substrate.

11. The semiconductor device of claim 1, wherein the angle of the outer included angle of the first conductive portion is different from the angle of the inner included angle of the first conductive portion.

12. The semiconductor device of claim 11, wherein the angle of the inner included angle of the first conductive portion is greater than the angle of the outer included angle of the first conductive portion.

13. A semiconductor device, comprising: substrate; A semiconductor layer is disposed on the substrate, wherein the semiconductor layer includes a channel region, the channel region including: First undoped region; The second undoped region; and The channel doped region is located between the first undoped region and the second undoped region; A gate structure is disposed on the semiconductor layer, wherein the gate structure includes: The first conductive portion overlaps the first undoped region in the normal direction of the substrate; The second conductive portion overlaps the second undoped region in the normal direction of the substrate; and A third conductive portion is disposed on the first conductive portion and the second conductive portion and partially overlaps the channel doped region in the normal direction of the substrate, wherein the first conductive portion and the second conductive portion are separated from each other, and the third conductive portion is electrically connected to the first conductive portion and the second conductive portion; and A second insulating layer is disposed on the semiconductor layer and located between the semiconductor layer and the gate structure. The channel doped region is a heavily doped region, and the width of the first conductive portion is greater than the width of the second conductive portion, so that the width of the first undoped region is greater than the width of the second undoped region.

14. The semiconductor device of claim 13, wherein the semiconductor layer further comprises: The first doped region and the second doped region are located on both sides of the channel region, respectively; as well as At least one lightly doped region is located between the first heavily doped region and the channel region, or between the second heavily doped region and the channel region. The at least one lightly doped region includes: The first lightly doped region is located between the first heavily doped region and the channel region; as well as The second lightly doped region is located between the second heavily doped region and the channel region. The width of the first lightly doped region is smaller than the width of the second lightly doped region.

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