Pulse modulation method, transmission control device and computing equipment based on three-level converter

Abstract

The present application discloses a pulse modulation method, apparatus, and computing device for a three-level converter. The method includes: normalizing a vector space to generate a normalized sector; converting a target vector into a corresponding vector within the normalized sector, recorded as a normalized vector; selecting a reference vector on a reference circle with the same angle as the normalized vector to calculate the action time of a basic vector for synthesizing the reference vector; obtaining the action time of the basic vector and a zero vector when synthesizing the normalized vector according to the step-down chopping law; performing a vector transformation operation to obtain the three most recent basic vectors and their action times of the normalized vector; composing the basic vectors and action times corresponding to the normalized vector into a switching timing diagram of the normalized vector according to a vector switching sequence; and converting the switching timing diagram of the normalized vector into a switching timing diagram of the target vector based on the corresponding relationship between the components of the normalized vector and the target vector on the coordinate axis. This method reduces the response time of the three-level converter and improves the efficiency of controlling the switching of switching devices.

Description

Technical Field

[0001] The present application relates to the field of power electronics technology, and in particular to a pulse modulation method, apparatus, and computing device based on a three-level converter. Background Art

[0002] Multilevel converters are widely used in high-power, high-voltage applications. Compared to two-level converters, three-level converters offer lower output current and voltage harmonics, higher voltage resistance for switching devices, better output waveform quality, and lower common-mode voltage. For two-level converter control, the SVPWM (space vector pulse width modulation) modulation algorithm has reached maturity.

[0003] In space vector modulation (SVM) of three-level converters, the traditional α-β coordinate system, GH coordinate system, KL coordinate system, and virtual coordinate system are currently used to control the switching devices. Due to the high computational complexity, traditional control algorithms cannot respond quickly when processing SVM.

[0004] However, for the control of three-level converters, the application of the existing simplified SVPWM algorithm still requires a large amount of calculation. Summary of the Invention

[0005] Embodiments of the present application provide a pulse modulation method, a computing device, and a storage medium based on a three-level converter, which reduce the time consumption of space vector modulation in the control of the three-level converter.

[0006] A pulse modulation method based on a three-level converter, comprising:

[0007] Normalize the vector space to generate a normalized sector;

[0008] Convert the target vector into the corresponding vector in the normalized sector, recorded as the normalized vector;

[0009] Select a reference vector on the reference circle with the same angle as the normalized vector, and calculate the action time of the basic vector of the synthetic reference vector;

[0010] According to the buck chopping law, when obtaining the synthetic normalized vector, the basic vector corresponding to the reference vector and the action time of the zero vector are used. When performing vector transformation operations, the three most recent basic vectors and their action times are obtained when obtaining the synthetic normalized vector. According to the vector switching sequence, the basic vectors corresponding to the normalized vector and their action times are combined to form its switching state timing diagram.

[0011] According to the corresponding relationship between the components of the normalized vector and the target vector on the coordinate axis, the switching state timing diagram of the normalized vector is converted into the timing diagram of the target vector.

[0012] Preferably, the normalized sector is specifically a 30° sector, which is specifically implemented as follows:

[0013] Starting from 0° and at intervals of 30°, the entire vector space can be divided into 12 sectors.

[0014] Preferably, it also includes:

[0015] Construct a reference vector, including:

[0016] The inscribed circle of the vector space is taken as the reference circle, and the vector whose end point is on the reference circle is taken as the reference vector.

[0017] Preferably, the method further comprises:

[0018] According to the volt-second balance formula, the action time of the basic vector corresponding to the synthesized reference vector is obtained.

[0019] Preferably, the method further comprises:

[0020] The time of the intermediate state in the switch state timing diagram is obtained by the relationship between the vectors in the space vector diagram, specifically:

[0021] Combined with the operation rules of the step-down chopper, when the synthetic normalized vector is obtained by chopping the spatial state vector diagram of the reference vector, the action time of the basic vector and the zero vector corresponding to the reference vector;

[0022] Combined with vector operations, the three most recent basic vectors and their action times are obtained when the synthetic normalized vector is obtained.

[0023] According to the vector switching sequence, the switching state timing diagram of the normalized vector is determined.

[0024] A pulse modulation control device based on a three-level converter, comprising:

[0025] A normalization unit, used to normalize the vector space and generate a normalized sector;

[0026] a conversion unit, configured to convert the target vector into a corresponding vector within the normalized sector, recorded as a normalized vector;

[0027] A selection unit is used to select a reference vector having the same angle as the normalized vector and calculate the action time of the basic vector for synthesizing the reference vector;

[0028] The vector transformation operation unit obtains the basic vector and the action time of the zero vector corresponding to the reference vector when obtaining the synthetic normalized vector according to the step-down chopping law; performs vector transformation operation to obtain the three most recent basic vectors and the action time of the synthetic normalized vector;

[0029] The timing diagram construction unit composes the basic vectors and action times corresponding to the normalized vectors into a switching state timing diagram according to the vector switching sequence.

[0030] The inverse conversion unit converts the switching state timing diagram of the normalized vector into the timing diagram of the target vector according to the corresponding relationship between the components of the normalized vector and the target vector on the coordinate axis.

[0031] Preferably, the normalization unit is specifically implemented as follows:

[0032] Starting from 0° and at intervals of 30°, the entire vector space can be divided into 12 sectors.

[0033] Preferably, the device further includes: a time calculation unit, which is specifically implemented as follows:

[0034] According to the volt-second balance formula, the action time of the basic vector corresponding to the synthesized reference vector is obtained.

[0035] Preferably, the device further comprises: an intermediate state calculation unit, which obtains the time of the intermediate state in the switch state timing diagram through the relationship between the vectors in the space vector diagram, which is specifically implemented as follows:

[0036] Combined with the operation rules of the step-down chopper, when the reference vector is chopped to obtain the synthetic normalized vector, the action time of the basic vector and the zero vector corresponding to the reference vector;

[0037] Combined with vector operations, the three most recent basic vectors corresponding to the normalized vector and their action times are obtained.

[0038] According to the vector action sequence, the switching state timing diagram of the normalized vector is determined.

[0039] A computing device comprising:

[0040] at least one processor; and

[0041] a memory communicatively connected to the at least one processor; wherein,

[0042] The memory stores instructions that can be executed by the at least one processor. The instructions are executed by the at least one processor to enable the at least one processor to perform the above method.

[0043] The pulse modulation method based on a three-level converter of the present invention normalizes the vector space to generate a normalized sector; converts a target vector into a corresponding vector within the normalized sector; selects a reference vector having the same angle as the target vector, wherein multiple reference vectors are selected; performs a vector transformation operation on the reference vector and a zero vector whose action time can be a negative number to obtain a basic vector corresponding to the reference vector; normalizes the entire vector space into a 30-degree sector, and proposes a universal three-level space vector pulse width modulation algorithm in combination with the operation rules of a step-down chopper to reduce the response time of the three-level converter and improve the on-off efficiency of the control switching device. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0045] Figure 1 A schematic diagram of a pulse modulation scenario based on a three-level converter in the prior art;

[0046] Figure 2 Schematic diagram of a flow chart of a pulse modulation method based on a three-level converter in an embodiment of the present application;

[0047] Figure 3 Schematic diagram of a flow chart of a pulse modulation method based on a three-level converter in an embodiment of the present application;

[0048] Figure 4 Schematic diagram of vector construction of a pulse modulation method based on a three-level converter in an embodiment of the present application;

[0049] Figure 5 Schematic diagram of a flow chart of a pulse modulation method based on a three-level converter in an embodiment of the present application;

[0050] Figure 6 Schematic diagram of a pulse modulation control device based on a three-level converter in an embodiment of the present application;

[0051] Figure 7 This is a schematic diagram of the structure of a computer-readable medium in an embodiment of the present application;

[0052] Figure 8 This is a schematic diagram of the structure of a computing device based on the implementation method of the present application in an embodiment of the present application. DETAILED DESCRIPTION

[0053] The embodiments of the present application provide a pulse modulation method, a computing device, and a storage medium based on a three-level converter, which reduce the modulation time of the three-level converter and improve the on-off efficiency of the control switching device.

[0054] To address the shortcomings of existing algorithms, this patent aims to reduce the response time of three-level converters. By normalizing the entire vector space into 30° sectors and combining the concepts of a DC / DC step-down chopper, a general three-level space vector pulse width modulation (SVPWM) algorithm is proposed, which is particularly suitable for the switching control speed requirements of three-level converters.

[0055] The following is combined with the reference Figure 1 The pulse modulation method based on the three-level converter provided in the embodiment of the present application is further described.

[0056] S11: Normalize the vector space to generate a normalized sector;

[0057] Preferably, the normalized sector is specifically a 30° sector, which is specifically implemented as follows:

[0058] Starting from 0° and at intervals of 30°, the entire vector space can be divided into 12 sectors.

[0059] The entire vector space is normalized into a 30° sector, and the target vector is converted into the corresponding vector within the normalized sector, which greatly reduces the spatial complexity of space vector modulation.

[0060] The vector space can be divided into 12 sectors at intervals of 30°. The vector space is normalized to the standardized 30° sector, i.e. sector 0.

[0061] As an example, the present invention is particularly applicable to the switch control requirements of a three-level converter. For a reference vector, three basic vectors corresponding to the reference vector are synthesized.

[0062] S12: Convert the target vector into a corresponding vector in the normalized sector, recorded as a normalized vector;

[0063] For the entire space vector diagram, a vector at any angle can be converted to a vector within sector 0 by the following formula to obtain a normalized vector:

[0064] Where: α is the target vector in the space vector The angle of θ is the normalized vector Angle;

[0065] S13: When obtaining a synthetic normalized vector according to the step-down chopping rule, the action time of the basic vector and the zero vector corresponding to the reference vector includes:

[0066] The inscribed circle of the vector space is taken as the reference circle, and the vector whose end point is on the reference circle is taken as the reference vector.

[0067] Referring to the concept of “DC chopping voltage regulation”, the action time of the basic vector corresponding to the normalized vector is obtained based on the reference vector, which reduces the time complexity of space vector modulation. When the modulus is smaller than the radius of the reference circle, based on the chopping concept, the equivalent switching state timing diagram of the vector in sector 0 can be obtained by superimposing a high-frequency PWM wave on the switching state timing diagram of its corresponding reference vector.

[0068] When the PWM wave is high, the vector The equivalent switching state of the target vector is the same as the reference vector; when the PWM wave is low, the three-phase equivalent switching states of the target vector are all 0, which is equivalent to the zero vector.

[0069] S14: performing vector transformation operation to obtain the three most recent basic vectors and the action time when the synthetic normalized vector is obtained;

[0070] The zero vector whose action time can be negative is introduced. The action time T of zero, small, medium and large basic vectors is obtained by chopping the spatial state vector diagram of the reference vector. z 、T s 、T m 、T l .

[0071] As one of the calculation methods, the T z 、T s 、T m 、T l The calculation method can be as follows:

[0072]

[0073] Where m is the ratio of the modulus of the normalized vector and the reference vector.

[0074] By means of vector conversion, the four basic vectors are converted into basic vectors whose three vectors corresponding to the normalized vector are closest to each other.

[0075] Based on the relationship between the action times of large, medium, small, and zero basic vectors, the four basic vectors are divided into three cases. Combined with vector operations, these four basic vectors are converted into the three closest basic vectors. S15: According to the vector switching sequence, the basic vectors and action times corresponding to the normalized vector are combined to form the switching state timing diagram of the normalized vector.

[0076] Among them, the switch state timing diagram is determined by its shape and the time of the intermediate state: the shape of the seven-segment switch state timing diagram can be divided into four categories.

[0077] S16: According to the corresponding relationship between the components of the normalized vector and the target vector on the coordinate axis, the switching state timing diagram of the normalized vector is converted into the timing diagram of the target vector.

[0078] refer to Figure 2 , the method further comprises:

[0079] S21: According to the volt-second balance formula, the action time of synthesizing the reference vector corresponding to the basic vector is obtained;

[0080] Find The reference vector with the same angle is used to synthesize the three basic vectors corresponding to the reference vector, and the action time T 01_r 、T 12_r 、T 1_r value.

[0081] The zero vector whose action time can be negative is introduced. The action time T of zero, small, medium and large basic vectors is obtained by chopping the spatial state vector diagram of the reference vector. z 、T s 、T m 、T l .

[0082] The switch state timing diagram is determined by its shape and the time of the intermediate state: the shape of the seven-segment switch state timing diagram can be divided into four categories.

[0083] according to and And the corresponding relationship between the components on the abc axis, The corresponding seven-segment switch state timing diagram is converted to Timing diagram of .

[0084] refer to Figure 3 , the more specific method also includes:

[0085] The time of the intermediate state in the switch state timing diagram is obtained by the relationship between the vectors in the space vector diagram, specifically:

[0086] S31: When a synthetic normalized vector is obtained by chopping the reference vector in accordance with the operation rule of the step-down chopper, the action time of the basic vector and the zero vector corresponding to the reference vector;

[0087] S32: Combine vector operations to obtain the three most recent basic vectors corresponding to the normalized vector and their action times;

[0088] S33: Determine a switching state timing diagram of the normalized vector according to the vector switching sequence.

[0089] refer to Figure 4 , showing the relationship between the reference circle, reference vector and target vector.

[0090] Figure 5 A pulse modulation control device based on a three-level converter is shown, comprising:

[0091] A normalization unit 51 is used to normalize the vector space to generate a normalized sector;

[0092] A conversion unit 52 is used to convert the target vector into a corresponding vector in the normalized sector, which is recorded as a normalized vector;

[0093] A selection unit 53 is used to select a reference vector having the same angle as the normalized vector and calculate the action time of the basic vector of the synthesized reference vector;

[0094] The vector conversion operation unit 54, in combination with the operation rules of the step-down chopper, obtains the basic vector and the zero vector corresponding to the reference vector when the synthetic normalized vector is obtained by chopping the reference vector; and obtains the nearest three basic vectors corresponding to the normalized vector and their action times by combining vector operations.

[0095] The timing diagram constructing unit 55 composes the basic vectors and the action time corresponding to the normalized vector into a switching state timing diagram of the normalized vector according to the vector switching sequence.

[0096] The inverse conversion unit 56 converts the switching state timing diagram of the normalized vector into the switching state timing diagram of the target vector according to the corresponding relationship between the components of the normalized vector and the target vector on the coordinate axis.

[0097] Figure 6 ,exist Figure 5 On the basis of the above, the device further includes: a time calculation unit 61, which is specifically implemented as follows:

[0098] According to the volt-second balance formula, the action time of the basic vector corresponding to the synthesized reference vector is obtained.

[0099] Preferably, the device further includes: an intermediate state calculation unit 62, which obtains the time of the intermediate state in the switch state timing diagram through the relationship between the vectors in the space vector diagram, which is specifically implemented as follows:

[0100] Combined with the operation rules of the step-down chopper, when the reference vector is chopped to obtain the synthetic normalized vector, the action time of the basic vector and the zero vector corresponding to the reference vector;

[0101] Combined with vector operations, the three most recent basic vectors corresponding to the normalized vector and their action times are obtained.

[0102] According to the vector switching sequence, the intermediate state time of the switch state timing diagram is determined.

[0103] The method of the present invention can also be implemented by computer readable medium 71, referring to Figure 7, stores computer executable instructions, namely, program instructions corresponding to the method of the present invention, and the computer executable instructions are used to execute the method described in the above embodiment.

[0104] A readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, which carries readable program code. Such propagated data signals may take a variety of forms, including, but not limited to, electromagnetic signals, optical signals, or any suitable combination thereof. A readable signal medium may also be any readable medium other than a readable storage medium that can transmit, propagate, or transfer a program for use by or in conjunction with an instruction execution system, apparatus, or device.

[0105] Program code embodied on a readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.

[0106] The program code for performing the operations of the present application can be written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java, C++, etc., and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code can be executed entirely on the user computing device, partially on the user device, as a separate software package, partially on the user computing device and partially on a remote computing device, or entirely on a remote computing device or server. In the case of a remote computing device, the remote computing device can be connected to the user computing device through any type of network, including a local area network (LAN) or a wide area network (WAN), or can be connected to an external computing device (e.g., via the Internet using an Internet service provider).

[0107] The present invention also discloses a computing device, which is described below with reference to Figure 8 80 according to this embodiment of the present application. Figure 8 The computing device 80 shown is only an example and should not limit the functionality and scope of use of the embodiments of the present application.

[0108] like Figure 8 As shown, the computing device 80 is a general-purpose computing device. Components of the computing device 80 may include, but are not limited to, at least one processor 81, at least one memory 82, and a bus 83 connecting different system components (including the memory 82 and the processor 81).

[0109] Bus 83 represents one or more of several types of bus structures, including a memory bus or memory controller, a peripheral bus, and a processor or local bus using any of a variety of bus architectures.

[0110] The memory 82 may include a readable medium in the form of a volatile memory, such as a random access memory (RAM) 821 and / or a cache memory 822 , and may further include a read-only memory (ROM) 823 .

[0111] The memory 82 may also include a program / utility 825 having a set (at least one) of program modules 824, such program modules 824 including but not limited to: an operating system, one or more application programs, other program modules, and program data, each of which or some combination may include an implementation of a network environment.

[0112] Computing device 80 may also communicate with one or more external devices 84 (e.g., a keyboard, pointing device, etc.), one or more devices that enable a user to interact with computing device 80, and / or any device that enables computing device 80 to communicate with one or more other computing devices (e.g., a router, a modem, etc.). Such communication may occur via input / output (I / O) interface 85. Furthermore, computing device 80 may also communicate with one or more networks (e.g., a local area network (LAN), a wide area network (WAN), and / or a public network such as the Internet) via network adapter 86. As shown, network adapter 86 communicates with other modules of computing device 80 via bus 83. It should be understood that, although not shown, other hardware and / or software modules may be used in conjunction with computing device 80, including but not limited to microcode, device drivers, redundant processors, external disk drive arrays, RAID systems, tape drives, and data backup storage systems.

[0113] In summary:

[0114] The vector space is normalized to generate a normalized sector; the target vector is converted into a corresponding vector within the normalized sector; multiple reference vectors are selected with the same angle as the target vector; the reference vectors and a zero vector whose action time can be negative are subjected to a vector transformation operation to obtain a basic vector corresponding to the reference vector. The entire vector space is normalized into a 30° sector. Combined with the operational rules of the buck chopper, a universal three-level space vector pulse width modulation algorithm is proposed to reduce the response time of the three-level converter and improve the on-off efficiency of the control switching device.

[0115] In some possible implementations, various aspects of the pulse modulation method based on a three-level converter provided in the present application may also be implemented in the form of a program product, which includes program code. When the program product is run on a computer device, the program code is used to enable the computer device to execute the steps of the encryption method for information to be verified and / or the verification method for information to be verified according to various exemplary embodiments of the present application described above in this specification. For example, the computer device may execute the following steps: Figure 1 Steps S11-S14 shown in .

[0116] In some possible implementations, a computing device according to the present application may include at least one processor and at least one memory (such as the aforementioned first server). The memory stores program code, and when the program code is executed by the processor, the processor executes the steps of the system permission activation method according to various exemplary embodiments of the present application described above in this specification.

[0117] The program product may employ any combination of one or more readable media. The readable medium may be a readable signal medium or a readable storage medium. The readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or component, or any combination thereof. More specific examples of readable storage media (a non-exhaustive list) include: an electrical connection with one or more wires, a portable disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof.

[0118] The program product for system permission opening of the embodiment of the present application can be a portable compact disc read-only memory (CD-ROM) and include program code, and can be run on a computing device. However, the program product of the present application is not limited thereto. In this document, a readable storage medium can be any tangible medium containing or storing a program, which can be used by or in combination with an instruction execution system, apparatus, or device.

[0119] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the steps in the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0120] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0121] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing the instructions executed on the computer or other programmable device for implementing the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0122] Although the preferred embodiments of the present application have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present application.

[0123] Obviously, those skilled in the art may make various changes and modifications to this application without departing from the spirit and scope of this application. Thus, if these modifications and variations of this application fall within the scope of the claims of this application and their equivalents, this application is intended to include these modifications and variations.

Claims

1. A pulse modulation method based on a three-level converter, characterized in that: include: Normalize the vector space to generate a normalized sector; Convert the target vector into the corresponding vector in the normalized sector, recorded as the normalized vector; Select a reference vector on the reference circle with the same angle as the normalized vector, and calculate the action time of the basic vector of the synthetic reference vector; According to the step-down chopping law, when obtaining the synthetic normalized vector, the action time of the basic vector and the zero vector corresponding to the reference vector; Perform vector transformation operations to obtain the three most recent basic vectors and action time of the normalized vector; According to the vector switching sequence, the basic vectors and action times corresponding to the normalized vectors are combined into a switching state timing diagram of the normalized vectors; Converting the switching state timing diagram of the normalized vector into the switching state timing diagram of the target vector according to the corresponding relationship between the components of the normalized vector and the target vector on the coordinate axis; The reference vector is constructed by the following steps: the inscribed circle of the three-level converter vector space is used as the reference circle, and the vector whose end point is on the reference circle is used as the reference vector; The three nearest basic vectors of the normalized vector are obtained by the following steps: Introduce a zero vector whose action time can be negative, and obtain the action time T of the zero, small, medium and large basic vectors by chopping the spatial state vector diagram of the reference vector z 、T s 、T m 、T l , through the vector conversion method, the four basic vectors are converted into the basic vectors with the closest distance to the three vectors corresponding to the normalized vector; The normalized vector is obtained by the following expression: The action times of zero, small, medium, and large basic vectors are calculated using the following expressions: Where: α is the target vector in the space vector diagram Angle; θ is the normalized vector Angle; T z 、T s 、T m 、T l is the action time of zero, small, medium and large basic vectors; T is the period; T 01_r 、T 12_r 、T 1_r is the action time of the basic vector corresponding to the synthetic reference vector; m is the ratio of the modulus of the normalized vector and the reference vector.

2. The method according to claim 1, characterized in that The normalized sector is specifically a 30° sector, which is specifically implemented as follows: Starting from 0° and at intervals of 30°, the entire vector space can be divided into 12 sectors.

3. The method according to any one of claims 1 or 2, characterized in that Also includes: According to the volt-second balance formula, the action time of the basic vector corresponding to the synthesized reference vector is obtained.

4. The method according to claim 3, characterized in that Also includes: The time of the intermediate state in the switch state timing diagram is obtained by the relationship between the vectors in the space vector diagram, specifically: According to the step-down chopping law, when obtaining the synthetic normalized vector, the action time of the basic vector and the zero vector corresponding to the reference vector; Perform vector transformation operations to obtain the three most recent basic vectors and their action times when synthesizing a normalized vector; determine the switching state timing diagram of the normalized vector based on the vector switching sequence.

5. A pulse modulation control device based on a three-level converter, executing the method according to any one of claims 1 to 4, characterized in that: include: A normalization unit, used to normalize the vector space and generate a normalized sector; a conversion unit, configured to convert the target vector into a corresponding vector within the normalized sector, recorded as a normalized vector; A selection unit is used to select a reference vector having the same angle as the normalized vector and calculate the action time of the basic vector for synthesizing the reference vector; The vector conversion operation unit obtains the basic vector and the action time of the zero vector corresponding to the reference vector when obtaining the synthetic normalized vector according to the step-down chopping law; Perform vector transformation operations to obtain the composite normalized vector, including the three most recent basic vectors and their action time; The timing diagram construction unit composes the basic vectors and action times corresponding to the normalized vector into a switching state timing diagram of the normalized vector according to the vector switching sequence; The inverse conversion unit converts the switching state timing diagram of the normalized vector into the timing diagram of the target vector according to the corresponding relationship between the components of the normalized vector and the target vector on the coordinate axis.

6. The device according to claim 5, characterized in that The normalization unit is specifically implemented as: Starting from 0° and at intervals of 30°, the entire vector space can be divided into 12 sectors.

7. The device according to any one of claims 5 or 6, characterized in that Also includes: The time calculation unit is specifically implemented as follows: According to the volt-second balance formula, the basic vector and action time for synthesizing the reference vector are obtained.

8. The device according to any one of claims 5 or 6, characterized in that Also includes: The intermediate state calculation unit obtains the time of the intermediate state in the switch state timing diagram through the relationship between the vectors in the space vector diagram. The specific implementation is: Combined with the operation rules of the step-down chopper, the reference vector is chopped to obtain the synthetic normalized vector, and the action time of the reference vector corresponding to the basic vector and the zero vector is calculated; Combined with vector operations, the three most recent basic vectors and their action times are obtained when the synthetic normalized vector is obtained; According to the vector switching sequence, the switching state timing diagram of the normalized vector is determined.

9. A computing device, characterized in that include: at least one processor; and a memory communicatively coupled to the at least one processor; The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method according to any one of claims 1 to 4.

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