Filters and their formation methods, electronic devices

Abstract

A filter and its forming method, an electronic device, and a resonator include an encapsulation layer located on a first connection layer. The encapsulation layer, a sealing layer, and a substrate form a first cavity. A protective layer covers the interface between the sealing layer and the encapsulation layer, and the interface between the sealing layer and the substrate. The protective layer strengthens the bonding force between the sealing layer and the encapsulation layer, and between the sealing layer and the substrate, making it less prone to delamination between the sealing layer and the substrate, and between the sealing layer and the encapsulation layer, in high-temperature and high-humidity environments. Furthermore, even if delamination occurs between the sealing layer and the substrate, and between the sealing layer and the encapsulation layer, the protective layer can prevent external moisture from penetrating the gap between the sealing layer and the substrate and entering the first cavity of the filter, avoiding oxidation and corrosion of the device structure. This improves the reliability of the filter performance and enables the filter to meet the requirements of high-performance radio frequency systems.

Description

Technical Field

[0001] This invention relates to the field of semiconductors, and more particularly to a filter, a method for forming the filter, and an electronic device thereof. Background Technology

[0002] Since the development of analog radio frequency (RF) communication technology in the early 1990s, RF front-end modules have gradually become core components of communication equipment. With the rapid development of wireless communication technology and the increasing maturity of 5G communication protocols, the market has imposed more stringent standards on the performance of RF filters. The performance of a filter is determined by the resonator units that make up the filter. Among existing filters, thin-film bulk acoustic resonators (FBARs) are among the most suitable filters for 5G applications due to their small size, low insertion loss, high out-of-band rejection, high quality factor, high operating frequency, large power capacity, and good electrostatic discharge (ESD) immunity.

[0003] To meet the goals of lower cost, higher reliability, faster speed and higher density packaging, advanced packaging methods mainly adopt wafer-level package system in package (WLPSiP). Compared with traditional system packaging, wafer-level package system in package completes the packaging integration process on the device wafer, which has advantages such as significantly reducing the area of ​​the package structure, reducing manufacturing costs, optimizing electrical performance, and batch manufacturing, and can significantly reduce workload and equipment requirements.

[0004] Currently, there is still room for improvement in the reliability of filters. Summary of the Invention

[0005] The problem solved by this invention is to provide a filter and its formation method, as well as an electronic device, to improve the performance of the filter.

[0006] To address the aforementioned problems, the present invention provides a resonator comprising: a substrate including a working region and an interconnect region surrounding the working region; a device structure located on the substrate in the working region; a first connection layer located on the substrate in the interconnect region, the first connection layer including an interconnect layer and an annular sealing layer surrounding the interconnect layer, the interconnect layer being electrically connected to the device structure; an encapsulation layer located on the first connection layer, the encapsulation layer, the sealing layer, and the substrate forming a first cavity, the edge of the encapsulation layer being located on the top surface of the sealing layer; and a protective layer covering the interface between the sealing layer and the encapsulation layer, and the interface between the sealing layer and the substrate.

[0007] Accordingly, the present invention also provides a method for forming a resonator, comprising: providing a substrate, the substrate including a working region and an interconnect region surrounding the working region, wherein a device structure is formed on the substrate of the working region; forming a first connection layer on the substrate of the interconnect region, the first connection layer including an interconnect layer and an annular sealing layer surrounding the interconnect layer, the interconnect layer being electrically connected to the device structure; forming an encapsulation layer on the first connection layer, the encapsulation layer, the sealing layer and the substrate forming a first cavity, the edge of the encapsulation layer being located on the top surface of the sealing layer; and forming a protective layer covering the interface between the sealing layer and the encapsulation layer, and the interface between the sealing layer and the substrate.

[0008] Accordingly, the present invention also provides an electronic device including the aforementioned filter.

[0009] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0010] In the filter provided by this embodiment of the invention, an encapsulation layer is located on the first connection layer. The encapsulation layer, the sealing layer, and the substrate form a first cavity. A protective layer covers the interface between the sealing layer and the encapsulation layer, as well as the interface between the sealing layer and the substrate. The protective layer can strengthen the bonding force between the sealing layer and the encapsulation layer, and between the sealing layer and the substrate, so that delamination is less likely to occur between the sealing layer and the substrate, and between the sealing layer and the encapsulation layer, in high-temperature and high-humidity environments. In addition, even if delamination occurs between the sealing layer and the substrate, and between the sealing layer and the encapsulation layer, the protective layer can prevent external moisture from passing through the gap between the sealing layer and the substrate and entering the first cavity of the filter, avoiding oxidation and corrosion of the device structure, which is beneficial to improving the reliability of the filter performance and enabling the filter to meet the requirements of high-performance radio frequency systems.

[0011] In an optional embodiment of the present invention, the filter has a buffer layer located between the sealing layer and the substrate. The buffer layer serves to buffer the thermal stress between the substrate and the sealing layer, so that during thermal processes (baking, reflow, or temperature cycling), delamination or damage is less likely to occur between the substrate and the buffer layer, or between the buffer layer and the sealing layer due to thermal stress. Furthermore, even if delamination occurs between the sealing layer and the substrate, or between the sealing layer and the encapsulation layer, the protective layer can prevent external moisture from passing through the gap between the sealing layer and the substrate and entering the first cavity of the filter, thus avoiding oxidation and corrosion of the device structure. This improves the reliability of the filter performance and enables the filter to meet the requirements of high-performance radio frequency systems. Attached Figure Description

[0012] Figure 1 This is a schematic diagram of a filter structure;

[0013] Figures 2 to 15This is a schematic diagram of the structure corresponding to each step in the first embodiment of the method for forming the resonator of the present invention;

[0014] Figures 16 to 18 This is a schematic diagram of the structure corresponding to each step in the second embodiment of the resonator formation method of the present invention. Detailed Implementation

[0015] As can be seen from the background technology, there is still room for improvement in the reliability of current filters. Now, combined with... Figure 1 A schematic diagram of a filter structure is shown, and the reasons for poor filter performance are analyzed.

[0016] The filter includes: a substrate 10; the substrate 10 includes a working region 10A and an interconnect region 10B surrounding the working region 10A; a device structure 12 located on the substrate 10 of the working region 10A; an interconnect layer 13 located on top of the substrate 10 of the interconnect region 10B; a sealing layer 16 located on top of the substrate 10 surrounding the interconnect layer 13; an encapsulation layer 11 located on top of the interconnect layer 13 and the sealing layer 16, the encapsulation layer 11, the sidewall of the interconnect layer 13, and the substrate 10 forming a cavity 19, the cavity 19 being used to accommodate the device structure 12; and a conductive pillar 17 penetrating the encapsulation layer 11 and electrically connecting the top of the interconnect layer 13.

[0017] Research has revealed that different materials have different coefficients of thermal expansion (CTE). Therefore, when the filter is subjected to temperature cycling or in high-temperature and high-humidity environments, the bonding force at the interface of different material layers is weak. Correspondingly, in the filter structure, the bonding force between the sealing layer 16 and the substrate 10, as well as between the sealing layer 16 and the encapsulation layer 11, is weak, making delamination more likely. External moisture can penetrate the gap between the sealing layer and the substrate and enter the cavity 19 of the filter, causing oxidation and corrosion of the device structure 12, which reduces and affects the reliability of the filter.

[0018] In the filter provided by this embodiment of the invention, an encapsulation layer is located on the first connection layer. The encapsulation layer, the sealing layer, and the substrate form a first cavity. A protective layer covers the interface between the sealing layer and the encapsulation layer, as well as the interface between the sealing layer and the substrate. The protective layer can strengthen the bonding force between the sealing layer and the encapsulation layer, and between the sealing layer and the substrate, so that delamination is less likely to occur between the sealing layer and the substrate, and between the sealing layer and the encapsulation layer, in high-temperature and high-humidity environments. In addition, even if delamination occurs between the sealing layer and the substrate, and between the sealing layer and the encapsulation layer, the protective layer can prevent external moisture from passing through the gap between the sealing layer and the substrate and entering the first cavity of the filter, avoiding oxidation and corrosion of the device structure, which is beneficial to improving the reliability of the filter performance and enabling the filter to meet the requirements of high-performance radio frequency systems.

[0019] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0020] Figures 2 to 15 This is a schematic diagram of the structure corresponding to each step in the first embodiment of the resonator formation method of the present invention.

[0021] refer to Figure 2 A substrate 100 is provided, the substrate 100 including a working region and an interconnect region surrounding the working region, and a device structure is formed on the substrate 100 of the working region.

[0022] The substrate 100 is used to provide a process platform for the subsequent formation of filters.

[0023] In this embodiment, the substrate 100 is a wafer-level substrate 100. By using a wafer-level substrate 100, wafer-level fabrication processes can be implemented in the filter formation method, which can reduce process costs and enable mass production, thereby improving the production efficiency of filter manufacturing.

[0024] In this embodiment, the substrate 100 is a wafer-level substrate 100. Therefore, the substrate 100 includes a plurality of device unit regions (not shown), and each device unit region includes an interconnect region 100B surrounding the working region 100A.

[0025] In this embodiment, the substrate 100 of the working area 100A of each device unit region has a second cavity 101, which is a bulk acoustic wave filter structure. In other embodiments, the substrate of the working area of ​​each device unit region may not have a second cavity, as it is ultimately used to form a surface acoustic wave filter.

[0026] The working area 100A is the area where the device structure 102 works. Specifically, the working area 100A is the working area where the filter performs filtering functions, and a first cavity is subsequently formed on the top of the working area 100A.

[0027] In this embodiment, the final filter includes a first cavity and a second cavity 101, and the corresponding filter is a bulk acoustic wave (BAW) filter. Specifically, the bulk acoustic wave resonator can be a diaphragm-type thin-film bulk acoustic resonator (FBAR). In other embodiments, the bulk acoustic wave filter can also be a reflective array bulk acoustic resonator (BAW-SMR) or an air-gap type thin-film bulk acoustic resonator.

[0028] The device structure 102 is used to realize the mutual conversion between electrical signals and acoustic signals, thereby enabling the filter to filter the signals. Specifically, the device structure 102 is an acoustic transducer with a piezoelectric stack structure, which includes a first electrode (not shown in the figure), a piezoelectric film (not shown in the figure) located on the first electrode, and a second electrode (not shown in the figure) located on the piezoelectric film.

[0029] In other embodiments, the final filter may also be a surface acoustic wave (SAW) filter. The substrate of each device unit region may also not have a second cavity.

[0030] Accordingly, the substrate is a piezoelectric substrate, enabling subsequent filters to utilize the piezoelectric effect for filtering. In this embodiment, the substrate material is lithium niobate (LiNbO3), lithium tantalate (LiTaO3), AlN, AlN-doped semiconductor materials, quartz, piezoelectric crystals, or piezoelectric ceramics. The piezoelectric crystals include, but are not limited to, quartz crystals, potassium sodium tartrate, and lithium niobate crystals. The piezoelectric ceramic layer material includes, but is not limited to, barium titanate, lead zirconate titanate, modified lead zirconate titanate, lead metaniobate, lithium lead barium niobate, and modified lead titanate. Lithium niobate or lithium tantalate can provide a very high electromechanical coupling coefficient, enabling the manufacture of filters exhibiting approximately 50% relative bandwidth.

[0031] The device structure is an interdigital transducer (IDT). The IDT includes two sets of interdigital electrodes with energy conversion functions: an input interdigital transducer and an output interdigital transducer. When the input interdigital transducer receives an electrical signal, the surface of the piezoelectric substrate vibrates, exciting an acoustic wave of the same frequency as the applied signal. This acoustic wave propagates along the surface of the piezoelectric substrate, and a portion of the acoustic wave is transmitted to the output interdigital transducer. The output interdigital transducer converts the mechanical vibration into an electrical signal, which is then output.

[0032] Continue to refer to Figure 2 The surface of the substrate 100 is then cleaned.

[0033] Specifically, cleaning the surface of the substrate 100 increases the bonding strength between the sealing layer 1032 subsequently formed on top of the substrate 100 and the substrate 100, and reduces the probability of delamination between the sealing layer 1032 and the substrate 100 due to thermal stress.

[0034] In this embodiment, the cleaning process for the surface of the substrate 100 includes one or both of dry plasma cleaning and wet cleaning.

[0035] refer to Figure 3 A first interconnect layer 103 is formed on the substrate 100 of the interconnect region 100B. The first interconnect layer 103 includes an interconnect layer 1031 and an annular sealing layer 1032 surrounding the interconnect layer 1031. The interconnect layer 1031 is electrically connected to the device structure 102.

[0036] The interconnect layer 1031 is electrically connected to the device structure 102. The interconnect layer 1031 serves as an input / output (I / O) terminal for the device structure 102, connecting it to an external circuit structure. The sealing layer 1032 protects the interconnect layer 1031 and the device structure from the side, reducing the probability of moisture entering the working area 100A and the probability of oxidation and corrosion of the device structure within the working area 100A. Correspondingly, it also reduces the probability of oxidation and corrosion of the interconnect layer 1031.

[0037] In this embodiment, the interconnect layer 1031 and the sealing layer 1032 are formed in the same step. Compared with the case where the interconnect layer 1031 and the sealing layer 1032 are formed in separate steps, this is beneficial to improving the formation efficiency of the filter and reducing the process cost.

[0038] In this embodiment, the material of the first interconnect layer 103 includes one or more of Ti, Cu, Al, and Ni. Specifically, Ti, Cu, Al, and Ni are all conductive materials, enabling the device structure in the working area 100A to be electrically connected to the external power distribution structure through the interconnect layer 1031. As an example, the material of the interconnect layer 1031 is Al.

[0039] The step of forming the first interconnect layer 103 includes: forming a first interconnect material layer (not shown in the figure) on the substrate 100 of the interconnect region 100B; and patterning the first interconnect material layer to form the first interconnect layer 103.

[0040] In this embodiment, a chemical electroplating process is used to form the first connecting material layer. In other embodiments, a physical vapor deposition (PVD), vacuum evaporation, or chemical vapor deposition process may also be used to form the first connecting material layer.

[0041] In this embodiment, the first connecting material layer is patterned using a dry etching process to form the first connecting layer 103.

[0042] It should be noted that the thickness of the interconnect layer 1031 should not be too large or too small. If the thickness of the interconnect layer 1031 is too large, it increases the difficulty and time of patterning the first connection material layer; if the thickness of the interconnect layer 1031 is too small, it may lead to an insufficient effective height of the first cavity subsequently formed in the working area 100A. Consequently, after the encapsulation layer 104 is deformed by external force, the probability of the encapsulation layer 104 contacting the device structure 102 increases, thereby reducing the reliability of the filter. Therefore, in this embodiment, the thickness of the interconnect layer 1031 is 2 micrometers to 30 micrometers.

[0043] The material of the sealing layer 1032 is the same as that of the first connecting layer 103, and the material of the sealing layer 1032 also includes one or more of Ti, Cu, Al and Ni.

[0044] The sealing layer 1032 is made of metal. Because metal atoms are closely packed, the sealing layer 1032 has good density and can effectively seal the filter. The sealing layer 1032 and the interconnect layer 1031 are made of the same material, which allows the sealing layer 1032 and the interconnect layer 1031 to be etched in the same step as the first interconnect material layer. This simplifies the filter fabrication process and improves efficiency.

[0045] In this embodiment, the sealing layer 1032 and the interconnect layer 1031 are formed in the same step, therefore the thickness of the sealing layer 1032 and the thickness of the interconnect layer 1031 are substantially the same. The thickness of the sealing layer 1032 is 2 micrometers to 30 micrometers. The height difference between the sealing layer 1032 and the interconnect layer 1031 is less than 3 micrometers. In other embodiments, the sealing layer and the interconnect layer may be formed separately.

[0046] In this embodiment, the distance w1 between the sealing layer 1032 and the interconnect layer 1031 (e.g., ...) Figure 3 The distance (as shown) is greater than 2 micrometers, such as 5 micrometers or 8 micrometers. In one embodiment, this distance is 3-10 micrometers. If the distance is too small, it can easily cause a short circuit; if the distance is too large, the resulting packaged device will occupy a large space, which is not conducive to chip miniaturization. Within the range allowed by the process, the smaller the distance difference, the more beneficial it is to the miniaturization of the package. In this embodiment, the width w2 of the sealing layer 1032 (as shown) is greater than 2 micrometers, such as 5 micrometers or 8 micrometers. Figure 3(As shown) is greater than 10 micrometers, such as 15 micrometers or 25 micrometers. In one embodiment, the width of the sealing layer 1032 is 20-40 micrometers, such as 30 micrometers. The width of the sealing layer 1032 determines the bonding strength between the sealing layer and the package. The wider the width, the greater the bonding strength, and the stronger the ability to prevent moisture from entering the cavity. A suitable width is selected based on the size of the package layer, taking into account both the bonding strength and the area occupied by the sealing layer. It should be noted that in the step of forming the first interconnect layer 103 on the substrate 100 of the interconnect region 100B, there are multiple interconnect layers 1031; and the multiple interconnect layers 1031 are spaced apart, so that the multiple interconnect layers 1031 do not contact each other, resulting in an open circuit between the multiple interconnect layers 1031. As an example, the figure shows two interconnect layers 1031, one for electrical connection to the first electrode of the piezoelectric stack structure, and the other for electrical connection to the second electrode of the piezoelectric stack structure.

[0047] In other embodiments, a surface acoustic wave (SAW) filter is ultimately formed, and the interconnect layer is used to electrically connect the input interdigital transducer and the output interdigital transducer, respectively.

[0048] As an example, such as Figure 3 As shown, two interconnect layers 1031 are located on both sides of the working area 100A.

[0049] The sealing layer 1032 is spaced apart from the interconnecting layer 1031, or the sealing layer 1032 is only connected to one interconnecting layer 1031, so that the sealing layer 1032 and the interconnecting layer 1031 are in an open circuit state, and the sealing layer 1032 cannot play the role of electrical connection.

[0050] It should be noted that when the sealing layer 1032 is connected to one interconnect layer 1031 and disconnected from another interconnect layer 1031, an insulating layer (not shown in the figure) is formed at the bottom of the interconnect layer 1031 connected to the sealing layer 1032, which is used to electrically isolate it from the substrate 100 and avoid affecting the working performance of the piezoelectric stack structure.

[0051] It should be noted that the sealing layer 1032 is annular, meaning that the sealing ring 1032 surrounds the interconnect layer, which helps to improve the sealing of the first cavity formed subsequently with the encapsulation layer.

[0052] refer to Figure 4 and Figure 5 An encapsulation layer 104 is formed on the first connection layer 103 (e.g., Figure 5 As shown, the encapsulation layer 104, the sealing layer 1032, and the substrate 100 form a first cavity 105, and the edge of the encapsulation layer 104 is located on the top surface of the sealing layer 1032.

[0053] The encapsulation layer 104 encapsulates the filter, providing sealing and moisture protection, reducing the impact of subsequent processes on the device structure 102, and thus improving the reliability of the resulting filter. Furthermore, sealing the first cavity 105 helps isolate it from the external environment, thereby improving the stability of the acoustic performance of the device structure 102.

[0054] In the step of forming an encapsulation layer 104 on the first interconnect layer 103, the encapsulation layer 104 includes an opening exposing the interconnect layer 1031. The opening provides space for subsequent formation of interconnect pillars.

[0055] In this embodiment, the step of forming the encapsulation layer 104 includes: forming an encapsulation material layer 106 (such as...) on the first connection layer 103. Figure 4 (as shown); the encapsulation material layer 106 is graphically represented to form an encapsulation layer 104, the encapsulation layer 104 including an opening 107 exposing the interconnect layer 1031.

[0056] In this embodiment, the encapsulation layer 104 is made of a photosensitive material. The encapsulation material layer 106 is patterned using photolithography, which helps reduce the difficulty of forming the encapsulation layer 104 from the patterned encapsulation material layer 106. Specifically, the photosensitive material is a dry film. Dry film is a permanent bonding film with high adhesive strength, thus ensuring the bonding strength between the encapsulation layer 104 and the interconnect layer 1031 and the sealing layer 1032. Simultaneously, it helps improve the sealing performance of the first cavity 105.

[0057] In other embodiments, the photosensitive material is a dry film, which can be formed into the encapsulation layer using a lamination process. This lamination process is performed in a vacuum environment, providing excellent stepped coverage and significantly improving the adhesion and bonding strength between the encapsulation layer and the interconnect and sealing layers.

[0058] In other embodiments, a liquid dry film can also be used to form the encapsulation layer, wherein the liquid dry film refers to a film in which the components exist in a liquid form. Accordingly, the steps for forming the encapsulation layer include: applying the liquid dry film using a spin-coating process; and curing the liquid dry film to form the encapsulation layer. The cured liquid dry film is also a photosensitive material. In other embodiments, the material of the encapsulation layer can also be a dielectric material or an organic material. Accordingly, the encapsulation layer can be formed using a deposition process or a coating process, respectively. The dielectric material can be silicon oxide, phosphosilicate glass (PSG), or borosilicate glass (BPSG), and the organic material can be polyimide.

[0059] It should be noted that the edge of the encapsulation layer 104 is located on the top surface of the sealing layer 1032, in preparation for the subsequent formation of a protective layer 109 covering the interface between the sealing layer 1032 and the encapsulation layer 104.

[0060] It should be noted that the thickness of the encapsulation layer 104 should not be too large or too small. If the thickness of the encapsulation layer 104 is too large, it increases the difficulty of removing the encapsulation layer 104 during the formation of the opening, and also makes the size of the opening formed in the encapsulation layer 104 larger. Consequently, the overall area of ​​the filter increases, resulting in excessive waste of encapsulation layer 104 material and increasing process costs. If the thickness of the encapsulation layer 104 is too small, it is easy for the encapsulation layer 104 to withstand external pressure, and the central area of ​​the encapsulation layer 104 is prone to collapse, which reduces the airtightness and waterproof performance of the encapsulation layer 104, thus placing higher demands on the subsequent manufacturing process and application environment of the filter. Therefore, in this embodiment, the thickness of the encapsulation layer 104 is 5 micrometers to 60 micrometers.

[0061] refer to Figures 6 to 9 A protective layer 109 is formed covering the interface between the sealing layer 1032 and the encapsulation layer 104, as well as the interface between the sealing layer 1032 and the substrate 100.

[0062] In the filter provided in this embodiment of the invention, an encapsulation layer 104 is located on the first connection layer 103. The encapsulation layer 104, the sealing layer 1032, and the substrate 100 form a first cavity 105. A protective layer 109 covers the interface between the sealing layer 1032 and the encapsulation layer 104, and the interface between the sealing layer 1032 and the substrate 100. The protective layer 109 can strengthen the bonding force between the sealing layer 1032 and the encapsulation layer 104, and between the sealing layer 1032 and the substrate 100, so that in high temperature and high humidity environments, the sealing layer 1032... Delamination is less likely to occur between the sealing layer 1032 and the substrate 100, and between the sealing layer 1032 and the encapsulation layer 104. Furthermore, even if delamination occurs between the sealing layer 1032 and the substrate 100, and between the sealing layer 1032 and the encapsulation layer 104, the protective layer 109 can prevent external moisture from passing through the gap between the sealing layer 1032 and the substrate 100 and entering the first cavity 105 of the filter, thus avoiding oxidation and corrosion of the device structure 102. This is beneficial to improving the reliability of the filter performance and enabling the filter to meet the requirements of high-performance radio frequency systems.

[0063] Specifically, a metal stack structure needs to be formed to electrically connect the interconnect layer 1031. The metal stack structure is formed by electroplating in an electrolyte solution. The protective layer 109 can prevent water vapor in the electrolyte solution from easily entering the first cavity 105.

[0064] In this embodiment, the step of forming the protective layer 109 includes: as follows Figure 6 As shown, a first seed layer 110 is formed to conformally cover the top and sidewalls of the encapsulation layer 104, the top and sidewalls of the first interconnect layer 103, and the substrate 100; as Figure 7 As shown, a first shielding layer 108 is formed on the first seed layer 110, the first shielding layer 108 covers the opening 107, exposing the interface between the encapsulation layer 104 and the sealing layer 1032, as well as the interface between the sealing layer 1032 and the substrate 100; a protective layer 109 is formed in the area exposed by the first shielding layer 108.

[0065] The first seed layer 110 provides a good interface state for forming the protective layer 109. In this embodiment, the material of the first seed layer 110 includes one or more of Ti, Cu, Ta, TiN, and Al.

[0066] The first seed layer 110 is a stacked structure. As an example, its structure includes: a 100-nanometer titanium layer and a 200-nanometer copper layer on the titanium layer, or a 200-nanometer titanium layer and a 500-nanometer copper layer.

[0067] In this embodiment, the first seed layer 110 is formed using physical vapor deposition, vacuum evaporation, chemical vapor deposition, or chemical copper plating.

[0068] The first shielding layer 108 defines the area where the protective layer 109 is formed, preparing for the subsequent formation of the protective layer 109.

[0069] In this embodiment, the material of the first shielding layer 108 is an organic material. The organic material has a large etching selectivity with the protective layer 109, so the protective layer 109 is less likely to be damaged in the subsequent step of removing the first shielding layer 108.

[0070] Specifically, the material of the first shielding layer 108 includes, but is not limited to: the material of the first shielding layer 108 can also be an organic material, such as: BARC (bottom anti-reflective coating) material, ODL (organic dielectric layer) material, photoresist, DARC (dielectric anti-reflective coating) material, DUO (Deep UV Light Absorbing Oxide) material or APF (Advanced Patterning Film) material.

[0071] Specifically, the steps for forming the first masking layer 108 include: forming a first masking material layer on the first seed layer 110, and patterning the first masking material layer to form the first masking layer 108.

[0072] In this embodiment, the protective layer 109 is made of one or more of copper, nickel, gold, and silver. In this embodiment, the protective layer is formed using physical vapor deposition, vacuum evaporation, chemical vapor deposition, or electroless copper plating. The protective layer 109 is made of metal, and the metal atoms in the protective layer 109 are closely arranged, resulting in good density. This makes it difficult for external moisture to penetrate the protective layer 109 and enter the first cavity of the filter, preventing oxidation and corrosion of the device structure and improving the reliability of the filter performance. Furthermore, the protective layer 109 is made of metal, which has good thermal conductivity, thus improving the heat dissipation performance of the device.

[0073] It should be noted that the protective layer 109 should not be too thick or too thin during the formation process. If the protective layer 109 is too thick, it will require excessive processing time and materials, resulting in low formation efficiency and high cost. If the protective layer 109 is too thin, its effect in preventing external moisture from entering the first cavity 105 will be ineffective. External moisture can pass through the gap between the sealing layer 1032 and the substrate 100 and enter the first cavity 105 of the filter, causing oxidation and corrosion of the device structure 102, reducing the reliability of the filter performance, and preventing the filter from meeting the requirements of a high-performance RF system. In this embodiment, the thickness of the protective layer 109 is 0.5 micrometers to 10 micrometers.

[0074] refer to Figure 8 The method for forming the filter further includes: after forming the protective layer 109, removing the first shielding layer 108.

[0075] Removing the first shielding layer 108 prepares for the subsequent formation of interconnect pillars and metal bump stacks on the interconnect pillars in the opening 107. In this embodiment, the first shielding layer 108 is removed using an ashing process or a wet adhesive removal process.

[0076] It should be noted that the first seed layer 110 is reserved to provide a good interface state for the subsequent formation of interconnect pillars 111, avoiding the formation of seed layers multiple times and simplifying the process flow.

[0077] refer to Figure 9 The method for forming the filter further includes: after removing the first shielding layer 108, forming an interconnect post 111 in the opening that is connected to the interconnecting layer.

[0078] Interconnect post 111 is used to connect interconnect layer 1031 to external electrical connections.

[0079] Specifically, the step of forming the interconnect post 111 includes: forming a protective layer 109 that exposes the opening 107; and forming the interconnect post 111 in the opening 107.

[0080] In this embodiment, a spin coating process is used to form the third masking layer 114 through patterning. The material of the third masking layer 114 is the same as that of the first masking layer 108, and will not be described again here.

[0081] In this embodiment, the interconnect pillar 111 is made of one or more of copper, nickel, gold, and silver. In this embodiment, the interconnect pillar is formed using physical vapor deposition, vacuum evaporation, chemical vapor deposition, or electroless copper plating.

[0082] refer to Figure 10 The method of forming the filter further includes forming a metal bump stack (Pillar) 112 on the top of the interconnect pillar 111.

[0083] The metal bump stack 112 is used to prepare for connecting the interconnect post 111 to an external circuit.

[0084] In this embodiment, the material of the metal bump stack 112 includes a copper layer and a nickel layer located on the copper layer. In other embodiments, the material of the metal bump stack may also include only a copper layer.

[0085] The method for forming the filter further includes forming a tin-silver alloy layer 113 (SnAg) on ​​the metal bump stack 112.

[0086] refer to Figure 11 The method for forming the filter further includes: after forming the metal bump stack, removing the second shielding layer, the first seed layer, and the third shielding layer 114.

[0087] In this embodiment, a wet etching process is used to remove the first seed layer 110. Specifically, the wet etching solution includes phosphoric acid and hydrogen peroxide, or sulfuric acid and hydrogen peroxide. It should be noted that when the first seed layer 110 is removed using the wet etching process, the protective layer 109 will also be slightly thinned. However, because the thickness of the protective layer 109 is much greater than the thickness of the first seed layer 110, the protective layer 109 can still provide good protection.

[0088] In this embodiment, the third masking layer 114 is removed by an ashing process or a wet adhesive removal process.

[0089] In other embodiments, such as Figures 12 to 14In the step of forming the protective layer 212, an interconnection structure 211 may also be formed on the bottom surface and side wall of the opening 207 and on the top of the sealing layer 2032.

[0090] The interconnect structure 211 electrically connects the interconnect layer 2031 at the bottom of the opening 207 to the external circuit structure. The interconnect structure 211 and the protective layer 212 are formed in the same step, which, compared to forming the interconnect structure 211 and the protective layer 212 in sequential steps, simplifies the filter fabrication process and reduces the filter manufacturing cost.

[0091] Specifically, the steps of forming the protective layer and the interconnection structure 211 include: as follows Figure 12 As shown, a first seed layer 210 is formed to conformally cover the top and sidewalls of the encapsulation layer 204, the top and sidewalls of the first connecting layer 103, and the substrate 200; a second shielding layer 208 is formed on the first seed layer 210, the second shielding layer 208 exposing the top portion of the opening 207 and the sealing layer 2032, as well as the interface between the sealing layer 1032 and the encapsulation layer 104, and the interface between the sealing layer 1032 and the substrate 100; as Figure 13 As shown, an electroplated layer is formed in the exposed area of ​​the second shielding layer 208, wherein the electroplated layer located in the opening 207 and on top of a portion of the sealing layer 2032 serves as the interconnect structure 211, and the electroplated layer located at the interface between the sealing layer 1032 and the encapsulation layer 104, and at the interface between the sealing layer 1032 and the substrate 100 serves as the protective layer 212.

[0092] The first seed layer 210 provides a good interface state for the formation of the electroplated layer. In other embodiments, the material of the first seed layer includes one or more of Ti, Cu, Ta, TiN, and Al. In this embodiment, the first seed layer is formed using a physical vapor deposition process, a vacuum evaporation process, a chemical vapor deposition process, or a chemical copper plating process.

[0093] The first seed layer 210 is a stacked structure. As an example, its structure includes: a 100-nanometer titanium layer and a 200-nanometer copper layer on the titanium layer, or a 200-nanometer titanium layer and a 500-nanometer copper layer.

[0094] In this embodiment, the electroplated layer has a multilayer structure comprising: a copper layer, a nickel layer on the copper layer, and a gold layer on the nickel layer. Gold is a non-reactive metal with good oxidation and corrosion resistance, and can protect the metal it covers.

[0095] In this embodiment, an electroplating process is used to conformally cover the first seed layer 210 with an electroplated layer. The thickness of the electroplated layer reaches the preset thickness of the interconnect structure 211 and the protective layer 212 to be formed subsequently.

[0096] In other embodiments, the electroplated layer may also be a copper layer, and an electroless nickel-gold plating or an electroless nickel-palladium-gold plating may be placed on the copper layer. Both electroless nickel-gold plating and electroless nickel-palladium-gold plating are inert metals with good oxidation and corrosion resistance, and can protect the metal they cover.

[0097] Other methods can also be used to form the protective layer and the interconnect structure. Specifically, the steps of forming the protective layer and the interconnect structure include: forming a first seed layer that conformally covers the top and sidewalls of the encapsulation layer, the top and sidewalls of the first interconnect layer, and the substrate; conformally covering the first seed layer with a second metal material layer; patterning the second metal material layer, with the second metal material layer located in the opening and on top of the sealing layer portion serving as the interconnect structure, and the second metal material layer located at the interface between the sealing layer and the encapsulation layer, and at the interface between the sealing layer and the substrate serving as the protective layer.

[0098] An electroplating process is used to conformally coat the first seed layer with a second metal material layer. The thickness of the second metal material layer reaches the preset thickness of the interconnect structure and protective layer to be formed subsequently.

[0099] like Figure 14 As shown, the method for forming the filter further includes: after forming the interconnect structure 211 and the protective layer 212, removing the second shielding layer 208.

[0100] For reference Figure 15 The side of the substrate 100 opposite to the interconnect layer 1031 and the sealing layer 1032 is thinned.

[0101] Thinning the side of the substrate 100 away from the interconnect layer 1031 and the sealing layer 1032 can reduce the thickness of the filter, which is beneficial to the miniaturization trend of filters.

[0102] In this embodiment, a grinding process is used to thin the side of the substrate 100 away from the interconnect layer 1031 and the sealing layer 1032. The grinding process is characterized by low cost, high efficiency, and simple operation. In other embodiments, a chemical mechanical planarization (CMP) process is used to thin the side of the substrate away from the interconnect layer and the sealing layer.

[0103] It should be noted that before thinning the side of the substrate 100 away from the interconnect layer 1031 and the sealing layer 1032, the tin-silver alloy layer in the metal bump stack needs to be reflowed to make the tin-silver alloy layer into tin-silver alloy spheres.

[0104] It should also be noted that, in this embodiment of the invention, after the encapsulation layer 104 is formed and the metal bumps are stacked, the side of the substrate 100 facing away from the interconnect layer 1031 and the sealing layer 1032 is thinned. In other embodiments, the side of the substrate to be formed with the interconnect layer and the sealing layer may also be thinned during the step of providing the substrate.

[0105] The method for forming the filter further includes: after thinning the substrate 100, cutting the multiple device units in the substrate 100.

[0106] Figures 16 to 18 This is a schematic diagram of the structure corresponding to each step of the second embodiment of the resonator formation method of the present invention.

[0107] The similarities between this embodiment and the first embodiment will not be repeated here, but the differences are as follows:

[0108] like Figure 16 As shown, the method for forming the filter includes: after providing a substrate 300, before forming a first interconnect layer 303 on the substrate 300 of the interconnect region 300B, forming a buffer layer 304 on the substrate 300 of the interconnect region 300B.

[0109] The buffer layer 304 is located between the sealing layer 3032 and the substrate 300. The buffer layer 304 serves to buffer the thermal stress between the substrate 300 and the sealing layer 3032, thus preventing delamination or damage between the substrate 300 and the buffer layer 304, and between the buffer layer 304 and the sealing layer 3032, during thermal processes (baking, reflow, or temperature cycling). Therefore, external moisture cannot easily penetrate the gap between the buffer layer 304 and the substrate 300.

[0110] The buffer layer 304 is made of a material with a coefficient of thermal expansion between that of the substrate 300 and the sealing layer 3032, giving the buffer layer 304 excellent buffering performance. Silicon has a coefficient of thermal expansion of 3.5 ppm / ℃, copper has a coefficient of thermal expansion of 17.5 ppm / ℃, and the buffer layer 304 has a coefficient of thermal expansion between 3.5 ppm / ℃ and 17.5 ppm / ℃.

[0111] The buffer layer 304 can also be a material with a Young's modulus lower than 1.0E11 Pa. In this embodiment, the substrate 300 is made of silicon, which has a Young's modulus of 1.1E11 Pa. The sealing layer 3032 and the interconnect layer 3031 are made of copper, which has a Young's modulus of 1.7E11 Pa. The buffer layer 304 has a Young's modulus lower than that of the substrate 300, the sealing layer 3032, and the interconnect layer 3031. During thermal processes (baking, reflow, or temperature cycling), it can buffer the substrate 300 and the sealing layer 3032, as well as the substrate 300 and the interconnect layer 3031.

[0112] If the Young's modulus of the buffer layer 304 is too high, during the heating process, delamination or damage may easily occur between the buffer layer 304 and the substrate 300, and between the buffer layer 304 and the sealing layer 3032. This will cause external moisture to easily pass through the gap between the buffer layer 304 and the substrate 300 and enter the first cavity 305, making the interior of the first cavity 305 prone to oxidation and corrosion.

[0113] In this embodiment, the buffer layer 304 is made of a photosensitive material. As an example, the buffer layer 304 is made of polyimide, which has a Young's modulus lower than 3E9 Pa. In other embodiments, the buffer layer material further includes silicon oxide, which has a Young's modulus of 7E10 Pa. In still other embodiments, the buffer layer material may also include silicon nitride, phosphosilicate glass, etc.

[0114] In this embodiment, the step of forming the buffer layer 304 includes: forming a buffer material layer (not shown in the figure) on the substrate 300; patterning the buffer material layer, with the remaining buffer material layer serving as the buffer layer 304.

[0115] In this embodiment, the buffer material layer is formed using a spin coating process, and the buffer layer 304 is patterned by photolithography. This helps to reduce damage to the substrate 300 during the formation of the buffer layer 304 and improves the electrical performance of the filter. In other embodiments, the material of the buffer layer includes silicon oxide, and the buffer material layer can be patterned using a dry etching process.

[0116] like Figure 17As shown, in the step of forming the first interconnect layer 303 on the substrate 300 in the interconnect region, the interconnect layer 3031 is formed on top of the buffer layer 304 and covers the sidewall of the buffer layer 304 near the working region 300A, and extends to the working region 300A to be electrically connected to the device structure; the sealing layer may also be formed only on top of the buffer layer 304, or the sealing layer 3032 is formed on top of the buffer layer 304, covering part of the top of the buffer layer 304 and the sidewall of the buffer layer 304 away from the working region 300A, and covering the interface between the buffer layer 304 and the substrate 300.

[0117] The buffer layer 304 is located between the sealing layer 3032 and the substrate 300. The buffer layer 304 serves to buffer the thermal stress between the substrate 300 and the sealing layer 3032, so that during thermal processes (baking, reflow, or temperature cycling), delamination or damage is less likely to occur between the substrate 300 and the buffer layer 304, or between the buffer layer 304 and the sealing layer 3032. In addition, even if delamination occurs between the sealing layer 3032 and the substrate 300, or between the sealing layer 3032 and the encapsulation layer 306, the protective layer 309 can prevent external moisture from passing through the gap between the sealing layer 3032 and the substrate 300 and entering the first cavity 305 of the filter, avoiding oxidation and corrosion of the device structure 302, which helps to improve the reliability of the filter performance and enables the filter to meet the requirements of high-performance radio frequency systems.

[0118] In this embodiment, in the step of forming the sealing layer 3032, the sealing layer 3032 is formed on top of the buffer layer 304, covering part of the top of the buffer layer 304 and the sidewall of the buffer layer 304 away from the working area 300A, and covering the interface between the buffer layer 304 and the substrate 300. This makes the interface between the buffer layer 304 and the substrate 300 blocked by the sealing layer 3032, making it difficult for external moisture to pass through the gap between the buffer layer 304 and the substrate 300 and enter the first cavity 305. This avoids oxidation and corrosion of the device structure 302, which is beneficial to improving the reliability of the filter performance and enabling the filter to meet the requirements of high-performance radio frequency systems.

[0119] In this embodiment, the step of forming the first connection layer 303 includes: forming a second seed material layer on the buffer layer 304 and the substrate 300 in the interconnect region; performing patterning processing on the second seed material layer to form a second seed layer; forming a first connection material layer on the second seed layer; and patterning the first connection material layer to form the first connection layer 303, wherein the first connection layer 303 includes an interconnect layer 3031 and a sealing layer 3032 located around the interconnect layer 3031.

[0120] In this embodiment, a chemical electroplating process is used to form the second seed material layer. In other embodiments, a physical vapor deposition process, a vacuum evaporation process, or a chemical vapor deposition process may also be used to form the second seed material layer.

[0121] In this embodiment, an electroplating process is used to form a first connecting material layer on the second seed layer.

[0122] In other embodiments, the sealing layer may also be formed only on top of the buffer layer.

[0123] This invention provides a resonator. (Reference) Figure 15 The diagram shows a structural schematic of the first embodiment of the resonator of the present invention.

[0124] The filter includes: a substrate 100, the substrate 100 including a working region 100A and an interconnect region 100B surrounding the working region 100A; a device structure 102 located on the substrate 100 of the working region 100A; a first interconnect layer 103 located on the substrate 100 of the interconnect region 100B, the first interconnect layer 103 including an interconnect layer and an annular sealing layer 1032 surrounding the interconnect layer, the interconnect layer 1031 being electrically connected to the device structure 102; an encapsulation layer 104 located on the first interconnect layer 103, the encapsulation layer 104, the sealing layer 1032, and the substrate 100 forming a first cavity 105, the edge of the encapsulation layer 104 being located on the top surface of the sealing layer 1032; and a protective layer 109 covering the interface between the sealing layer 1032 and the encapsulation layer 104, and the interface between the sealing layer 1032 and the substrate 100.

[0125] In the filter provided in this embodiment of the invention, an encapsulation layer 104 is located on the first connection layer 103. The encapsulation layer 104, the sealing layer 1032, and the substrate 100 form a first cavity 105. A protective layer 109 covers the interface between the sealing layer 1032 and the encapsulation layer 104, and the interface between the sealing layer 1032 and the substrate 100. The protective layer 109 can strengthen the bonding force between the sealing layer 1032 and the encapsulation layer 104, and between the sealing layer 1032 and the substrate 100, so that in high temperature and high humidity environments, the sealing layer 1032... Delamination is less likely to occur between the sealing layer 1032 and the substrate 100, and between the sealing layer 1032 and the encapsulation layer 104. Furthermore, even if delamination occurs between the sealing layer 1032 and the substrate 100, and between the sealing layer 1032 and the encapsulation layer 104, the protective layer 109 can prevent external moisture from passing through the gap between the sealing layer 1032 and the substrate 100 and entering the first cavity 105 of the filter, thus avoiding oxidation and corrosion of the device structure 102. This is beneficial to improving the reliability of the filter performance and enabling the filter to meet the requirements of high-performance radio frequency systems.

[0126] In this embodiment, the substrate 100 is a wafer-level substrate 100. By using a wafer-level substrate 100, wafer-level fabrication processes can be implemented in the filter formation method, which can reduce process costs and enable mass production, thereby improving the production efficiency of filter manufacturing.

[0127] In this embodiment, the substrate 100 is a wafer-level substrate 100. Therefore, the substrate 100 includes a plurality of device unit regions (not shown), and each device unit region includes an interconnect region 100B surrounding the working region 100A.

[0128] In this embodiment, the substrate 100 of the working area 100A of each device unit region has a second cavity 101, which is a bulk acoustic wave filter structure. In other embodiments, the filter is a surface acoustic wave filter, and the substrate of the working area of ​​each device unit region may not have a second cavity.

[0129] The substrate 100 includes a working area 100A, which is the region where the device structure 102 operates. Specifically, the working area 100A is the working area where the filter performs its filtering function.

[0130] In this embodiment, the filter includes a first cavity 105 and a second cavity 101, forming a bulk acoustic wave (BAW) filter. Specifically, the bulk acoustic wave resonator can be a diaphragm-type thin-film bulk acoustic resonator (FBAR). In other embodiments, the bulk acoustic wave filter can also be a reflective array bulk acoustic resonator (BAW-SMR) or an air-gap type thin-film bulk acoustic resonator.

[0131] The device structure 102 is used to realize the mutual conversion between electrical signals and acoustic signals, thereby enabling the filter to filter the signals. Specifically, the device structure 102 is an acoustic transducer with a piezoelectric stack structure, which includes a first electrode (not shown in the figure), a piezoelectric film (not shown in the figure) located on the first electrode, and a second electrode (not shown in the figure) located on the piezoelectric film.

[0132] In other embodiments, the final filter may also be a surface acoustic wave (SAW) filter. The substrate of each device unit region may also not have a second cavity.

[0133] Accordingly, the substrate is a piezoelectric substrate, enabling subsequent filters to utilize the piezoelectric effect for filtering. In this embodiment, the substrate material is lithium niobate (LiNbO3), lithium tantalate (LiTaO3), AlN, AlN-doped semiconductor materials, quartz, piezoelectric crystals, or piezoelectric ceramics. The piezoelectric crystals include, but are not limited to, quartz crystals, potassium sodium tartrate, and lithium niobate crystals. The piezoelectric ceramic layer material includes, but is not limited to, barium titanate, lead zirconate titanate, modified lead zirconate titanate, lead metaniobate, lithium lead barium niobate, and modified lead titanate. Lithium niobate or lithium tantalate can provide a very high electromechanical coupling coefficient, enabling the manufacture of filters exhibiting approximately 50% relative bandwidth.

[0134] The device structure is an interdigital transducer (IDT). The IDT includes two sets of interdigital electrodes with energy conversion functions: an input interdigital transducer and an output interdigital transducer. When the input interdigital transducer receives an electrical signal, the surface of the piezoelectric substrate vibrates, exciting an acoustic wave of the same frequency as the applied signal. This acoustic wave propagates along the surface of the piezoelectric substrate, and a portion of the acoustic wave is transmitted to the output interdigital transducer. The output interdigital transducer converts the mechanical vibration into an electrical signal, which is then output.

[0135] The interconnect layer 1031 is electrically connected to the device structure 102. The interconnect layer 1031 serves as an input / output (I / O) terminal for the device structure 102, connecting it to an external circuit structure. The sealing layer 1032 protects the interconnect layer 1031 and the device structure from the side, reducing the probability of moisture entering the working area 100A. Consequently, it reduces the probability of oxidation and corrosion of the device structure in the working area 100A and the interconnect structure in the interconnect area 100B. It also reduces the probability of oxidation and corrosion of the interconnect layer 1031.

[0136] In this embodiment, the material of the first interconnect layer 103 includes one or more of Ti, Cu, Al, and Ni. Specifically, Ti, Cu, Al, and Ni are all conductive materials, enabling the device structure in the working area 100A to be electrically connected to the external power distribution structure through the interconnect layer 1031. As an example, the material of the interconnect layer 1031 is Al.

[0137] It should be noted that the thickness of the interconnect layer 1031 should not be too large or too small. If the thickness of the interconnect layer 1031 is too large, it increases the difficulty of forming the first connection layer 103; if the thickness of the interconnect layer 1031 is too small, it is easy to cause the effective height of the first cavity 105 in the working area 100A to be too small. Correspondingly, after the encapsulation layer 104 is deformed by external force, the probability of the encapsulation layer 104 contacting the device structure 102 increases, thereby reducing the reliability of the filter. Therefore, in this embodiment, the thickness of the interconnect layer 1031 is 2 micrometers to 30 micrometers.

[0138] The material of the sealing layer 1032 is the same as that of the first connecting layer 103, and the material of the sealing layer 1032 also includes one or more of Ti, Cu, Al and Ni.

[0139] The sealing layer 1032 is made of metal. Because metal atoms are closely packed, the sealing layer 1032 has good density and can effectively seal the filter. The sealing layer 1032 and the interconnect layer 1031 are made of the same material, which allows the sealing layer 1032 and the interconnect layer 1031 to be etched in the same step as the first interconnect material layer. This simplifies the filter fabrication process and improves efficiency.

[0140] In this embodiment, the sealing layer 1032 and the interconnect layer 1031 are formed in the same step, therefore the thickness of the sealing layer 1032 is the same as the thickness of the interconnect layer 1031. The thickness of the sealing layer 1032 is 2 micrometers to 30 micrometers. The height difference between the sealing layer 1032 and the interconnect layer 1031 is less than 3 micrometers.

[0141] In this embodiment, the distance w1 between the sealing layer 1032 and the interconnect layer 1031 (e.g., ...) Figure 15 The distance (as shown) is greater than 2 micrometers, such as 5 micrometers or 8 micrometers. In one embodiment, this distance is 3-10 micrometers. If the distance is too small, it can easily cause a short circuit; if the distance is too large, the resulting packaged device will occupy a large space, which is not conducive to chip miniaturization. Within the range allowed by the process, the smaller the distance difference, the more beneficial it is to the miniaturization of the package. In this embodiment, the width w2 of the sealing layer 1032 (as shown) is greater than 2 micrometers, such as 5 micrometers or 8 micrometers. Figure 15 (As shown) is greater than 10 micrometers, such as 15 micrometers or 25 micrometers. In one embodiment, the width of the sealing layer 1032 is 20-40 micrometers, such as 30 micrometers. The width of the sealing layer 1032 determines the bonding strength between the sealing layer and the encapsulation. The wider the width, the greater the bonding strength, and the stronger the ability to prevent moisture from entering the cavity. Based on the size of the encapsulation layer, a suitable width is selected by comprehensively considering the bonding strength and the area occupied by the sealing layer.

[0142] It should be noted that there are multiple interconnect layers 1031; and the multiple interconnect layers 1031 are spaced apart, so that the multiple interconnect layers 1031 do not contact each other, thus making the multiple interconnect layers 1031 disconnected. As an example, the figure shows two interconnect layers 1031, one for electrical connection with the first electrode of the piezoelectric stack structure, and the other for electrical connection with the second electrode of the piezoelectric stack structure.

[0143] As an example, two interconnect layers 1031 are located on both sides of the working area 100A.

[0144] The sealing layer 1032 is spaced apart from the interconnecting layer 1031, or the sealing layer 1032 is only connected to one interconnecting layer 1031, so that the sealing layer 1032 and the interconnecting layer 1031 are in an open circuit state, and the sealing layer 1032 cannot play the role of electrical connection.

[0145] It should be noted that when the sealing layer 1032 is connected to one interconnect layer 1031 and disconnected from another interconnect layer 1031, an insulating layer (not shown in the figure) is formed at the bottom of the interconnect layer 1031 connected to the sealing layer 1032, which is used to electrically isolate it from the substrate 100 and avoid affecting the working performance of the piezoelectric stack structure.

[0146] It should be noted that the sealing layer 1032 is annular, that is, the sealing ring 1032 surrounds the interconnect layer, which helps to improve the airtightness of the first cavity formed with the encapsulation layer 1032.

[0147] The encapsulation layer 104 encapsulates the filter and serves to seal and prevent moisture, thereby improving the reliability of the filter. Moreover, by sealing the first cavity 105, it is also beneficial to isolate the first cavity 105 from the external environment, thereby maintaining the stability of the acoustic performance of the device structure 102.

[0148] In this embodiment, the encapsulation layer 104 includes an opening 107 exposing the interconnect layer 1031. The opening 107 provides space for the interconnect pillars 111.

[0149] In this embodiment, the encapsulation layer 104 is made of a photosensitive material. Patterning the encapsulation material layer using photolithography reduces the difficulty of patterning the encapsulation material layer and forming the encapsulation layer 104. Specifically, the photosensitive material is a dry film. Dry film is a permanent bonding film with high adhesive strength, ensuring the bonding strength between the encapsulation layer 104 and the interconnect layer 1031 and sealing layer 1032. Simultaneously, it improves the sealing performance of the first cavity 105.

[0150] In this embodiment, the photosensitive material is a film-like dry film, which simplifies the process of forming the encapsulation layer 104. In this embodiment, the encapsulation layer 104 is formed using a lamination process. This lamination process is performed in a vacuum environment, providing excellent step coverage and significantly improving the adhesion and bonding strength between the encapsulation layer 104 and the interconnect layer 1031 and sealing layer 1032.

[0151] In other embodiments, a liquid dry film can also be used to form the encapsulation layer, wherein the liquid dry film refers to a film in which the components exist in a liquid form. Accordingly, the steps for forming the encapsulation layer include: coating the liquid dry film using a spin-coating process; and curing the liquid dry film to form the encapsulation layer. The cured liquid dry film is also a photosensitive material. In other embodiments, the material of the encapsulation layer can also be a dielectric material or an organic material. Accordingly, the encapsulation layer can be formed using a deposition process or a coating process, respectively. The dielectric material can be silicon oxide, phosphosilicate glass (PSG), or borosilicate glass (BPSG), and the organic material can be polyimide.

[0152] It should be noted that the edge of the encapsulation layer 104 is located on the top surface of the sealing layer, so that the protective layer 309 can cover the interface between the sealing layer 1032 and the encapsulation layer 104.

[0153] It should be noted that the thickness of the encapsulation layer 104 should not be too large or too small. If the thickness of the encapsulation layer 104 is too large, it increases the difficulty of removing the encapsulation layer 104 during the formation of the opening, and also makes the size of the opening formed in the encapsulation layer 104 larger. Consequently, the overall area of ​​the filter increases, resulting in excessive waste of encapsulation layer 104 material and increasing process costs. If the thickness of the encapsulation layer 104 is too small, it is easy for the encapsulation layer 104 to withstand external pressure, and the central area of ​​the encapsulation layer 104 is prone to collapse, which reduces the airtightness and waterproof performance of the encapsulation layer 104, thus placing higher demands on the subsequent manufacturing process and application environment of the filter. Therefore, in this embodiment, the thickness of the encapsulation layer 104 is 5 micrometers to 60 micrometers.

[0154] The filter further includes: interconnecting posts 111, located at the opening 107 (e.g., ...). Figure 6 As shown, it is connected to the interconnect layer 1031.

[0155] In this embodiment, the interconnect pillars 111 are made of one or more of the following materials: copper, nickel, gold, and silver.

[0156] In this embodiment, the material of the protective layer 109 includes one or more of copper, nickel, gold, and silver. The protective layer 109 is made of metal, and the metal atoms in the protective layer 109 are closely arranged, resulting in good density. This makes it difficult for external moisture to penetrate the protective layer 109 and enter the first cavity of the filter, preventing oxidation and corrosion of the device structure and improving the reliability of the filter performance.

[0157] It should be noted that the protective layer 109 should not be too thick or too thin. If the protective layer 109 is too thick, it will require excessive processing time and materials, resulting in low formation efficiency and high cost. If the protective layer 109 is too thin, its effect in preventing external moisture from entering the first cavity 105 will be ineffective. External moisture can pass through the gap between the sealing layer 1032 and the substrate 100 and enter the first cavity 105 of the filter, causing oxidation and corrosion of the device structure, reducing the reliability of the filter performance, and preventing the filter from meeting the requirements of a high-performance RF system. In this embodiment, the thickness of the protective layer 109 is 0.5 micrometers to 10 micrometers.

[0158] It should be noted that the filter further includes a first seed layer 110, located between the protective layer 109 and the sealing layer 1032. The first seed layer 110 is also located between the interconnect pillar 111 and the encapsulation layer 104.

[0159] The first seed layer 110 provides a good interface state for forming the protective layer 109 and the interconnect pillars 111. In this embodiment, the material of the first seed layer 110 includes one or more of Ti, Cu, Ta, TiN, and Al.

[0160] The first seed layer 110 is a stacked structure. As an example, its structure includes: a 100-nanometer titanium layer and a 200-nanometer copper layer on the titanium layer, or a 200-nanometer titanium layer and a 500-nanometer copper layer.

[0161] The filter further includes a metal bump stack 112 located on top of the interconnect post 111. The metal bump stack 112 is used to prepare for connection of the interconnect post 111 to an external circuit.

[0162] In this embodiment, the material of the metal bump stack 112 includes a copper layer and a nickel layer located on the copper layer. In other embodiments, the metal bump stack 112 may also include only a copper layer.

[0163] It should be noted that the filter also includes a tin-silver alloy layer 113 (SnAg) located on the metal bump stack 112.

[0164] like Figure 14As shown, based on the protective layer structure of the first embodiment of the filter, another electrical connection structure of the filter is illustrated. The similarities with the first embodiment of the filter will not be repeated here. The difference from the first embodiment is that an interconnection structure 211 is formed in the opening 207. The interconnection structure 211 is located on the bottom surface and side wall of the opening 207, as well as part of the top of the sealing layer 2032.

[0165] Interconnection structure 211 is used to electrically connect the interconnection layer at the bottom of opening 207 to the external circuit structure.

[0166] In this embodiment, the interconnect structure 211 is a multilayer structure, including: a copper layer, a nickel layer on the copper layer, and a gold layer on the nickel layer. Gold is an inert metal with good oxidation and corrosion resistance, and can protect the metal it covers. In other embodiments, the interconnect structure may also be a copper layer, and an electroless nickel-gold plating or an electroless nickel-palladium-gold plating on the copper layer. Electroless nickel-gold plating and electroless nickel-palladium-gold plating are both inert metals with good oxidation and corrosion resistance, and can protect the metal they cover.

[0167] refer to Figure 18 The diagram shows a schematic representation of the resonator of the second embodiment of the present invention. The similarities between this embodiment and the first embodiment will not be repeated here; the differences are as follows:

[0168] The filter further includes: a buffer layer 304 located on the interconnect region 300B of the substrate 300; an interconnect layer 3031 located on top of the buffer layer 304 and covering the sidewall of the buffer layer 304 near the working region 300A, and extending to the working region 300A to be electrically connected to the device structure 302; a sealing layer 3032 located on top of the buffer layer 304; or the sealing layer 3032 covers a portion of the top of the buffer layer 304 and the sidewall of the buffer layer 304 away from the working region 300A, and covers the interface between the buffer layer 304 and the substrate 300.

[0169] The buffer layer 304 is located between the sealing layer 3032 and the substrate 300. The buffer layer 304 serves to buffer the thermal stress between the substrate 300 and the sealing layer 3032. Therefore, during thermal processes (baking, reflow, or temperature cycling), the substrate 300 and the buffer layer 304, and the buffer layer 304 and the sealing layer 3032 are less likely to delaminate or break due to thermal stress. In addition, even if delamination occurs between the sealing layer 3032 and the substrate 300, and between the sealing layer 3032 and the encapsulation layer 306, the protective layer 309 can prevent external moisture from passing through the gap between the sealing layer 3032 and the substrate 300 and entering the first cavity 305 of the filter, avoiding oxidation and corrosion of the device structure 302. This helps to improve the reliability of the filter performance and enables the filter to meet the requirements of high-performance radio frequency systems.

[0170] In this embodiment, a sealing layer 3032 is formed on top of the buffer layer 304, covering part of the top of the buffer layer 304 and the sidewall of the buffer layer 304 away from the working area 300A, and covering the interface between the buffer layer 304 and the substrate 300. This prevents external moisture from easily passing through the gap between the buffer layer 304 and the substrate 300 and entering the first cavity 105, thus avoiding oxidation and corrosion of the device structure 302. This improves the reliability of the filter performance and enables the filter to meet the requirements of a high-performance radio frequency system.

[0171] The buffer layer 304 is made of a material with a coefficient of thermal expansion between that of the substrate 300 and the sealing layer 3032, giving the buffer layer 304 excellent buffering performance. Silicon has a coefficient of thermal expansion of 3.5 ppm / ℃, copper has a coefficient of thermal expansion of 17.5 ppm / ℃, and the buffer layer 304 has a coefficient of thermal expansion between 3.5 ppm / ℃ and 17.5 ppm / ℃.

[0172] The buffer layer 304 can also be a material with a Young's modulus lower than 1.0E11 Pa. In this embodiment, the substrate 300 is made of silicon, which has a Young's modulus of 1.1E11 Pa. The sealing layer 3032 and the interconnect layer 3031 are made of copper, which has a Young's modulus of 1.7E11 Pa. The buffer layer 304 has a Young's modulus lower than that of the substrate 300, the sealing layer 3032, and the interconnect layer 3031. During thermal processes (baking, reflow, or temperature cycling), it can buffer the substrate 300 and the sealing layer 3032, as well as the interconnect layer 3031.

[0173] In this embodiment, the buffer layer 304 is made of a photosensitive material and is patterned using photolithography. This helps reduce damage to the substrate 300 during the formation of the buffer layer 304, thereby improving the electrical performance of the filter. As an example, the buffer layer 304 is made of polyimide, which has a Young's modulus lower than 3E9 Pa. In other embodiments, the buffer layer material further includes silicon oxide, which has a Young's modulus of 7E10 Pa. In still other embodiments, the buffer layer material may also include silicon nitride, phosphosilicate glass, etc.

[0174] In other embodiments, the sealing layer may also be located only on top of the buffer layer.

[0175] In this embodiment, the filter can be formed using the formation method of the foregoing embodiments, or it can be formed using other formation methods. For a detailed description of the filter in this embodiment, please refer to the corresponding descriptions in the foregoing embodiments; these descriptions will not be repeated here.

[0176] Accordingly, embodiments of the present invention also provide an electronic device, the electronic device including the filter described in the foregoing embodiments.

[0177] The filter can be integrated into various electronic devices. As the foregoing analysis shows, the filter has high reliability, which correspondingly enables the development of highly reliable electronic devices. These electronic devices can also include personal computers, smartphones and other mobile terminals, media players, navigation devices, video game devices, game controllers, tablet computers, wearable devices, security access control systems, POS terminals, medical devices, flight simulators, etc.

[0178] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A filter, characterized in that, include: A substrate, the substrate including a working region and an interconnect region surrounding the working region; A buffer layer is located on the interconnect region of the substrate; the material of the buffer layer is a material with a coefficient of thermal expansion between that of the substrate and the sealing layer. The device structure is located on the substrate of the working area; A first interconnect layer is located on the substrate of the interconnect region. The first interconnect layer includes an interconnect layer and an annular sealing layer surrounding the interconnect layer. The interconnect layer is electrically connected to the device structure, and the sealing layer surrounds the interconnect layer. The interconnect layer is located on top of the buffer layer and covers the sidewall of the buffer layer near the working area, and extends to the working area to be electrically connected to the device structure. The sealing layer is located on top of the buffer layer. Alternatively, the sealing layer covers a portion of the top of the buffer layer and the sidewall of the buffer layer away from the working area, and covers the interface between the buffer layer and the substrate. An encapsulation layer is located on the first connection layer. The encapsulation layer, the sealing layer, and the substrate form a first cavity. The edge of the encapsulation layer is located on the top surface of the sealing layer. A protective layer covers the interface between the sealing layer and the encapsulation layer, as well as the interface between the sealing layer and the substrate.

2. The filter as described in claim 1, characterized in that, The material of the buffer layer includes silicon oxide, polyimide, silicon nitride, or phosphosilicate glass.

3. The filter as described in claim 1, characterized in that, The protective layer is made of one or more of copper, nickel, gold, and silver.

4. The filter as described in claim 1, characterized in that, The thickness of the protective layer is 0.5 micrometers to 10 micrometers.

5. The filter as described in claim 1, characterized in that, The number of interconnect layers is multiple, and the multiple interconnect layers are spaced apart; The sealing layer is spaced apart from the interconnecting layer, or the sealing layer is connected to only one of the interconnecting layers.

6. The filter as described in claim 1, characterized in that, The encapsulation layer includes an opening that exposes the interconnect layer; The filter further includes an interconnect pillar located in the opening and connected to the interconnect layer.

7. The filter as described in claim 6, characterized in that, The filter further includes: an interconnect structure located on the bottom and sidewalls of the opening, and on top of the sealing layer.

8. The filter as described in claim 6, characterized in that, The filter further includes a metal bump stack located on top of the interconnect pillars.

9. The filter as described in claim 1, characterized in that, The filter includes a surface acoustic wave filter; Alternatively, the working area of ​​the substrate may also have a second cavity, which is covered by the device structure, and the filter may include a bulk acoustic wave filter.

10. A method for forming a filter, characterized in that, include: A substrate is provided, the substrate including a working region and an interconnect region surrounding the working region, and a device structure is formed on the substrate of the working region; A buffer layer is formed on the substrate of the interconnect region; the material of the buffer layer is a material whose coefficient of thermal expansion is between that of the substrate and the sealing layer. A first interconnect layer is formed on the substrate of the interconnect region. The first interconnect layer includes an interconnect layer and an annular sealing layer surrounding the interconnect layer. The interconnect layer is electrically connected to a device structure, and the sealing layer surrounds the interconnect layer. In the step of forming the first interconnect layer on the substrate of the interconnect region, the interconnect layer is formed on top of a buffer layer and covers the sidewall of the buffer layer near the working area, and extends to the working area to be electrically connected to the device structure; the sealing layer is formed on top of the buffer layer; or the sealing layer is formed on top of the buffer layer, covering a portion of the top of the buffer layer and the sidewall of the buffer layer away from the working area, and covering the interface between the buffer layer and the substrate. An encapsulation layer is formed on the first connection layer, and the encapsulation layer, the sealing layer and the substrate form a first cavity, with the edge of the encapsulation layer located on the top surface of the sealing layer; A protective layer is formed covering the interface between the sealing layer and the encapsulation layer, as well as the interface between the sealing layer and the substrate.

11. The method for forming a filter as described in claim 10, characterized in that, The material of the buffer layer includes silicon oxide, polyimide, silicon nitride, or phosphosilicate glass.

12. The method for forming a filter as described in claim 10, characterized in that, The protective layer is made of one or more of copper, nickel, gold, and silver.

13. The method for forming a filter as described in claim 10, characterized in that, In the step of forming a first interconnect layer on the substrate of the interconnect region, the number of interconnect layers is multiple, and the multiple interconnect layers are spaced apart; The sealing layer is spaced apart from the interconnecting layer, or the sealing layer is connected to only one interconnecting layer.

14. The method for forming a filter as described in claim 10, characterized in that, In the step of forming an encapsulation layer on the first interconnect layer, the encapsulation layer includes an opening exposing the interconnect layer; The method for forming the filter further includes: after forming the protective layer, forming an interconnect post connected to the interconnect layer in the opening; and after forming the interconnect post, forming a metal bump stack on top of the interconnect post.

15. The method for forming a filter as described in claim 14, characterized in that, The steps for forming the protective layer include: A first seed layer is formed to conformally cover the top and sidewalls of the encapsulation layer, the top and sidewalls of the sealing layer, and the substrate; A first shielding layer is formed on the first seed layer, the first shielding layer covering the opening and exposing the interface between the encapsulation layer and the sealing layer, as well as the interface between the sealing layer and the substrate; A protective layer is formed in the area exposed by the first shielding layer.

16. The method for forming a filter as described in claim 10, characterized in that, In the step of forming an encapsulation layer on the first interconnect layer, the encapsulation layer includes an opening exposing the interconnect layer; In the step of forming the protective layer, an interconnection structure is formed on the bottom surface and sidewalls of the opening, and on the top of the sealing layer.

17. The method for forming a filter as described in claim 16, characterized in that, The steps of forming the protective layer and the interconnect structure include: A first seed layer is formed to conformally cover the top and sidewalls of the encapsulation layer, the top and sidewalls of the sealing layer, and the substrate; A second shielding layer is formed on the first seed layer, the second shielding layer exposing the top of the opening and the sealing layer, the interface between the sealing layer and the encapsulation layer, and the interface between the sealing layer and the substrate; An electroplated layer is formed in the area exposed by the second shielding layer. The electroplated layer located in the opening and on top of the sealing layer portion serves as the interconnect structure. The electroplated layer located at the interface between the sealing layer and the encapsulation layer, and at the interface between the sealing layer and the substrate, serves as the protective layer. The method for forming the filter further includes: after forming the interconnect structure and the protective layer, removing the second shielding layer.

18. An electronic device, characterized in that, Includes the filter as described in any one of claims 1 to 9.

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