Video frame decoding method, chip and storage medium

Abstract

The present application discloses a method, chip, and storage medium for decoding a video frame. The method includes: receiving first decoding information sent by a CPU; the first decoding information includes a first video frame and a hard decoding instruction; responding to the hard decoding instruction to obtain a first CDF table required for decoding the first video frame; and decoding the first video frame using the first CDF table to obtain a decoded video frame. Thus, in the present application, the CPU is responsible for preparing the first video frame and the hard decoding instruction, and the hardware decoding chip is responsible for responding to the hard decoding instruction to obtain the first CDF table required for decoding the first video frame, and using the first CDF table to complete hardware decoding of the first video frame. Therefore, during the decoding process of the hardware decoding chip, the CPU can prepare multiple video frames and corresponding hard decoding instructions in advance, so that after the hardware decoding chip decodes the first video frame, it can immediately decode the next first video frame. In this way, the hardware decoding chip can work continuously, effectively improving the system hardware decoding performance.

Description

Technical Field

[0001] The present application relates to decoding technology, and in particular to a video frame decoding method, chip, and storage medium. Background Art

[0002] Video decoding performed using an application-specific integrated circuit (ASIC) is called hardware decoding. When an existing ASIC decodes video frames using the VP9 or AV1 decoding format, the cumulative distribution function (CDF) table required for decoding the video frame is the CDF table of the specified reference frame corresponding to the video frame. Therefore, the ASIC sends the CDF table output after decoding the current video frame to the central processing unit (CPU). The CPU obtains the CDF table of the specified reference frame (e.g., the current video frame) required for decoding the next video frame and sends it to the ASIC, which then uses this CDF table to decode the next video frame. This means that the CPU and ASIC operate in series, which inevitably leads to ASIC inactivity, resulting in reduced system hardware decoding performance. Summary of the Invention

[0003] The present application aims to provide a video frame decoding method, chip and storage medium.

[0004] The technical solution of this application is achieved as follows:

[0005] In a first aspect, a method for decoding a video frame is provided, which is applied to a hardware decoding chip, and the method comprises:

[0006] Receive first decoding information sent by a central processing unit (CPU); wherein the first decoding information includes a first video frame and a hard decoding instruction;

[0007] In response to the hard decoding instruction, obtaining a first cumulative distribution function (CDF) table required for decoding the first video frame;

[0008] The first video frame is decoded using a first CDF table to obtain a decoded video frame.

[0009] In a second aspect, a hardware decoding chip is provided, the hardware decoding chip comprising:

[0010] A receiving unit, configured to receive first decoding information sent by a central processing unit (CPU); wherein the first decoding information includes a first video frame and a hard decoding instruction;

[0011] an acquiring unit, configured to respond to the hard decoding instruction and acquire a first cumulative distribution function (CDF) table required for decoding the first video frame;

[0012] A decoding unit is configured to decode the first video frame using a first CDF table to obtain a decoded video frame.

[0013] In a third aspect, a hardware decoding chip is provided, comprising: a processor and a memory configured to store a computer program that can be run on the processor, wherein the processor is configured to execute the steps of the method of the first aspect when running the computer program.

[0014] According to a fourth aspect, a computer-readable storage medium is provided, on which a computer program is stored, wherein the computer program implements the steps of the method according to the first aspect when executed by a processor.

[0015] The present application discloses a method, chip and storage medium for decoding a video frame. In the present application, the CPU is responsible for preparing a first video frame and a hard decoding instruction. The hardware decoding chip is responsible for responding to the hard decoding instruction, obtaining a first CDF table required for decoding the first video frame, and using the first CDF table to complete the hardware decoding of the first video frame. Therefore, during the decoding process of the hardware decoding chip, the CPU can prepare multiple video frames and corresponding hard decoding instructions in advance, so that after the hardware decoding chip decodes the first video frame, it can immediately decode the next first video frame. In this way, the hardware decoding chip can work continuously, effectively improving the system hardware decoding performance, while also ensuring the smoothness of video playback. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 1 is a schematic diagram of a first flow chart of a method for decoding a video frame in an embodiment of the present application;

[0017] Figure 2 Schematic diagram of a second flow chart of a method for decoding a video frame according to an embodiment of the present application;

[0018] Figure 3 Schematic diagram of a third flow chart of a method for decoding a video frame in an embodiment of the present application;

[0019] Figure 4 Schematic diagram of the fourth flow chart of the method for decoding a video frame in an embodiment of the present application;

[0020] Figure 5 This is a first schematic diagram of the composition structure of the hardware decoding chip in an embodiment of the present application;

[0021] Figure 6 This is a second schematic diagram of the hardware decoding chip structure in an embodiment of the present application. DETAILED DESCRIPTION

[0022] In order to enable a more detailed understanding of the features and technical contents of the embodiments of the present application, the implementation of the embodiments of the present application is described in detail below with reference to the accompanying drawings. The attached drawings are for reference only and are not used to limit the embodiments of the present application.

[0023] The embodiment of the present application provides a method for decoding a video frame. Figure 1 This is a first flow chart of a method for decoding video frames in an embodiment of the present application, which is applied to a hardware decoding chip. Here, the hardware decoding chip is used to perform hardware decoding on the video frames. Through hardware decoding, most decoding tasks can be transferred to a dedicated hardware decoding chip, reducing the computational burden of the CPU and improving the response speed of the system; in addition, the hardware decoding chip can decode video data faster, thereby improving the efficiency and smoothness of video playback. Exemplarily, the hardware decoding chip can be an application-specific integrated circuit chip ASIC, a field-programmable gate array (FPGA), or other logic circuit chips with the same function.

[0024] like Figure 1 As shown, the decoding method of the video frame may specifically include:

[0025] Step 101: Receive first decoding information sent by a central processing unit (CPU); wherein the first decoding information includes a first video frame and a hard decoding instruction.

[0026] Step 102: Responding to a hard decoding instruction, obtaining a first cumulative distribution function (CDF) table required for decoding the first video frame.

[0027] It should be noted that the type of the first video frame generally includes Class I and Non-Class I. Different types of first video frames require different methods for obtaining the first CDF table. Here, when the first video frame is the first video frame among multiple video frames, the type of the first video frame is Class I. When the first video frame is any video frame other than the first video frame among multiple video frames, the type of the first video frame is Non-Class I (specifically, including Class B and Class P).

[0028] In some embodiments, obtaining a first cumulative distribution function (CDF) table required for decoding the first video frame includes:

[0029] When the type of the first video frame is type I, obtaining an initial CDF table defined by the standard;

[0030] The initial CDF table is used as a first CDF table required for decoding the first video frame.

[0031] Here, the type of the first video frame is Class I, that is, the first video frame is the first video frame among multiple video frames. Since the first video frame has no reference frame, the CDF table required for decoding the first video frame is the initial CDF table. Therefore, it is necessary to obtain the initial CDF table defined by the standard.

[0032] In some embodiments, obtaining a first cumulative distribution function (CDF) table required for decoding the first video frame includes:

[0033] When the type of the first video frame is non-type I, obtaining a first CDF table required for decoding the first video frame from a first CDF table sequence;

[0034] The first CDF table sequence includes a CDF table corresponding to a reference frame of the first video frame.

[0035] Here, the first video frame is of non-Class I type, meaning it is a video frame other than the first video frame among the multiple video frames. Because the other video frames have corresponding reference frames, the first CDF table required for decoding the first video frame can be obtained from the CDF table corresponding to the reference frame (or at least one reference frame) of the first video frame. In practical applications, the first CDF table is specifically specified by primary_ref_frame.

[0036] For example, if the currently used codec format is the AV1 format, and the AV1 format stipulates that each frame can have 7 reference frames, each reference frame has a corresponding CDF table. That is to say, each frame has at least 1 reference frame and a maximum of 7 reference frames. Here, considering that a certain frame has 7 reference frames, the first CDF table sequence includes CDF tables for 7 reference frames. Of course, if the number of reference frames of a certain frame is less than 7, for example 2, it means that only 2 serial number positions in the first CDF table sequence store CDF tables, and the remaining serial number positions have no CDF tables, that is, they are empty. It should be noted that the present application is not limited to the AV1 format, but can also be AP9, AV2, VVC and other codec formats.

[0037] Step 103: Decode the first video frame using the first CDF table to obtain a decoded video frame.

[0038] In some embodiments, the method further includes: during the decoding process, updating the first CDF table to obtain a new first CDF table.

[0039] Here, the execution entity of steps 101 to 103 may be a processor of a hardware decoding chip.

[0040] Using the above technical solution, in this application, the CPU is responsible for preparing the first video frame and the hard decoding instruction, the hardware decoding chip is responsible for responding to the hard decoding instruction, obtaining the first CDF table required for decoding the first video frame, and using the first CDF table to complete the hardware decoding of the first video frame. Therefore, during the decoding process of the hardware decoding chip, the CPU can prepare multiple video frames and corresponding hard decoding instructions in advance, so that after the hardware decoding chip decodes the first video frame, it can immediately decode the next first video frame. In this way, the hardware decoding chip can work continuously, effectively improving the system hardware decoding performance, while also ensuring the smoothness of video playback.

[0041] In addition, the existing general-purpose operating system based on a general-purpose CPU works in a preemptive manner, and any CPU task may be suspended by a higher-priority task. The smoothness of the system hardware is easily affected. During the hardware decoding process, for example, when the current CPU needs to prepare the next video frame and the corresponding hard decoding instruction, it is suspended, and the recovery time will be very long, which usually causes the video frame to be decoded too late and the video to be not smooth. In this regard, since the CPU is preparing multiple video frames and the corresponding hard decoding instructions during the decoding process of the hardware decoding chip in this application, the two are executed in parallel and do not participate in the decoding execution process. Therefore, even if a higher-priority task is suspended, the CPU has enough time to process the higher-priority task, and it will not affect the decoding process of the hardware decoding chip.

[0042] Based on the above embodiments, the present application specifically proposes a method for decoding a video frame. Figure 2 FIG. 2 is a second flow chart of the method for decoding a video frame in an embodiment of the present application. Figure 2 As shown, the decoding method of the video frame specifically includes:

[0043] Step 201: Receive first decoding information sent by a CPU; wherein the first decoding information includes a first video frame and a hard decoding instruction.

[0044] Step 202: In response to the hard decoding instruction, when the type of the first video frame is Class I, an initial CDF table defined by the standard is obtained; and the initial CDF table is used as a first CDF table required for decoding the first video frame.

[0045] Here, the first video frame may be understood as the first video frame among multiple video frames, and the type of the first video frame is Class I. Since the first video frame has no reference frame, the CDF table required for decoding the first video frame is the initial CDF table, and therefore, the initial CDF table defined by the standard needs to be obtained.

[0046] Step 203: Decode the first video frame using the first CDF table to obtain a decoded video frame.

[0047] Step 204: During the decoding process, the first CDF table is updated to obtain a new first CDF table.

[0048] Step 205: When it is determined that the initial CDF table sequence needs to be updated, the new first CDF table is updated to a specified position in the initial CDF table sequence to obtain a first CDF table sequence.

[0049] Here, the initial CDF table sequence includes the CDF table corresponding to the reference frame of the first video frame. Since the first video frame has no reference frame, the content of the initial CDF table sequence is empty.

[0050] In practice, disable_frame_end_update_cdf is used to determine whether the initial CDF table sequence needs to be updated. If so, the refresh_frame_flag is used to update the new first CDF table to the specified position in the initial CDF table sequence, thereby obtaining the first CDF table sequence. It should be noted that there is no limit to the number of specified positions; it can be one or more, depending on the specific situation.

[0051] For example, if the currently used codec format is AV1, and AV1 specifies that each frame can have seven reference frames, each with a corresponding CDF table. In other words, each frame has at least one reference frame and a maximum of seven reference frames. Here, considering that a certain frame has seven reference frames, an initial CDF table sequence that can include seven CDF tables is pre-established.

[0052] In practice, the hard decode instructions include a first memory copy instruction (Memory to Memory, M2M), a decode instruction, and a second M2M instruction. These three instructions are arranged in order of execution: the first one in the order of execution is executed first, and the second one in the order of execution is executed last. The M2M instruction is used to copy data from source memory to target memory.

[0053] Here, the standard-defined initial CDF table is pre-cached in a preset buffer. Specifically, the hardware decoding chip first responds to the first M2M instruction to copy the standard-defined initial CDF table from the preset buffer to the memory on the hardware decoding chip (corresponding to step 202). Next, in response to the decoding instruction, the first video frame is decoded using the standard-defined initial CDF table (i.e., the first CDF table) (corresponding to steps 203 and 204). Finally, in response to the second M2M instruction, step 205 is executed.

[0054] In some embodiments, after step 203, the method further includes:

[0055] An interrupt instruction and the decoded video frame are sent to the CPU, so that the CPU responds to the interrupt instruction, stops constructing decoding information, and sends the decoded video frame to a display unit for display.

[0056] It should be noted that the CPU is responsible for preparing the first video frame and the hard decoding instruction, the hardware decoding chip is responsible for responding to the hard decoding instruction, obtaining the first CDF table required for decoding the first video frame, and using the first CDF table to complete the hardware decoding of the first video frame. Therefore, during the decoding process of the hardware decoding chip, the CPU can prepare multiple video frames and corresponding hard decoding instructions in advance. However, after the hardware decoding chip ASIC decodes the first video frame, it sends an interrupt instruction and a decoded video frame to the CPU to notify the CPU to stop preparing decoding information (including video frames and hard decoding instructions), and the decoded video frame needs to be sent to the display unit for display.

[0057] In some embodiments, the method further includes: receiving second decoding information sent by the CPU during the display of the decoded video frame.

[0058] That is, when the decoded video frame is displayed on the display unit, the hardware decoding chip receives the second decoding information sent by the CPU and then decodes the next first video frame.

[0059] Figure 3 FIG3 is a third flow chart of the method for decoding a video frame in an embodiment of the present application, as shown in FIG3. Figure 3 As shown, the decoding method of the video frame specifically includes:

[0060] Step 301: Receive second decoding information sent by a CPU; wherein the second decoding information includes a first video frame and a hard decoding instruction.

[0061] Step 302: In response to a hard decoding instruction, when the type of the first video frame is non-Class I, obtain a first CDF table required for decoding the first video frame from a first CDF table sequence; wherein the first CDF table sequence includes a CDF table corresponding to a reference frame of the first video frame.

[0062] Here, the first video frame can be understood as other video frames in multiple video frames except the first video frame, and the types of other video frames are non-I type. Other video frames can include the second video frame, the third video frame, and so on.

[0063] Here, when the second video frame is used as the first video frame, the reference frame of the second video frame is only the first video frame. Therefore, the first CDF table sequence includes the CDF table decoded and output for the first video frame, and the CDF table decoded and output for the first video frame is the first CDF table required for decoding the first video frame.

[0064] Step 303: Decode the first video frame using the first CDF table to obtain a decoded video frame.

[0065] Step 304: During the decoding process, the first CDF table is updated to obtain a new first CDF table.

[0066] Step 305: If it is determined that the first CDF table sequence needs to be updated, update the new first CDF table to a specified position in the first CDF table sequence.

[0067] In actual applications, disable_frame_end_update_cdf is used to determine whether the first CDF table sequence needs to be updated. If so, the new first CDF table is updated to a specified position in the first CDF table sequence according to refresh_frame_flag, thereby obtaining a new first CDF table sequence (i.e., a CDF table including a reference frame (at least one reference frame) of the third video frame). It should be noted that there is no limit to the number of specified positions, and the number can be one or more, depending on the specific situation.

[0068] In practice, the hard decode instructions include a first memory copy instruction (Memory to Memory, M2M), a decode instruction, and a second M2M instruction. These three instructions are arranged in order of execution: the first one in the order of execution is executed first, and the second one in the order of execution is executed last. The M2M instruction is used to copy data from source memory to target memory.

[0069] Here, the standard-defined initial CDF table is pre-cached in a preset buffer. Specifically, the hardware decoding chip first responds to the first M2M instruction by copying the first CDF table required for decoding the first video frame from the first CDF table sequence to memory on the hardware decoding chip (corresponding to step 302). Secondly, in response to the decoding instruction, the first video frame is decoded using the first CDF table (corresponding to steps 303 and 304). Finally, in response to the second M2M instruction, step 305 is executed.

[0070] In some embodiments, after step 303, the method further includes:

[0071] An interrupt instruction and the decoded video frame are sent to the CPU, so that the CPU responds to the interrupt instruction, stops constructing decoding information, and sends the decoded video frame to a display unit for display.

[0072] In some embodiments, the method further includes: receiving second decoding information sent by the CPU during the display of the decoded video frame.

[0073] When there are multiple video frames, steps 301 to 305 are repeatedly executed to finally complete the decoding of the multiple video frames.

[0074] Figure 4 This is a fourth flow chart of the method for decoding a video frame in an embodiment of the present application, as shown in FIG. Figure 4 As shown, the decoding method of the video frame specifically includes:

[0075] start;

[0076] CPU: Sets ASIC registers to store video frame 1 and hard decoding instruction 1, video frame 2 and hard decoding instruction 2, and so on. After starting the ASIC decoding operation, video frame 1 and hard decoding instruction 1 are first sent to the ASIC.

[0077] Wherein, video frame 1 can be understood as the first video frame among the multiple video frames, and video frame 2 can be understood as the second video frame among the multiple video frames;

[0078] ASIC: Video frame 1 is of type I and responds to hard decoding instruction 1. Hard decoding instruction 1 includes a first M2M instruction, a decoding instruction, and a second M2M instruction. These three instructions are arranged in the order of execution. First, the first M2M instruction is responded to, which is used to copy the standard-defined initial CDF table from a preset buffer area to the memory on the hardware decoding chip. Second, in response to the decoding instruction, video frame 1 is decoded using the initial CDF table to obtain decoded video frame 1. During the decoding process, the initial CDF table is updated to obtain a new CDF table.

[0079] ASIC: Then, sends an interrupt instruction and decoded video frame 1 to the CPU, so that the CPU responds to the interrupt instruction, stops compiling decoding information, and sends the decoded video frame 1 to the display unit for display;

[0080] Finally, in response to the second M2M instruction, if it is determined that the initial CDF table sequence needs to be updated, the new CDF table is updated to a specified position in the initial CDF table sequence to obtain a first CDF table sequence;

[0081] CPU: During the display process of decoded video frame 1, it obtains video frame 2 and hard decoding instruction 2 from the ASIC register and sends them to the ASIC;

[0082] ASIC: Video frame 2 is of non-Class I type and responds to hard decoding instruction 2. Hard decoding instruction 2 includes a first M2M instruction, a decoding instruction, and a second M2M instruction. These three instructions are arranged in the order of execution. First, the ASIC responds to the first M2M instruction to obtain the first CDF table required for decoding video frame 2 from the first CDF table sequence. Second, the ASIC responds to the decoding instruction to decode video frame 2 using the first CDF table to obtain decoded video frame 2. During the decoding process, the first CDF table is updated to obtain a new first CDF table.

[0083] ASIC: Then, sends an interrupt instruction and decoded video frame 2 to the CPU, so that the CPU responds to the interrupt instruction, stops compiling decoding information, and sends decoded video frame 2 to the display unit for display;

[0084] Finally, in response to the second M2M instruction, if it is determined that the first CDF table sequence needs to be updated, the new first CDF table is updated to a specified position in the first CDF table sequence.

[0085] When there are multiple video frames, the above steps are repeated to finally complete the decoding of the multiple video frames.

[0086] In this way, during the decoding process of the hardware decoding chip, the CPU can prepare multiple video frames and corresponding hardware decoding instructions in advance, so that after the hardware decoding chip decodes video frame 1, it can immediately decode the next video frame 2, and so on. In this way, the hardware decoding chip can work continuously, effectively improving the system hardware decoding performance, while also ensuring the smoothness of video playback.

[0087] For example, if 30 video frames are transmitted per second, 30 frames need to be decoded. The average CPU time required to prepare the hardware decoding instructions for each frame is Tc = 2ms, and the average hardware decoding time for one frame is Tf = 32ms. The total time required using the technical solution of this application is Tf * 30 + Tc = 962ms, which meets the requirement for smooth playback, that is, the total time required is less than 1s. This ensures the smoothness of video playback.

[0088] In order to implement the method of the embodiment of the present application, based on the same inventive concept, the embodiment of the present application further provides a hardware decoding chip. Figure 5 This is a first schematic diagram of the hardware decoding chip structure in the embodiment of the present application. Figure 5 As shown, the hardware decoding chip 50 includes:

[0089] The receiving unit 501 is configured to receive first decoding information sent by a central processing unit (CPU); wherein the first decoding information includes a first video frame and a hard decoding instruction;

[0090] An acquiring unit 502 is configured to respond to the hard decoding instruction and acquire a first cumulative distribution function (CDF) table required for decoding the first video frame;

[0091] The decoding unit 503 is configured to decode the first video frame using the first CDF table to obtain a decoded video frame.

[0092] Using the above technical solution, in this application, the CPU is responsible for preparing the first video frame and the hard decoding instruction, the hardware decoding chip is responsible for responding to the hard decoding instruction, obtaining the first CDF table required for decoding the first video frame, and using the first CDF table to complete the hardware decoding of the first video frame. Therefore, during the decoding process of the hardware decoding chip, the CPU can prepare multiple video frames and corresponding hard decoding instructions in advance, so that after the hardware decoding chip decodes the first video frame, it can immediately decode the next first video frame. In this way, the hardware decoding chip can work continuously, effectively improving the system hardware decoding performance, while also ensuring the smoothness of video playback.

[0093] In some embodiments, the acquiring unit 502 is specifically configured to acquire, when the type of the to-be-decoded video frame is non-type I, a first CDF table required for decoding the first video frame from a first CDF table sequence;

[0094] The first CDF table sequence includes a CDF table corresponding to a reference frame of the first video frame.

[0095] In some embodiments, the acquiring unit 502 is specifically configured to acquire an initial CDF table defined by a standard when the type of the first video frame is type I;

[0096] The initial CDF table is used as a first CDF table required for decoding the first video frame.

[0097] In some embodiments, an updating unit is further included, configured to update the first CDF table during decoding to obtain a new first CDF table.

[0098] In some embodiments, the updating unit is further configured to update the new first CDF table to a specified position in the second CDF table sequence when it is determined that the second CDF table sequence needs to be updated;

[0099] The second CDF table sequence is the first CDF table sequence or an initial CDF table sequence defined by a standard.

[0100] In some embodiments, a sending unit is further included for sending an interrupt instruction and the decoding result to the CPU, so that the CPU responds to the interrupt instruction, stops assembling the decoding information, and sends the decoding result to the display unit for display.

[0101] In some embodiments, the receiving unit 501 is further configured to receive second decoding information sent by the CPU during the display of the decoding result.

[0102] The present application also provides another hardware decoding chip. Figure 6 This is a second schematic diagram of the hardware decoding chip structure in the embodiment of the present application. Figure 6 As shown, the hardware decoding chip 60 includes: a processor 601 and a memory 602 configured to store a computer program that can be run on the processor;

[0103] The processor 601 is configured to execute the method steps in the aforementioned embodiment when running the computer program.

[0104] Of course, in actual application, Figure 6 As shown, the various components in the hardware decoding chip 60 are coupled together via a bus system 603. It is understood that the bus system 603 is used to achieve connection and communication between these components. In addition to the data bus, the bus system 603 also includes a power bus, a control bus, and a status signal bus. However, for the sake of clarity, Figure 6 Various buses are labeled as bus system 603.

[0105] In practical applications, the processor may be at least one of an application-specific integrated circuit (ASIC), a digital signal processing device (DSPD), a programmable logic device (PLD), a field-programmable gate array (FPGA), a controller, a microcontroller, and a microprocessor. It is understood that for different devices, the electronic device used to implement the functions of the processor may also be other, and the embodiments of the present application do not specifically limit this.

[0106] The above-mentioned memory can be a volatile memory (volatile memory), such as a random-access memory (RAM); or a non-volatile memory (non-volatile memory), such as a read-only memory (ROM), a flash memory, a hard disk (HDD) or a solid-state drive (SSD); or a combination of the above types of memory, and provides instructions and data to the processor.

[0107] In an exemplary embodiment, the present application also provides a computer-readable storage medium for storing a computer program.

[0108] Optionally, the computer-readable storage medium can be applied to any one of the methods in the embodiments of the present application, and the computer program enables the computer to execute the corresponding processes implemented by the processor in each method in the embodiments of the present application. For the sake of brevity, they are not repeated here.

[0109] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely schematic. For example, the division of the units is merely a logical function division. In actual implementation, there may be other division methods, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the components shown or discussed can be through some interfaces, and the indirect coupling or communication connection of the devices or units can be electrical, mechanical or other forms.

[0110] The units described above as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units; some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0111] In addition, the functional units in the embodiments of the present invention can all be integrated into one processing module, or each unit can be a separate unit, or two or more units can be integrated into one unit; the above-mentioned integrated unit can be implemented in the form of hardware or in the form of hardware plus software functional units. It can be understood by those skilled in the art that all or part of the steps of the above-mentioned method embodiments can be completed by hardware related to program instructions, and the above-mentioned program can be stored in a computer-readable storage medium. When the program is executed, it executes the steps of the above-mentioned method embodiments; and the above-mentioned storage medium includes various media that can store program codes, such as mobile storage devices, read-only memories (ROMs), random access memories (RAMs), magnetic disks or optical disks.

[0112] The methods disclosed in the several method embodiments provided in this application can be arbitrarily combined without conflict to obtain new method embodiments.

[0113] The features disclosed in the several product embodiments provided in this application can be arbitrarily combined without conflict to obtain new product embodiments.

[0114] The features disclosed in the several method or device embodiments provided in this application can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0115] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any modifications or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present invention should be included in the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims.

Claims

1. A method for decoding a video frame, characterized in that: Applied to a hardware decoding chip, the method includes: Receive first decoding information sent by a central processing unit (CPU); wherein the first decoding information includes a first video frame and a hard decoding instruction; In response to the hard decoding instruction, obtaining a first cumulative distribution function (CDF) table required for decoding the first video frame; Decoding the first video frame using a first CDF table to obtain a decoded video frame; The obtaining of the first cumulative distribution function (CDF) table required for decoding the first video frame includes: when the type of the first video frame is non-Class I, obtaining the first CDF table required for decoding the first video frame from a first CDF table sequence; wherein the first CDF table sequence includes a CDF table corresponding to a reference frame of the first video frame; when the type of the first video frame is Class I, obtaining an initial CDF table defined by a standard; and using the initial CDF table as the first CDF table required for decoding the first video frame.

2. The method according to claim 1, characterized in that The method further comprises: During the decoding process, the first CDF table is updated to obtain a new first CDF table.

3. The method according to claim 2, characterized in that The method further comprises: If it is determined that the second CDF table sequence needs to be updated, updating the new first CDF table to a specified position in the second CDF table sequence; The second CDF table sequence is the first CDF table sequence or an initial CDF table sequence defined by a standard.

4. The method according to claim 1, wherein After decoding the first video frame using the first CDF table to obtain a decoded video frame, the method further includes: An interrupt instruction and the decoded video frame are sent to the CPU, so that the CPU responds to the interrupt instruction, stops constructing decoding information, and sends the decoded video frame to a display unit for display.

5. The method according to claim 4, characterized in that The method further comprises: During the display process of the decoded video frame, second decoding information sent by the CPU is received.

6. A hardware decoding chip, characterized in that: The hardware decoding chip includes: A receiving unit, configured to receive first decoding information sent by a central processing unit (CPU); wherein the first decoding information includes a first video frame and a hard decoding instruction; an acquiring unit, configured to respond to the hard decoding instruction and acquire a first cumulative distribution function (CDF) table required for decoding the first video frame; a decoding unit, configured to decode the first video frame using a first CDF table to obtain a decoded video frame; The acquisition unit is specifically used to obtain a first CDF table required for decoding the first video frame from a first CDF table sequence when the type of the first video frame is non-Class I; wherein the first CDF table sequence includes a CDF table corresponding to a reference frame of the first video frame; when the type of the first video frame is Class I, obtain an initial CDF table defined by the standard; and use the initial CDF table as the first CDF table required for decoding the first video frame.

7. A hardware decoding chip, characterized in that: The hardware decoding chip includes: a processor and a memory, Wherein, the memory is used to store computer programs; The processor is configured to execute the steps of the method according to any one of claims 1 to 5 when the computer program is running.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 5 are implemented.

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