Memory devices and methods of manufacturing memory devices

Abstract

Provided herein can be memory devices and methods of manufacturing memory devices. A memory device can include a connection structure formed on a substrate, a lower contact formed on the connection structure, an upper contact formed on the lower contact, a dummy pattern configured to surround and be spaced apart from the lower contact, an etch stop pattern formed in an upper region of the dummy pattern, and a dummy contact formed above the etch stop pattern.

Description

Technical Field

[0001] Various embodiments of this disclosure generally relate to memory devices and methods of manufacturing memory devices, and more specifically, to 3D memory devices and methods of manufacturing 3D memory devices. Background Technology

[0002] To improve the integration of memory devices, a 3D memory device comprising multiple memory cells arranged in three dimensions has been proposed.

[0003] A 3D memory device may include a cell region and a peripheral circuit region. The cell region may include multiple memory cells capable of storing data. The peripheral circuit region may include multiple transistors capable of controlling the memory cells.

[0004] As the integration of 3D memory devices increases, not only are the sizes of components included in the cell area or peripheral circuit area reduced, but the distance between components also decreases, which increases the difficulty of the manufacturing process. Summary of the Invention

[0005] Embodiments of this disclosure may provide a memory device. The memory device may include: a connection structure formed on a substrate; a lower contact formed on the connection structure; an upper contact formed on the lower contact; a dummy pattern configured to surround and spaced apart from the lower contact; an etch stop pattern formed in an upper region of the dummy pattern; and a dummy contact formed above the etch stop pattern.

[0006] Embodiments of this disclosure may provide a method for manufacturing a memory device. The method may include: providing a substrate defining a cell region and a peripheral region; forming conductive patterns on the substrate of the cell region and the peripheral region; forming a lower contact between the conductive patterns in the peripheral region; forming an etch stop pattern in the conductive patterns of the cell region and the peripheral region; forming a stacked structure on the etch stop pattern; forming holes in the stacked structure in the peripheral region configured to expose the lower contact and the etch stop pattern, respectively; and forming a dummy contact contacting the portion of the etch stop pattern and an upper contact contacting the lower contact by filling the holes formed in the peripheral region with a conductive material. Attached Figure Description

[0007] Figure 1 This is a diagram illustrating a memory device according to an embodiment of the present disclosure.

[0008] Figure 2 It is a diagram used to illustrate the setup of the memory cell array and peripheral circuitry.

[0009] Figure 3 It is a diagram used to illustrate storage blocks.

[0010] Figure 4 This is a diagram illustrating the layout of a memory device according to an embodiment of the present disclosure.

[0011] Figure 5 This is a diagram illustrating the final structure of a memory device according to an embodiment of the present disclosure.

[0012] Figure 6A , Figure 6B , Figure 6C , Figure 6D , Figure 6E , Figure 6F , Figure 6G , Figure 6H , Figure 6I , Figure 6J , Figure 6K , Figure 6L , Figure 6M , Figure 6N , Figure 6O and Figure 6P This is a diagram illustrating a method for manufacturing a memory device according to the present disclosure.

[0013] Figure 7 This is a diagram illustrating a memory card system using a memory device according to an embodiment of the present disclosure.

[0014] Figure 8 This is a diagram illustrating a solid-state drive (SSD) system of a memory device according to an embodiment of the present disclosure. Detailed Implementation

[0015] The specific structural or functional descriptions provided below are intended to describe embodiments based on the concept of this disclosure. Embodiments based on the concept of this disclosure may be modified and substituted with other equivalent embodiments, and should not be construed as limited to the embodiments described below.

[0016] Although the terms “first” and “second” are used in this document to describe various elements, these elements are not limited by these terms. The terms are used to distinguish one element from others.

[0017] Various embodiments of this disclosure relate to a memory device and a method for manufacturing a memory device capable of preventing the generation of bridging caused by dummy contacts during a manufacturing process for forming dummy contacts in a peripheral circuit region. It will be understood that when an element, contact, structure, pattern, line, or layer is referred to as being "on" another element, contact, structure, pattern, line, or layer, "connected to" or "attached to" another element, contact, structure, pattern, line, or layer, it can be directly connected to or attached to the other element, contact, structure, pattern, line, or layer, or intermediate elements, contacts, structures, patterns, lines, or layers may exist. Conversely, when an element, contact, structure, pattern, line, or layer is referred to as being "directly on" another element, contact, structure, pattern, line, or layer, "directly connected to" or "directly attached to" another element, contact, structure, pattern, line, or layer, no intermediate elements, contacts, structures, patterns, lines, or layers exist.

[0018] Figure 1 This is a diagram illustrating a memory device according to an embodiment of the present disclosure.

[0019] Reference Figure 1 The memory device 100 may include a memory cell array 110 and peripheral circuitry 190.

[0020] The memory cell array 110 may include a plurality of memory cells in which data is stored. As an embodiment, the memory cell array 110 may include a 3D memory cell array. Depending on the programming method, the plurality of memory cells may store one bit of data or multiple bits of data, including two or more bits. The plurality of memory cells may form a plurality of memory cell strings. For example, each memory cell string may include a plurality of memory cells connected in series via a channel layer. The channel layer may be connected between the source line and multiple bit lines BL.

[0021] The peripheral circuitry 190 can be configured to perform programming operations for storing data in the memory cell array 110, reading operations for outputting data stored in the memory cell array 110, and erasing operations 110 for erasing data stored in the memory cell array 110. The peripheral circuitry 190 may include a row decoder 120, a voltage generation circuit 130, a source line driver 140, a control circuit 150, a page buffer set 160, a column decoder 170, and input / output circuitry 180.

[0022] The row decoder 120 can be connected to the memory cell array 110 via multiple drain select lines DSL, multiple word lines WL, and multiple source select lines SSL. The row decoder 120 can transmit the operating voltage Vop to the multiple drain select lines DSL, multiple word lines WL, and multiple source select lines SSL in response to the row address RADD.

[0023] The voltage generation circuit 130 can generate different operating voltages Vop for programming, reading, or erasing operations in response to the operation signal OP_S.

[0024] The source line driver 140 can send the source voltage Vsl it provides to the source line connected to the memory cell array 110 in response to the source line control signal SL_S.

[0025] Control circuit 150 can output operation signal OP_S, row address RADD, source line control signal SL_S, page buffer control signal PB_S and column address CADD in response to command CMD and address ADD.

[0026] Page buffer group 160 may include multiple page buffers connected to memory cell array 110 via bit lines BL. The page buffers may temporarily store data DATA received via multiple bit lines BL in response to a page buffer control signal PB_S. The page buffers may sense the voltage or current of the multiple bit lines BL during read operations.

[0027] Column decoder 170 can send data DATA input from input / output circuit 180 to page buffer 160 or send data DATA stored in page buffer 160 to input / output circuit 180 in response to column address CADD. Column decoder 170 can send data DATA to and receive data DATA from input / output circuit 180 via column line CLL. Column decoder 170 can send data DATA to and receive data DATA from page buffer 160 via data line DTL.

[0028] The input / output circuit 180 can transmit commands CMD and addresses ADD received from an external device (e.g., a controller) of the memory device 100 to the control circuit 150, and can output data read from the selected memory cell to the external device during a read operation.

[0029] Figure 2 It is a diagram used to illustrate the setup of the memory cell array and peripheral circuitry.

[0030] Reference Figure 2The memory device 100 may include peripheral circuitry 190 and a memory cell array 110. The peripheral circuitry 190 may be disposed above a substrate, and the memory cell array 110 may be disposed above the peripheral circuitry 190. The memory cell array 110 may include first memory blocks BLK1 to j-th memory blocks BLKj. Multiple bit lines BL may be disposed above the first memory blocks BLK1 to j-th memory blocks BLKj.

[0031] Multiple bit lines BL can be arranged to be spaced apart from each other along the X direction and can extend along the Y direction. First memory blocks BLK1 to j-th memory blocks BLKj can be arranged to be spaced apart from each other along the Y direction. First memory blocks BLK1 to j-th memory blocks BLKj can be separated from each other by a slit SLT.

[0032] When the region in which the first memory blocks BLK1 to j-th memory blocks BLKj are formed is defined as cell region CE, the first peripheral region 1PE can be defined in the X direction relative to cell region CE, and the second peripheral region 2PE can be defined in the -X direction relative to cell region CE. Because the first memory blocks BLK1 to j-th memory blocks BLKj are formed above the peripheral circuitry 190, the first memory blocks BLK1 to j-th memory blocks BLKj and a portion of the peripheral circuitry 190 can be electrically connected to each other through the first peripheral region 1PE or the second peripheral region 2PE. The first peripheral region 1PE and the second peripheral region 2PE can include various patterns of the process used to manufacture the memory device 100, and can include transistors used as peripheral circuitry.

[0033] Since the first storage block BLK1 to the j-th storage block BLKj are configured to be identical to each other, the first storage block BLK1 is used as an example, and its detailed description will be given below.

[0034] Figure 3 It is a diagram used to illustrate storage blocks.

[0035] Reference Figure 3 The first memory cell string CS1 and the second memory cell string CS2, connected to the first bit line BL1 to the i-th bit line BLi (i is a positive integer), can be connected to the first memory block BLK1. Although in Figure 3 Two memory cell strings, CS1 and CS2, are connected to a single bit line, but the number of memory cell strings connected to a single bit line is not limited to the number shown in the figure.

[0036] The first memory cell string CS1 and the second memory cell string CS2 can be connected between the source line SL and the first bit line BL1 to the i-th bit line BLi. The source line SL can be connected to the first memory cell string CS1 and the second memory cell string CS2.

[0037] Each of the first memory cell string CS1 and the second memory cell string CS2 may include a source selection transistor SST, a plurality of memory cells MC1 to MCn and a drain selection transistor DST, which are connected to the source line SL and the first bit line BL1 to the i-th bit line BLi.

[0038] A source-select transistor (SST) controls the electrical connection between multiple memory cells MC1 to MCn and the source line SL. At least one source-select transistor (SST) can be connected between the source line SL and the multiple memory cells MC1 to MCn. The gate of the source-select transistor (SST) can be connected to the source-select line SSL. The source-select transistor (SST) can be turned on or off in response to a voltage applied to the source-select line SSL.

[0039] Multiple memory cells MC1 to MCn can be disposed between the source select transistor SST and the drain select transistor DST. These memory cells MC1 to MCn can be connected in series between the source select transistor SST and the drain select transistor DST. The gates of the memory cells MC1 to MCn can be connected to corresponding word lines among multiple word lines WL1 to WLn. The operation of the memory cells MC1 to MCn can be controlled by the voltage applied to the corresponding word lines WL1 to WLn. Memory cells connected to the same word line can form a page, and memory cells can be selected on a page-by-page basis during programming or reading operations.

[0040] The drain-select transistor (DST) controls the electrical connections between multiple memory cells MC1 to MCn and bit lines BL1 to BLi. The gate of the DST can be connected to either drain-select line DSL1 or DSL2. The operation of the DST can be controlled based on the voltage applied to drain-select lines DSL1 or DSL2.

[0041] The first drain select line DSL1 can be connected to multiple first memory cell strings CS1, and the second drain select line DSL2 can be connected to multiple second memory cell strings CS2. Therefore, one of the pages included in the multiple first memory cell strings CS1 or multiple second memory cell strings CS2 can be selected by selecting one of the multiple word lines WL1 to WLn and selecting either the first drain select line DSL1 or the second drain select line DSL2.

[0042] Multiple first memory cell strings CS1 and multiple second memory cell strings CS2 can be connected together to multiple word lines WL1 to WLn.

[0043] The configuration of the first storage block BLK1 can be changed in various ways, and is not limited to these. Figure 3 The configuration shown.

[0044] Figure 4 This is a diagram illustrating the layout of a memory device according to an embodiment of the present disclosure.

[0045] Reference Figure 4 The first peripheral region 1PE can be defined in the region adjacent to the cell region CE along the X direction. The block region BR and the slim region SM can be defined within the cell region CE.

[0046] The memory block region BR may include multiple memory blocks BLK1 and BLK2. The multiple memory blocks BLK1 and BLK2 may include multiple cell plugs CPL passing through stacked gate lines GT. The multiple memory blocks BLK1 and BLK2 may be configured to be spaced apart from each other along the Y direction, and the gate lines GT included in memory blocks BLK1 and BLK2 respectively may extend along the X direction. The cell plugs CPL may be configured to be spaced apart from each other along both the X and Y directions. The multiple memory blocks BLK1 and BLK2, spaced apart from each other along the Y direction, may be separated from each other by a slit SLT. Figure 4 The diagram illustrates portions of a first memory block BLK1 and a second memory block BLK2, which can be separated from each other by a slit SLT. A source contact SCT can be formed within the slit SLT. The source contact SCT can contact a source line SL formed below (from) the first memory block BLK1 and the second memory block BLK2 in the -Z direction. An insulating layer for resisting the source contact SCT and the gate line GT can be formed between the source contact SCT and the first memory block BLK1 and the second memory block BLK2.

[0047] The thinned region SM may include an edge portion of the gate line GT extending from the memory block region BR. The edge portions of the stacked gate line GT may be stacked in a stepped shape, and gate contacts CTg configured to send different voltages to the gate line GT may be formed in the edge portions of the gate line GT. A portion of the source line SL may be exposed beneath the gate line GT.

[0048] The first peripheral region 1PE may include a main contact CTm and a dummy contact CTd. The main contact CTm may be formed simultaneously with a discharge contact (not shown) for transmitting charges that can be generated in the conductive layer during the manufacturing process of the memory device. For example, peripheral circuitry configured to transmit different voltages during programming, reading, or erasing operations of the memory cell may be formed in the first peripheral region 1PE. As used herein, the terms "simultaneously" and "at the same time" refer to processes occurring at overlapping time intervals. For example, if a first process occurs at a first time interval and a second process occurs simultaneously at a second time interval, the first and second time intervals overlap at least partially, such that there exists a time when both the first and second processes occur.

[0049] For example, the main contact CTm can be formed above the peripheral circuitry formed in the first peripheral region 1PE. Dummy contacts CTd can be formed to facilitate the etching process performed in the region where the main contact CTm is to be formed. For example, dummy contacts CTd can be formed to prevent contact holes formed in the region where the main contact CTm is to be formed from being etched deeper or shallower than the target depth. For example, dummy contacts CTd are formed in a region adjacent to the main contact CTm but not in contact with it. Therefore, the main contact CTm can be formed in the first insulating pattern 1ISP, and the dummy contact CTd can be formed in the first dummy pattern 1DM surrounding the first insulating pattern 1ISP. The first dummy pattern 1DM can be surrounded by a second insulating pattern 2ISP, and the second insulating pattern 2ISP can be surrounded by the second dummy pattern 2DM.

[0050] Unlike the main contact CTm, the dummy contacts CTd are not connected to the external circuitry because they are not used as actual contacts. That is, the dummy contacts CTd are formed only in the first dummy pattern 1DM.

[0051] Therefore, in this embodiment, the etch stop pattern ES is formed in the first dummy pattern 1DM to prevent the dummy contact CTd from being formed deeper than the target depth. The etch stop pattern ES can be formed simultaneously with the etch stop pattern used to prevent over-etching of the slot SLT.

[0052] Because the etch stop pattern ES is formed simultaneously with the etch stop pattern in the cell region CE, the detailed structure will be described below with reference to the cross-section taken along line I-I' of the cell region CE and the cross-section taken along line II-II' of the first peripheral region 1PE.

[0053] Figure 5 This is a diagram illustrating the final structure of a memory device according to an embodiment of the present disclosure.

[0054] Reference Figure 5The section taken along line I-I' shows the local structure of the unit region CE, and the section taken along line II-II' shows the local structure of the first peripheral region 1PE.

[0055] The junction region JUC, to which voltage can be transmitted, can be formed in the substrate SUB of the cell region CE and the first peripheral region 1PE.

[0056] A first interlayer insulating layer 1ITL can be formed on a substrate SUB of the cell region CE and the first peripheral region 1PE, and a first connection structure 1ITC including a plurality of transistors TR in the peripheral circuit and a junction region JUC connected to the transistors TR can be formed in the first interlayer insulating layer 1ITL. For example, the first connection structure 1ITC can be configured with a plurality of contacts and wires. The first interlayer insulating layer 1ITL can be formed of oxide or silicon oxide. A portion of the junction region JUC formed in the first peripheral region 1PE can be connected to a ground terminal GND or other transistors.

[0057] In the cell region CE, a source line SL can be formed above a first interlayer insulating layer 1ITL, and in the first peripheral region 1PE, a first conductive layer 1CD to a third conductive layer 3CD, a first insulating layer 1IS, and a second insulating layer 2IS can be formed above the first interlayer insulating layer 1ITL. The source line SL formed in the cell region CE may include a first conductive layer 1CD and a fourth conductive layer 4CD. The first conductive layer 1CD and the fourth conductive layer 4CD formed in the cell region CE can be used as source lines SL connected to a memory block. The first conductive layer 1CD to the third conductive layer 3CD formed in the first peripheral region 1PE may be a dummy structure retained during the process of forming the source line SL of the cell region. The first conductive layer 1CD to the fourth conductive layer 4CD can be formed as conductive layers. For example, the first conductive layer 1CD to the fourth conductive layer 4CD can be formed as the same conductive layer or different conductive layers. For example, each of the first conductive layer 1CD to the fourth conductive layer 4CD can be formed as a doped polysilicon layer or a metal layer. A first insulating layer 1IS or a second insulating layer 2IS may be formed between a first conductive layer 1CD and a third conductive layer 3CD retained in the first peripheral region 1PE. The first insulating layer 1IS and the second insulating layer 2IS may be formed of an oxide layer or a silicon oxide layer.

[0058] A portion of the first conductive layer 1CD to the third conductive layer 3CD, as well as portions of the first insulating layer 1IS and the second insulating layer 2IS, retained in the first peripheral region 1PE, can be used as a first dummy pattern 1DM, and the remaining portions can be used as a second dummy pattern 2DM. A first insulating pattern 1ISP can be formed inside the first dummy pattern 1DM, and a second insulating pattern 2ISP can be formed between the first dummy pattern 1DM and the second dummy pattern 2DM. A lower contact CTU perpendicularly passing through the first insulating pattern 1ISP can be formed in the first insulating pattern 1ISP. The lower contact CTU is a contact formed in the lower portion of the main contact CTm and can contact the first connection structure 1ITC formed in the first peripheral region 1PE.

[0059] An etch stop pattern ES can be formed in the third conductive layer 3CD formed above the first dummy pattern 1DM. An etch stop pattern ES can be formed and retained in the first peripheral region 1PE to prevent excessive execution of the etching process for forming the fourth hole 4Hc above the lower contact CTU. For example, when performing the etching process for forming the fourth hole 4Hc above the lower contact CTU, a fifth hole 5Hc can be formed simultaneously above the first dummy pattern 1DM. The etch stop pattern ES retained in the first peripheral region 1PE is formed simultaneously with the etch stop pattern 41 in the unit region CE, but the etch stop pattern 41 formed in the unit region CE can be removed in a subsequent process.

[0060] The first stacked structure 1STK, together with the upper contact CTp and dummy contact CTd perpendicularly passing through the first stacked structure 1STK, can be formed above the first dummy pattern 1DM and the second dummy pattern 2DM, as well as the first insulating pattern 1ISP and the second insulating pattern 2ISP, in the first peripheral region 1PE. The first stacked structure 1STK may include alternating layers of a third insulating pattern 3ISP and a sacrificial pattern SFL. The third insulating pattern 3ISP may be formed of oxide or silicon oxide, and the sacrificial pattern SFL may be formed of a material having an etch selectivity different from that of the third insulating pattern 3ISP. For example, the sacrificial pattern SFL may be formed of a nitride layer. The upper contact CTp is a contact formed in the upper region of the main contact CTm and may contact the upper part of the lower contact CTU. That is, each main contact CTm may be configured with an upper contact CTp and a lower contact CTU. The upper contact CTp and the dummy contact CTd may be formed in the fourth hole 4Hc and the fifth hole 5Hc perpendicularly passing through the first stacked structure 1STK. When performing the etching process to form the fourth hole 4Hc, the etch stop pattern ES can be used to stop the etching process at an appropriate time. Because the upper contact CTp and the dummy contact CTd are formed simultaneously in both the fourth hole 4Hc and the fifth hole 5Hc, they can be formed from the same conductive material. For example, the dummy contact CTd, the upper contact CTp, and the lower contact CTu can be formed from the same conductive material.

[0061] The second connection structure 2ITC can be formed above the upper contact CTp. The second connection structure 2ITC can be formed of a conductive material. The second connection structure 2ITC can be connected to a line extending from the cell region CE or a gate line.

[0062] The second stacked structure 2STK, along with the cell plug CPL and source contact SCT passing vertically through the second stacked structure 2STK, can be formed above the source line SL in the cell region CE. The second stacked structure 2STK may include alternating layers of a third insulating pattern 3ISP and a fifth conductive layer 5CD. The third insulating pattern 3ISP can be formed of an oxide layer or a silicon oxide layer. The fifth conductive layer 5CD serves as the gate line ( Figure 4 The GT in the figure can be formed of metallic materials such as tungsten (W), molybdenum (Mo), cobalt (Co), nickel (Ni), or semiconductor materials such as silicon (Si) or polycrystalline silicon (Poly-Si), but is not limited thereto. In an embodiment, the vertical direction can be the Z direction.

[0063] The memory plug layer (CPL) may include material layers constituting the memory cell. For example, each CPL may include a core pillar (CP), a channel layer (CH), a tunnel isolation layer (TX), a charge trapping layer (CT), and a barrier layer (BX). The core pillar (CP) may be formed in a cylindrical shape at the center of the CPL and may be formed of an insulating material. The channel layer (CH) may be formed in a cylindrical shape surrounding the side surfaces of the core pillar (CP) and may be formed of a polysilicon layer. The tunnel isolation layer (TX) may be formed in a cylindrical shape surrounding the side surfaces of the channel layer (CH) and may be formed of an oxide layer or a silicon oxide layer. The charge trapping layer (CT) may be formed in a cylindrical shape surrounding the side surfaces of the tunnel isolation layer (TX) and may be formed of a nitride layer capable of trapping charges. The barrier layer (BX) may be formed in a cylindrical shape surrounding the side surfaces of the charge trapping layer (CT) and may be formed of an oxide layer or a silicon oxide layer.

[0064] The manufacturing method for forming the memory device described above will be described in detail below.

[0065] Figures 6A to 6P This is a diagram illustrating a method for manufacturing a memory device according to the present disclosure.

[0066] Reference Figure 6A A first interlayer insulating layer 1ITL can be formed on a substrate SUB in the cell region CE and the first peripheral region 1PE, and a first connection structure 1ITC including a plurality of transistors TR in the peripheral circuit and a junction region JUC connected to the transistors TR can be formed in the first interlayer insulating layer 1ITL. For example, the first connection structure 1ITC can be configured with a plurality of contacts and wires. The first interlayer insulating layer 1ITL can be formed of oxide or silicon oxide.

[0067] The first conductive layers 1CD to the third conductive layers 3CD, as well as the first insulating layer 1IS and the second insulating layer 2IS, can be formed above the first interlayer insulating layer 1ITL. For example, the first insulating layer 1IS can be formed between the first conductive layer 1CD and the second conductive layer 2CD, and the second insulating layer 2IS can be formed between the second conductive layer 2CD and the third conductive layer 3CD. The first conductive layers 1CD to the third conductive layers 3CD can be formed as the same conductive layer or as different conductive layers. For example, the first conductive layers 1CD to the third conductive layers 3CD can be formed from a doped polysilicon layer or a metal layer. The first insulating layer 1IS and the second insulating layer 2IS can be formed from an oxide layer or a silicon oxide layer.

[0068] Reference Figure 6BA first dummy pattern 1DM and a second dummy pattern 2DM can be formed by patterning a first conductive layer 1CD to a third conductive layer 3CD, a first insulating layer 1IS, and a second insulating layer 2IS in a first peripheral region 1PE. Specifically, this can be described by etching portions of the first conductive layer 1CD to the third conductive layer 3CD, the first insulating layer 1IS, and the second insulating layer 2IS in the first peripheral region 1PE to form a first trench 1TC and a second trench 2TC spaced apart from each other. The first trench 1TC can be formed above the first connection structure 1ITC, and the second trench 2TC can be formed in a region spaced apart from and surrounding the first trench 1TC. The first conductive layer 1CD to the third conductive layer 3CD, the first insulating layer 1IS, and the second insulating layer 2IS retained between the first trench 1TC and the second trench 2TC constitute the first dummy pattern 1DM, and the first conductive layer 1CD to the third conductive layer 3CD, the first insulating layer 1IS, and the second insulating layer 2IS retained near the second trench 2TC constitute the second dummy pattern 2DM. A first insulating pattern 1ISP can be formed in a first trench 1TC, and a second insulating pattern 2ISP can be formed in a second trench 2TC. The first insulating pattern 1ISP and the second insulating pattern 2ISP can be formed from an oxide layer or a silicon oxide layer. (Refer to...) Figure 5 and Figure 6B In the first peripheral region 1PE, a first insulating pattern 1ISP can be formed above the first connection structure 1ITC, and a first dummy pattern 1DM can be formed to surround the side surface of the first insulating pattern 1ISP. A second insulating pattern 2ISP can be formed to surround the side surface of the first dummy pattern 1DM, and a second dummy pattern 2DM can be formed to surround the side surface of the second insulating pattern 2ISP.

[0069] Reference Figure 6C The first hole 1Hc, which exposes a portion of the first connection structure 1ITC, can be formed by etching a portion of the first insulating pattern 1ISP. For example, the first hole 1Hc can be formed in the first insulating pattern 1ISP by performing an anisotropic dry etching process.

[0070] Reference Figure 6D The lower contact CTU can be formed in the first via 1Hc. For example, a conductive material is formed over the entire structure to fill the first via 1Hc, and a planarization process can be performed to expose the third conductive layer 3CD. After the planarization process, the conductive material remaining in the first via 1Hc can constitute the lower contact CTU.

[0071] Reference Figure 6EThe third trench 3TC can be formed by etching a portion of the third conductive layer 3CD formed in the cell region CE. The third trench 3TC can be formed in the region of the cell region where the slit is to be formed. Simultaneously, a fourth trench 4TC can be formed in a portion of the third conductive layer 3CD in the first peripheral region 1PE. For example, the fourth trench 4TC can be formed by etching a portion of the third conductive layer 3CD included in the first dummy pattern 1DM. (Refer to...) Figure 4 and Figure 6E Since the third groove 3TC is formed in the region where the slit SLT is to be formed, the third groove 3TC can be formed as a line extending along the X direction, and the fourth groove 4TC can be formed as a hole or a rectangular shape with spaced apart from each other in the first dummy pattern 1DM.

[0072] Reference Figure 6F The etch stop pattern ES can be formed in the third trench 3TC and the fourth trench 4TC. The etch stop pattern ES can be formed of a conductive material. For example, the etch stop pattern ES can be formed of tungsten (W), titanium (Ti), or titanium nitride (TiN), or a mixture of two or more selected therefrom.

[0073] Reference Figure 6G The first stacked structure 1STK can be formed over the entire structure of the cell region CE and the first peripheral region 1PE. The first stacked structure 1STK may include alternating layers of a third insulating pattern 3ISP and a sacrificial pattern SFL. The third insulating pattern 3ISP can be formed of oxide or silicon oxide, and the sacrificial pattern SFL can be formed of a material having an etch selectivity different from that of the third insulating pattern 3ISP. For example, the sacrificial pattern SFL can be formed of a nitride layer.

[0074] Reference Figure 6H The third hole 3Hc can be formed in the first stacked structure 1STK formed in the cell region CE. For example, the third hole 3Hc that exposes a portion of the third conductive layer 3CD can be formed by etching a portion of the first stacked structure 1STK formed in the cell region CE.

[0075] Reference Figure 6HCell plugs (CPLs) can be formed in a third hole (3Hc). In an embodiment, the third hole (3Hc) can be referred to as a vertical hole. Cell plugs (CPLs) can include material layers constituting memory cells. Each cell plug (CPL) can include a core pillar (CP), a channel layer (CH), a tunnel isolation layer (TX), a charge trapping layer (CT), and a barrier layer (BX). For example, the barrier layer (BX) can be formed in a cylindrical shape along the side surface of the third hole (3Hc), and the charge trapping layer (CT) can be formed in a cylindrical shape along the inner surface of the barrier layer (BX). The tunnel isolation layer (TX) can be formed in a cylindrical shape along the inner surface of the charge trapping layer (CT), and the channel layer (CH) can be formed in a cylindrical shape along the inner surface of the tunnel isolation layer (TX). The core pillar (CP) can be formed in a cylindrical shape in the region surrounded by the channel layer (CH). The barrier layer (BX), the tunnel isolation layer (TX), and the core pillar (CP) can be formed of an oxide layer or a silicon oxide layer. The charge trapping layer (CT) can be formed of a nitride layer capable of trapping charges. The channel layer (CH) can be formed of a polysilicon layer.

[0076] Reference Figure 6I A slot SLT can be formed between cell plugs (CPLs) to expose an etch stop pattern (ES) in the cell region (CE). The slot SLT is a trench used to separate memory blocks from each other and can be formed by etching a first stacked structure (1STK) formed in the cell region (CE) using a dry etching process. The etching process for forming the slot SLT can be performed until the etch stop pattern (ES) is exposed. A portion of the third insulating pattern (3ISP) and sacrificial pattern (SPL) in the first stacked structure (1STK) is included through the side surface of the slot SLT formed in the cell region (CE). To prevent the third insulating pattern (3ISP) and sacrificial pattern (SPL) exposed through the slot SLT from being damaged in subsequent processes, a protective layer (PT) can be formed on the side surface of the slot SLT. The material forming the protective layer (PT) can vary depending on the layer exposed through the bottom of the slot SLT. For example, a third conductive layer 3CD, a second insulating layer 2IS, a first insulating layer 1IS, and a first conductive layer 1CD are formed below the slit SLT, and the third conductive layer 3CD, the second insulating layer 2IS, the second conductive layer 2CD, and the first insulating layer 1IS can be removed in a subsequent process. Therefore, the protective layer PT can be formed of a material having an etch selectivity different from that of the third conductive layer 3CD, the second insulating layer 2IS, the second conductive layer 2CD, and the first insulating layer 1IS. For example, the protective layer PT may comprise an oxide layer, a nitride layer, and an oxide layer sequentially formed on the sidewalls of the slit SLT.

[0077] Reference Figure 6JAn etching process can be performed to remove the etch stop pattern ES, the third conductive layer 3CD, the second insulating layer 2IS, the second conductive layer 2CD, and the first insulating layer 1IS exposed through the bottom of the slit SLT. For example, the third conductive layer 3CD exposed through the bottom of the slit SLT can be removed. When removing the third conductive layer 3CD, since the second insulating layer 2IS is exposed through the bottom of the slit SLT, the second insulating layer 2IS can be removed after removing the third conductive layer 3CD. In this way, the second conductive layer 2CD and the first insulating layer 1IS can be removed sequentially. When removing the third conductive layer 3CD, the second insulating layer 2IS, the second conductive layer 2CD, and the first insulating layer 1IS, a first groove 1RES, serving as an empty space, can be formed between the first conductive layer 1CD and the first stacked structure 1STK in the cell region CE.

[0078] Reference Figure 6K The fourth conductive layer 4CD can fill the first recess 1RES. The fourth conductive layer 4CD can be formed of the same material as the first conductive layer 1CD. For example, the fourth conductive layer 4CD can be formed of a doped polysilicon layer or a metal layer. The first conductive layer 1CD and the fourth conductive layer 4CD formed in the cell region CE can be used as source lines SL connected to the memory block.

[0079] Reference Figure 6L An etching process can be performed to remove the protective layer PT formed in the slit SLT. When the protective layer PT is removed, the third insulating pattern 3ISP and the sacrificial pattern SFL can be exposed through the slit SLT. An etching process can be performed to selectively remove the sacrificial pattern SFL from the exposed third insulating pattern 3ISP and sacrificial pattern SFL. When the sacrificial pattern SFL is removed, a second groove 2RES can be formed between the third insulating patterns 3ISP.

[0080] Reference Figure 6M The fifth conductive layer 5CD can fill the second recess 2RES. The fifth conductive layer 5CD can be used as a drain select line, a source select line, or a word line, and some of them can be used as dummy lines. After the fifth conductive layer 5CD is formed, an etching process can be performed to remove the fifth conductive layer 5CD retained in the slot SLT. Subsequently, a third insulating layer 3IS is formed along the side surface of the slot SLT, and a source contact SCT can be formed in the slot SLT on which the third insulating layer 3IS is formed. The source contact SCT can be formed of a conductive layer. Because the source contact SCT contacts the fourth conductive layer 4CD formed below the slot SLT, the voltage supplied to the source contact SCT can be transmitted to the source line SL. The third insulating layer 3IS can be formed of an oxide layer or a silicon oxide layer to resist the source contact SCT and the fifth conductive layer 5CD from each other.

[0081] Reference Figure 6N An etching process for forming a fourth hole 4Hc that exposes the lower contact CTU in the first peripheral region 1PE can be performed. The etching process can be performed as an anisotropic dry etching process. Simultaneously, a fifth hole 5Hc can be formed above the etching stop pattern ES to prevent over- or under-execution of the etching process for forming the fourth hole 4Hc. For example, an etching process for simultaneously forming the fourth hole 4Hc and the fifth hole 5Hc can be performed until the etching stop pattern ES is exposed through the fifth hole 5Hc. In other words, the etching process for forming the fourth hole 4Hc and the fifth hole 5Hc can be stopped when the etching stop pattern ES is exposed. Therefore, defects in the manufacturing process, such as excessive damage to the top surface of the lower contact CTU exposed through the fourth hole 4Hc or the lower contact CTU not being exposed through the fourth hole 4Hc, can be prevented. Because the etching processes for forming the fourth hole 4Hc and the fifth hole 5Hc start and stop simultaneously, the depths Ht of the fourth hole 4Hc and the fifth hole 5Hc can be equal to each other, and their widths Wt can also be equal to each other.

[0082] Reference Figure 6O The upper contact CTp and the dummy contact CTd can be formed simultaneously in the fourth hole 4Hc and the fifth hole 5Hc. For example, the upper contact CTp can be formed in the fourth hole 4Hc, and the dummy contact CTd can be formed in the fifth hole 5Hc. Because the upper contact CTp contacts the lower contact CTU below it, the upper contact CTp and the lower contact CTU can be electrically connected to the first connection structure 1ITC. Therefore, a main contact CTm configured with the upper contact CTp and the lower contact CTU can be formed. Because the dummy contact CTd is formed only in the first stacked structure 1STK due to the etch stop pattern ES, it is not used as a structure for transmitting voltage in the first peripheral region 1PE.

[0083] Reference Figure 6P A second connection structure 2ITC, which connects to a line or gate line extending from the cell region CE, may be formed above the main contact DTm. For example, the second connection structure 2ITC may include contacts and lines formed of a conductive material.

[0084] Figure 7 This is a diagram illustrating a memory card system using a memory device according to an embodiment of the present disclosure.

[0085] Reference Figure 7 The memory card system 3000 may include a controller 3100, a memory device 3200, and a connector 3300.

[0086] Controller 3100 can be coupled to memory device 3200. Controller 3100 can access memory device 3200. For example, controller 3100 can control programming, reading, or erasing operations of memory device 3200, or it can control background operations of memory device 3200. Controller 3100 can provide an interface between memory device 3200 and a host. Controller 3100 can run firmware for controlling memory device 3200. In this example, controller 3100 may include components such as random access memory (RAM), a processor, a host interface, a memory interface, and an error correction block.

[0087] Controller 3100 can communicate with external devices via connector 3300. Controller 3100 can communicate with external devices (e.g., a host) based on a specific communication protocol. In embodiments, controller 3100 can communicate with external devices via at least one of various communication standards or protocols such as Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), Fast PCI (PCI-E), Advanced Technology Attachment (ATA) protocol, Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Memory (UFS), WiFi, Bluetooth, and High-Speed ​​Non-Volatile Memory (NVMe). In embodiments, connector 3300 can be defined by at least one of the aforementioned communication protocols.

[0088] Memory device 3200 may include memory cells and can be coupled with memory units. Figure 1 The memory device 100 shown is configured in the same manner.

[0089] The controller 3100 and the memory device 3200 can be integrated into a single semiconductor device to form a memory card. For example, the controller 3100 and the memory device 3200 can be integrated into a single semiconductor device, which can then form a memory card such as a PCMCIA card, a compact flash memory card (CF), a smart media card (SM or SMC), a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro or eMMC), an SD card (SD, miniSD, microSD or SDHC), or a universal flash memory (UFS).

[0090] Figure 8 This is a diagram illustrating a solid-state drive (SSD) system of a memory device according to an embodiment of the present disclosure.

[0091] Reference Figure 8The SSD system 4000 may include a host 4100 and an SSD 4200. The SSD 4200 can exchange signals with the host 4100 through a signal connector 4001 and can receive power through a power connector 4002. The SSD 4200 may include a controller 4210, a plurality of memory devices 4221 to 422n, an auxiliary power supply 4230, and a buffer memory 4240.

[0092] The controller 4210 can control multiple memory devices 4221 to 422n in response to signals received from the host 4100. In this embodiment, the received signals can be signals based on the interface between the host 4100 and the SSD 4200. For example, the signals can be defined by at least one of various interfaces such as Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), Fast PCI (PCI-E), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Memory (UFS), WiFi, Bluetooth, and High-Speed ​​Non-Volatile Memory (NVMe).

[0093] Each of the plurality of memory devices 4221 to 422n may include a unit therein capable of storing data. Each of the memory devices 4221 to 422n can be coupled with... Figure 1 The memory device 100 shown is configured in the same manner.

[0094] Auxiliary power supply 4230 can be connected to host 4100 via power connector 4002. Auxiliary power supply 4230 can be supplied with power voltage from host 4100 and can be charged. When power supply from host 4100 is not smooth, auxiliary power supply 4230 can provide power voltage to SSD 4200. In implementations, auxiliary power supply 4230 can be located inside or outside SSD 4200. For example, auxiliary power supply 4230 can be located within the motherboard and can also provide auxiliary power to SSD 4200.

[0095] Buffer memory 4240 can be used as buffer memory for SSD 4200. For example, buffer memory 4240 can temporarily store data received from host 4100 or data received from multiple memory devices 4221 to 422n, or it can temporarily store metadata (e.g., a mapping table). Buffer memory 4240 may include volatile memory such as dynamic random access memory (DRAM), synchronous DRAM (SDRAM), double data rate (DDR) SDRAM, and low power DDR (LPDDR) SDRAM, or non-volatile memory such as ferroelectric RAM (FRAM), resistive RAM (ReRAM), spin-transfer torque magnetic RAM (STT-MRAM), and phase-change RAM (PRAM).

[0096] This disclosure, in its implementation, can prevent bridging during the formation of dummy contacts in a memory device, thereby increasing the yield of the manufacturing process for the memory device.

[0097] Cross-references to related applications

[0098] This application claims priority to Korean Patent Application No. 10-2021-0182933, filed on December 20, 2021, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference.

Claims

1. A memory device, the memory device comprising: A connection structure formed on a substrate; Lower contact, the lower contact being formed on the connection structure; Upper contact, the upper contact being formed on the lower contact; A dummy pattern that surrounds and is spaced apart from the lower contact; An etch stop pattern is formed in the upper region of the dummy pattern; as well as A dummy contact is formed above the etch stop pattern.

2. The memory device according to claim 1, further comprising: A transistor that transmits or blocks voltage between the connection structure and the lower contact.

3. The memory device according to claim 1, wherein, The lower contact contacts the connection structure by perpendicularly passing through the insulating pattern surrounded by the dummy pattern.

4. The memory device according to claim 1, wherein, The upper contact contacts the lower contact by perpendicularly passing through a stacked structure formed above the lower contact, the dummy pattern, and the etch stop pattern.

5. The memory device according to claim 1, wherein, The lower contact and the upper contact are used as main contacts for electrical connection via the connection structure to the grounding terminal formed in the substrate.

6. The memory device according to claim 1, wherein, The lower contact, the upper contact, and the dummy contact are formed of the same material.

7. The memory device according to claim 1, wherein, The width of the upper contact is equal to the width of the dummy contact.

8. The memory device according to claim 1, wherein, The virtual pattern includes: First conductive layer; A first insulating layer is formed on the first conductive layer; A second conductive layer is formed on the first insulating layer; A second insulating layer, the second insulating layer being formed on the second conductive layer; and A third conductive layer is formed on the second insulating layer.

9. The memory device according to claim 1, wherein, The etch stop pattern is formed of a conductive material.

10. The memory device according to claim 1, wherein, The etch stop pattern is formed by at least one of tungsten (W), titanium (Ti), and titanium nitride (TiN).

11. A method of manufacturing a memory device, the method comprising the following steps: A substrate is provided, wherein a cell region and a peripheral region are defined; Conductive patterns are formed on the substrate in the unit region and the peripheral region; A lower contact is formed between the conductive patterns in the peripheral region; An etch stop pattern is formed in the conductive pattern in the unit region and the peripheral region; A stacked structure is formed on the etch stop pattern; Holes are formed in the stacked structure in the peripheral region to expose the lower contact and the etch stop pattern, respectively; as well as A dummy contact that contacts the portion of the etch stop pattern and an upper contact that contacts the lower contact are formed by filling the holes formed in the peripheral region with a conductive material.

12. The method according to claim 11, further comprising the following step: Before the conductive pattern is formed on the substrate. A junction region is formed in the substrate; as well as A connection structure is formed on the junction region.

13. The method according to claim 12, wherein, The lower contact is formed to contact the connection structure.

14. The method according to claim 11, wherein, The etch stop pattern formed in the cell region is formed along the direction extending from the slit that separates the memory blocks, and The pattern formed in the etch stop pattern in the peripheral region is formed in the region where the dummy contact is to be formed.

15. The method according to claim 11, wherein, The etch stop pattern is formed by at least one of tungsten (W), titanium (Ti), and titanium nitride (TiN).

16. The method according to claim 11, wherein, The etch stop pattern is formed by a mixture of at least two of tungsten (W), titanium (Ti), and titanium nitride (TiN).

17. The method according to claim 11, wherein, The step of forming the hole is performed by an etching process used to remove a portion of the stacked structure in the vertical direction.

18. The method according to claim 11, further comprising the step of: Between forming the stacked structure and forming the holes Forming a unit plug that passes through the stacked structure in the unit region; A slit is formed to expose the etch stop pattern by passing through the stacked structure between the unit plugs; The groove is formed by removing a portion of the conductive pattern and the etch stop pattern formed below the slit; The groove is filled with a conductive material; Remove the sacrificial pattern included in the stacked structure in the unit region; as well as Gate lines are formed in the region from which the sacrifice pattern has been removed.

19. The method according to claim 18, wherein, The steps for forming the unit plug include the following: Forming vertical holes through the stacked structure formed in the unit region; and A barrier layer, a charge trapping layer, a tunnel isolation layer, a channel layer, and a core pillar are formed from the side surface of the vertical hole.

20. The method according to claim 18, wherein, The step of forming the slit is performed by an etching process for separating the stacked structure formed in the cell region in a first direction.

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