Display substrate and display device

Abstract

The present disclosure provides a display substrate and a display device. The display substrate comprises a substrate and an initialization signal transmission layer disposed on the substrate; the initialization signal transmission layer comprises a plurality of first transmission portions and a plurality of second transmission portions; the plurality of first transmission portions are arranged along a first direction, and each first transmission portion comprises at least a portion extending along a second direction intersecting the first direction; each second transmission portion comprises at least a portion extending along the first direction, and adjacent first transmission portions are coupled by at least one second transmission portion; a target transmission portion is included in the plurality of first transmission portions, and a second transmission portion between the target transmission portion and an adjacent previous first transmission portion is staggered with a second transmission portion between the target transmission portion and an adjacent next first transmission portion in the second direction.

Description

[0001] This application is a divisional application of Chinese patent application No. 202180002610.3, filed on September 23, 2021. Technical Field

[0002] This disclosure relates to the field of display technology, and more particularly to a display substrate and a display device. Background Technology

[0003] Touch panels are increasingly used in computers, watches, mobile phones, and other fields as an important medium for human-computer interaction. As screen sizes become larger and refresh rates become higher, the panels face increasingly heavy loading loads and problems such as insufficient charging time. Summary of the Invention

[0004] The purpose of this disclosure is to provide a display substrate and a display device.

[0005] To achieve the above objectives, this disclosure provides the following technical solution:

[0006] A first aspect of this disclosure provides a display substrate, comprising: a substrate and a plurality of sub-pixels disposed on the substrate, each sub-pixel including a sub-pixel driving circuit, the orthographic projection of the sub-pixel driving circuit onto the substrate having a maximum first width along a second direction; the display substrate further comprising:

[0007] An initialization signal transmission layer is disposed on the substrate; the initialization signal transmission layer includes a plurality of first transmission sections and a plurality of second transmission sections; the plurality of first transmission sections are arranged along a first direction, each first transmission section including at least a portion extending along a second direction, the second direction intersecting the first direction; each second transmission section including at least a portion extending along the first direction, and adjacent first transmission sections are coupled to each other through at least one second transmission section.

[0008] The plurality of first transmission sections includes a target transmission section, the target transmission section including at least a portion extending along the second direction, a second transmission section located between the target transmission section and its adjacent previous first transmission section, and a second transmission section located between the target transmission section and its adjacent next first transmission section offset from the target transmission section by a first distance in the second direction, the first distance being greater than or equal to the first width.

[0009] Optionally, the display substrate includes a first initialization signal transmission layer and a second initialization signal transmission layer;

[0010] The initialization signal transmission layer is either the first initialization signal transmission layer or the second initialization signal transmission layer; or...

[0011] The display substrate includes at least two initialization signal transmission layers, the first of which is the first initialization signal transmission layer, and the second of which is the second initialization signal transmission layer.

[0012] Optionally, the display substrate may further include a third initialization signal transmission layer.

[0013] Optionally, the third of the at least two initialization signal transmission layers is the third initialization signal transmission layer.

[0014] Optionally, the display substrate includes a first initialization signal transmission layer, a second initialization signal transmission layer, and a third initialization signal transmission layer;

[0015] The initialization signal transmission layer is one of the first initialization signal transmission layer, the second initialization signal transmission layer, and the third initialization signal transmission layer.

[0016] Optionally, the plurality of first transmission units includes a non-target transmission unit, a second transmission unit located between the non-target transmission unit and its adjacent previous first transmission unit, and a second transmission unit located between the non-target transmission unit and its adjacent next first transmission unit, which are arranged in a row along the first direction.

[0017] Optionally, the second transmission unit in the first initialization signal transmission layer and the second transmission unit in the second initialization signal transmission layer are offset in the second direction.

[0018] Optionally, the second transmission unit in the first initialization signal transmission layer and the second transmission unit in the second initialization signal transmission layer are offset in the second direction; and / or,

[0019] The second transmission unit in the first initialization signal transmission layer and the second transmission unit in the third initialization signal transmission layer are offset in the second direction; and / or,

[0020] The second transmission unit in the second initialization signal transmission layer and the second transmission unit in the third initialization signal transmission layer are offset in the second direction.

[0021] Optionally, the display substrate further includes a plurality of sub-pixels, each sub-pixel including a sub-pixel driving circuit; the plurality of sub-pixel driving circuits included in the plurality of sub-pixel are divided into multiple rows of sub-pixel driving circuits, and each sub-pixel driving circuit in each row of sub-pixel driving circuits is coupled to the corresponding first transmission unit.

[0022] Adjacent first transmission units are coupled to each other through a plurality of second transmission units, wherein the distance between adjacent second transmission units is greater than or equal to the maximum width of the orthographic projection of a sub-pixel driving circuit on the substrate in the second direction.

[0023] Optionally, in the sub-pixel driving circuits located in the same row, adjacent sub-pixel driving circuits are arranged symmetrically.

[0024] The sub-pixel also includes multiple data lines and multiple power lines, with adjacent data lines arranged symmetrically along the second direction and adjacent power lines arranged symmetrically along the second direction.

[0025] Optionally, the first transmission unit and the second transmission unit are formed as an integral structure.

[0026] Optionally, the display substrate further includes a plurality of sub-pixels; each sub-pixel includes a sub-pixel driving circuit, and the sub-pixel driving circuit includes a driving transistor;

[0027] The orthographic projection of the second transmission section onto the substrate overlaps with the orthographic projection of the gate of the corresponding driving transistor onto the substrate.

[0028] Optionally, the display substrate includes a plurality of data lines, each data line including at least a portion extending along the first direction;

[0029] The sub-pixel driving circuit further includes: a first transistor and a fourth transistor, wherein the first transistor is coupled to the first terminal and the second terminal of the driving transistor, and the fourth transistor is coupled to the first terminal of the driving transistor and the corresponding data line; the first transistor includes a first active layer, and the fourth transistor includes a fourth active layer.

[0030] At least a portion of the orthographic projection of the second transmission unit onto the substrate is located between the orthographic projection of the first active layer onto the substrate and the orthographic projection of the fourth active layer onto the substrate.

[0031] Optionally, the display substrate further includes a power line; the sub-pixel further includes a light-emitting element; the sub-pixel driving circuit further includes a fifth transistor and a sixth transistor, the fifth transistor being coupled to the first terminal of the driving transistor and the corresponding power line, and the sixth transistor being coupled to the second terminal of the driving transistor and the light-emitting element; the fifth transistor includes a fifth active layer, and the sixth transistor includes a sixth active layer;

[0032] At least a portion of the orthographic projection of the second transmission unit onto the substrate is located between the orthographic projection of the fifth active layer onto the substrate and the orthographic projection of the sixth active layer onto the substrate.

[0033] Optionally, the plurality of sub-pixels are divided into multiple groups of sub-pixels, each group of sub-pixels including a first sub-pixel and a second sub-pixel;

[0034] Both the first sub-pixel and the second sub-pixel include a second conductive portion, and the second conductive portion in the first sub-pixel is coupled to the second conductive portion in the second sub-pixel;

[0035] The fifth transistor in the first sub-pixel is coupled to the second conductive portion; the fifth transistor in the second sub-pixel is coupled to the second conductive portion, and the second conductive portion in the second sub-pixel is coupled to the corresponding power line;

[0036] At least a portion of the second transmission unit is located in the sub-pixel driving circuit layout area of ​​the first sub-pixel, and the orthographic projection of the second transmission unit on the substrate does not overlap with the orthographic projection of the second conductive part in the first sub-pixel on the substrate.

[0037] Optionally, the sub-pixel driving circuit further includes an eighth transistor, which is coupled to the first or second terminal of the driving transistor, and the eighth transistor is used to reset the first or second terminal;

[0038] The eighth transistor includes an eighth active layer, and at least a portion of the orthographic projection of the second transmission portion onto the substrate is aligned with the orthographic projection of the eighth active layer onto the substrate along the second direction.

[0039] Optionally, the display substrate includes a plurality of sub-pixels, each sub-pixel including a light-emitting element and a sub-pixel driving circuit; the sub-pixel driving circuit includes a driving transistor and further includes:

[0040] The second transistor is coupled to the gate of the driving transistor and the initialization signal transmission layer, respectively.

[0041] A seventh transistor is coupled to both the light-emitting element and the initialization signal transmission layer.

[0042] Optionally, the display substrate includes a plurality of sub-pixels, each sub-pixel including a light-emitting element and a sub-pixel driving circuit; the sub-pixel driving circuit includes a driving transistor and further includes:

[0043] The second transistor is coupled to the gate of the driving transistor and the first initialization signal transmission layer, respectively.

[0044] The seventh transistor is coupled to both the light-emitting element and the second initialization signal transmission layer.

[0045] Optionally, the display substrate includes a plurality of sub-pixels, each sub-pixel including a light-emitting element and a sub-pixel driving circuit; the sub-pixel driving circuit includes a driving transistor and further includes:

[0046] The second transistor is coupled to the gate of the driving transistor and the first initialization signal transmission layer, respectively.

[0047] A seventh transistor is coupled to both the light-emitting element and the second initialization signal transmission layer.

[0048] The eighth transistor is coupled to the first terminal of the driving transistor and the third initialization signal transmission layer.

[0049] Optionally, the display substrate further includes a display area and a peripheral area surrounding the display area, and the display substrate further includes:

[0050] A first signal line is located in the peripheral area of ​​the display substrate. The first signal line includes at least a portion extending along the first direction. The first signal line is coupled to the first initialization signal transmission layer.

[0051] The first signal line is made of a second source-drain metal layer, and the first transmission section of the first initialization signal transmission layer is made of a first gate metal layer.

[0052] Optionally, the display substrate further includes:

[0053] The second signal line is located in the peripheral area of ​​the display substrate. The second signal line includes at least a portion extending along the first direction. The orthographic projection of the first signal line on the substrate is located between the display area and the orthographic projection of the second signal line on the substrate. The second signal line is coupled to the second initialization signal transmission layer.

[0054] The second signal line and the first transmission section included in the second initialization signal transmission layer are both made of a first source-drain metal layer.

[0055] Optionally, the display substrate further includes:

[0056] The third signal line, the orthographic projection of the third signal line on the substrate, is located between the orthographic projections of the first signal line on the substrate and the orthographic projections of the second signal line on the substrate, and the third signal line is coupled to the third initialization signal transmission layer;

[0057] The third signal line is fabricated using the first source-drain metal layer, and the third initialization signal transmission layer is fabricated using the third gate metal layer.

[0058] Based on the above-described display substrate technical solution, a second aspect of this disclosure provides a display device including the above-described display substrate. Attached Figure Description

[0059] The accompanying drawings, which are included to provide a further understanding of this disclosure and form part of this disclosure, illustrate exemplary embodiments of the present disclosure and are used to explain the disclosure, but do not constitute an undue limitation of the disclosure. In the drawings:

[0060] Figure 1 This is a first circuit diagram of a sub-pixel driving circuit provided in an embodiment of the present disclosure;

[0061] Figure 2 This is a first structural schematic diagram of a display substrate provided in an embodiment of the present disclosure;

[0062] Figure 3 A schematic diagram of a target transmission unit and a non-target transmission unit provided in an embodiment of this disclosure;

[0063] Figure 4 This is a second circuit diagram of the sub-pixel driving circuit provided in an embodiment of the present disclosure;

[0064] Figure 5 This is a schematic diagram of the second structure of the display substrate provided in an embodiment of the present disclosure;

[0065] Figure 6 A schematic diagram of the third structure of the display substrate provided in an embodiment of this disclosure;

[0066] Figure 7 A third circuit diagram of the sub-pixel driving circuit provided in an embodiment of this disclosure;

[0067] Figure 8 This is a schematic diagram of the fourth structure of the display substrate provided in an embodiment of this disclosure;

[0068] Figure 9 A timing diagram illustrating the charging of node N1 by the first initialization signal transmission layer according to an embodiment of this disclosure;

[0069] Figure 10 A schematic diagram illustrating the reset speed of the mesh-like initialization signal transmission layer and the existing initialization signal transmission layer for anode reset, as provided in the embodiments of this disclosure;

[0070] Figure 11 This is a schematic diagram of the first layout of sub-pixels provided in an embodiment of the present disclosure;

[0071] Figure 12 This is a schematic diagram of the second layout of sub-pixels provided in an embodiment of the present disclosure;

[0072] Figure 13This is a schematic diagram of the layout of two adjacent sub-pixels provided in an embodiment of this disclosure;

[0073] Figure 14 for Figure 13 A schematic diagram of the layout of the light-shielding layer in the middle;

[0074] Figure 15 for Figure 13 A schematic diagram of the layout of the poly active layer in the diagram;

[0075] Figure 16 for Figure 13 A schematic diagram of the layout of the first gate metal layer;

[0076] Figure 17 for Figure 13 Schematic diagram of the layout of the second gate metal layer;

[0077] Figure 18 for Figure 13 A schematic diagram of the layout of the first connecting hole;

[0078] Figure 19 for Figure 13 A schematic diagram of the layout of the second connecting hole;

[0079] Figure 20 for Figure 13 Schematic diagram of the layout of the third gate metal layer;

[0080] Figure 21 for Figure 13 Schematic diagram of the layout of the medium oxide active layer;

[0081] Figure 22 for Figure 13 A schematic diagram of the layout of the first source / drain metal layer in the middle;

[0082] Figure 23 for Figure 13 A schematic diagram of the via layout formed in the first planarization layer;

[0083] Figure 24 for Figure 13 A schematic diagram of the layout of the second source / drain metal layer in the middle;

[0084] Figure 25 for Figure 13 A schematic diagram of the via layout formed in the second flattening layer.

[0085] Figure 26 This is a schematic diagram of the layout of the second source / drain metal layer and the anode layer provided in an embodiment of this disclosure;

[0086] Figure 27 A schematic diagram of the layout of the anode layer provided in an embodiment of this disclosure;

[0087] Figure 28A schematic diagram of the layout of pixel openings provided in an embodiment of this disclosure;

[0088] Figure 29a This is a layout method for sub-pixels provided in an embodiment of the present disclosure;

[0089] Figure 29b Another layout method for sub-pixels provided in the embodiments of this disclosure;

[0090] Figure 30 A timing diagram of the sub-pixel driving circuit provided in an embodiment of this disclosure;

[0091] Figure 31a for Figure 13 A schematic diagram of the layout of the middle poly active layer and the first gate metal layer;

[0092] Figure 31b for Figure 13 A schematic diagram of the layout of the oxide active layer, the second gate metal layer, and the third gate metal layer;

[0093] Figure 32 This is a first schematic diagram of the signal line film layer provided in an embodiment of this disclosure;

[0094] Figure 33 This is a second schematic diagram of the signal line film layer provided in an embodiment of this disclosure;

[0095] Figure 34 This is a third schematic diagram of the signal line film layer provided in an embodiment of this disclosure;

[0096] Figure 35 This is a fourth schematic diagram of the signal line film layer provided in an embodiment of this disclosure;

[0097] Figure 36 for Figure 35 Schematic diagram of the layout of the middle shading layer;

[0098] Figure 37 This is a fifth schematic diagram of the signal line film layer provided in the embodiments of this disclosure;

[0099] Figure 38 for Figure 37 A schematic diagram of the layout of the conductive connection pattern in the middle;

[0100] Figure 39 A schematic diagram of the layout of a display substrate provided in an embodiment of this disclosure;

[0101] Figure 40 for Figure 39 Schematic diagram of the layout of the middle shading layer;

[0102] Figure 41 for Figure 39 Schematic diagram of the layout of the poly active layer;

[0103] Figure 42 for Figure 39 A schematic diagram of the layout of the first gate metal layer;

[0104] Figure 43 for Figure 39 Schematic diagram of the layout of the second gate metal layer;

[0105] Figure 44 for Figure 39 A schematic diagram of the layout of the first connecting hole;

[0106] Figure 45 for Figure 39 A schematic diagram of the layout of the oxide active layer in the image;

[0107] Figure 46 for Figure 39 A schematic diagram of the layout of the second connecting hole;

[0108] Figure 47 for Figure 39 A schematic diagram of the layout of the third gate metal layer;

[0109] Figure 48 for Figure 39 A schematic diagram of the layout of the first source / drain metal layer in the image;

[0110] Figure 49 for Figure 39 A schematic diagram of the via layout formed by the first planarization layer in the middle;

[0111] Figure 50 for Figure 39 A schematic diagram of the layout of the second source / drain metal layer in the image;

[0112] Figure 51 for Figure 39 A schematic diagram of the layout of the first and second source / drain metal layers in the image;

[0113] Figure 52 This is a cross-sectional schematic diagram of a display substrate provided in an embodiment of this disclosure;

[0114] Figure 53 This is another schematic diagram of the layout of the display substrate provided in an embodiment of the present disclosure;

[0115] Figure 54 This is a schematic diagram of a conductive connection pattern provided in an embodiment of the present disclosure. Detailed Implementation

[0116] To further illustrate the display substrate and display device provided in the embodiments of this disclosure, a detailed description is provided below with reference to the accompanying drawings.

[0117] As screen sizes increase and refresh rates rise, the loading load on panels becomes heavier, leading to more severe problems such as insufficient charging time. Therefore, reducing loading and shortening charging time are urgent issues that need to be addressed.

[0118] Please see Figure 2 , Figure 3 , Figure 5 , Figure 6 and Figure 8 This disclosure provides a display substrate, including: a substrate and a plurality of sub-pixels disposed on the substrate, each sub-pixel including a sub-pixel driving circuit, the orthographic projection of the sub-pixel driving circuit on the substrate having a maximum first width along a second direction; the display substrate further includes: an initialization signal transmission layer (e.g., a first initialization signal transmission layer Vinit1, a second initialization signal transmission layer Vinit2, and a third initialization signal transmission layer Vinit3) disposed on the substrate; the initialization signal transmission layer includes a plurality of first transmission portions 20 and a plurality of second transmission portions 21; the plurality of first transmission portions 20 are arranged along a first direction, each first transmission portion 20 including at least a portion extending along a second direction, the second direction intersecting the first direction; each second transmission portion 21 includes at least a portion extending along the first direction, and adjacent first transmission portions 20 are coupled through at least one second transmission portion 21;

[0119] The plurality of first transmission units 20 includes a target transmission unit 201, the target transmission unit 201 including at least a portion extending along the second direction, a second transmission unit 21 located between the target transmission unit 201 and its adjacent previous first transmission unit 20, and the second transmission unit 21 located between the target transmission unit 201 and its adjacent next first transmission unit 20 being offset from the target transmission unit 201 by a first distance in the second direction, the first distance being greater than or equal to the first width.

[0120] For example, the first distance is equal to the first width; or the first distance is an integer multiple of the first width.

[0121] For example, the second transmission section 21, which is offset along the second direction, is connected to the sub-pixel driving circuits of different columns.

[0122] It needs to be explained that, Figure 3 The thicker lines represent the target transmission unit 201, and the thinner lines represent the non-target transmission unit 202. Figure 2 , Figure 5 , Figure 6 and Figure 8 The diagram also illustrates the fan-out region FO, the gate drive circuit GOA, and the negative power supply line VSS.

[0123] It is worth noting that Figure 1 , Figure 4 and Figure 7 In this circuit, the timing of the signals transmitted by the reset line R1, the first scan line S1, the second scan line S2, the third scan line S3, and the light emission control line E1 can be set according to actual needs. For example, without the eighth transistor T8, the timing of the signals transmitted by the first scan line S1, the second scan line S2, and the third scan line S3 can be set to be the same, but it is not limited to this.

[0124] It is worth noting that both the target transmission unit 201 and the non-target transmission unit 202 in this disclosure are used to transmit initialization signals. They are not related to being or not being transmission targets, but are simply different names defined according to the different layout of the second transmission unit 21 to which they are coupled.

[0125] For example, the initialization signal transmission layer is used to transmit initialization signals.

[0126] For example, the display substrate includes a display area AA and a peripheral area 40 surrounding the display area AA. The first transmission unit 20 can extend from the display area AA to the peripheral area 40 and can be coupled to a corresponding signal line of the peripheral area 40 to receive a corresponding initialization signal.

[0127] For example, the display substrate includes a plurality of sub-pixels, the plurality of sub-pixels including a plurality of sub-pixel driving circuits, the plurality of sub-pixel driving circuits being arranged in an array and capable of being divided into multiple rows of sub-pixel driving circuits arranged along a first direction, each row of sub-pixel driving circuits including a plurality of sub-pixel driving circuits arranged along a second direction.

[0128] For example, the arrangement of the plurality of sub-pixels includes: RGBG, GGRB, etc.

[0129] Figure 29a This is a schematic diagram of a planar structure of a display substrate according to an embodiment of the present disclosure. Figure 29aAs shown, the display substrate may include multiple pixel units P arranged in a matrix. At least one pixel unit P may include a first-color sub-pixel P1 emitting a first-color light, a second-color sub-pixel P2 emitting a second-color light, and two third-color sub-pixels P3 emitting a third-color light. Each of the four sub-pixels may include a sub-pixel driving circuit and a light-emitting element. The sub-pixel driving circuit in each sub-pixel is connected to a scan line, a data line, and a light-emitting control line, respectively. The sub-pixel driving circuit is configured to receive the data voltage transmitted by the data line and output a corresponding current to the light-emitting element under the control of the scan line and the light-emitting control line. The light-emitting element in each sub-pixel is connected to the sub-pixel driving circuit of its respective sub-pixel and is configured to emit light of a corresponding brightness in response to the current output by the sub-pixel driving circuit of its respective sub-pixel.

[0130] In an exemplary embodiment, the first color sub-pixel P1 can be a red sub-pixel (R) emitting red light, and the sub-pixel driving circuit of sub-pixel P1 is electrically connected to the first electrode (i.e., anode) of the light-emitting element emitting red light. The second color sub-pixel P2 can be a blue sub-pixel (B) emitting blue light, and the sub-pixel driving circuit of sub-pixel P2 is electrically connected to the first electrode of the light-emitting element emitting blue light. The third sub-pixel P3 can be a green sub-pixel (G) emitting green light, and the sub-pixel driving circuit of sub-pixel P3 is electrically connected to the first electrode of the light-emitting element emitting green light. In an exemplary embodiment, the main body shape of the first electrode of the sub-pixel can be rectangular, rhomboid, pentagonal, or hexagonal. The first electrodes of the four sub-pixels can be arranged in a square to form a GGRB pixel arrangement, such as... Figure 29a As shown; alternatively, a diamond arrangement can be used to form an RGBG pixel layout, such as... Figure 29b As shown. In an exemplary embodiment, the four sub-pixels can be arranged in a horizontal or vertical manner. In an exemplary embodiment, a pixel unit can include three sub-pixels, and the first electrodes of the three sub-pixels can be arranged in a horizontal, vertical, or triangular manner. This disclosure does not limit the specific arrangement.

[0131] For example, the multiple rows of sub-pixel driving circuits correspond one-to-one with the multiple first transmission units 20, and each sub-pixel driving circuit in each row of sub-pixel driving circuits is coupled to the corresponding first transmission unit 20.

[0132] For example, the first transmission section 20 includes a portion extending in a second direction and also includes a portion extending in a first direction.

[0133] For example, the first transmission unit 20 includes a portion extending along a second direction, a portion extending along a first direction, and a portion extending along a third direction, which intersects both the first direction and the second direction.

[0134] For example, adjacent first transmission units 20 are coupled together by a plurality of second transmission units 21. The number of the plurality of second transmission units 21 is less than or equal to the number of sub-pixel driving circuits included in a row of sub-pixel driving circuits.

[0135] For example, a portion of the second transmission unit 21 can extend from the display area AA to the peripheral area 40. For example, this portion of the second transmission unit 21 can also be coupled to a corresponding signal line in the peripheral area 40 to receive a corresponding initialization signal.

[0136] For example, the first transmission unit 20 and the second transmission unit 21 are arranged on the same layer or on different layers.

[0137] For example, the plurality of first transmission units 20 includes at least one target transmission unit 201, and a second transmission unit 21 located between the target transmission unit 201 and its adjacent previous first transmission unit 20 is offset from the second transmission unit 21 located between the target transmission unit 201 and its adjacent next first transmission unit 20 in the second direction.

[0138] For example, the aforementioned offset distance is greater than or equal to the maximum width of the orthogonal projection of a sub-pixel driving circuit on the substrate in the second direction.

[0139] For example, the first direction includes the longitudinal direction, and the second direction includes the transverse direction.

[0140] For example, the display substrate includes a plurality of gate lines and a plurality of data lines, the gate lines including at least a portion extending along the second direction, and the data lines including at least a portion extending along the first direction.

[0141] As can be seen from the specific structure of the display substrate described above, the display substrate provided in this embodiment includes an initialization signal transmission layer comprising a plurality of first transmission portions 20 and a plurality of second transmission portions 21. Each first transmission portion 20 includes at least a portion extending along a second direction, and each second transmission portion 21 includes at least a portion extending along a first direction. Adjacent first transmission portions 20 are coupled together via at least one second transmission portion 21. This configuration results in the initialization signal transmission layer being formed in a grid pattern. Compared to a conventional initialization signal transmission layer that only includes a horizontal portion, this grid-like initialization signal transmission layer can reduce initialization signal loading by approximately 20%, resulting in faster initialization signal charging and better reset performance for the corresponding nodes. This beneficial effect is even more significant for large-screen, high-frequency panels.

[0142] More specifically, such as Figure 9 The diagram shows a simulation of the initialization signal transmission layer using a mesh design. During the effective low-level period of the reset signal input at the reset terminal, the initialization signal transmitted by the initialization signal transmission layer can be fully written, thus resetting node N1.

[0143] like Figure 10 As shown, the reset speed when using a grid-shaped initialization signal transmission layer is faster than the reset speed when using an initialization signal transmission layer that only includes the horizontal portion. When using an initialization signal transmission layer that only includes the horizontal portion, the reset speed achievable at the edge of the horizontal portion is faster than the reset speed achievable at the center of the horizontal portion.

[0144] In the display substrate provided in this embodiment, the plurality of first transmission sections 20 include a target transmission section 201. A second transmission section 21 located between the target transmission section 201 and its adjacent previous first transmission section 20 is offset from the second transmission section 21 located between the target transmission section 201 and its adjacent next first transmission section 20 in the second direction. This arrangement helps to increase the spacing between adjacent second transmission sections 21 along the first direction, reduce the layout density of the second transmission sections 21, and overcome the problem of insufficient layout space.

[0145] like Figure 5 and Figure 6 As shown, in some embodiments, the display substrate is configured to include a first initialization signal transmission layer Vinit1 and a second initialization signal transmission layer Vinit2;

[0146] The initialization signal transmission layer is either the first initialization signal transmission layer Vinit1 or the second initialization signal transmission layer Vinit2; or...

[0147] The display substrate includes at least two initialization signal transmission layers, the first of which is the first initialization signal transmission layer Vinit1, and the second of which is the second initialization signal transmission layer Vinit2.

[0148] For example, the first initialization signal transmission layer Vinit1 is used to transmit the first initialization signal, and the second initialization signal transmission layer Vinit2 is used to transmit the second initialization signal.

[0149] For example, the initialization signal transmission layer is either the first initialization signal transmission layer Vinit1 or the second initialization signal transmission layer Vinit2, such that the first initialization signal transmission layer Vinit1 or the second initialization signal transmission layer Vinit2 includes the first transmission unit 20 and the second transmission unit 21, and the first initialization signal transmission layer Vinit1 or the second initialization signal transmission layer Vinit2 is formed in a grid shape.

[0150] For example, the display substrate includes at least two initialization signal transmission layers, the first of which is the first initialization signal transmission layer Vinit1, and the second of which is the second initialization signal transmission layer Vinit2, such that both the first initialization signal transmission layer Vinit1 and the second initialization signal transmission layer Vinit2 include the first transmission part 20 and the second transmission part 21, and both the first initialization signal transmission layer Vinit1 and the second initialization signal transmission layer Vinit2 are formed in a mesh shape.

[0151] For example, the first initialization signal transmission layer Vinit1 and the second initialization signal transmission layer Vinit2 are mutually insulated.

[0152] The above configuration allows at least one of the first initialization signal transmission layer Vinit1 and the second initialization signal transmission layer Vinit2 to be formed into a mesh structure, which helps to reduce the loading of the first initialization signal transmission layer Vinit1 and the second initialization signal transmission layer Vinit2.

[0153] like Figure 8 As shown, in some embodiments, the display substrate further includes a third initialization signal transmission layer, Vinit3.

[0154] For example, the third initialization signal transmission layer Vinit3 is used to transmit the third initialization signal.

[0155] For example, the first initialization signal, the second initialization signal, and the third initialization signal are all different.

[0156] For example, at least two of the first initialization signal, the second initialization signal, and the third initialization signal are different.

[0157] For example, the third initialization signal may be a high-level signal.

[0158] For example, the third initialization signal transmission layer Vinit3 includes only a plurality of the first transmission units 20. This arrangement reduces the overall layout space occupied by the first initialization signal transmission layer Vinit1, the second initialization signal transmission layer Vinit2, and the third initialization signal transmission layer Vinit3 when laying them out, thus reducing the layout difficulty of the first initialization signal transmission layer Vinit1, the second initialization signal transmission layer Vinit2, and the third initialization signal transmission layer Vinit3.

[0159] In some embodiments, the third of the at least two initialization signal transmission layers is the third initialization signal transmission layer Vinit3.

[0160] For example, the display substrate includes two initialization signal transmission layers, one of which is the first initialization signal transmission layer Vinit1, and the other of which is the third initialization signal transmission layer Vinit3. The second initialization signal transmission layer Vinit2 includes only a plurality of the first transmission units 20.

[0161] For example, the display substrate includes two initialization signal transmission layers, one of which is the second initialization signal transmission layer Vinit2, and the other of which is the third initialization signal transmission layer Vinit3. The first initialization signal transmission layer Vinit1 includes only a plurality of the first transmission units 20.

[0162] For example, the display substrate includes three initialization signal transmission layers, the first of which is the first initialization signal transmission layer Vinit1, the second of which is the second initialization signal transmission layer Vinit2, and the third of which is the third initialization signal transmission layer Vinit3.

[0163] In the display substrate provided in the above embodiments, at least two of the first initialization signal transmission lines, the second initialization signal transmission line, and the third initialization signal transmission line adopt a mesh structure, which is beneficial to reduce the loading of the first initialization signal transmission layer Vinit1, the second initialization signal transmission layer Vinit2, and / or the third initialization signal transmission layer Vinit3.

[0164] like Figure 8 As shown, in some embodiments, the display substrate is configured to include a first initialization signal transmission layer Vinit1, a second initialization signal transmission layer Vinit2, and a third initialization signal transmission layer Vinit3; the initialization signal transmission layer is one of the first initialization signal transmission layer Vinit1, the second initialization signal transmission layer Vinit2, and the third initialization signal transmission layer Vinit3.

[0165] For example, the initialization signal transmission layer is one of the first initialization signal transmission layer Vinit1, the second initialization signal transmission layer Vinit2, and the third initialization signal transmission layer Vinit3. The remaining two of the first initialization signal transmission layer Vinit1, the second initialization signal transmission layer Vinit2, and the third initialization signal transmission layer Vinit3 that are not specified each include only a plurality of the first transmission units 20.

[0166] The above setup not only helps reduce the loading of the initialization signal transmission line, but also overcomes the problem of insufficient layout space and reduces layout difficulty.

[0167] like Figure 2 and Figure 3 As shown, in some embodiments, the plurality of first transmission units 20 are configured to include a non-target transmission unit 202, a second transmission unit 21 located between the non-target transmission unit 202 and its adjacent previous first transmission unit 20, and the second transmission unit 21 located between the non-target transmission unit 202 and its adjacent next first transmission unit 20 are arranged in a row along the first direction.

[0168] For example, the plurality of first transmission units 20 includes a plurality of non-target transmission units 202, and the plurality of non-target transmission units 202 includes at least two adjacent non-target transmission units 202, that is, there is no target transmission unit 201 between the at least two adjacent non-target transmission units 202.

[0169] For example, the non-separated second transmission section 21 can span 2 to 3 sub-pixel driving circuit layout areas along the first direction, that is, the non-separated second transmission section 21 can connect to two sub-pixel driving circuits located in the same column in the first direction, or connect to three sub-pixel driving circuits located in the same column.

[0170] Taking the second initialization signal transmission layer Vint2, which includes a first transmission unit 20 and a second transmission unit 21, as an example, the second transmission unit 21 can simultaneously electrically connect two or three sub-pixel driving circuits located in the same column in the first direction.

[0171] For example, the second transmission section 21 located between the non-target transmission section 202 and its adjacent previous first transmission section 20 is formed as an integral structure with the second transmission section 21 located between the non-target transmission section 202 and its adjacent next first transmission section 20.

[0172] For example, the second transmission section 21 located between the non-target transmission section 202 and its adjacent previous first transmission section 20 is not separated from the second transmission section 21 located between the non-target transmission section 202 and its adjacent next first transmission section 20 in the second direction. This arrangement effectively utilizes limited layout space, better achieves a grid-like structure for the initialization signal lines, and more effectively reduces the loading of the initialization signal lines.

[0173] like Figure 6 As shown, in some embodiments, the second transmission unit 21 in the first initialization signal transmission layer Vinit1 and the second transmission unit 21 in the second initialization signal transmission layer Vinit2 are offset in the second direction.

[0174] For example, the distance between the second transmission unit 21 in the first initialization signal transmission layer Vinit1 and the second transmission unit 21 in the second initialization signal transmission layer Vinit2 in the second direction is greater than or equal to the maximum layout space occupied by a sub-pixel driving circuit in the second direction.

[0175] The above configuration not only reduces the mutual interference between the first initialization signal transmission layer Vinit1 and the second initialization signal transmission layer Vinit2, but also reduces the layout difficulty of the first initialization signal transmission layer Vinit1 and the second initialization signal transmission layer Vinit2.

[0176] In some embodiments, the orthographic projection of the second transmission unit 21 in the first initialization signal transmission layer Vinit1 onto the substrate and the orthographic projection of the second transmission unit 21 in the second initialization signal transmission layer Vinit2 onto the substrate are at least partially overlapped.

[0177] The above configuration can make better use of the available layout space, enabling the first initialization signal transmission layer Vinit1 and the second initialization signal transmission layer Vinit2 to achieve a better grid-like layout.

[0178] In some embodiments, the second transmission unit 21 in the first initialization signal transmission layer Vinit1 and the second transmission unit 21 in the second initialization signal transmission layer Vinit2 are offset in the second direction; and / or,

[0179] The second transmission unit 21 in the first initialization signal transmission layer Vinit1 and the second transmission unit 21 in the third initialization signal transmission layer Vinit3 are offset in the second direction; and / or,

[0180] The second transmission unit 21 in the second initialization signal transmission layer Vinit2 and the second transmission unit 21 in the third initialization signal transmission layer Vinit3 are offset in the second direction.

[0181] For example, the second transmission unit 21 in the first initialization signal transmission layer Vinit1 and the second transmission unit 21 in the second initialization signal transmission layer Vinit2 are offset in the second direction; the second transmission unit 21 in the first initialization signal transmission layer Vinit1 and the second transmission unit 21 in the third initialization signal transmission layer Vinit3 are offset in the second direction; the second transmission unit 21 in the second initialization signal transmission layer Vinit2 and the second transmission unit 21 in the third initialization signal transmission layer Vinit3 are offset in the second direction.

[0182] For example, the term "offset" for the two second transmission units 21 mentioned in this disclosure means that the sub-pixel driving circuit layout areas where the two second transmission units 21 are located are not in the same column.

[0183] For example, the second transmission unit 21 in the first initialization signal transmission layer Vinit1 and the second transmission unit 21 in the second initialization signal transmission layer Vinit2 are offset in the second direction; or, the second transmission unit 21 in the first initialization signal transmission layer Vinit1 and the second transmission unit 21 in the third initialization signal transmission layer Vinit3 are offset in the second direction; or, the second transmission unit 21 in the second initialization signal transmission layer Vinit2 and the second transmission unit 21 in the third initialization signal transmission layer Vinit3 are offset in the second direction.

[0184] For example, the second transmission unit 21 in the first initialization signal transmission layer Vinit1 and the second transmission unit 21 in the second initialization signal transmission layer Vinit2 are offset in the second direction; the second transmission unit 21 in the first initialization signal transmission layer Vinit1 and the second transmission unit 21 in the third initialization signal transmission layer Vinit3 are offset in the second direction; the second transmission unit 21 in the second initialization signal transmission layer Vinit2 and the second transmission unit 21 in the third initialization signal transmission layer Vinit3 are not offset in the second direction.

[0185] For example, the second transmission unit 21 in the first initialization signal transmission layer Vinit1 and the second transmission unit 21 in the second initialization signal transmission layer Vinit2 are offset in the second direction; the second transmission unit 21 in the first initialization signal transmission layer Vinit1 and the second transmission unit 21 in the third initialization signal transmission layer Vinit3 are not offset in the second direction; the second transmission unit 21 in the second initialization signal transmission layer Vinit2 and the second transmission unit 21 in the third initialization signal transmission layer Vinit3 are offset in the second direction.

[0186] For example, the second transmission unit 21 in the first initialization signal transmission layer Vinit1 and the second transmission unit 21 in the second initialization signal transmission layer Vinit2 are not separated in the second direction; the second transmission unit 21 in the first initialization signal transmission layer Vinit1 and the second transmission unit 21 in the third initialization signal transmission layer Vinit3 are separated in the second direction; the second transmission unit 21 in the second initialization signal transmission layer Vinit2 and the second transmission unit 21 in the third initialization signal transmission layer Vinit3 are separated in the second direction.

[0187] For example, the second transmission unit 21 in the first initialization signal transmission layer Vinit1 and the second transmission unit 21 in the second initialization signal transmission layer Vinit2 are not separated in the second direction; the second transmission unit 21 in the first initialization signal transmission layer Vinit1 and the second transmission unit 21 in the third initialization signal transmission layer Vinit3 are not separated in the second direction; the second transmission unit 21 in the second initialization signal transmission layer Vinit2 and the second transmission unit 21 in the third initialization signal transmission layer Vinit3 are offset in the second direction.

[0188] For example, the second transmission unit 21 in the first initialization signal transmission layer Vinit1 and the second transmission unit 21 in the second initialization signal transmission layer Vinit2 are not separated in the second direction; the second transmission unit 21 in the first initialization signal transmission layer Vinit1 and the second transmission unit 21 in the third initialization signal transmission layer Vinit3 are staggered in the second direction; the second transmission unit 21 in the second initialization signal transmission layer Vinit2 and the second transmission unit 21 in the third initialization signal transmission layer Vinit3 are not separated in the second direction.

[0189] For example, the second transmission unit 21 in the first initialization signal transmission layer Vinit1 and the second transmission unit 21 in the second initialization signal transmission layer Vinit2 are offset in the second direction; the second transmission unit 21 in the first initialization signal transmission layer Vinit1 and the second transmission unit 21 in the third initialization signal transmission layer Vinit3 are not offset in the second direction; the second transmission unit 21 in the second initialization signal transmission layer Vinit2 and the second transmission unit 21 in the third initialization signal transmission layer Vinit3 are not offset in the second direction.

[0190] For example, the second transmission unit 21 in the first initialization signal transmission layer Vinit1 and the second transmission unit 21 in the second initialization signal transmission layer Vinit2 are not separated in the second direction; the second transmission unit 21 in the first initialization signal transmission layer Vinit1 and the second transmission unit 21 in the third initialization signal transmission layer Vinit3 are not separated in the second direction; the second transmission unit 21 in the second initialization signal transmission layer Vinit2 and the second transmission unit 21 in the third initialization signal transmission layer Vinit3 are not separated in the second direction.

[0191] The above configuration can make better use of the available layout space, enabling the first initialization signal transmission layer Vinit1 and the second initialization signal transmission layer Vinit2 to achieve a better grid-like layout.

[0192] In some embodiments, the display substrate further includes a plurality of sub-pixels, each sub-pixel including a sub-pixel driving circuit; the plurality of sub-pixel driving circuits included in the plurality of sub-pixels are divided into multiple rows of sub-pixel driving circuits, and each sub-pixel driving circuit in each row of sub-pixel driving circuits is coupled to the corresponding first transmission unit 20.

[0193] Adjacent first transmission units 20 are coupled to each other by a plurality of second transmission units 21, wherein the distance between adjacent second transmission units 21 is greater than or equal to the maximum width of the orthographic projection of a sub-pixel driving circuit on the substrate in the second direction.

[0194] For example, the sub-pixel driving circuit includes structures such as 7T1C (i.e., 7 transistors and one capacitor) or 8T1C (i.e., 8 transistors and one capacitor), but is not limited to these.

[0195] For example, adjacent first transmission units 20 are coupled to each other by a plurality of second transmission units 21, wherein the distance between adjacent second transmission units 21 is equal to the maximum width of the orthographic projection of two sub-pixel driving circuits on the substrate in the second direction.

[0196] For example, adjacent first transmission units 20 are coupled to each other by a plurality of second transmission units 21, wherein the distance between adjacent second transmission units 21 is equal to the maximum width of the orthographic projection of the four sub-pixel driving circuits on the substrate in the second direction.

[0197] The above configuration can make better use of the available layout space, enabling the first initialization signal transmission layer Vinit1 and the second initialization signal transmission layer Vinit2 to achieve a better grid-like layout.

[0198] like Figures 13 to 26 As shown, in some embodiments, in sub-pixel driving circuits located in the same row, adjacent sub-pixel driving circuits are arranged symmetrically; the sub-pixel also includes multiple data lines and multiple power lines VDD, with adjacent data lines arranged symmetrically along the second direction and adjacent power lines VDD arranged symmetrically along the second direction.

[0199] It should be noted that "symmetrical distribution overall" means that the transistor channels are symmetrically distributed and the sub-pixel driving circuit is roughly symmetrical as a whole, but it does not require that every film layer be completely symmetrical. For example, the second conductive part 82, which is made using the second source and drain metal layer, is asymmetrical.

[0200] For example, the display substrate further includes: multiple first scan lines S1, multiple second scan lines S2, multiple third scan lines S3, multiple reset lines R1, and multiple light emission control lines E1. The display substrate includes multiple driving circuit layout areas, each of which houses a corresponding sub-pixel driving circuit. The first scan lines S1 are partially symmetrically located in two adjacent driving circuit layout areas along a second direction, with the axis of symmetry located at the boundary between the two adjacent driving circuit layout areas and extending along the first direction.

[0201] The second scan line S2 is partially symmetrical in two adjacent drive circuit layout areas along the second direction, with the axis of symmetry located at the boundary of the two adjacent drive circuit layout areas and extending along the first direction.

[0202] The third scan line S3 is partially symmetrical in two adjacent drive circuit layout areas along the second direction, with the axis of symmetry located at the boundary of the two adjacent drive circuit layout areas and extending along the first direction.

[0203] The reset line R1 is partially symmetrical in two adjacent drive circuit layout areas along the second direction, with the axis of symmetry located at the intersection of the two adjacent drive circuit layout areas and extending along the first direction.

[0204] The light-emitting control line E1 is partially symmetrical in two adjacent drive circuit layout areas along the second direction, with the axis of symmetry located at the intersection of the two adjacent drive circuit layout areas and extending along the first direction.

[0205] For example, the sub-pixel further includes a light-emitting element, the light-emitting element including an anode, the anode being located on the side of the sub-pixel driving circuit facing away from the substrate.

[0206] The above arrangement ensures that the structures below the anode (i.e., between the anode and the substrate), such as the sub-pixel driving circuit, the first scan line S1, the second scan line S2, the third scan line S3, the reset line R1, the light emission control line E1, the data line, and the power line VDD, are symmetrically arranged, which can effectively improve the flatness of the anode 50. Furthermore, it can improve the pixel transmittance.

[0207] It needs to be explained, such as Figures 26 to 28 As shown, the display substrate includes a pixel defining layer that defines a pixel opening 51.

[0208] In some embodiments, the first transmission unit 20 and the second transmission unit 21 are configured as an integral structure.

[0209] The above configuration allows the first transmission unit 20 and the second transmission unit 21 to be formed and connected simultaneously in the same patterning process, thereby greatly simplifying the manufacturing process of the initial signal transmission layer and reducing manufacturing costs.

[0210] In some embodiments, such as Figure 7 As shown, the sub-pixel driving circuit includes a storage capacitor C, a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and an eighth transistor T8.

[0211] The storage capacitor C is coupled to both the power supply line VDD and the gate of the third transistor T3. For example, the gate of the third transistor T3 is multiplexed as the first plate of the storage capacitor C, and the second plate C-2 of the storage capacitor C is coupled to the power supply line VDD.

[0212] The gate of the first transistor T1 is coupled to the second scan line S2, the first terminal of the first transistor T1 is coupled to the second terminal of the third transistor T3, and the second terminal of the first transistor T1 is coupled to the gate of the third transistor T3.

[0213] The gate of the second transistor T2 is coupled to the reset line R1, the first terminal of the second transistor T2 is coupled to the first initialization signal transmission layer Vinit1, and the second terminal of the second transistor T2 is coupled to the gate of the third transistor T3.

[0214] The gate of the fourth transistor T4 is coupled to the first scan line S1, the first electrode of the fourth transistor T4 is coupled to the light emission control line E1, and the second electrode of the fourth transistor T4 is coupled to the first electrode of the third transistor T3.

[0215] The gate of the fifth transistor T5 is coupled to the light-emitting control line E1, the first terminal of the fifth transistor T5 is coupled to the power supply line VDD, and the second terminal of the fifth transistor T5 is coupled to the first terminal of the third transistor T3.

[0216] The gate of the sixth transistor T6 is coupled to the light-emitting control line E1, the first terminal of the sixth transistor T6 is coupled to the second terminal of the third transistor T3, and the second terminal of the sixth transistor T6 is coupled to the light-emitting element O1.

[0217] The gate of the seventh transistor T7 is coupled to the third scan line S3, the first electrode of the seventh transistor T7 is coupled to the second initialization signal transmission layer Vinit2, and the second electrode of the seventh transistor T7 is coupled to the light-emitting element O1.

[0218] The gate of the eighth transistor T8 is coupled to the third scan line S3, the first terminal of the eighth transistor T8 is coupled to the third initialization signal transmission layer Vinit3, and the second terminal of the eighth transistor T8 is coupled to the first or second terminal of the third transistor T3.

[0219] It needs to be explained that, Figure 7 The diagram also illustrates node N1, which is the node connected to the gate of the third transistor T3, which is the driving transistor.

[0220] In some embodiments, the first transistor T1 and the second transistor T2 are oxide thin-film transistors.

[0221] For example, the first transistor T1 and the second transistor T2 include oxide transistors, that is, the pixel driving circuit may simultaneously include low temperature polysilicon (LTPS) transistors and oxide transistors, that is, LTPO technology is used.

[0222] By setting the first transistor T1 and the second transistor T2 to be oxide thin film transistors, it is beneficial to reduce the gate leakage current of the driving transistor and ensure the stability of the gate potential of the driving transistor.

[0223] like Figure 30 As shown, Figure 7 The timing diagram corresponding to the driving method of the neutron pixel driving circuit can be divided into four stages: reset stage t1, threshold compensation stage t2, buffer stage t3, and emission stage t4.

[0224] During the reset phase t1: the light emission control line E1, the reset line R1, and the first scan line S1 output high-level signals, the second scan line S2 and the third scan line S3 output low-level signals, the second transistor T2, the seventh transistor T7, and the eighth transistor T8 are turned on, the first initialization signal transmission layer Vinit1 inputs the first initialization signal, the power supply line VDD inputs the power supply signal, and the second initialization signal transmission layer Vinit2 inputs the second initialization signal. The voltages of the first initialization signal and the second initialization signal can be the same or different.

[0225] During the threshold compensation stage t2: the light emission control line E1, the second scan line S2, and the third scan line S3 output high-level signals, the reset line R1 and the first scan line S1 output low-level signals, the first transistor T1 and the fourth transistor T4 are turned on, and the data line D1 writes the compensation voltage Vdata+Vth to the first node N1, where Vdata is the voltage value corresponding to the data signal and Vth is the threshold voltage of the driving transistor.

[0226] During the buffer phase t3: the light emission control line E1, the third scan line S3, and the first scan line S1 output high-level signals, while the second scan line S2 and the reset line R1 output low-level signals, and all transistors are turned off.

[0227] During the light-emitting stage t4: the third scan line S3 and the first scan line S1 output high-level signals, the light-emitting control line E1, the second scan line S2, and the reset line R1 output low-level signals, the fifth transistor T5 and the sixth transistor T6 are turned on, and the driving transistors emit light under the action of the voltage Vdata+Vth stored in the storage capacitor C.

[0228] It should be understood that in other exemplary embodiments, the driving method may not include a buffer phase; the second transistor T2 and the seventh transistor T7 may also be turned on at different phases. In the threshold compensation phase t2, the effective level (low level) duration corresponding to the first scan line S1 may be less than the effective level (high level) duration corresponding to the second scan line S2. In this threshold compensation phase t2, the first scan line S1 can scan one row of sub-pixel driving circuits, and the second scan line S2 can scan multiple rows of sub-pixel driving circuits, such as two rows of sub-pixel driving circuits.

[0229] By providing a high potential to the source of the driving transistor via T8, the image retention problem caused by the different gate-source voltage difference of the driving transistor under different data signals in the sub-pixel driving circuit can be effectively improved.

[0230] For example, the reset line R1 includes two layers, one layer made of a second gate metal layer and the other layer made of a third gate metal layer.

[0231] For example, the second scan line S2 includes two layers, one layer made of a second gate metal layer and the other layer made of a third gate metal layer.

[0232] like Figures 11 to 25 As shown, in some embodiments, the display substrate further includes a plurality of sub-pixels; each sub-pixel includes a sub-pixel driving circuit, and the sub-pixel driving circuit includes a driving transistor (i.e., a third transistor T3);

[0233] The orthographic projection of the second transmission section 21 onto the substrate overlaps with the orthographic projection of the gate of the corresponding driving transistor (i.e., the gate T3-g of the third transistor T3) onto the substrate.

[0234] It needs to be explained that, Figure 15 The diagram illustrates the third active layer 33 and the seventh active layer 37. Figure 21 The second active layer 32 is shown in the diagram.

[0235] like Figures 12 to 25 As shown, in some embodiments, the display substrate includes a plurality of data lines D1, each data line D1 including at least a portion extending along the first direction;

[0236] The sub-pixel driving circuit further includes: a first transistor T1 and a fourth transistor T4, wherein the first transistor T1 is coupled to the first and second terminals of the driving transistor, and the fourth transistor T4 is coupled to the first terminal of the driving transistor and the corresponding data line; the first transistor T1 includes a first active layer 31, and the fourth transistor T4 includes a fourth active layer 34.

[0237] At least a portion of the orthographic projection of the second transmission unit 21 onto the substrate is located between the orthographic projection of the first active layer 31 onto the substrate and the orthographic projection of the fourth active layer 34 onto the substrate.

[0238] like Figures 12 to 25 As shown, in some embodiments, the display substrate further includes a power line VDD; the sub-pixel further includes a light-emitting element O1; the sub-pixel driving circuit further includes a fifth transistor T5 and a sixth transistor T6, the fifth transistor T5 being coupled to the first terminal of the driving transistor and the corresponding power line VDD, and the sixth transistor T6 being coupled to the second terminal of the driving transistor and the light-emitting element O1; the fifth transistor T5 includes a fifth active layer 35, and the sixth transistor T6 includes a sixth active layer 36;

[0239] At least a portion of the orthographic projection of the second transmission unit 21 onto the substrate is located between the orthographic projection of the fifth active layer 35 onto the substrate and the orthographic projection of the sixth active layer 36 onto the substrate.

[0240] like Figures 12 to 25 As shown, in some embodiments, the plurality of sub-pixels are divided into multiple groups of sub-pixels, each group of sub-pixels including a first sub-pixel and a second sub-pixel;

[0241] Both the first sub-pixel and the second sub-pixel include a second conductive portion 82, and the second conductive portion 82 in the first sub-pixel is coupled to the second conductive portion 82 in the second sub-pixel.

[0242] The fifth transistor T5 in the first sub-pixel is coupled to the second conductive part 82; the fifth transistor T5 in the second sub-pixel is coupled to the second conductive part 82, and the second conductive part 82 in the second sub-pixel is coupled to the corresponding power line VDD;

[0243] At least a portion of the second transmission section 21 is located in the sub-pixel driving circuit layout area of ​​the first sub-pixel, and the orthographic projection of the second transmission section 21 on the substrate does not overlap with the orthographic projection of the second conductive section 82 in the first sub-pixel on the substrate.

[0244] like Figure 13 , Figure 22 , Figure 31a and Figure 31bAs shown, the first transistor T1 and the second transistor T2 are coupled to the gate of the third transistor T3 through the first conductive part 81. The fifth transistor T5 is coupled to the power line VDD through the second conductive part 82. The fourth transistor T4 is coupled to the corresponding data line through the third conductive part 83. The second transistor T2 is coupled to the first initialization signal transmission layer Vinit1 through the fourth conductive part 84. The first transistor T1 is coupled to the third transistor T3 through the fifth conductive part 85. The sixth transistor T6 and the seventh transistor T7 are coupled to the anode through the sixth conductive part 86. The eighth transistor T8 is coupled to the third transistor T3 through the seventh conductive part 87. The eighth transistor T8 is coupled to the third initialization signal transmission layer Vinit3 through the eighth conductive part 88.

[0245] For example, at least a portion of the second transmission unit 21 is located in the sub-pixel driving circuit layout area in the first sub-pixel, while the second transmission unit 21 is not located in the sub-pixel driving circuit layout area in the second sub-pixel.

[0246] For example, the second conductive portion 82 in the first sub-pixel and the second conductive portion 82 in the second sub-pixel are formed as an integral structure.

[0247] For example, the area of ​​the second conductive portion 82 in the first sub-pixel is smaller than the area of ​​the second conductive portion 82 in the second sub-pixel.

[0248] For example, the orthographic projection of the second transmission portion 21 on the substrate does not overlap with the orthographic projection of the second conductive portion 82 in the first sub-pixel on the substrate. For example, the orthographic projection of the second transmission portion 21 on the substrate and the orthographic projection of the second conductive portion 82 in the first sub-pixel on the substrate are aligned along a second direction.

[0249] The above arrangement helps to compensate for the symmetry of the second conductive part 82 in the first sub-pixel and the second sub-pixel.

[0250] like Figures 12 to 25 As shown, in some embodiments, the sub-pixel driving circuit further includes an eighth transistor T8, which is coupled to the first or second terminal of the driving transistor, and is used to reset the first or second terminal.

[0251] The eighth transistor T8 includes an eighth active layer 38, and at least a portion of the orthographic projection of the second transmission section 21 onto the substrate is arranged along the second direction with the orthographic projection of the eighth active layer 38 onto the substrate.

[0252] For example, in the same sub-pixel, the orthographic projection of the second transmission unit 21 onto the substrate is located between the projection of the seventh active layer 37 onto the substrate and the orthographic projection of the eighth active layer 38 onto the substrate.

[0253] In some embodiments, the orthographic projection of the second transmission section 21 on the substrate overlaps with the orthographic projection portion of the reset line R1 on the substrate.

[0254] In some embodiments, the orthographic projection of the second transmission section 21 on the substrate overlaps with the orthographic projection portion of the first scan line S1 on the substrate.

[0255] In some embodiments, the orthographic projection of the second transmission section 21 on the substrate overlaps with the orthographic projection portion of the second scan line S2 on the substrate.

[0256] In some embodiments, the orthographic projection of the second transmission section 21 on the substrate overlaps with the orthographic projection portion of the third scan line S3 on the substrate.

[0257] In the display substrate provided in the above embodiments, the second transmission unit 21 is arranged in the above position, which helps to reduce the layout difficulty of the second transmission unit 21 and also helps to improve the overall working stability of the sub-pixel driving circuit.

[0258] like Figure 1 As shown, in some embodiments, the display substrate includes a plurality of sub-pixels, each sub-pixel including a light-emitting element O1 and a sub-pixel driving circuit; the sub-pixel driving circuit includes a driving transistor and further includes:

[0259] The second transistor T2 is coupled to the gate of the driving transistor and the initialization signal transmission layer, respectively.

[0260] The seventh transistor T7 is coupled to the light-emitting element O1 and the initialization signal transmission layer.

[0261] For example, the second transistor T2 is coupled to the gate of the driving transistor and the first initialization signal transmission layer Vinit1, respectively; the seventh transistor T7 is coupled to the light-emitting element O1 and the first initialization signal transmission layer Vinit1, respectively.

[0262] like Figure 4 As shown, in some embodiments, the display substrate includes a plurality of sub-pixels, each sub-pixel including a light-emitting element O1 and a sub-pixel driving circuit; the sub-pixel driving circuit includes a driving transistor and further includes:

[0263] The second transistor T2 is coupled to the gate of the driving transistor and the first initialization signal transmission layer Vinit1, respectively.

[0264] The seventh transistor T7 is coupled to the light-emitting element O1 and the second initialization signal transmission layer Vinit2.

[0265] like Figure 7 As shown, in some embodiments, the display substrate includes a plurality of sub-pixels, each sub-pixel including a light-emitting element O1 and a sub-pixel driving circuit; the sub-pixel driving circuit includes a driving transistor and further includes:

[0266] The second transistor T2 is coupled to the gate of the driving transistor and the first initialization signal transmission layer Vinit1, respectively.

[0267] The seventh transistor T7 is coupled to the light-emitting element O1 and the second initialization signal transmission layer Vinit2 respectively;

[0268] The eighth transistor T8 is coupled to the first terminal of the driving transistor and the third initialization signal transmission layer Vinit3.

[0269] like Figure 2 As shown, in some embodiments, the display substrate further includes a display area AA and a peripheral area 40 surrounding the display area AA, and the display substrate further includes:

[0270] A first signal line 11 is located in the peripheral region 40 of the display substrate. The first signal line 11 includes at least a portion extending along the first direction. The first signal line 11 is coupled to the first initialization signal transmission layer Vinit1.

[0271] The first signal line 11 is made of a second source-drain metal layer, and the first transmission section 20 of the first initialization signal transmission layer Vinit1 is made of a first gate metal layer.

[0272] For example, the first signal line 11 is located on the left and right sides of the display area AA, the left and right sides are arranged along the second direction, and the display area AA is located between the first signal lines 11.

[0273] For example, the first signal line 11 is coupled to the first transmission section 20 of the first initialization signal transmission layer Vinit1.

[0274] For example, the display substrate includes the following layers stacked on the substrate in a direction away from the substrate: a light-shielding layer LS, an isolation layer, a first buffer layer, a poly active layer, a first gate insulating layer, a first gate metal layer, a second gate insulating layer, a second gate metal layer, a first interlayer insulating layer, a second buffer layer, an oxide active layer (such as IGZO), a third gate insulating layer, a third gate metal layer, a second interlayer insulating layer, a first source / drain metal layer, a passivation layer, a first planarization layer, a second source / drain metal layer, a second planarization layer, an anode layer, a pixel defining layer, a spacer layer, a light-emitting functional layer, a cathode layer, and an encapsulation layer.

[0275] For example, the orthographic projection of the light-shielding layer on the substrate at least partially overlaps with the orthographic projection of the channel portion of the third transistor T3 on the substrate, thereby blocking the influence of light on the channel portion and shielding the influence of nearby charges on the channel portion. For example, the light-shielding layer has a stable potential, such as a power supply potential. For example, the light-shielding layer is formed as a single layer structure.

[0276] For example, the first signal line 11 is coupled to the first initialization signal transmission layer Vinit1 via a conductive connection portion, which is coupled to the first transmission portion 20 of the first signal line 11 and the first initialization signal transmission layer Vinit1 via vias. For example, the conductive connection portion is made using the first source / drain metal layer.

[0277] like Figure 5 and Figure 6 As shown, in some embodiments, the display substrate further includes:

[0278] The second signal line 12 is located in the peripheral region 40 of the display substrate. The second signal line 12 includes at least a portion extending along the first direction. The orthographic projection of the first signal line 11 on the substrate is located between the display region AA and the orthographic projection of the second signal line 12 on the substrate. The second signal line 12 is coupled to the second initialization signal transmission layer Vinit2.

[0279] The first transmission section 20 included in the second signal line 12 and the second initialization signal transmission layer Vinit2 is made of a first source-drain metal layer.

[0280] For example, the second signal line 12 is located on the left and right sides of the display area AA, the left and right sides are arranged along the second direction, and the display area AA is located between the second signal lines 12.

[0281] For example, the second signal line 12 is coupled to the first transmission section 20 of the second initialization signal transmission layer Vinit2.

[0282] For example, the second signal line 12 and the first transmission section 20 of the second initialization signal transmission layer Vinit2 are formed as an integral structure.

[0283] like Figure 8 As shown, in some embodiments, the display substrate further includes:

[0284] The third signal line 13, the orthographic projection of the third signal line 13 on the substrate, is located between the orthographic projection of the first signal line 11 on the substrate and the orthographic projection of the second signal line 12 on the substrate, and the third signal line 13 is coupled to the third initialization signal transmission layer Vinit3;

[0285] The third signal line 13 is fabricated using the first source-drain metal layer, and the third initialization signal transmission layer Vinit3 is fabricated using the third gate metal layer.

[0286] For example, the third signal line 13 is located on the left and right sides of the display area AA, the left and right sides are arranged along the second direction, and the display area AA is located between the third signal lines 13.

[0287] For example, the third signal line 13 is coupled to the first transmission section 20 of the third initialization signal transmission layer Vinit3.

[0288] For example, the third signal line 13 is coupled to the first transmission section 20 of the third initialization signal transmission layer Vinit3 via a via.

[0289] For example, the first signal line, the second signal line and the third signal line may be provided only in one side of the display substrate, such as the left side, the right side, the top side or the bottom side.

[0290] This disclosure also provides a display device, including the display substrate provided in the above embodiments.

[0291] For example, the display device includes an active matrix organic light-emitting diode display device.

[0292] It should be noted that the display device can be any product or component with display function, such as a television, monitor, digital photo frame, mobile phone, or tablet computer. The display device also includes flexible circuit boards, printed circuit boards, and backplanes.

[0293] In the display substrate provided in the above embodiments, the initialization signal transmission layer includes a plurality of first transmission sections 20 and a plurality of second transmission sections 21. Each first transmission section 20 includes at least a portion extending along a second direction, and each second transmission section 21 includes at least a portion extending along a first direction. Adjacent first transmission sections 20 are coupled through at least one second transmission section 21. This configuration forms the initialization signal transmission layer in a grid pattern. Compared to a conventional initialization signal transmission layer that only includes a horizontal portion, this grid-like initialization signal transmission layer can reduce initialization signal loading by approximately 20%, resulting in faster initialization signal charging and better reset performance for corresponding nodes. This beneficial effect is even more significant for large-screen, high-frequency panels.

[0294] In the display substrate provided in the above embodiment, the plurality of first transmission sections 20 include a target transmission section 201. A second transmission section 21 located between the target transmission section 201 and its adjacent previous first transmission section 20 is offset from the second transmission section 21 located between the target transmission section 201 and its adjacent next first transmission section 20 in the second direction. This arrangement helps to increase the spacing between adjacent second transmission sections 21 along the first direction, reduce the layout density of the second transmission sections 21, and overcome the problem of insufficient layout space.

[0295] Therefore, the display device provided in this disclosure embodiment also has the above-mentioned beneficial effects when including the above-described display substrate, which will not be repeated here.

[0296] In related technologies, some signal line films have a large voltage drop when transmitting signals, which causes display products to fail to meet the screen performance requirements in high-brightness display mode, resulting in poor display uniformity.

[0297] Please see Figures 32 to 37 This disclosure provides a display substrate, including: a substrate and a signal line film layer disposed on the substrate; the signal line film layer includes:

[0298] A first conductive layer (including a first conductive pattern 70 and a second conductive pattern 71) and a second conductive layer (including a third conductive pattern 72) are stacked together; and,

[0299] A conductive connection layer (including conductive connection pattern 74) is disposed in a different layer from both the first conductive layer and the second conductive layer. The orthographic projection of the conductive connection layer on the substrate at least partially overlaps with the orthographic projection of the first conductive layer on the substrate, and the orthographic projection of the conductive connection layer on the substrate at least partially overlaps with the orthographic projection of the second conductive layer on the substrate. The conductive connection layer is coupled to both the first conductive layer and the second conductive connection layer.

[0300] For example, the signal line film layer is used to transmit a DC signal with a fixed potential.

[0301] For example, the signal line diaphragm layer includes a positive power signal line diaphragm layer (i.e., power line VDD), which is used to transmit a positive power signal.

[0302] For example, at least a portion of the conductive connection layer is located between the first conductive layer and the second conductive layer.

[0303] For example, the first conductive layer, the second conductive layer, and the conductive connection layer are all made of metallic materials.

[0304] For example, both the first conductive layer and the second conductive layer are formed as a mesh structure.

[0305] For example, the orthographic projection of the conductive connection layer on the substrate and the orthographic projection of the first conductive layer on the substrate have an overlapping area, in which the conductive connection layer and the first conductive layer are coupled through at least one via.

[0306] For example, the orthographic projection of the conductive connection layer on the substrate and the orthographic projection of the second conductive layer on the substrate have an overlapping area, in which the conductive connection layer and the second conductive layer are coupled through at least one via.

[0307] As can be seen from the specific structure of the display substrate provided in the embodiments of this disclosure, the signal line film layer in the display substrate provided in the embodiments of this disclosure includes a first conductive layer, a conductive connection layer, and a second conductive layer stacked together. This arrangement enables the signal line film layer to form a multi-layer network stacked structure, effectively reducing the voltage drop generated when the signal line film layer transmits signals. When the display substrate is applied to a display product, the uniformity of the display product in high-brightness display mode is ensured. Moreover, forming the signal line film layer into a multi-layer network stacked structure helps with heat dissipation of the display product in high-brightness display mode.

[0308] Please see Figures 32 to 38 In some embodiments, the conductive connection layer includes a plurality of conductive connection patterns 74;

[0309] The first conductive layer includes a plurality of first conductive patterns 70 arranged along a first direction; the first conductive pattern 70 includes at least a portion extending along a second direction, which intersects with the first direction, and the first conductive pattern 70 includes a plurality of first cutout areas 703; the first conductive pattern 70 is coupled to the corresponding conductive connection pattern 74.

[0310] For example, the conductive connection layer includes a plurality of conductive connection patterns 74, which are independent of each other.

[0311] For example, the plurality of conductive connection patterns 74 are arranged in an array.

[0312] For example, the plurality of conductive connection patterns 74 have identical structures.

[0313] For example, at least some of the conductive connection patterns 74 have different shapes.

[0314] For example, the display substrate includes a display area and a peripheral area surrounding the display area. The display area is divided into a plurality of display sub-regions, each of which corresponds one-to-one with a plurality of conductive connection patterns 74, and the conductive connection patterns 74 are located within their respective display sub-regions.

[0315] For example, the first direction includes the longitudinal direction, and the second direction includes the transverse direction.

[0316] like Figure 39 and Figure 52 As shown, exemplarily, the display substrate includes a plurality of gate lines and a plurality of data lines D1, the gate lines including at least a portion extending along the second direction, and the data lines D1 including at least a portion extending along the first direction.

[0317] For example, the display substrate includes a plurality of sub-pixels, and each sub-pixel includes a sub-pixel driving circuit. The plurality of sub-pixel driving circuits included in the plurality of sub-pixel pixels are divided into multiple rows of sub-pixel driving circuits arranged along a first direction. The first conductive layer includes a plurality of first conductive patterns 70 arranged along the first direction. The plurality of first conductive patterns 70 correspond one-to-one with the multiple rows of sub-pixel driving circuits.

[0318] For example, the first conductive pattern 70 is laid out within the layout area where the corresponding sub-pixel driving circuit row is located.

[0319] For example, each of the first conductive patterns 70 corresponds to at least one conductive connection pattern 74, and the first conductive pattern 70 is coupled to the corresponding conductive connection pattern 74.

[0320] For example, each of the first conductive patterns 70 corresponds to a plurality of conductive connection patterns 74, and the first conductive pattern 70 is coupled to the corresponding plurality of conductive connection patterns 74. For example, the plurality of conductive connection patterns 74 are arranged at intervals along the second direction.

[0321] For example, the first conductive pattern 70 includes a plurality of first cutout areas 703. The sub-pixel driving circuit includes a first node. The first node is located in the first cutout area 703.

[0322] For example, the orthographic projection of the boundary of the first cutout region 703 onto the substrate 60 surrounds the orthographic projection of the first node onto the substrate 60. The first node can be coupled to other conductive structures through the cutout region.

[0323] In the display substrate provided in the above embodiments, by setting the first conductive layer to include a plurality of first conductive patterns 70 arranged along a first direction, and the first conductive patterns 70 being coupled to the corresponding conductive connection patterns 74, and the first conductive patterns 70 including a plurality of first hollow areas 703, the first conductive layer is formed into a grid structure, thereby effectively reducing the voltage drop generated when the signal line film layer transmits signals. When the display substrate is applied to a display product, the uniformity of the display product in high-brightness display mode is ensured. Moreover, forming the first conductive layer into a grid structure helps the display product dissipate heat in high-brightness display mode.

[0324] Please see Figures 32 to 38 , Figure 52 In some embodiments, the first conductive pattern 70 includes a plurality of first portions 701 and a plurality of second portions 702, the first portions 701 and the second portions 702 being alternately arranged along the second direction;

[0325] The width of the first portion 701 in the direction perpendicular to the second direction is less than the distance between the two furthest boundaries of the second portion 702 in the direction perpendicular to the second direction; the second portion 702 includes the first hollow area 703.

[0326] For example, the first portion 701 and the second portion 702 are formed as a single structure.

[0327] For example, the first portion 701 includes a strip-shaped pattern extending along the second direction.

[0328] For example, the second part 702 includes block graphics.

[0329] For example, the orthographic projection of the first portion 701 on the substrate 60 does not overlap with the orthographic projection of the second conductive layer on the substrate 60.

[0330] For example, the orthographic projection of the first portion 701 on the substrate 60 at least partially overlaps with the orthographic projection of the second conductive layer on the substrate 60.

[0331] For example, the orthographic projection of the second portion 702 on the substrate 60 at least partially overlaps with the orthographic projection of the second conductive layer on the substrate 60.

[0332] For example, the orthographic projection of the first portion 701 on the substrate 60 and the orthographic projection of the corresponding conductive connection pattern 74 on the substrate 60 have an overlapping area, in which the first portion 701 is coupled to the corresponding conductive connection pattern 74.

[0333] For example, the orthographic projection of the second portion 702 on the substrate 60 and the orthographic projection of the corresponding conductive connection pattern 74 on the substrate 60 have an overlapping area, in which the second portion 702 is coupled to the corresponding conductive connection pattern 74.

[0334] For example, the width of the first portion 701 in the direction perpendicular to the second direction is less than the minimum distance between the two furthest boundaries of the second portion 702 in the direction perpendicular to the second direction.

[0335] For example, the width of the first portion 701 in the direction perpendicular to the second direction is less than the maximum distance between the two furthest boundaries of the second portion 702 in the direction perpendicular to the second direction.

[0336] In the display substrate provided in the above embodiments, by setting the first conductive pattern 70 to include a plurality of first portions 701 and a plurality of second portions 702, the first portions 701 and the second portions 702 are alternately arranged along the second direction; and by setting the width of the first portion 701 in the direction perpendicular to the second direction to be smaller than the distance between the two furthest boundaries of the second portion 702 in the direction perpendicular to the second direction, the first conductive layer effectively utilizes the limited layout space while avoiding short circuits with the surrounding conductive structures, better realizes the meshing of the first conductive layer, and significantly reduces the voltage drop generated when the first conductive layer transmits signals.

[0337] In the display substrate provided in the above embodiments, by setting the width of the first portion 701 in the direction perpendicular to the second direction to be smaller than the distance between the two furthest boundaries of the second portion 702 in the direction perpendicular to the second direction; the second portion 702 includes the first hollow area 703; not only can a larger hollow area be formed, but the difficulty of forming the hollow area can also be effectively reduced.

[0338] Please see Figures 32 to 38In some embodiments, the plurality of first portions 701 include a plurality of first target portions 7011 and a plurality of second target portions 7012, the first target portions 7011 and the second target portions 7012 are alternately arranged, the width of the first target portion 7011 in the direction perpendicular to the second direction is greater than the width of the second target portion 7012 in the direction perpendicular to the second direction; the first target portion 7011 is coupled to the corresponding conductive connection pattern 74.

[0339] For example, the second conductive layer includes a plurality of third conductive patterns 72 arranged along a second direction, each third conductive pattern 72 including at least a portion extending along a first direction, and each third conductive pattern 72 including a plurality of second cutout areas 721. The orthographic projection of the boundary of the second cutout area 721 onto the substrate 60 surrounds the orthographic projection of the second target portion 7012 onto the substrate 60.

[0340] For example, the orthographic projection of the second cutout area 721 on the substrate 60 does not overlap with the orthographic projection of the first target portion 7011 on the substrate 60.

[0341] For example, the orthographic projection of the second cutout area 721 on the substrate 60 at least partially overlaps with the orthographic projection of the second target portion 7012 on the substrate 60.

[0342] For example, the first cutout area 703 and the second cutout area 721 at least partially overlap.

[0343] For example, the first target portion 7011 or the second target portion 7012 is disposed between adjacent second portions 702.

[0344] For example, the second portion 702 is disposed between adjacent first target portion 7011 and second target portion 7012.

[0345] For example, in the same first conductive pattern 70, a first target portion 7011, a second portion 702, a second target portion 7012 and a second portion 702 arranged in sequence constitute a repeating unit, and the first conductive pattern 70 includes a plurality of such repeating units.

[0346] For example, the orthographic projection of the first target portion 7011 on the substrate 60 has an overlapping area with the orthographic projection of the corresponding conductive connection pattern 74 on the substrate 60, in which the first target portion 7011 and the corresponding conductive connection pattern 74 are coupled through a via.

[0347] In the display substrate provided in the above embodiments, by setting the plurality of first portions 701 including a plurality of first target portions 7011 and a plurality of second target portions 7012, the first target portions 7011 and the second target portions 7012 are alternately arranged, and the width of the first target portion 7011 in the direction perpendicular to the second direction is greater than the width of the second target portion 7012 in the direction perpendicular to the second direction; this allows the first conductive layer to effectively utilize the limited layout space while avoiding short circuits with the surrounding conductive structures, better realize the meshing of the first conductive layer, and significantly reduce the voltage drop generated when the first conductive layer transmits signals.

[0348] In the display substrate provided in the above embodiments, by setting the first target portion 7011 to be coupled with the corresponding conductive connection pattern 74, the stability and reliability of the electrical connection performance between the first conductive layer and the conductive connection pattern 74 can be well guaranteed.

[0349] Please see Figures 32 to 38 In some embodiments, the first target portion 7011 and the second target portion 7012 are offset along the first direction.

[0350] The above configuration allows the first conductive layer to effectively utilize the limited layout space while avoiding short circuits with the surrounding conductive structures, thus better realizing the meshing of the first conductive layer and significantly reducing the voltage drop generated when the first conductive layer transmits signals.

[0351] Please see Figure 33 In some embodiments, the first conductive layer further includes a plurality of second conductive patterns 71, and adjacent first conductive patterns 70 are coupled to each other through at least one second conductive pattern 71.

[0352] For example, the second conductive pattern 71 includes at least a portion extending along the first direction.

[0353] For example, the second conductive pattern 71 is formed as a strip structure.

[0354] For example, the second conductive pattern 71 and the first conductive pattern 70 are formed as an integral structure.

[0355] For example, second conductive patterns 71 located in the same column along the first direction are sequentially coupled to form an integral structure.

[0356] For example, adjacent first conductive patterns 70 are coupled together by a plurality of second conductive patterns 71.

[0357] For example, the orthographic projection of the second conductive pattern 71 on the substrate 60 at least partially overlaps with the orthographic projection of the conductive connection pattern 74 on the substrate 60.

[0358] For example, the orthographic projection of the second conductive pattern 71 onto the substrate 60 at least partially overlaps with the orthographic projection of the first portion 701 onto the substrate 60.

[0359] For example, the orthographic projection of the second conductive pattern 71 onto the substrate 60 at least partially overlaps with the orthographic projection of the first target portion 7011 onto the substrate 60.

[0360] For example, the orthographic projection of the second conductive pattern 71 onto the substrate 60 does not overlap with the orthographic projection of the second target portion 7012 onto the substrate 60.

[0361] For example, the orthographic projection of the second conductive pattern 71 onto the substrate 60 does not overlap with the orthographic projection of the second portion 702 onto the substrate 60.

[0362] For example, the second conductive pattern 71 can be made of an oxide active layer (such as an IGZO film layer), and the oxide active layer can be formed into a conductor through a conductor-forming process, thereby transmitting a positive power signal.

[0363] In the display substrate provided in the above embodiments, the first conductive layer further includes a plurality of second conductive patterns 71, and adjacent first conductive patterns 70 are coupled through at least one second conductive pattern 71, further expanding the grid pattern of the first conductive layer. This effectively reduces the voltage drop generated when the signal line film layer transmits signals. When the display substrate is applied to a display product, the uniformity of the display product in high-brightness display mode is ensured. Moreover, forming the signal line film layer into a multi-layer network stacked structure helps with heat dissipation of the display product in high-brightness display mode.

[0364] Please see Figures 32 to 38 In some embodiments, the conductive connection layer includes a plurality of conductive connection patterns 74;

[0365] The second conductive layer includes a plurality of third conductive patterns 72 arranged along a second direction, each third conductive pattern 72 including at least a portion extending along a first direction, the second direction intersecting the first direction; each third conductive pattern 72 includes a plurality of second cutout areas 721; each third conductive pattern 72 is coupled to a corresponding conductive connection pattern 74.

[0366] For example, the conductive connection layer includes a plurality of conductive connection patterns 74, which are independent of each other.

[0367] For example, the plurality of conductive connection patterns 74 are arranged in an array.

[0368] For example, the plurality of conductive connection patterns 74 have identical structures.

[0369] For example, at least some of the conductive connection patterns 74 have different shapes.

[0370] For example, the display substrate includes a display area and a peripheral area surrounding the display area. The display area is divided into a plurality of display sub-regions, each of which corresponds one-to-one with a plurality of conductive connection patterns 74, and the conductive connection patterns 74 are located within their respective display sub-regions.

[0371] For example, the first direction includes the longitudinal direction, and the second direction includes the transverse direction.

[0372] For example, the display substrate includes a plurality of gate lines and a plurality of data lines D1, wherein the gate lines include at least a portion extending along the second direction, and the data lines D1 include at least a portion extending along the first direction.

[0373] For example, the display substrate includes a plurality of sub-pixels, and each sub-pixel includes a sub-pixel driving circuit. The plurality of sub-pixel driving circuits included in the plurality of sub-pixel pixels are divided into multiple columns of sub-pixel driving circuits arranged along a second direction. The second conductive layer includes a plurality of third conductive patterns 72 arranged along the second direction. The plurality of third conductive patterns 72 correspond one-to-one with the multiple columns of sub-pixel driving circuits.

[0374] For example, at least a portion of the third conductive pattern 72 is disposed within the layout area where the corresponding sub-pixel driving circuit column is located.

[0375] For example, each of the third conductive patterns 72 corresponds to at least one conductive connection pattern 74, and the third conductive pattern 72 is coupled to the corresponding conductive connection pattern 74.

[0376] For example, each of the third conductive patterns 72 corresponds to a plurality of conductive connection patterns 74, and the third conductive pattern 72 is coupled to the corresponding plurality of conductive connection patterns 74. For example, the third conductive pattern 72 is coupled to the corresponding plurality of conductive connection patterns 74 through vias. For example, the plurality of conductive connection patterns 74 are arranged at intervals along the first direction.

[0377] For example, adjacent third conductive patterns 72 are electrically connected by at least one of the conductive connection patterns 74.

[0378] For example, adjacent third conductive patterns 72 are electrically connected by a plurality of conductive connection patterns 74. The plurality of conductive connection patterns 74 are arranged at intervals along the first direction.

[0379] In the display substrate provided in the above embodiments, by providing the second conductive layer including a plurality of third conductive patterns 72 arranged along a second direction, each third conductive pattern 72 including a plurality of second hollow areas 721; the third conductive patterns 72 are coupled to the corresponding conductive connection patterns 74; thus, the second conductive layer is formed into a mesh structure, thereby effectively reducing the voltage drop generated when the signal line film layer transmits signals. When the display substrate is applied to a display product, the uniformity of the display product in high-brightness display mode is ensured. Moreover, forming the first conductive layer into a mesh structure helps the display product dissipate heat in high-brightness display mode.

[0380] In some embodiments, the first cutout area 703 and the second cutout area 721 are configured to at least partially overlap.

[0381] The above configuration method is beneficial to improving the transmittance of the display substrate.

[0382] Please see Figures 32 to 38 In some embodiments, the third conductive pattern 72 includes a plurality of third portions 722 and a plurality of fourth portions 723, the third portions 722 and the fourth portions 723 being alternately arranged along the first direction;

[0383] The width of the third portion 722 in the direction perpendicular to the first direction is smaller than the distance between the two furthest boundaries of the fourth portion 723 in the direction perpendicular to the first direction; the fourth portion 723 includes the second hollow area 721.

[0384] For example, the third part 722 and the fourth part 723 are formed as an integral structure.

[0385] For example, the fourth portion 723 includes a strip-shaped pattern that extends at least partially along the first direction.

[0386] For example, the third part 722 includes block graphics.

[0387] For example, the orthographic projection of the third portion 722 on the substrate 60 does not overlap with the orthographic projection of the first conductive layer on the substrate 60.

[0388] For example, the orthographic projection of the third portion 722 onto the substrate 60 at least partially overlaps with the orthographic projection of the first conductive layer onto the substrate 60.

[0389] For example, the orthographic projection of the fourth portion 723 on the substrate 60 at least partially overlaps with the orthographic projection of the second conductive layer on the substrate 60.

[0390] For example, the orthographic projection of the third portion 722 on the substrate 60 and the orthographic projection of the corresponding conductive connection pattern 74 on the substrate 60 have an overlapping area, in which the third portion 722 is coupled to the corresponding conductive connection pattern 74.

[0391] For example, the orthographic projection of the fourth portion 723 on the substrate 60 and the orthographic projection of the corresponding conductive connection pattern 74 on the substrate 60 have an overlapping area, in which the fourth portion 723 is coupled to the corresponding conductive connection pattern 74.

[0392] For example, the width of the third portion 722 in the direction perpendicular to the first direction is less than the minimum distance between the two furthest boundaries of the fourth portion 723 in the direction perpendicular to the first direction.

[0393] For example, the width of the third portion 722 in the direction perpendicular to the first direction is less than the maximum distance between the two furthest boundaries of the fourth portion 723 in the direction perpendicular to the first direction.

[0394] In the display substrate provided in the above embodiments, by setting the third conductive pattern 72 to include a plurality of third portions 722 and a plurality of fourth portions 723, the third portions 722 and the fourth portions 723 are alternately arranged along the first direction; and by setting the width of the third portion 722 in the direction perpendicular to the first direction to be smaller than the distance between the two furthest boundaries of the fourth portion 723 in the direction perpendicular to the first direction, the second conductive layer effectively utilizes the limited layout space while avoiding short circuits with the surrounding conductive structures, better realizes the meshing of the second conductive layer, and significantly reduces the voltage drop generated when the second conductive layer transmits signals.

[0395] In the display substrate provided in the above embodiments, by setting the width of the third part 722 in the direction perpendicular to the first direction to be smaller than the distance between the two furthest boundaries of the fourth part 723 in the direction perpendicular to the first direction; the fourth part 723 includes the second hollow area 721; not only can a larger hollow area be formed, but the difficulty of forming the hollow area can also be effectively reduced.

[0396] like Figure 34 As shown, in some embodiments, the second conductive layer further includes a plurality of fourth conductive patterns 73, and adjacent third conductive patterns 72 are coupled to each other through at least one of the fourth conductive patterns 73.

[0397] For example, the fourth conductive pattern 73 and the third conductive pattern 72 are formed as an integral structure.

[0398] For example, the fourth conductive pattern 73 includes a strip pattern extending along the second direction.

[0399] For example, adjacent third conductive patterns 72 are coupled to each other by a plurality of fourth conductive patterns 73, which are spaced apart along the first direction.

[0400] For example, the fourth conductive pattern 73 and the conductive connection pattern 74 are alternately arranged along the first direction.

[0401] For example, the orthographic projection of the fourth conductive pattern 73 on the substrate 60 at least partially overlaps with the orthographic projection of the conductive connection pattern 74 on the substrate 60.

[0402] For example, the orthographic projection of the fourth conductive pattern 73 on the substrate 60 does not overlap with the orthographic projection of the conductive connection pattern 74 on the substrate 60.

[0403] For example, the orthographic projection of the fourth conductive pattern 73 on the substrate 60 at least partially overlaps with the orthographic projection of the second conductive pattern 71 on the substrate 60.

[0404] For example, the orthographic projection of the fourth conductive pattern 73 on the substrate 60 does not overlap with the orthographic projection of the first conductive pattern 70 on the substrate 60.

[0405] In the display substrate provided in the above embodiments, the second conductive layer further includes a plurality of fourth conductive patterns 73, and adjacent third conductive patterns 72 are coupled through at least one of the fourth conductive patterns 73; this further expands the grid pattern of the second conductive layer. This effectively reduces the voltage drop generated when the signal line film layer transmits signals. When the display substrate is applied to a display product, the uniformity of the display product in high-brightness display mode is ensured. Moreover, forming the signal line film layer into a multi-layer network stacked structure helps with heat dissipation of the display product in high-brightness display mode.

[0406] Please see Figures 32 to 36 In some embodiments, the conductive connection pattern 74 includes a main body portion 741, which is coupled to the corresponding first conductive pattern 70 and the third conductive pattern 72.

[0407] For example, the main body 741 includes block graphics.

[0408] For example, the orthographic projection of the main body portion 741 on the substrate 60 at least partially overlaps with the orthographic projection of the first conductive pattern 70 on the substrate 60. The orthographic projection of the main body portion 741 on the substrate 60 at least partially overlaps with the orthographic projection of the third conductive pattern 72 on the substrate 60.

[0409] For example, the main body portion 741 is coupled to the corresponding first conductive pattern 70 and the third conductive pattern 72 through through holes.

[0410] like Figure 37 and Figure 38 As shown, in some embodiments, the conductive connection pattern 74 further includes at least one first extension 742 extending from the main body portion 741.

[0411] For example, the main body 741 and the first extension 742 are formed as an integral structure.

[0412] For example, the first extension 742 includes at least a portion extending along the first direction.

[0413] For example, the conductive connection pattern 74 includes four first extensions 742.

[0414] In the display substrate provided in the above embodiments, by setting the conductive connection pattern 74 to include at least one first extension portion 742 extending from the main body portion 741, the conductive connection pattern 74 has multiple branch lines, which helps the conductive connection pattern 74 to dissipate heat.

[0415] like Figure 54 As shown, in some embodiments, the conductive connection pattern 74 further includes a first extension 742, which is fabricated using an oxide active layer (such as an IGZO film). The oxide active layer can be made into a conductor through a conductor-enhancing process. The two ends of the first extension formed using the conductor-enhanced oxide active layer can be electrically connected to the main body (fabricated using a first source / drain metal layer) and the third conductive pattern 72 (fabricated using a second source / drain metal layer) respectively via vias, thereby enabling the transmission of positive power signals.

[0416] like Figure 51 and Figure 54 As shown, exemplarily, the conductive connection pattern 74 also includes a connection portion 744, and the first extension portion 742 is coupled to the connection portion 744 through a via.

[0417] For example, the connecting part 744 and the main body part 741 are made of the same layer and material.

[0418] The above-mentioned use of a conductive oxide active layer to form the first extension can effectively avoid the first conductive part 81 and the seventh conductive part 87, which is beneficial to improving the yield of the display substrate.

[0419] like Figure 37 and Figure 38 As shown, in some embodiments, the orthographic projection of the first extension 742 on the substrate 60 at least partially overlaps with the orthographic projection of the second conductive layer on the substrate 60.

[0420] For example, the orthographic projection of the first extension 742 on the substrate 60 is located inside the orthographic projection of the second conductive layer on the substrate 60.

[0421] For example, the orthographic projection of the first extension 742 on the substrate 60 does not overlap with the orthographic projection of the second conductive pattern 71 on the substrate 60.

[0422] For example, the orthographic projection of a portion of the first extension 742 onto the substrate 60 at least partially overlaps with the orthographic projection of the first conductive pattern 70 onto the substrate 60.

[0423] In the display substrate provided in the above embodiments, by setting the orthographic projection of the first extension 742 on the substrate 60 to at least partially overlap with the orthographic projection of the second conductive layer on the substrate 60, the layout difficulty of the first extension 742 is effectively reduced.

[0424] like Figure 37 and Figure 38 As shown, in some embodiments, the first extension 742 is coupled to the second conductive layer through a via.

[0425] For example, the orthographic projection of the first extension 742 on the substrate 60 overlaps with the orthographic projection of the second conductive layer on the substrate 60, and in the overlapping area, the first extension 742 and the second conductive layer are coupled through a via.

[0426] The above-mentioned configuration allows the first extension 742 to be coupled to the second conductive layer through a via, thereby increasing the area of ​​the second conductive layer at the via and effectively reducing the voltage drop of the signal line film layer.

[0427] like Figure 35 and Figure 36 As shown, in some embodiments, the display substrate further includes:

[0428] The light-shielding layer LS is formed in a mesh structure and is coupled to the signal line film layer.

[0429] For example, the light-shielding layer is located between the sub-pixel driving circuit and the substrate 60. The sub-pixel driving circuit includes a driving transistor (such as a third transistor T3), and the orthographic projection of the light-shielding layer onto the substrate 60 at least partially overlaps with the orthographic projection of the channel portion of the driving transistor onto the substrate 60. This arrangement allows the light-shielding layer to block light from shining from the substrate 60 side onto the channel portion, ensuring the stability of the driving transistor's characteristics.

[0430] By coupling the light-shielding layer to the signal line film layer, the light-shielding layer has a stable potential. In this way, the light-shielding layer can effectively shield the influence of surrounding charges on the channel portion, ensuring the stability of the driving transistor's characteristics.

[0431] By coupling the light-shielding layer to the signal line film layer, the grid structure of the signal line film layer is effectively extended at another spatial level, significantly reducing the voltage drop generated when the signal line film layer transmits signals. When this display substrate is applied to display products, it ensures the uniformity of the display in high-brightness display mode. Furthermore, forming the signal line film layer into a multi-layered network structure facilitates heat dissipation in high-brightness display mode.

[0432] In some embodiments, the display substrate further includes peripheral signal lines located in the peripheral region of the display substrate and coupled to a signal line film layer.

[0433] The light-shielding layer includes a peripheral portion located in the peripheral region, and the peripheral portion is coupled to the peripheral signal line.

[0434] For example, the display substrate further includes a driver chip, the peripheral signal lines are coupled to the driver chip, and the peripheral signal lines are also coupled to the signal line film layer. The peripheral signal lines are used to transmit the signals provided by the driver chip to the signal line film layer.

[0435] For example, the orthographic projection of the peripheral signal line on the substrate 60 overlaps with the orthographic projection of the peripheral portion of the light-shielding layer on the substrate 60, and in this overlap area, the peripheral signal line and the peripheral portion of the light-shielding layer are coupled through vias. The light-shielding layer LS is coupled to the signal line film layer in the peripheral region through the peripheral signal line.

[0436] In some embodiments, the first conductive layer is made of a second gate metal layer, the second conductive layer is made of a second source / drain metal layer, and the conductive connection layer is made of a first source / drain metal layer.

[0437] like Figure 52As shown, exemplarily, the display substrate includes the following layers stacked on the substrate 60 (e.g., a polyimide substrate) in a direction away from the substrate 60: a first buffer layer Buf, a light-shielding layer LS, an isolation layer Bar, a poly active layer POL, a first gate insulating layer GI1, a first gate metal layer Gate1, a second gate insulating layer GI2, a second gate metal layer Gate2, a first interlayer insulating layer ILD, a second buffer layer, an oxide active layer (e.g., IGZO), a third gate insulating layer, a third gate metal layer, a second interlayer insulating layer, a first source / drain metal layer SD1, a passivation layer PVX, a first planarization layer PLN1, a second source / drain metal layer SD2, a second planarization layer PLN2, an anode layer 50, a pixel defining layer PDL, a spacer layer PS, a light-emitting functional layer, a cathode layer, and an encapsulation layer.

[0438] In the display substrate provided in the above embodiments, by setting the first conductive layer to be made of the second gate metal layer, the second conductive layer to be made of the second source / drain metal layer, and the conductive connection layer to be made of the first source / drain metal layer, the signal line film layer can be made using the existing film layers in the display substrate without adding additional patterning processes, thereby effectively simplifying the manufacturing process of the display substrate and reducing the manufacturing cost of the display substrate.

[0439] In the display substrate provided in the above embodiments, the first conductive layer is made of a second gate metal layer, the second conductive layer is made of a second source / drain metal layer, the conductive connection layer is made of a first source / drain metal layer, and the conductive connection layer acts as a bridge, being coupled to the second conductive layer through vias penetrating the passivation layer and the first planarization layer, and being coupled to the first conductive layer through vias penetrating the first interlayer insulating layer, the second buffer layer, the third gate insulating layer, and the second interlayer insulating layer.

[0440] For example, the display substrate undergoes a 13-mask process, and the process flow sequence includes:

[0441] Choose a rigid or flexible substrate;

[0442] A buffer layer is formed on the substrate using materials such as SiOx and SiNx;

[0443] A light-shielding layer LS is formed using Mo metal material through a 1mask process;

[0444] A poly active layer is formed using P-Si material through a 2mask process;

[0445] The first gate insulating layer GI1 is formed using SiO x material;

[0446] The first gate metal layer, Gate1, is formed using a 3-mask process with Mo metal material.

[0447] The second gate insulating layer GI2 is formed using materials such as SiOx and SiNx;

[0448] The second gate metal layer, Gate2, is formed using a 4mask process with Mo metal material.

[0449] Interlayer insulating layer (ILD) is formed using materials such as SiOx and SiNx through a 5mask process;

[0450] A via is formed between the first source / drain metal layer SD1 and the light-shielding layer LS using a 6-mask process;

[0451] The first source / drain metal layer SD1 of the Ti-Al-Ti stacked structure was formed using a 7mask process.

[0452] The passivation layer PVX is formed using SiOx or SiNx through an 8mask process;

[0453] The first planarization layer PLN1 is formed using organic materials through a 9mask process;

[0454] The second source / drain metal layer SD2 of the Ti-Al-Ti stacked structure was formed by a 10-mask process.

[0455] The second planarization layer PLN2 is formed using organic materials through the 11mask process;

[0456] The anode layer 50 is formed using indium tin oxide through a 12-mask process.

[0457] The pixel delimiting layer (PDL) and spacer layer (PS) are formed using an organic material through a 13mask process.

[0458] like Figures 39 to 53 As shown, in some embodiments, the conductive connection pattern 74 includes a main body portion 741 and a second extension portion 743 extending from the main body portion 741. The main body portion 741 includes at least a portion extending along a second direction, and the second extension portion 743 includes at least a portion extending along a first direction, which intersects the second direction.

[0459] The display substrate further includes a plurality of sub-pixels, each sub-pixel including a sub-pixel driving circuit, the sub-pixel driving circuit including a driving transistor and a fifth transistor T5, the first terminal of the fifth transistor T5 being coupled to the corresponding second extension 743, and the second terminal of the fifth transistor T5 being coupled to the first terminal of the driving transistor.

[0460] For example, the main body 741 and the second extension 743 are formed as an integral structure.

[0461] For example, the second extension 743 includes a strip structure extending along the first direction.

[0462] For example, the display substrate further includes a plurality of light-emitting control lines E1, the light-emitting control lines E1 including at least a portion extending along the second direction.

[0463] For example, the multiple sub-pixel driving circuits in the display substrate are divided into multiple rows of sub-pixel driving circuits, and the multiple rows of sub-pixel driving circuits correspond one-to-one with the multiple light-emitting control lines E1.

[0464] For example, the gate of each fifth transistor T5 included in each row of the sub-pixel driving circuit is coupled to the corresponding light-emitting control line E1. The first terminal of the fifth transistor T5 is coupled to the corresponding second extension 743, and the second terminal of the fifth transistor T5 is coupled to the first terminal of the driving transistor.

[0465] The above-described coupling of the first terminal of the fifth transistor T5 to the corresponding second extension 743 enables the connection of the first terminal of the fifth transistor T5 to a power signal while reducing the difficulty of display substrate layout.

[0466] like Figures 39 to 53 As shown, in some embodiments, the plurality of sub-pixel driving circuits included by the plurality of sub-pixel driving circuits are divided into multiple rows of sub-pixel driving circuits, and each row of sub-pixel driving circuits includes a plurality of the sub-pixel driving circuits arranged along the second direction; the plurality of sub-pixel driving circuits included by each row of sub-pixel driving circuits are divided into multiple sub-pixel driving circuit groups, and each sub-pixel driving circuit group includes two adjacent sub-pixel driving circuits.

[0467] The first pole of the two fifth transistors T5 included in the sub-pixel driving circuit group is coupled to the second extension 743 of the corresponding conductive connection pattern 74.

[0468] For example, the multiple conductive connection patterns 74 included in the display substrate are divided into multiple rows of conductive connection patterns 74, and each row of conductive connection patterns 74 includes multiple conductive connection patterns 74 arranged along the second direction. The multiple rows of conductive connection patterns 74 correspond one-to-one with the multiple rows of sub-pixel driving circuits.

[0469] For example, the multiple conductive connection patterns 74 included in the display substrate are divided into multiple columns of conductive connection patterns 74, each column of conductive connection patterns 74 includes multiple conductive connection patterns 74 arranged along the first direction, and the columns of conductive connection patterns 74 are arranged alternately with the third conductive pattern 72.

[0470] For example, each row of subpixel driving circuits includes multiple subpixel driving circuits divided into multiple subpixel driving circuit groups. Each subpixel driving circuit group includes two adjacent subpixel driving circuits, and each subpixel driving circuit belongs to only one subpixel driving circuit group.

[0471] For example, the plurality of sub-pixel driving circuit groups in the display substrate correspond one-to-one with the plurality of conductive connection patterns 74.

[0472] The first pole of the two fifth transistors T5 in the sub-pixel driving circuit group described above is coupled to the second extension 743 of the corresponding conductive connection pattern 74, which effectively reduces the layout difficulty of the display substrate.

[0473] like Figures 39 to 53 As shown, in some embodiments, the sub-pixel driving circuit further includes a first transistor T1 and a second transistor T2; the second terminals of the first transistor T1 and the second transistor T2 are respectively coupled to the gate of the driving transistor (i.e., the gate T3-g of the third transistor T3) through a first conductive portion 81; the main body portion 741 is located between the two first conductive portions 81 included in the corresponding sub-pixel driving circuit group.

[0474] For example, the display substrate further includes a plurality of second scan lines S2 and a plurality of reset lines R1, wherein at least a portion of the second scan lines S2 and at least a portion of the reset lines R1 extend along the second direction.

[0475] For example, the multi-row sub-pixel driving circuit in the display substrate corresponds one-to-one with the multiple second scan lines S2. The multi-row sub-pixel driving circuit in the display substrate corresponds one-to-one with the multiple reset lines R1.

[0476] For example, the gate of each first transistor T1 in each row of sub-pixel driving circuit is coupled to the corresponding second scan line S2, and the gate of each second transistor T2 in each row of sub-pixel driving circuit is coupled to the corresponding reset line R1.

[0477] For example, each sub-pixel driving circuit includes a first conductive part 81.

[0478] The above-mentioned arrangement of the main body 741 between the two first conductive parts 81 included in the corresponding sub-pixel driving circuit group not only reduces the layout difficulty of the display substrate, but also improves the working stability of the sub-pixel driving circuit.

[0479] like Figures 39 to 53As shown, in some embodiments, the main body 741 is provided with a symmetrical pattern, the axis of symmetry of the symmetrical pattern extends along the first direction, and the axis of symmetry is located between two sub-pixel driving circuits included in the sub-pixel driving circuit group corresponding to the main body 741.

[0480] For example, the second extension 743 is also symmetrical about the axis of symmetry.

[0481] The above setup not only reduces the layout difficulty of the display substrate, but also improves the working stability of the sub-pixel driving circuit.

[0482] like Figures 39 to 53 As shown, in some embodiments, adjacent third conductive patterns 72 are coupled by at least one conductive connection pattern 74.

[0483] In some embodiments, at least a portion of the conductive connection pattern 74 is coupled to a fourth portion 723 comprising two adjacent third conductive patterns 72.

[0484] For example, adjacent third conductive patterns 72 are coupled by a plurality of conductive connection patterns 74.

[0485] The above configuration reduces the layout difficulty of the display substrate, optimizes the grid structure of the signal line film layer, helps to reduce the voltage drop of the signal line film layer, and improves the heat dissipation performance of the signal line film layer.

[0486] like Figures 39 to 53 As shown, in some embodiments, the display substrate further includes multiple reset lines R1, multiple first scan lines S1 and multiple second scan lines S2, wherein at least a portion of the reset lines R1, at least a portion of the first scan lines S1 and at least a portion of the second scan lines S2 extend along a second direction.

[0487] The third part 722 is configured to have an orthographic projection on the substrate 60, which overlaps with the orthographic projection of the corresponding reset line R1 on the substrate 60, overlaps with the orthographic projection of the corresponding first scan line S1 on the substrate 60, and overlaps with the orthographic projection of the corresponding second scan line S2 on the substrate 60.

[0488] For example, the multi-row sub-pixel driving circuit in the display substrate corresponds one-to-one with the multiple first scan lines S1.

[0489] For example, all the third portions 722 included in the display substrate are divided into multiple rows of third portions 722, and each row of third portions 722 includes a plurality of third portions 722 arranged along the second direction.

[0490] For example, the third portion 722 of the multiple rows corresponds one-to-one with the multiple reset lines R1; the third portion 722 of the multiple rows corresponds one-to-one with the multiple first scan lines S1; and the third portion 722 of the multiple rows corresponds one-to-one with the multiple second scan lines S2.

[0491] The above configuration reduces the layout difficulty of the display substrate, optimizes the grid structure of the signal line film layer, helps to reduce the voltage drop of the signal line film layer, and improves the heat dissipation performance of the signal line film layer.

[0492] like Figures 39 to 53 As shown, in some embodiments, the display substrate further includes multiple light-emitting control lines E1, multiple third scan lines S3, a first initialization signal transmission layer Vinit1, a second initialization signal transmission layer Vinit2, and a third initialization signal transmission layer Vinit3.

[0493] The orthographic projection of the fourth part 723 on the substrate 60 overlaps with the orthographic projection of the corresponding light-emitting control line E1 on the substrate 60, overlaps with the orthographic projection of the corresponding third scan line S3 on the substrate 60, overlaps with the orthographic projection of the first initialization signal transmission layer Vinit1 on the substrate 60, overlaps with the orthographic projection of the second initialization signal transmission layer Vinit2 on the substrate 60, and overlaps with the orthographic projection of the third initialization signal transmission layer Vinit3 on the substrate 60.

[0494] For example, the multi-row sub-pixel driving circuit in the display substrate corresponds one-to-one with the multiple third scan lines S3.

[0495] For example, the first initialization signal transmission layer Vinit1, the second initialization signal transmission layer Vinit2, and the third initialization signal transmission layer Vinit3 all include a first transmission section, the first transmission section including at least a portion extending along the second direction.

[0496] For example, all the fourth portions 723 included in the display substrate are divided into multiple rows of fourth portions 723, and each row of fourth portions 723 includes multiple fourth portions 723 arranged along the second direction. The multiple rows of fourth portions 723 correspond one-to-one with the multiple rows of sub-pixel driving circuits in the display substrate.

[0497] For example, the multiple rows of fourth portions 723 correspond one-to-one with the multiple third scan lines S3. The multiple rows of fourth portions 723 correspond one-to-one with the multiple first transmission units included in the first initialization signal transmission layer Vinit1. The multiple rows of fourth portions 723 correspond one-to-one with the multiple first transmission units included in the second initialization signal transmission layer Vinit2. The multiple rows of fourth portions 723 correspond one-to-one with the multiple first transmission units included in the third initialization signal transmission layer Vinit3.

[0498] The above configuration reduces the layout difficulty of the display substrate, optimizes the grid structure of the signal line film layer, helps to reduce the voltage drop of the signal line film layer, and improves the heat dissipation performance of the signal line film layer.

[0499] like Figures 39 to 53 As shown, in some embodiments, the display substrate further includes a plurality of data lines D1, the data lines D1 including at least a portion extending along the first direction;

[0500] The display substrate further includes a plurality of sub-pixels, each sub-pixel including a sub-pixel driving circuit, the sub-pixel driving circuit including a driving transistor, a fourth transistor T4 and a fifth transistor T5, the fourth transistor T4 being coupled to the first electrode of the first transistor T1 and the corresponding data line D1, and the fifth transistor T5 being coupled to the first electrode of the driving transistor and the corresponding conductive connection pattern 74.

[0501] The fourth transistor T4 includes a fourth active layer 34, and the fifth transistor T5 includes a fifth active layer 35. The orthographic projection of the fourth portion 723 on the substrate 60 does not overlap with the orthographic projection of the fourth active layer 34 on the substrate 60, nor with the orthographic projection of the fifth active layer 35 on the substrate 60.

[0502] For example, the display substrate includes multiple sub-pixel driving circuits divided into multiple columns of sub-pixel driving circuits, each column of sub-pixel driving circuits corresponding to one of the multiple data lines D1, and the first pole of each fourth transistor T4 in each column of sub-pixel driving circuits is coupled to the corresponding data line D1.

[0503] For example, the display substrate includes multiple first scan lines S1, and the gate of each fourth transistor T4 in each row of sub-pixel driving circuit is coupled to the corresponding first scan line S1.

[0504] For example, the fourth transistor T4 includes a fourth active layer 34, which is capable of forming the channel region of the fourth transistor T4.

[0505] For example, the fifth transistor T5 includes a fifth active layer 35, which is capable of forming the channel region of the fifth transistor T5.

[0506] The above-mentioned configuration ensures that the orthographic projection of the fourth part 723 on the substrate 60 does not overlap with the orthographic projection of the fourth active layer 34 on the substrate 60, nor with the orthographic projection of the fifth active layer 35 on the substrate 60. This reduces the layout difficulty of the display substrate, optimizes the grid structure of the signal line film layer, helps to reduce the voltage drop of the signal line film layer, and improves the heat dissipation performance of the signal line film layer.

[0507] like Figures 39 to 53 As shown, in some embodiments, the display substrate further includes a second initialization signal transmission layer Vinit2;

[0508] The display substrate further includes a plurality of sub-pixels, each sub-pixel including a sub-pixel driving circuit, the sub-pixel driving circuit including a driving transistor, a sixth transistor T6, a seventh transistor T7 and a light-emitting element O1, the sixth transistor T6 being coupled to the second electrode of the driving transistor and the light-emitting element O1 respectively, and the seventh transistor T7 being coupled to the light-emitting element O1 and the second initialization signal transmission layer Vinit2 respectively.

[0509] The sixth transistor T6 includes a sixth active layer 36, the seventh transistor T7 includes a seventh active layer 37, and the orthographic projection of the fourth portion 723 on the substrate 60 surrounds at least a portion of the orthographic projection of the seventh active layer 37 on the substrate 60, and also surrounds the orthographic projection of the sixth active layer 36 on the substrate 60.

[0510] For example, the gate of each sixth transistor T6 in each row of sub-pixel driving circuit is coupled to the corresponding light-emitting control line E1.

[0511] For example, the gate of each seventh transistor T7 in each row of sub-pixel driving circuit is coupled to the corresponding third scan line S3.

[0512] The above-described fourth part 723 is projected onto the substrate 60, surrounding at least a portion of the projected image of the seventh active layer 37 onto the substrate 60, and also surrounding the projected image of the sixth active layer 36 onto the substrate 60; this reduces the layout difficulty of the display substrate, optimizes the grid structure of the signal line film layer, helps to reduce the voltage drop of the signal line film layer, and improves the heat dissipation performance of the signal line film layer.

[0513] like Figures 39 to 53As shown, in some embodiments, the display substrate further includes a plurality of sub-pixels, each sub-pixel including a sub-pixel driving circuit, the sub-pixel driving circuit including a driving transistor, the gate of the driving transistor being projected onto the substrate 60, and overlapping with the projected portion of the fourth portion 723 onto the substrate 60.

[0514] The above configuration reduces the layout difficulty of the display substrate, optimizes the grid structure of the signal line film layer, helps to reduce the voltage drop of the signal line film layer, and improves the heat dissipation performance of the signal line film layer.

[0515] like Figures 39 to 53 As shown, in some embodiments, the display substrate further includes a third initialization signal transmission layer, Vinit3;

[0516] The display substrate further includes a plurality of sub-pixels, each sub-pixel including a sub-pixel driving circuit, the sub-pixel driving circuit including a driving transistor and an eighth transistor T8, the first terminal of the eighth transistor T8 being coupled to the third initialization signal transmission layer Vinit3, and the second terminal of the eighth transistor T8 being coupled to either the first or second terminal of the driving transistor; the eighth transistor T8 includes an eighth active layer 38, the orthographic projection of the eighth active layer 38 on the substrate 60 at least partially overlapping the orthographic projection of the fourth portion 723 on the substrate 60.

[0517] For example, the third initialization signal transmitted by the third initialization signal transmission layer Vinit3 can be a high-level signal, such as a positive power supply signal or 0.5 to 1.5 times the voltage value of the positive power supply signal.

[0518] For example, when the third initialization signal is a positive power signal, the third initialization signal transmission layer Vinit3 can be coupled to the signal line film layer in the peripheral area of ​​the display substrate; alternatively, in the display area, in the area where the third initialization signal transmission layer Vinit3 overlaps with the second conductive layer, the third initialization signal transmission layer Vinit3 can be coupled to the second conductive layer through a via.

[0519] like Figure 53 As shown, in the display area, in the region where the third initialization signal transmission layer Vinit3 overlaps with the second conductive layer, the third initialization signal transmission layer Vinit3 and the second conductive layer are coupled through via 90, but not limited to this.

[0520] For example, the gate of each eighth transistor T8 in each row of sub-pixel driving circuit is coupled to the corresponding third scan line S3.

[0521] For example, the first terminal of each eighth transistor T8 in each row of sub-pixel driving circuit is coupled to the corresponding first transmission unit in the third initialization signal transmission layer Vinit3.

[0522] The above-mentioned configuration, wherein the orthographic projection of the eighth active layer 38 on the substrate 60 and the orthographic projection of the fourth part 723 on the substrate 60 overlap at least partially, reduces the layout difficulty of the display substrate, optimizes the grid structure of the signal line film layer, and helps to reduce the voltage drop of the signal line film layer and improve the heat dissipation performance of the signal line film layer.

[0523] like Figures 39 to 53 As shown, in some embodiments, the display substrate further includes a plurality of data lines D1, each data line D1 including at least a portion extending along the first direction; two data lines D1 are present between adjacent third conductive patterns 72.

[0524] For example, the two data lines D1 located between adjacent third conductive patterns 72 are symmetrically arranged about the axis of symmetry.

[0525] like Figures 39 to 53 As shown, in some embodiments, the display substrate further includes a plurality of sub-pixels, each sub-pixel including a sub-pixel driving circuit, the sub-pixel driving circuit including a driving transistor and a storage capacitor, the gate of the driving transistor being reused as the first substrate of the storage capacitor, and the second portion 702 being reused as the second electrode of the storage capacitor.

[0526] The above configuration reduces the layout difficulty of the display substrate, optimizes the grid structure of the signal line film layer, helps to reduce the voltage drop of the signal line film layer, and improves the heat dissipation performance of the signal line film layer.

[0527] This disclosure also provides a display device, including the display substrate provided in the above embodiments.

[0528] In the display substrate provided in the above embodiments, the signal line film layer includes a first conductive layer, a conductive connection layer, and a second conductive layer stacked together. This arrangement forms the signal line film layer as a multi-layer network structure, effectively reducing the voltage drop generated when the signal line film layer transmits signals. When the display substrate is applied to a display product, the uniformity of the display in high-brightness display mode is ensured. Moreover, forming the signal line film layer as a multi-layer network structure helps with heat dissipation of the display product in high-brightness display mode.

[0529] The display device provided in this embodiment includes the above-described display substrate and has the same beneficial effects as described above, which will not be repeated here.

[0530] It should be noted that the display device can be any product or component with display function, such as a television, monitor, digital photo frame, mobile phone, or tablet computer. The display device also includes flexible circuit boards, printed circuit boards, and backplanes.

[0531] It should be noted that, in the embodiments of this disclosure, "same layer" can refer to film layers located on the same structural layer. Alternatively, for example, film layers located on the same layer can be layer structures formed by using the same film deposition process to form a specific pattern, and then patterning the film layer using the same photomask through a single patterning process. Depending on the specific pattern, the single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the formed layer structure can be continuous or discontinuous. These specific patterns may also be at different heights or have different thicknesses.

[0532] In the various method embodiments of this disclosure, the sequence numbers of each step are not intended to limit the order of the steps. For those skilled in the art, any changes in the order of the steps are within the scope of protection of this disclosure without any creative effort.

[0533] It should be noted that the various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the method embodiments are basically similar to the product embodiments, so the description is relatively simple, and the relevant parts can be referred to the description of the product embodiments.

[0534] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connection,” “coupled,” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0535] It is understandable that when a component such as a layer, film, region, or substrate is referred to as being "above" or "below" another component, the component may be "directly" located "above" or "below" the other component, or there may be intermediate components present.

[0536] In the description of the above embodiments, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0537] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A display substrate, comprising: A substrate, an initialization signal transmission layer disposed on the substrate, and a plurality of sub-pixels, wherein each sub-pixel includes a sub-pixel driving circuit, the sub-pixel driving circuit including a first conductive connection portion, a driving transistor, and a storage capacitor; The storage capacitor includes a first electrode plate and a second electrode plate disposed opposite to each other; the second electrode plate includes a via, through which the first conductive connection portion passes and is coupled to the gate of the driving transistor; the first electrode plate includes a first side and a second side disposed opposite to each other along a second direction, and a third side and a fourth side disposed opposite to each other along a first direction, the first direction intersecting the second direction; The initialization signal transmission layer includes a plurality of first transmission units and a plurality of second transmission units; the plurality of first transmission units are arranged along the first direction, and each first transmission unit includes at least a portion extending along the second direction; each second transmission unit includes at least a portion extending along the first direction, and adjacent first transmission units are coupled together by at least one second transmission unit. The distance between adjacent second transmission sections along the second direction is greater than or equal to the maximum first width of the orthogonal projection of the sub-pixel driving circuit on the substrate along the second direction; In the sub-pixel driving circuit layout area including the second transmission section, the orthographic projection of the second transmission section on the substrate at least partially overlaps with the orthographic projection of the corresponding first electrode plate on the substrate, and the second side is the side closer to the second transmission section. Along the second direction, the distance between the orthographic projection of the via on the substrate and the orthographic projection of the first side on the substrate is less than the distance between the orthographic projection of the via on the substrate and the orthographic projection of the second side on the substrate. Along the first direction, the distance between the orthographic projection of the via on the substrate and the orthographic projection of the third side on the substrate is greater than the distance between the orthographic projection of the via on the substrate and the orthographic projection of the fourth side on the substrate.

2. The display substrate according to claim 1, wherein, The display substrate further includes a power line and a light emission control line. The sub-pixel driving circuit further includes a fifth transistor. The gate of the fifth transistor is coupled to the corresponding light emission control line. The first electrode of the fifth transistor is coupled to the corresponding power line. The second electrode of the fifth transistor is coupled to the first electrode of the driving transistor. The orthographic projection of the third side onto the substrate is located between the orthographic projection of the fourth side onto the substrate and the orthographic projection of the light-emitting control line onto the substrate.

3. The display substrate according to claim 2, wherein, The driving transistor includes a third active layer, and the orthographic projection of the third side onto the substrate is located between the orthographic projection of the third active layer onto the substrate and the orthographic projection of the light-emitting control line onto the substrate.

4. The display substrate according to claim 1, wherein, In the sub-pixel driving circuit layout area that does not include the second transmission section, along the first direction, the distance between the orthographic projection of the via on the substrate and the orthographic projection of the third side on the substrate is less than the distance between the orthographic projection of the via on the substrate and the orthographic projection of the fourth side on the substrate.

5. The display substrate according to claim 1 or 4, wherein, In the sub-pixel driving circuit layout area that does not include the second transmission section, the distance between the orthographic projection of the via on the substrate along the second direction and the orthographic projection of the first side on the substrate is less than the distance between the orthographic projection of the via on the substrate and the orthographic projection of the second side on the substrate.

6. The display substrate according to claim 5, wherein, The first electrode plate in the sub-pixel driving circuit layout area containing the second transmission section is mirror-symmetrical to the first electrode plate in the adjacent sub-pixel driving circuit layout area that does not contain the second transmission section along the second direction.

7. The display substrate according to any one of claims 1 to 4, wherein, The display substrate includes a plurality of data lines, each data line including at least a portion extending along the first direction; The sub-pixel driving circuit further includes: a first transistor and a fourth transistor, wherein the first transistor is coupled to the first terminal and the second terminal of the driving transistor, and the fourth transistor is coupled to the first terminal of the driving transistor and the corresponding data line; the first transistor includes a first active layer, and the fourth transistor includes a fourth active layer. At least a portion of the orthographic projection of the second transmission unit onto the substrate is located between the orthographic projection of the first active layer onto the substrate and the orthographic projection of the fourth active layer onto the substrate.

8. The display substrate according to any one of claims 1 to 4, wherein, The display substrate further includes a power line; the sub-pixel further includes a light-emitting element; the sub-pixel driving circuit further includes a fifth transistor and a sixth transistor, the fifth transistor being coupled to the first terminal of the driving transistor and the corresponding power line, and the sixth transistor being coupled to the second terminal of the driving transistor and the light-emitting element; the fifth transistor includes a fifth active layer, and the sixth transistor includes a sixth active layer; At least a portion of the orthographic projection of the second transmission unit onto the substrate is located between the orthographic projection of the fifth active layer onto the substrate and the orthographic projection of the sixth active layer onto the substrate.

9. The display substrate according to claim 8, wherein, The plurality of sub-pixels are divided into multiple groups of sub-pixels, each group of sub-pixels including a first sub-pixel and a second sub-pixel; Both the first sub-pixel and the second sub-pixel include a second conductive portion, and the second conductive portion in the first sub-pixel is coupled to the second conductive portion in the second sub-pixel; The fifth transistor in the first sub-pixel is coupled to the second conductive portion; the fifth transistor in the second sub-pixel is coupled to the second conductive portion, and the second conductive portion in the second sub-pixel is coupled to the corresponding power line; At least a portion of the second transmission unit is located in the sub-pixel driving circuit layout area of ​​the first sub-pixel, and the orthographic projection of the second transmission unit on the substrate does not overlap with the orthographic projection of the second conductive part in the first sub-pixel on the substrate.

10. The display substrate according to claim 8, wherein, The sub-pixel driving circuit further includes an eighth transistor, which is coupled to the first or second terminal of the driving transistor, and is used to reset the first or second terminal. The eighth transistor includes an eighth active layer, and at least a portion of the orthographic projection of the second transmission portion onto the substrate is aligned with the orthographic projection of the eighth active layer onto the substrate along the second direction.

11. The display substrate according to claim 10, wherein, The sub-pixel driving circuit further includes a seventh transistor, which is coupled to the light-emitting element and is used to reset the light-emitting element; The seventh transistor includes a seventh active layer, and at least a portion of the orthographic projection of the second transmission section onto the substrate is located between the orthographic projection of the seventh active layer onto the substrate and the orthographic projection of the eighth active layer onto the substrate.

12. The display substrate according to claim 1, wherein, The display substrate includes a first initialization signal transmission layer and a second initialization signal transmission layer; The initialization signal transmission layer is either the first initialization signal transmission layer or the second initialization signal transmission layer; or... The display substrate includes at least two initialization signal transmission layers, the first of which is the first initialization signal transmission layer, and the second of which is the second initialization signal transmission layer.

13. The display substrate according to claim 12, wherein, The display substrate includes a plurality of sub-pixels, and each sub-pixel includes a light-emitting element and a sub-pixel driving circuit. The sub-pixel driving circuit includes a driving transistor and further includes: The second transistor is coupled to the gate of the driving transistor and the first initialization signal transmission layer, respectively. The seventh transistor is coupled to both the light-emitting element and the second initialization signal transmission layer.

14. The display substrate according to claim 12, wherein, The display substrate further includes a third initialization signal transmission layer; The initialization signal transmission layer is at least one of the first initialization signal transmission layer, the second initialization signal transmission layer, and the third initialization signal transmission layer.

15. The display substrate according to claim 14, wherein, The display substrate includes a plurality of sub-pixels, and each sub-pixel includes a light-emitting element and a sub-pixel driving circuit. The sub-pixel driving circuit includes a driving transistor and further includes: The second transistor is coupled to the gate of the driving transistor and the first initialization signal transmission layer, respectively. The seventh transistor is coupled to both the light-emitting element and the second initialization signal transmission layer. The eighth transistor is coupled to the first terminal of the driving transistor and the third initialization signal transmission layer.

16. The display substrate according to claim 14, wherein, The display substrate further includes a display area and a peripheral area surrounding the display area, and the display substrate further includes: A first signal line is located in the peripheral area of ​​the display substrate. The first signal line includes at least a portion extending along the first direction. The first signal line is coupled to the first initialization signal transmission layer. The first signal line is made of a second source-drain metal layer, and the first transmission section of the first initialization signal transmission layer is made of a first gate metal layer.

17. The display substrate according to claim 16, wherein, The display substrate further includes: The second signal line is located in the peripheral area of ​​the display substrate. The second signal line includes at least a portion extending along the first direction. The orthographic projection of the first signal line on the substrate is located between the display area and the orthographic projection of the second signal line on the substrate. The second signal line is coupled to the second initialization signal transmission layer. The second signal line and the first transmission section included in the second initialization signal transmission layer are both made of a first source-drain metal layer.

18. The display substrate according to claim 17, wherein, The display substrate further includes: The third signal line, the orthographic projection of the third signal line on the substrate, is located between the orthographic projections of the first signal line on the substrate and the orthographic projections of the second signal line on the substrate, and the third signal line is coupled to the third initialization signal transmission layer; The third signal line is fabricated using the first source-drain metal layer, and the third initialization signal transmission layer is fabricated using the third gate metal layer.

19. A display substrate, comprising: A substrate, an initialization signal transmission layer disposed on the substrate, and a plurality of sub-pixels, wherein each sub-pixel includes a sub-pixel driving circuit, and the sub-pixel driving circuit includes a first conductive connection portion, a first transistor, a driving transistor, and a storage capacitor. The first transistor is coupled to the first and second terminals of the driving transistor, respectively; The storage capacitor includes a first electrode plate and a second electrode plate disposed opposite to each other; the second electrode plate includes a via, through which the first conductive connection portion passes and is coupled to the gate of the driving transistor; the first electrode plate includes a first side and a second side disposed opposite to each other along a second direction, and a third side and a fourth side disposed opposite to each other along a first direction, the first direction intersecting the second direction; The initialization signal transmission layer includes a plurality of first transmission units and a plurality of second transmission units; the plurality of first transmission units are arranged along the first direction, and each first transmission unit includes at least a portion extending along the second direction; each second transmission unit includes at least a portion extending along the first direction, and adjacent first transmission units are coupled together by at least one second transmission unit. The distance between adjacent second transmission sections along the second direction is greater than or equal to the maximum first width of the orthogonal projection of the sub-pixel driving circuit on the substrate along the second direction; In the sub-pixel driving circuit layout area including the second transmission section, the orthographic projection of the second transmission section on the substrate at least partially overlaps with the orthographic projection of the corresponding first electrode plate on the substrate, and at least partially overlaps with the orthographic projection of the corresponding second electrode plate on the substrate. The second side is the side away from the first transistor. Along the second direction, the distance between the orthographic projection of the via on the substrate and the orthographic projection of the first side on the substrate is less than the distance between the orthographic projection of the via on the substrate and the orthographic projection of the second side on the substrate. Along the first direction, the distance between the orthographic projection of the via on the substrate and the orthographic projection of the third side on the substrate is greater than the distance between the orthographic projection of the via on the substrate and the orthographic projection of the fourth side on the substrate.

20. A display device comprising a display substrate as claimed in any one of claims 1 to 19.

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