Display device

Abstract

A display device is provided. The display device includes a substrate including a display area and a non-display area at least partially surrounding the display area; a plurality of pixels in the display area; a data driving unit in the non-display area; a plurality of data lines in the display area; a plurality of data connection lines in the non-display area and electrically connecting the data driving unit and the plurality of data lines together; and a plurality of high-potential voltage connection lines in the non-display area and configured to provide a high-potential voltage to the plurality of pixels, wherein the high-potential voltage connection lines include a plurality of holes in a region of the high-potential voltage connection lines overlapping the plurality of data connection lines in the non-display area.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0184335, filed on December 21, 2021, with the Korean Intellectual Property Office, the entirety of which is incorporated herein by reference. Technical Field

[0003] The present invention relates to a display device, and more specifically, to a display device that can suppress image quality degradation by unifying the resistance-capacitance (RC) delay caused by length deviations between multiple data lines. Background Technology

[0004] Recently, with the full arrival of the information age, display devices used to visually display electrical information signals are developing rapidly. Various research efforts are ongoing to develop thinner, lighter display devices with low power consumption and improved performance.

[0005] Representative display devices include liquid crystal displays (LCDs), field-emitting diode (FED) displays, electrowetting displays (EWDs), and organic light-emitting diode (OLEDs).

[0006] In display devices, electroluminescent display devices include organic light-emitting display devices, and specifically refer to self-emissive display devices. Unlike liquid crystal displays, electroluminescent display devices do not require a separate light source, thus allowing for the manufacture of thin and lightweight display devices. Furthermore, electroluminescent display devices offer advantages in power consumption because they operate at low voltage. Moreover, due to their superior performance in color reproduction, response speed, viewing angle, and contrast ratio (CR), electroluminescent display devices are expected to be used in various fields. Summary of the Invention

[0007] One objective of this invention is to provide a display device that can reduce the deviation of RC delay between multiple data lines by adjusting the parasitic capacitance between the high-potential voltage link line and the data link line.

[0008] Another objective of this invention is to provide a display device that can reduce the difference in data load between the periphery and the center of a substrate.

[0009] The purpose of this invention is not limited to the above-described purpose, and other purposes not mentioned above will be clearly understood by those skilled in the art based on the following description.

[0010] In one embodiment, a display device includes: a substrate including a display area and a non-display area at least partially surrounding the display area; a plurality of pixels in the display area; a data driving unit in the non-display area; a plurality of data lines in the display area; a plurality of data interconnects in the non-display area and electrically connecting the data driving unit and the plurality of data lines together; and a plurality of high-potential voltage interconnects in the non-display area and configured to provide a high-potential voltage to the plurality of pixels, wherein the high-potential voltage interconnects include a plurality of holes in areas where the high-potential voltage interconnects overlap with the plurality of data interconnects in the non-display area.

[0011] In one or more embodiments, the high-potential voltage wiring includes a mesh pattern.

[0012] In one or more embodiments, the non-display area includes: a first non-display area, in which the data driving unit is located; a second non-display area between the first non-display area and the display area; and a curved area between the first non-display area and the second non-display area, wherein the high-potential voltage connection includes: a first high-potential voltage connection, which is located in the first non-display area and overlaps with a first portion of a plurality of data connections in the first non-display area; a second high-potential voltage connection, which is located in the second non-display area and overlaps with a second portion of a plurality of data connections in the second non-display area; and a plurality of third high-potential voltage connections, which are located in the curved area and electrically connect the first high-potential voltage connection and the second high-potential voltage connection, wherein the plurality of holes are located in the first high-potential voltage connection and the second high-potential voltage connection.

[0013] In one or more embodiments, the proportion of the region where the plurality of holes are provided decreases as the area of ​​the overlap between the first high-potential voltage connection and the second high-potential voltage connection and the plurality of data connections decreases.

[0014] In one or more embodiments, the number of holes per unit area among the plurality of holes decreases as the area of ​​overlap between the first high-potential voltage connection and the second high-potential voltage connection and the plurality of data connections decreases.

[0015] In one or more embodiments, the size of the plurality of holes decreases as the area of ​​overlap between the first high-potential voltage connection and the second high-potential voltage connection and the plurality of data connections decreases.

[0016] In one or more embodiments, the proportion of the regions in which the plurality of holes are provided in the first high-potential voltage connection and the second high-potential voltage connection increases in the direction from the center portion of the substrate to the periphery of the substrate.

[0017] In one or more embodiments, the substrate has a corner region, the display region has a shape corresponding to the corner region, and a second high-potential voltage connection in the corner region has a shape corresponding to the shape of the display region and the shape of the substrate.

[0018] In one or more embodiments, the corners of the substrate have a rounded shape, and the corners of the display area have a rounded shape.

[0019] In one or more embodiments, the width of the second high-potential voltage connection in the corner region is smaller than the width of the second high-potential voltage connection in the central region.

[0020] In one or more embodiments, the plurality of data lines extend from the first non-display area toward the display area.

[0021] In one or more embodiments, the length of the plurality of data lines increases in the direction from the center portion of the substrate to the peripheral region of the substrate.

[0022] In one or more embodiments, the plurality of data lines are located on a different layer than the high-potential voltage lines.

[0023] In one or more embodiments, the first area of ​​the first high-potential voltage line and the second high-potential voltage line that overlap with the data lines disposed at the central portion of the substrate is greater than the second area of ​​the first high-potential voltage line and the second high-potential voltage line that overlap with the data lines disposed in the peripheral area of ​​the substrate.

[0024] In one or more embodiments, the plurality of holes are arranged differently in different regions on the first high-potential voltage connection and the second high-potential voltage connection that overlap with the plurality of data connections.

[0025] In one or more embodiments, the number of holes in the first high-potential voltage connection and the second high-potential voltage connection increases in the direction from the central portion of the substrate to the peripheral region of the substrate.

[0026] In one or more embodiments, the number of holes per unit area in the first high-potential voltage connection and the second high-potential voltage connection is constant.

[0027] In one or more embodiments, the size of the holes in the first high-potential voltage connection and the second high-potential voltage connection increases in the direction from the central portion of the substrate to the peripheral region of the substrate.

[0028] In one embodiment, a display device includes: a substrate including a display area and a non-display area at least partially surrounding the display area; a plurality of pixels in the display area; a data driving unit in the non-display area; a plurality of data lines in the display area; a plurality of data interconnects in the non-display area and electrically connecting the data driving unit and the plurality of data lines together; and a plurality of high-potential voltage interconnects in the non-display area and configured to provide a high-potential voltage to the plurality of pixels, wherein as the length of the plurality of data interconnects increases from the center of the substrate to the periphery of the substrate, the area of ​​the high-potential voltage interconnects overlapping the plurality of data interconnects in the non-display area decreases in the direction from the center of the substrate toward the periphery of the substrate.

[0029] In one or more embodiments, the high-potential voltage line includes a plurality of holes in the region where the high-potential voltage line overlaps with the plurality of data lines.

[0030] In one or more embodiments, the density of the plurality of holes in the high-potential voltage interconnect increases from the center of the substrate toward the periphery of the substrate.

[0031] In one or more embodiments, the plurality of holes have the same size.

[0032] In one or more embodiments, the size of a plurality of holes in the high-potential voltage line increases from the center of the substrate toward the periphery of the substrate.

[0033] In one or more embodiments, the density of the plurality of holes in the high-potential voltage interconnect is the same across the high-potential voltage interconnect.

[0034] In one embodiment, a display device includes: a substrate including a display area and a non-display area at least partially surrounding the display area; a plurality of pixels in the display area; a data driving unit in the non-display area; a plurality of data lines in the display area; a plurality of data interconnects in the non-display area and electrically connecting the data driving unit and the plurality of data lines together, the plurality of data interconnects including a first data interconnect and a second data interconnect longer than the first data interconnect; and a plurality of high-potential voltage interconnects in the non-display area and configured to provide a high-potential voltage to the plurality of pixels, wherein the area of ​​a first portion of the high-potential voltage interconnect overlapping with the first data interconnect is greater than the area of ​​a second portion of the high-potential voltage interconnect overlapping with the second data interconnect longer than the first data interconnect.

[0035] In one or more embodiments, a first portion of the high-potential voltage connection includes a plurality of first holes, and a second portion of the high-potential voltage connection includes a plurality of second holes.

[0036] In one or more embodiments, the density of a plurality of first holes in the first portion of the high-potential voltage connection is less than the density of a plurality of second holes in the second portion of the high-potential voltage connection.

[0037] In one or more embodiments, the size of a plurality of first holes in the first portion of the high-potential voltage connection is smaller than the size of a plurality of second holes in the second portion of the high-potential voltage connection.

[0038] Further details of the exemplary embodiments are included in the detailed description and accompanying drawings.

[0039] According to the present invention, the proportion of the region in which multiple holes are provided varies according to the area of ​​overlap between the high-potential voltage interconnect and the data interconnect. Therefore, the deviation in RC delay between the peripheral and central regions of the substrate can be reduced.

[0040] According to the present invention, the image quality of a display device can be improved by reducing the deviation of RC delay between multiple data lines.

[0041] The effects of the present invention are not limited to those illustrated above, and include many other different effects in this application. Attached Figure Description

[0042] The above and other aspects, features, and advantages of the invention will become more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, wherein:

[0043] Figure 1 This is a schematic top view of a display device according to an embodiment of the present invention;

[0044] Figure 2 This is according to an embodiment of the present invention. Figure 1 Enlarged top view of region A in the diagram;

[0045] Figure 3 This is a cross-sectional view of a display device according to an embodiment of the present invention;

[0046] Figure 4 It is along the embodiment of the present invention Figure 2 A sectional view taken by line IV-IV';

[0047] Figure 5 It is along the embodiment of the present invention Figure 2 A sectional view taken by line V-V';

[0048] Figure 6 This is an enlarged top view of a display device according to another embodiment of the present invention;

[0049] Figure 7 It is according to another embodiment of the present invention along Figure 6 A sectional view taken from line VII-VII';

[0050] Figure 8 It is according to another embodiment of the present invention along Figure 6 The sectional view taken from VIII-VIII'. Detailed Implementation

[0051] The advantages and features of the present invention, and the methods for achieving these advantages and features, are described below with reference to the appendix. Figure 1 The exemplary embodiments described in detail will become clear. However, the invention is not limited to the exemplary embodiments disclosed herein, but will be implemented in various forms. Exemplary embodiments are provided by way of example only to enable those skilled in the art to fully understand the disclosure and scope of the invention. Therefore, the invention will be limited only by the scope of the appended claims.

[0052] The shapes, dimensions, proportions, angles, quantities, etc., shown in the accompanying drawings for the purpose of describing exemplary embodiments of the invention are merely examples, and the invention is not limited thereto. Similar reference numerals denote similar elements throughout the application. Furthermore, in the following description of the invention, detailed explanations of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of the invention. Terms such as “comprising,” “having,” and “including” as used herein are generally intended to allow for the addition of additional components, unless these terms are used in conjunction with the term “only.”

[0053] Even if not explicitly stated, the components are still interpreted as including the usual error range.

[0054] When using terms such as “on top of,” “above,” “below,” and “after” to describe the positional relationship between two parts, one or more parts may be placed between the two parts, unless these terms are used with the terms “immediately following” or “directly.”

[0055] When one element or layer is disposed "on" another element or layer, the element or layer may be disposed directly on the other element or layer or other elements or layers may be inserted between them.

[0056] Although the terms "first," "second," etc., are used to describe various components, these components are not limited by these terms. These terms are merely used to distinguish one component from other components. Therefore, within the technical concept of this invention, the first component mentioned below can be a second component.

[0057] The same reference numerals generally refer to the same elements throughout the application.

[0058] For ease of illustration, the dimensions and thickness of each component shown in the accompanying drawings are illustrated. However, the invention is not limited to the dimensions and thickness of the illustrated components.

[0059] The features of the various embodiments of the present invention may be combined or integrated with each other in part or in whole, and may be interlocked and operated in various technical ways. These embodiments may be implemented independently of each other or in association with each other.

[0060] Hereinafter, a display device according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

[0061] Figure 1 This is a schematic top view of a display device according to an embodiment of the present invention. For ease of description, Figure 1 Only the substrate 110, pad portion PAD, and data driving unit DD among the various components of the display device 100 are shown. However, the display device may include... Figure 1 Other components besides those shown.

[0062] Reference Figure 1 The substrate 110 includes a display area AA and a non-display area NA.

[0063] The substrate 110 is a basic component for supporting various parts of the display device 100 and may be made of an insulating material. For example, the substrate 110 may be made of a plastic material such as glass or polyimide.

[0064] The display area AA is the region where an image is displayed. Multiple pixels are disposed in the display area AA. Display elements for displaying the image and driving components for operating the display elements may be disposed in the display area AA. For example, in the case where the display device 100 is an organic light-emitting display device, the display element may be an organic light-emitting element including an anode, an organic layer, and a cathode. The driving components may include various components for operating the organic light-emitting element, such as power lines PL, gate lines, data lines, thin-film transistors, and storage capacitors. Hereinafter, for ease of description, it is assumed that the display device 100 is an organic light-emitting display device. However, the display device 100 is not limited to organic light-emitting display devices.

[0065] Reference Figure 1 The substrate 110 may have a variant corner region. The display area AA may have a shape corresponding to the variant corner region of the substrate 110. The corners of the substrate 110 and the display area AA may each have a rounded shape. However, the present invention is not limited thereto. The substrate 110 and the display area AA may have various shapes suitable for the design of an electronic device equipped with the display device 100.

[0066] The non-display area NA is the region where no image is displayed. Various lines and circuits used to operate the display elements in the display area AA are located in the non-display area NA. For example, data drive units DD, interconnects, and pads PAD can be located in the non-display area NA.

[0067] The non-display area NA can be a region extending from the display area AA. However, the invention is not limited thereto. The non-display area NA can be a region surrounding the display area AA.

[0068] In one embodiment, the non-display area NA includes a first non-display area NA1, a curved area BA, and a second non-display area NA2. The second non-display area NA2 extends from the display area AA. The curved area BA extends from the second non-display area NA2. The curved area BA can be bent. The first non-display area NA1 extends from the curved area BA.

[0069] Data drive unit (DD), pad section (PAD), etc., can be located in the first non-display area (NA1). Pads connecting to various signal lines or PCBs are located on the pad section (PAD). Power pads, data pads, gate pads, etc., can be located on the pad section (PAD).

[0070] The data driver unit DD can be mounted on or connected to a separate PCB and connected to the display panel via pads (PADs). Optionally, the data driver unit DD can be mounted or connected between the pads (PADs) and the display area AA in the form of a chip-on-panel (COP). The data driver unit DD includes at least one source driver integrated circuit (IC). The at least one source driver IC is provided with source timing control signals from a timing controller and digital video data. The at least one source driver IC generates a data voltage by converting the digital video data into gamma voltage in response to the source timing control signals and provides the data voltage via data lines in the display area AA.

[0071] Multiple bending patterns are disposed in the bending zone BA. The bending zone BA is the area on the final product that is bent. Cracks can occur because stress is concentrated on the bending patterns disposed in the bending zone BA when bending. Therefore, the bending patterns can be patterns with specific shapes to reduce the incidence of cracking. For example, the bending patterns can be made by repeatedly distributing conductive patterns having at least one of diamond, rhombus, zigzag, and circular shapes. However, the invention is not limited to this. In addition to the shapes described above, the bending patterns can have other shapes to reduce stress concentration on the bending patterns and cracking.

[0072] The second non-display area NA2 is the region located between the curved area BA and the display area AA. Connections such as voltage lines and data lines can be provided in the second non-display area NA2. That is, the second non-display area NA2 is used to transmit signals output from the driving component to the display area AA. In the case where the substrate 110 includes a deformable corner area, the second non-display area NA2 may have a shape corresponding to the shape of the substrate 110 and the shape of the display area AA.

[0073] Figure 2 According to one implementation method Figure 1 An enlarged top view of region A in the diagram. For ease of description, Figure 2 The following components of the display device 100 are shown: substrate 110, pad portion PAD, data drive unit DD, data line DL, data connection line DLL, and high-potential voltage connection 160. (For ease of illustration) Figure 2 The data connection DLL, which overlaps with the high-potential voltage connection 160, is marked with a dashed line.

[0074] Reference Figure 2 The display device 100 may include a display area AA and a non-display area NA. The non-display area NA may include a first non-display area NA1, a second non-display area NA2, and a curved area BA.

[0075] In the display area AA, multiple data lines DL and multiple gate lines can be configured to intersect each other. Furthermore, pixels can be arranged in a matrix shape in each area where multiple data lines DL and multiple gate lines intersect.

[0076] Each pixel may include a light-emitting element and a driving thin-film transistor configured to control the amount of current flowing through the light-emitting element. Pixels of the display device 100 may be provided with a high-potential voltage via a high-potential voltage connection 160 disposed in the non-display area NA. Pixels of the display device 100 may be provided with a low-potential voltage via a low-potential voltage connection.

[0077] The high-potential voltage connection 160 can be supplied with a high-potential voltage from the power pads provided on the pad section PAD, and transmit the high-potential voltage to the high-potential power lines provided in the display area AA. The high-potential voltage connection 160 may include a first high-potential voltage connection 161, a second high-potential voltage connection 162, and multiple third high-potential voltage connections 163.

[0078] The first high-potential voltage connection 161 is provided in the first non-display area NA1. In this case, the first high-potential voltage connection can be provided between the curved area BA and the pad portion PAD. The first high-potential voltage connection 161 can receive the high-potential voltage from the power pad of the pad portion PAD.

[0079] A third high-potential voltage connection 163 is disposed in the bending region BA and connects the first high-potential voltage connection 161 and the second high-potential voltage connection 162 together. Since the third high-potential voltage connection 163 is disposed in the bending region BA, it can have a pattern with a specific shape to reduce the incidence of breakage during the bending process. However, the invention is not limited thereto. The third high-potential voltage connection 163 can receive a high-potential voltage from the first high-potential voltage connection 161 and transmit the high-potential voltage to the second high-potential voltage connection 162.

[0080] The second high-potential voltage connection 162 is disposed in the second non-display area NA2. Therefore, the second high-potential voltage connection 162 can be disposed between the display area AA and the curved area BA. Thus, when both the substrate 110 and the display area AA have shapes corresponding to the deformed corner areas, the second high-potential voltage connection 162 can have a shape in the deformed corner area that corresponds to the shape of the display area AA and the shape of the substrate 110. That is, the second high-potential voltage connection 162 can have a shape in the deformed corner area that matches the shape of the display area AA and the shape of the substrate 110. For example, each of the corner areas of the substrate 110 and the display area AA has... Figure 2In the case of the circular shape shown, the width of the second high-potential voltage connection 162 in the deformed corner area can be smaller than the width of the second high-potential voltage connection 162 in the center area. The second high-potential voltage connection 162 can receive high-potential voltage from the third high-potential voltage connection 163 and transmit the high-potential voltage to the display area AA.

[0081] Next, the pixels of the display device 100 can be supplied with data voltage via data lines DLLs provided in the non-display area NA and via data lines provided in the display area. The data voltage can be supplied to the data driving unit DD via the data pads of the pad portion PAD. The data driving unit DD is provided in the first non-display area NA1 and is configured as an integrated circuit (IC). The data driving unit DD samples and latches the data signal provided from the timing controller, converts the data signal into a gamma reference voltage, and outputs the gamma reference voltage in response to the data timing control signal provided from the timing controller. The data driving unit DD outputs the data signal via multiple data lines DLLs.

[0082] Since the data driver unit DD and data pads located in the first non-display area NA1 are connected to the data lines in the display area AA via the data connection DLL, the data connection DLL is located in the first non-display area NA1, the curved area BA, and the second non-display area NA2. That is, the data connection DLL can extend from the first non-display area NA1 towards the display area AA via the curved area BA. The data connection DLL can be as follows... Figure 2 The diagram shows the configuration. However, the invention is not limited thereto. The data line DLL formed in the non-display area NA can be connected to the data line DL formed in the display area AA in various ways.

[0083] Since the data connection DLL extends from the data driving unit DD through the non-display area NA towards the display area AA, there are areas in the first non-display area NA1 and the second non-display area NA2 where the data connection DLL overlaps with the high-potential voltage connection 160. In this case, a plurality of holes H1 can be provided in the areas where the first and second high-potential voltage connections 161 and 162 overlap with the first and second portions of the data connection DLL, respectively. Therefore, the first and second high-potential voltage connections 161 and 162 can have a mesh pattern in which a plurality of holes H1 are arranged. However, the present invention is not limited thereto. The high-potential voltage connection 160 can have various shapes including a plurality of holes H1.

[0084] The proportion of the area with multiple holes H1 decreases as the area of ​​overlap between the first and second high-potential voltage connections 161 and 162 and the multiple data connections DLL decreases. That is, for each unit area of ​​the high-potential voltage connection 160, the proportion of the area with multiple holes H1 increases as the area of ​​overlap between the first and second high-potential voltage connections 161 and 162 and the multiple data connections DLL increases. The multiple data connections DLL need to transmit data signals from the data driving unit DD to the display area AA of the substrate 110. Therefore, the data connections DLL can have the shortest length in the central portion of the substrate 110, and the length of the data connections DLL can increase in the direction toward the peripheral area of ​​the substrate 110. That is, the data connections DLL located in the central portion of the substrate 110 have a relatively short length, thus having low resistance. The data connections DLL located in the peripheral area of ​​the substrate 110 have a relatively long length, thus having high resistance. Therefore, the areas of the first and second high-potential voltage lines 161 and 162 that overlap with the data connection DLL located at the center of the substrate 110 need to be larger than the areas of the first and second high-potential voltage lines 161 and 162 that overlap with the data connection DLL located in the peripheral area of ​​the substrate 110, in order to reduce the deviation of the RC delay between the data connection DLL located at the center of the substrate 110 and the data connection DLL located in the peripheral area of ​​the substrate 110. Therefore, the proportion of the area where multiple holes H1 are provided per unit area of ​​the first and second high-potential voltage lines 161 and 162 can increase in the direction from the center of the substrate 110 toward the periphery. Thus, as... Figure 2 As shown, the density of holes H1 in the central portion of the substrate with a shorter width of the data interconnect DLL is less than the density of holes H1 in the corners of the substrate 110 located at the periphery of the substrate 110, where the data interconnect DLL has a longer length than the data interconnect DLL in the central portion of the substrate 110. As a result, the density of holes H1 increases from the central portion of the substrate 110 toward the periphery of the substrate 110.

[0085] In the following text, reference will be made to Figures 3 to 5 The components of the display device 100 according to an embodiment of the present invention will be described in more detail.

[0086] Figure 3 This is a cross-sectional view of a display device according to an embodiment of the present invention.

[0087] Reference Figure 3According to an embodiment of the present invention, the display device 100 may include a substrate 110, a buffer layer 111, a first thin film transistor 120, a gate insulating layer 112, a first interlayer insulating layer 113, a conductive layer 150, a second interlayer insulating layer 114, a first planarization layer 115, a connecting electrode 190, a second planarization layer 116, a dam 117, a light-emitting element 130, a sealing portion 140, and a conductive layer 150.

[0088] The substrate 110 can support the various components of the display device 100. The substrate 110 can be made of a flexible plastic material or glass. When the substrate 110 is made of a plastic material, it can be made of polyimide (PI) for example.

[0089] A buffer layer 111 may be disposed on the substrate 110. The buffer layer 111 may be a single layer made of silicon nitride (SiNx) or silicon oxide (SiOx) or a multilayer comprising the above layers. The buffer layer 111 may be used to increase the bonding force between the substrate 110 and the multiple layers formed on the buffer layer 111, and to prevent alkaline materials from leaking from the substrate 110.

[0090] Thin-film transistor 120 may be disposed on buffer layer 111. Thin-film transistor 120 may include active layer 121, gate 124, source 122, and drain 123. In this case, depending on the pixel circuit design, source 122 may be drain, and drain 123 may be source. Active layer 121 of thin-film transistor 120 may be disposed on buffer layer 111.

[0091] The active layer 121 can be made of various materials such as polycrystalline silicon, amorphous silicon, or oxide semiconductor layers. The active layer 121 may include a channel region formed during the operation of the thin-film transistor 120, and source and drain regions disposed on opposite sides of the channel region. The source region refers to the portion of the active layer 121 connected to the source 122. The drain region refers to the portion of the active layer 121 connected to the drain 123.

[0092] A gate insulating layer 112 may be disposed on the active layer 121 of the thin-film transistor 120. The gate insulating layer 112 may be a single layer made of silicon nitride (SiNx) or silicon oxide (SiOx) or a multilayer comprising the above layers. The gate insulating layer 112 may have contact holes through which the source 122 and drain 123 of the thin-film transistor 120 are connected to the source region and drain region of the active layer 121 of the thin-film transistor 120.

[0093] The gate 124 of the thin-film transistor 120 may be disposed on the gate insulating layer 112. The gate 124 may be configured as a single layer or multiple layers made of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), neodymium (Nd), and their alloys. The gate 124 may be formed on the gate insulating layer 112 and overlap with the channel region of the active layer 121 of the thin-film transistor 120.

[0094] A first interlayer insulating layer 113 may be disposed on the gate insulating layer 112 and the gate 124. The first interlayer insulating layer 113 may be a single layer made of silicon nitride (SiNx) or silicon oxide (SiOx) or a multilayer comprising the above layers. The first interlayer insulating layer 113 may have contact holes through which the source and drain regions of the active layer 121 of the thin-film transistor 120 are exposed.

[0095] The conductive layer 150 may be disposed on the first interlayer insulating layer 113. The conductive layer 150 may be a line or electrode disposed between the gate 124, the source 122 and the drain 123.

[0096] A second interlayer insulating layer 114 may be disposed on the first interlayer insulating layer 113 and the conductive layer 150. The second interlayer insulating layer 114 may have the same material as the first interlayer insulating layer 113. That is, the second interlayer insulating layer 114 may be a single layer made of silicon nitride (SiNx) or silicon oxide (SiOx) or a multilayer comprising the above layers. The second interlayer insulating layer 114 may have contact holes through which the source and drain regions of the active layer 121 of the thin-film transistor 120 are exposed.

[0097] The source 122 and drain 123 of the thin-film transistor 120 can be disposed on the second interlayer insulating layer 114.

[0098] The source 122 and drain 123 of the thin-film transistor 120 can be connected to the active layer 121 of the thin-film transistor 120 via contact holes formed in the gate insulating layer 112, the first interlayer insulating layer 113, and the second interlayer insulating layer 114. Therefore, the source 122 of the thin-film transistor 120 can be connected to the source region of the active layer 121 via contact holes formed in the gate insulating layer 112, the first interlayer insulating layer 113, and the second interlayer insulating layer 114. Furthermore, the drain 123 of the thin-film transistor 120 can be connected to the drain region of the active layer 121 via contact holes formed in the gate insulating layer 112, the first interlayer insulating layer 113, and the second interlayer insulating layer 114.

[0099] The source 122 and drain 123 of the thin-film transistor 120 can be formed using the same process. Furthermore, the source 122 and drain 123 of the thin-film transistor 120 can be made of the same material. Each of the source 122 and drain 123 of the thin-film transistor 120 can be configured as a single layer or multiple layers made of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), neodymium (Nd), or an alloy thereof.

[0100] The first planarization layer 115 can be disposed on the source 122, the drain 123, and the second interlayer insulating layer 114. For example... Figure 3 As shown, the first planarization layer 115 may have contact holes for exposing the drain 123. The first planarization layer 115 may be an organic material layer for planarizing the upper portion of the thin-film transistor 120. For example, the first planarization layer 115 may be made of organic materials such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, and polyimide resin. However, the invention is not limited thereto. The first planarization layer 115 may also be an inorganic material layer for protecting the thin-film transistor 120. For example, the first planarization layer 115 may be made of inorganic materials such as silicon nitride (SiNx) or silicon oxide (SiOx). The first planarization layer 115 may be a single layer made of silicon nitride (SiNx) or silicon oxide (SiOx) or a multilayer comprising the aforementioned layers.

[0101] A connection electrode 190 may be disposed on the first planarization layer 115. Furthermore, the connection electrode 190 may be connected to the drain 123 of the thin-film transistor 120 via contact holes in the first planarization layer 115. The connection electrode 190 may be used to electrically connect the thin-film transistor 120 and the light-emitting element 130. For example, the connection electrode 190 may be used to electrically connect the drain 123 of the thin-film transistor 120 and the first electrode 131 of the light-emitting element 130. The connection electrode 190 may be configured as a single layer or multiple layers made of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), neodymium (Nd), and their alloys. The connection electrode 190 may be made of the same material as the source 122 and drain 123 of the thin-film transistor 120.

[0102] The second planarization layer 116 may be disposed on the connecting electrode 190 and the first planarization layer 115. Furthermore, as... Figure 3 As shown, the second planarization layer 116 may have contact holes for exposing the connection electrode 190. The second planarization layer 116 may be an organic material layer for planarizing the upper part of the thin-film transistor 120. For example, the second planarization layer 116 may be made of organic materials such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, and polyimide resin.

[0103] The light-emitting element 130 may be disposed on the second planarization layer 116. The light-emitting element 130 may include a first electrode 131, a light-emitting structure 132, and a second electrode 133. The first electrode 131 of the light-emitting element 130 may be disposed on the second planarization layer 116. The first electrode 131 may be electrically connected to the connecting electrode 190 through a contact hole formed in the second planarization layer 116. Therefore, the first electrode 131 of the light-emitting element 130 may be connected to the connecting electrode 190 through a contact hole formed in the second planarization layer 116, thereby the first electrode 131 may be electrically connected to the thin-film transistor 120.

[0104] The first electrode 131 may have a multilayer structure comprising a transparent conductive film and an opaque conductive film with high reflectivity. The transparent conductive film may be made of a material such as indium tin oxide (ITO) or indium zinc oxide (IZO), which have relatively large work function values. Furthermore, the opaque conductive film may have a single-layer or multilayer structure made of Al, Ag, Cu, Pb, Mo, Ti, or alloys thereof. For example, the first electrode 131 may have a structure in which a transparent conductive film, an opaque conductive film, and a transparent conductive film are stacked sequentially. However, the invention is not limited thereto. The first electrode may have a structure in which a transparent conductive film and an opaque conductive film are stacked sequentially.

[0105] Since the display device 100 according to the embodiment of the present invention is a top-emitting display device, the first electrode 131 can be an anode. When the display device 100 is a bottom-emitting display device, the first electrode 131 disposed on the second planarization layer 116 can be a cathode.

[0106] A dam 117 may be disposed on the first electrode 131 and the second planarization layer 116. The dam 117 may have an opening for exposing the first electrode 131. Since the dam 117 can define the light-emitting area of ​​the display device 100, the dam 117 may be referred to as a pixel defining film.

[0107] The light-emitting structure 132, including the light-emitting layer, can be disposed on the first electrode 131.

[0108] The light-emitting structure 132 of the light-emitting element 130 can be formed by stacking a positive hole layer, a light-emitting layer, and an electron layer sequentially or in reverse order on the first electrode 131. Furthermore, the light-emitting structure 132 may have a first light-emitting structure and a second light-emitting structure facing each other with a charge-generating layer interposed between them. In this case, the light-emitting layer of either the first or second light-emitting structure emits blue light, and the light-emitting layer of the other emits yellow-green light. Therefore, white light can be emitted through the first and second light-emitting structures. The white light emitted through the light-emitting structure 132 can enter a color filter located on the upper part of the light-emitting structure 132, thereby realizing a color image. Furthermore, each of the light-emitting structures 132 can emit light corresponding to the color of each sub-pixel, thereby realizing a color image without the need for a separate color filter. For example, the light-emitting structure 132 of the red (R) sub-pixel can emit red light, the light-emitting structure 132 of the green (G) sub-pixel can emit green light, and the light-emitting structure 132 of the blue (B) sub-pixel can emit blue light.

[0109] The second electrode 133 may be further disposed on the light-emitting structure 132. The second electrode 133 of the light-emitting element 130 may be disposed on the light-emitting structure 132 and face each other with the first electrode 131 having the light-emitting structure 132 inserted therebetween. In the display device 100 according to an embodiment of the present invention, the second electrode 133 may be a cathode. A sealing portion 140 for suppressing moisture penetration may be further disposed on the second electrode 133.

[0110] The sealing portion 140 may include a first inorganic sealing layer 141, an organic sealing layer 142, and a second inorganic sealing layer 143. The first inorganic sealing layer 141 of the sealing portion 140 may be disposed on the second electrode 133. Furthermore, the organic sealing layer 142 may be disposed on the first inorganic sealing layer 141. Furthermore, the second inorganic sealing layer 143 may be disposed on the organic sealing layer 142. Each of the first inorganic sealing layer 141 and the second inorganic sealing layer 143 of the sealing portion 140 may be made of an inorganic material such as silicon nitride (SiNx) or silicon oxide (SiOx). The organic sealing layer 142 of the sealing portion 140 may be made of an organic material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, and polyimide resin.

[0111] The second inorganic sealing layer 143 may cover the upper and side surfaces of each of the first inorganic sealing layer 141 and the organic sealing layer 142. The second inorganic sealing layer 143 may reduce or inhibit the penetration of external moisture or oxygen into the first inorganic sealing layer 141 and the organic sealing layer 142. In this case, the first inorganic sealing layer 141 and the second inorganic sealing layer 143 can be used to inhibit the penetration of moisture or oxygen. The organic sealing layer 142 may be used to planarize the upper part of the first inorganic sealing layer 141. Therefore, the sealing portion 140 may cover the gate drive circuit and dam in the display area AA and the non-display area NA. However, the construction of the sealing portion 140 is not limited to this.

[0112] Figure 4 It is based on one implementation method along Figure 2 A sectional view taken from line IV-IV'. Figure 5 It is based on one implementation method along Figure 2 A cross-sectional view taken along line V-V'. For ease of description, Figure 4 and 5 Only the components from the substrate 110 to the second planarization layer 116 among the various components of the display device 100 are shown. (Refer to...) Figure 4 and 5 Only the second high-potential voltage connection 162 is described. The structure of the second high-potential voltage connection 162 can be applied equivalently to the first high-potential voltage connection 161.

[0113] Reference Figure 4 and 5 The data connection DLL can be disposed between the gate insulating layer 112 and the first interlayer insulating layer 113. That is, the data connection DLL can be formed on the same layer as the gate 124 of the thin-film transistor 120 in the display area AA. However, the present invention is not limited thereto. The data connection DLL can be formed on the same layer as the conductive layer 150 in the display area AA. That is, the data connection DLL can be disposed between the first interlayer insulating layer 113 and the second interlayer insulating layer 114. Specifically, in the first non-display area NA1 and the second non-display area NA2, the data connection DLL can be formed on the same layer as the gate 124 or the conductive layer 150. However, the present invention is not limited thereto, and the data connection DLL can be formed on the same layer as the various conductive components on the substrate 110 using the same material. However, the data connection DLL can be disposed on a different layer than the layer on which the high-potential voltage connection 160 is disposed.

[0114] The high-potential voltage connection 160 can be disposed on the second interlayer insulating layer 114. The first planarization layer 115 and the second planarization layer 116 can be disposed on the second high-potential voltage connection 162. Figure 4 and 5 It is along Figure 2A cross-sectional view taken from lines IV-IV' and V-V'. The second high-potential voltage connection 162 may be disposed on the second interlayer insulation layer 114.

[0115] As described above, a plurality of holes H1 may be disposed in the region where the first and second high-potential voltage connections 161 and 162 overlap with the data connection DLL. Therefore, the first and second high-potential voltage connections 161 and 162 may have a mesh pattern in which a plurality of holes H1 are arranged.

[0116] Furthermore, the proportion of the area occupied by the multiple holes H1 per unit area of ​​the high-potential voltage interconnect 160 decreases as the area of ​​the overlap between the first high-potential voltage interconnect 161 and the second high-potential voltage interconnect 162 and the multiple data interconnects DLL decreases. The multiple data interconnects DLL transmit data signals from the data driving unit DD to the display area AA of the substrate 110. Therefore, the data interconnects DLL can have the shortest length at the center of the substrate 110, and the length of the data interconnects DLL can increase in the direction toward the peripheral area of ​​the substrate 110. That is, the data interconnects DLL located at the center of the substrate 110 have a relatively shorter length than the data interconnects DLL in the peripheral area, thus having a lower resistance compared to the data interconnects DLL in the peripheral area. The data interconnects DLL located in the peripheral area of ​​the substrate 110 have a relatively longer length than the data interconnects DLL in the center of the substrate 110, thus having a higher resistance compared to the data interconnects DLL in the center of the substrate 110. Therefore, the areas of the first high-potential voltage connection 161 and the second high-potential voltage connection 162 overlapping with the data connection DLL disposed in the central portion of the substrate 110 need to be larger than the areas of the first high-potential voltage connection 161 and the second high-potential voltage connection 162 overlapping with the data connection DLL disposed in the peripheral area of ​​the substrate 110, in order to reduce the deviation of the RC delay between the data connection DLL disposed in the central portion of the substrate 110 and the data connection DLL disposed in the peripheral area of ​​the substrate 110. Therefore, the proportion of the area where multiple holes H1 are disposed per unit area of ​​the first high-potential voltage connection 161 and the second high-potential voltage connection 162 can increase in the direction from the central portion of the substrate 110 toward the periphery. Multiple data connections may include a first data connection and a second data connection longer than the first data connection, wherein the area of ​​the first portion of the high-potential voltage connection overlapping with the first data connection can be larger than the area of ​​the second portion of the high-potential voltage connection overlapping with the second data connection longer than the first data connection. The first portion of the high-potential voltage interconnect may include a plurality of first holes, and the second portion of the high-potential voltage interconnect may include a plurality of second holes. The density of the plurality of first holes in the first portion of the high-potential voltage interconnect may be less than the density of the plurality of second holes in the second portion of the high-potential voltage interconnect. The size of the plurality of first holes in the first portion of the high-potential voltage interconnect may be less than the size of the plurality of second holes in the second portion of the high-potential voltage interconnect.

[0117] Reference Figure 2 , 45. For each unit area of ​​the first high-potential voltage interconnect 161 and the second high-potential voltage interconnect 162, the proportion of the area where multiple holes H1 are provided can vary depending on the number of holes H1. That is, the size of the multiple holes H1 is equal to each other throughout the entire area of ​​the high-potential voltage interconnect 160, but the length of the high-potential voltage interconnect 160 is relatively long. Therefore, for each unit area, the number of holes H1 provided on the high-potential voltage interconnect 160 can increase as the area where the high-potential voltage interconnect overlaps with the data interconnect DLL increases (or decrease as the area where the high-potential voltage interconnect overlaps with the data interconnect DLL decreases). That is, the overlap length of the data interconnect DLL with the high-potential voltage interconnect 160 located at the center of the substrate 110 is shorter, and the overlap length of the data interconnect DLL with the high-potential voltage interconnect 160 located at the periphery of the substrate 110 is longer. Therefore, the number of holes H1 on the first high-potential voltage interconnect 161 and the second high-potential voltage interconnect 162 at the periphery of the substrate 110 can be greater than the number at the center of the substrate 110.

[0118] In typical display devices, data interconnects (DLLs) include portions extending in an inclined direction rather than a straight direction to reduce the size of the non-display area (NA). Therefore, the length of the data interconnects can vary depending on their location. For example, among multiple data interconnects receiving signals from the same data drive unit, the data interconnect located in the central portion is relatively shorter, while the data interconnect located in the peripheral area is relatively longer. Consequently, the line resistance of the interconnect located in the peripheral area is greater than that of the interconnect located in the central portion, resulting in a greater RC delay value for the data interconnect in the peripheral area compared to the data interconnect in the central portion.

[0119] Furthermore, the increasing demand for high-resolution and high-speed products leads to increased display device resolution and consequently, increased data load on the display panel. This results in a gradual decrease in pixel charging time and insufficient operating time. When the operating time is insufficient as described above, pixels that have not yet been charged with data voltage are generated due to RC delay. This can cause color mixing defects in adjacent pixels. Therefore, it is necessary to reduce the RC delay of the data interconnects. Since the RC delay of the data interconnects is proportional to the data load of the display panel, the data load needs to be reduced in the case of high-resolution and large-area products. In this case, the data load of the display panel is determined based on the resistance and capacitance of the data interconnects, and the resistance and capacitance of the data interconnects increase proportionally to the length of the interconnects. Therefore, the data load of the display panel tends to increase further in the peripheral area compared to the center of the substrate.

[0120] Therefore, in the display device 100 according to an embodiment of the present invention, multiple holes H1 are provided differently for each region on the first high-potential voltage connection 161 and the second high-potential voltage connection 162 that overlap with the data connection DLL. Therefore, the deviation in RC delay between the multiple data connection DLLs can be reduced. When multiple holes H1 are provided on the high-potential voltage connection 160, the area of ​​overlap between the high-potential voltage connection 160 and the data connection DLL is reduced, thereby reducing the parasitic capacitance applied to the data connection DLL. When the parasitic capacitance applied to the data connection DLL decreases, the resistance of the data connection DLL remains the same, but the data load decreases. Therefore, the RC delay of the data connection is reduced, which is beneficial for ensuring operating time even in the case of products with high resolution and high-speed operation.

[0121] Furthermore, in the display device 100 according to an embodiment of the present invention, the proportion of the area of ​​the plurality of holes H1 can be increased proportionally to the area of ​​overlap between the data interconnect DLL and the high-potential voltage interconnect 160. This is to minimize the area of ​​overlap between the data interconnect DLL and the high-potential voltage interconnect 160 by providing a large number of holes H1, since parasitic capacitance increases with the increase of the area of ​​overlap between the data interconnect DLL and the high-potential voltage interconnect 160. Among the plurality of data interconnect DLLs, the data interconnect DLLs provided in the central portion of the substrate 110 can have a relatively short length, thereby having low resistance. The area of ​​overlap between the data interconnect DLLs provided in the central portion of the substrate 110 and the high-potential voltage interconnect 160 can be small. Conversely, among the plurality of data interconnect DLLs, the data interconnect DLLs provided in the peripheral area of ​​the substrate 110 can have a relatively long length, thereby having high resistance. The area of ​​overlap between the data interconnect DLLs provided in the peripheral area of ​​the substrate 110 and the high-potential voltage interconnect 160 can be large. Therefore, the number of holes H1 provided on the first high-potential voltage connection 161 and the second high-potential voltage connection 162 can increase in the direction from the center portion of the substrate 110 to the peripheral region, thereby the parasitic capacitance applied to the data connection DLL located in the peripheral region of the substrate 110 is lower than the parasitic capacitance applied to the data connection located in the center portion of the substrate. Therefore, in the display device 100 according to an embodiment of the present invention, the number of holes H1 varies according to the area of ​​overlap between the data connection DLL and the high-potential voltage connection 160. Therefore, the deviation of RC delay between multiple data connections can be reduced, and image quality can be improved.

[0122] Figure 6 This is an enlarged top view of a display device according to another embodiment of the present invention. Figure 7 It is according to another embodiment of the present invention along Figure 6 A sectional view taken from line VII-VII'. Figure 8 It is along Figure 6The sectional view taken from VIII-VIII'. For ease of description, Figure 6 Only the substrate 110, pad portion PAD, data drive unit DD, data line DL, data connection line DLL, and high-potential voltage connection 260 among the various components of the display device 200 are shown. For ease of illustration, Figure 6 The data connection DLL, which overlaps with the high-potential voltage connection 260, is marked with a dashed line. For ease of description... Figure 7 and 8 Only the components from substrate 110 to second planarization layer 116 among the various components of display device 200 are shown. (Refer to...) Figure 7 and 8 Only the second high-potential voltage connection 262 is described. The structure of the second high-potential voltage connection 262 can be applied equivalently to the first high-potential voltage connection 261.

[0123] Since the data connection DLL extends from the data driving unit DD through the non-display area NA towards the display area AA, there is an area where the data connection DLL overlaps with the high-potential voltage connection 260. In this case, a plurality of holes H2 can be provided in the area where the first and second high-potential voltage connections 261 and 262 overlap with the data connection DLL. Therefore, the first and second high-potential voltage connections 261 and 262 can have a mesh pattern in which a plurality of holes H2 are arranged. However, the invention is not limited thereto. The high-potential voltage connection 260 can have various shapes including a plurality of holes H2.

[0124] The size of the plurality of holes H2 in the high-potential voltage interconnects 260 can decrease as the area of ​​overlap between the first and second high-potential voltage interconnects 261 and 262 and the plurality of data interconnects DLL decreases. That is, the size of the holes H2 in the high-potential voltage interconnects increases from the center of the substrate 110 toward the periphery of the substrate 110. The plurality of data interconnects DLL need to transmit data signals from the data driving unit DD to the display area AA of the substrate 110. Therefore, the data interconnects DLL can have the shortest length in the central portion of the substrate 110, and the length of the data interconnects DLL can increase in the direction toward the periphery of the substrate 110. That is, the data interconnects DLL located in the central portion of the substrate 110 have a relatively shorter length than the data interconnects DLL located on the periphery of the substrate 110, thus having low resistance. The data interconnects DLL located in the periphery of the substrate 110 have a relatively longer length than the data interconnects DLL located in the central portion of the substrate 110, thus having high resistance. Therefore, the areas of the first and second high-potential voltage lines 261 and 262 that overlap with the data connection DLL located at the center of the substrate 110 need to be larger than the areas of the first and second high-potential voltage lines 261 and 262 that overlap with the data connection DLL located in the peripheral area of ​​the substrate 110, in order to reduce the deviation of the RC delay between the data connection DLL located at the center of the substrate 110 and the data connection DLL located in the peripheral area of ​​the substrate 110. Therefore, the number of holes H2 provided per unit area of ​​the first and second high-potential voltage lines 261 and 262 is equal to each other. However, the size of the plurality of holes H2 can increase in the direction from the center of the substrate to the periphery.

[0125] Reference Figures 6 to 8 The size of the plurality of holes H2 can vary depending on the regions of the first and second high-potential voltage interconnects 261 and 262. That is, the number (e.g., density) of holes H2 per unit area is constant or the same throughout the region or across the high-potential voltage interconnects, but the length of the high-potential voltage interconnect 260 is relatively long. Therefore, the size of the plurality of holes H2 disposed on the high-potential voltage interconnect 260 can increase as the area where the high-potential voltage interconnect 260 overlaps with the data interconnect DLL increases. That is, the length of the data interconnect DLL overlapping with the high-potential voltage interconnect 260 located at the center of the substrate 110 is shorter, and the length of the data interconnect DLL overlapping with the high-potential voltage interconnect 260 located at the periphery of the substrate 110 is longer. Therefore, the size of the plurality of holes H2 on the first and second high-potential voltage interconnects 261 and 262 at the periphery of the substrate 110 can be larger than the size at the center of the substrate 110.

[0126] In a display device 200 according to another embodiment of the present invention, multiple holes H2 are provided differently for respective areas on the first high-potential voltage connection 261 and the second high-potential voltage connection 262 that overlap with the data connection DLL. Therefore, the deviation in RC delay between the multiple data connection DLLs can be reduced. When multiple holes H2 are provided on the high-potential voltage connection 260, the area of ​​overlap between the high-potential voltage connection 260 and the data connection DLL is reduced, thereby reducing the parasitic capacitance applied to the data connection DLL. When the parasitic capacitance applied to the data connection DLL decreases, the resistance of the data connection DLL remains the same, but the data load decreases. Therefore, the RC delay of the data connection is reduced, which is beneficial for ensuring operating time even in the case of products with high resolution and high-speed operation.

[0127] Furthermore, in the display device 200 according to another embodiment of the present invention, the size of the plurality of holes H2 can be increased proportionally to the area where the data interconnect DLL and the high-potential voltage interconnect 260 overlap. This is to minimize the overlapping area of ​​the data interconnect DLL and the high-potential voltage interconnect 260 by increasing the size of the plurality of holes H2, since parasitic capacitance increases with the increase of the overlapping area of ​​the data interconnect DLL and the high-potential voltage interconnect 260. Among the plurality of data interconnect DLLs, the data interconnect DLL disposed in the central portion of the substrate 110 can have a relatively short length, thereby having low resistance. The overlapping area between the data interconnect DLL disposed in the central portion of the substrate 110 and the high-potential voltage interconnect 260 can be small. Conversely, among the plurality of data interconnect DLLs, the data interconnect DLL disposed in the peripheral area of ​​the substrate 110 can have a relatively long length, thereby having high resistance. The overlapping area between the data interconnect DLL disposed in the peripheral area of ​​the substrate 110 and the high-potential voltage interconnect 260 can be large. Therefore, the size of the plurality of holes H2 disposed on the first high-potential voltage connection 261 and the second high-potential voltage connection 262 can be increased in the direction from the center portion of the substrate 110 to the peripheral region, thereby the parasitic capacitance applied to the data connection DLL located in the peripheral region of the substrate 110 is lower than the parasitic capacitance applied to the data connection DLL located in the center portion of the substrate 110. Therefore, in the display device 200 according to another embodiment of the present invention, the size of the plurality of holes H2 is changed according to the area of ​​overlap between the data connection DLL and the high-potential voltage connection 260. Therefore, the deviation of RC delay between the plurality of data connection DLLs can be minimized, and the image quality can be improved.

[0128] Exemplary embodiments of the present invention can also be described as follows:

[0129] According to one aspect of the present invention, a display device is provided. The display device includes a substrate, the substrate including a display area and a non-display area configured to surround the display area; a plurality of pixels disposed in the display area; a data driving unit disposed in the non-display area; a plurality of data lines disposed in the display area; a plurality of data interconnects disposed in the non-display area and configured to connect the data driving unit and the plurality of data lines; and a plurality of high-potential voltage interconnects disposed in the non-display area and configured to provide a high-potential voltage to the plurality of pixels, wherein the high-potential voltage interconnects include a plurality of holes disposed in the region where the high-potential voltage interconnects overlap with the plurality of data interconnects.

[0130] The high-potential voltage connection can be configured as a mesh pattern.

[0131] The non-display area may include: a first non-display area in which the data driving unit is disposed; a second non-display area disposed between the first non-display area and the display area; and a curved area disposed between the first non-display area and the second non-display area.

[0132] The high-potential voltage connection may include: a first high-potential voltage connection, which is disposed in the first non-display area and configured to overlap with the plurality of data connections; a second high-potential voltage connection, which is disposed in the second non-display area and configured to overlap with the plurality of data connections; and a plurality of third high-potential voltage connections, which are disposed in the bending area and configured to connect the first high-potential voltage connection and the second high-potential voltage connection.

[0133] The plurality of holes can be disposed on the first high-potential voltage connection line and the second high-potential voltage connection line.

[0134] The proportion of the area where the plurality of holes are provided can decrease as the area of ​​the overlap between the first high-potential voltage connection and the second high-potential voltage connection and the plurality of data connections decreases.

[0135] The number of holes per unit area can be reduced as the area of ​​overlap between the first high-potential voltage connection and the second high-potential voltage connection and the plurality of data connections decreases.

[0136] The size of the plurality of holes can be reduced as the area of ​​overlap between the first high-potential voltage connection and the second high-potential voltage connection and the plurality of data connections decreases.

[0137] The proportion of the regions where the plurality of holes are provided on the first high-potential voltage connection and the second high-potential voltage connection can increase in the direction from the center of the substrate to the periphery.

[0138] The substrate may have a deformable corner area, the display area may have a shape corresponding to the deformable corner area, and the second high-potential voltage connection in the deformable corner area may have a shape corresponding to the shape of the display area and the shape of the substrate.

[0139] Each of the corners of the substrate and the corners of the display area may have a rounded shape.

[0140] The width of the second high-potential voltage connection in the deformed corner region may be smaller than the width of the second high-potential voltage connection in the central region.

[0141] Although exemplary embodiments of the present invention have been described in detail with reference to the accompanying drawings, the present invention is not limited thereto, and can be implemented in many different forms without departing from the technical concept of the present invention. Therefore, the exemplary embodiments of the present invention are provided for illustrative purposes only and are not intended to limit the technical concept of the present invention. The scope of the technical concept of the present invention is not limited thereto. Therefore, it should be understood that the above exemplary embodiments are merely illustrative in all respects and do not limit the present invention. The scope of protection of the present invention should be interpreted based on the appended claims, and all technical concepts within the equivalent scope should be interpreted as falling within the scope of the present invention.

Claims

1. A display device, comprising: A substrate, the substrate including a display area and a non-display area at least partially surrounding the display area; Multiple pixels in the display area; The data driving unit in the non-display area; Multiple data lines in the display area; Multiple data lines, located in the non-display area, electrically connect the data driving unit and the multiple data lines together; and Multiple high-potential voltage lines are provided, located in the non-display area and configured to provide high-potential voltages to the multiple pixels. The high-potential voltage connection includes multiple holes, which are located in the area where the high-potential voltage connection overlaps with multiple data connections in the non-display area. The proportion of the area with the plurality of holes per unit area of ​​the high-potential voltage interconnect increases from the center of the substrate toward the periphery.

2. The display device according to claim 1, wherein the high-potential voltage interconnect includes a mesh pattern.

3. The display device according to claim 1, wherein the non-display area comprises: The data driving unit is located in the first non-display area; A second non-display area between the first non-display area and the display area; as well as In the curved area between the first non-display area and the second non-display area The high-potential voltage connection includes: The first high-potential voltage connection is located in the first non-display area and overlaps with the first portion of multiple data connections in the first non-display area. The second high-potential voltage connection is located in the second non-display area and overlaps with the second portion of multiple data connections in the second non-display area; as well as Multiple third high-potential voltage lines are connected within the bending region and electrically connect the first high-potential voltage lines and the second high-potential voltage lines. The plurality of holes are located in the first high-potential voltage connection and the second high-potential voltage connection.

4. The display device according to claim 3, wherein the proportion of the area where the plurality of holes are provided for each unit area of ​​the high-potential voltage interconnect decreases as the area of ​​the first high-potential voltage interconnect and the second high-potential voltage interconnect overlapping with the plurality of data interconnects decreases.

5. The display device according to claim 4, wherein the number of holes per unit area among the plurality of holes decreases as the area of ​​overlap between the first high-potential voltage connection and the second high-potential voltage connection and the plurality of data connections decreases.

6. The display device according to claim 3, wherein the size of the plurality of holes decreases as the area of ​​the overlap between the first high-potential voltage connection and the second high-potential voltage connection and the plurality of data connections decreases.

7. The display device according to claim 3, wherein the substrate has a corner region, the display region has a shape corresponding to the corner region, and the second high-potential voltage connection in the corner region has a shape corresponding to the shape of the display region and the shape of the substrate.

8. The display device according to claim 7, wherein the corners of the substrate have a rounded shape, and the corners of the display area have a rounded shape.

9. The display device according to claim 7, wherein the width of the second high-potential voltage connection in the corner area is smaller than the width of the second high-potential voltage connection in the center area.

10. The display device according to claim 3, wherein the plurality of data lines extend from the first non-display area toward the display area.

11. The display device according to claim 1, wherein the length of the plurality of data lines increases in the direction from the central portion of the substrate to the peripheral region of the substrate.

12. The display device according to claim 1, wherein the plurality of data lines are located on a different layer than the high-potential voltage lines.

13. The display device according to claim 3, wherein the first area of ​​the first high-potential voltage line and the second high-potential voltage line overlapping with the data lines disposed at the center portion of the substrate is greater than the second area of ​​the first high-potential voltage line and the second high-potential voltage line overlapping with the data lines disposed in the peripheral area of ​​the substrate.

14. The display device according to claim 3, wherein the plurality of holes are arranged differently in different regions of the first high-potential voltage connection and the second high-potential voltage connection that overlap with the plurality of data connections.

15. The display device of claim 3, wherein the number of holes in the first high-potential voltage connection and the second high-potential voltage connection increases in the direction from the central portion of the substrate to the peripheral region of the substrate.

16. The display device of claim 6, wherein the number of holes per unit area in the first high-potential voltage connection and the second high-potential voltage connection is constant.

17. The display device of claim 3, wherein the size of the aperture in the first high-potential voltage connection and the second high-potential voltage connection increases in the direction from the central portion of the substrate to the peripheral region of the substrate.

18. A display device, comprising: A substrate, the substrate including a display area and a non-display area at least partially surrounding the display area; Multiple pixels in the display area; The data driving unit in the non-display area; Multiple data lines in the display area; Multiple data lines, located in the non-display area, electrically connect the data driving unit and the multiple data lines together; and Multiple high-potential voltage lines are provided, located in the non-display area and configured to provide high-potential voltages to the multiple pixels. In the non-corner area of ​​the substrate, as the length of the multiple data interconnects increases from the center to the periphery of the substrate, the area of ​​the high-potential voltage interconnects overlapping with the multiple data interconnects in the non-display area decreases from the center of the substrate towards the periphery. The high-potential voltage connection includes multiple holes in the area where the high-potential voltage connection overlaps with the multiple data connections.

19. The display device of claim 18, wherein the density of the plurality of holes in the high-potential voltage line increases from the center of the substrate toward the periphery of the substrate.

20. The display device according to claim 19, wherein the plurality of holes have the same size.

21. The display device of claim 18, wherein the size of the plurality of holes in the high-potential voltage line increases from the center of the substrate toward the periphery of the substrate.

22. The display device of claim 21, wherein the density of the plurality of holes in the high-potential voltage connection is the same across the high-potential voltage connection.

23. A display device, comprising: A substrate, the substrate including a display area and a non-display area at least partially surrounding the display area; Multiple pixels in the display area; The data driving unit in the non-display area; Multiple data lines in the display area; Multiple data lines, located in the non-display area, electrically connect the data driving unit and the multiple data lines together. The multiple data lines include a first data line and a second data line longer than the first data line; and Multiple high-potential voltage lines are provided, located in the non-display area and configured to provide high-potential voltages to the multiple pixels. Specifically, in the non-corner region of the substrate, the area of ​​the first portion of the high-potential voltage connection that overlaps with the first data connection is greater than the area of ​​the second portion of the high-potential voltage connection that overlaps with the second data connection that is longer than the first data connection. The first part of the high-potential voltage connection includes a plurality of first holes, and the second part of the high-potential voltage connection includes a plurality of second holes.

24. The display device according to claim 23, wherein the density of the plurality of first holes in the first portion of the high-potential voltage connection is less than the density of the plurality of second holes in the second portion of the high-potential voltage connection.

25. The display device of claim 23, wherein the size of the plurality of first holes in the first portion of the high-potential voltage connection is smaller than the size of the plurality of second holes in the second portion of the high-potential voltage connection.

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