System and method for stabilizing a modem while waiting for ap-driven link recovery

Abstract

Various embodiments of methods and systems for bootstrapping a modem-directed application processor (111) in a portable computing device (“PCD”) (102) are disclosed. An exemplary method includes an application processor (111) that transitions to an idle state, such as a WFI state, during a duration of the boot sequence, which occurs concurrently with processing performed by a DMA engine (114) and / or an encryption engine. That is, the application processor (111) can “sleep” while the DMA engine (114) and / or the encryption engine processes a workload in response to instructions received from the application processor (111).

Description

Background Technology

[0001] Portable computing devices (“PCDs”) are becoming necessities for people both personally and professionally. These devices may include cellular phones, portable digital assistants (“PDAs”), portable game consoles, PDAs, and other portable electronic devices.

[0002] PCD typically includes an application processor (“AP”), which is included in a complex system known as a mobile chipset or system-on-a-chip (“SoC”). The AP is usually the overall manager of the functions performed by the SoC, and therefore, the AP often acts as the “master” processor, directing the activities of other “slave” processors that are dedicated to performing specific functions. For example, the modem processor of the SoC is often designated as a slave processor of the AP.

[0003] On many SoCs, modems operate according to the Peripheral Component Interconnect Fast (“PCIe”) protocol. The PCIe protocol not only specifies what a modem should do, but also when it is permitted to do so. As understood by those skilled in the art, the PCIe protocol is a low-level standard for SoC components and is used by endpoint components, such as modems, to communicate with the host processor, such as an AP, via a high-data-rate PCIe bus.

[0004] In contrast, APs typically operate according to the Modem Host Interface (“MHI”) protocol, which sits “above” the PCIe standard. That is, the MHI protocol is a host protocol that defines the actions of the AP, including its entry and exit from sleep states (i.e., its modes) and the transitions between endpoint sleep states. The PCIe root complex runs on the host AP and is used by the AP to manage the PCIe channel links available to endpoint components, packet processing between modules, and so on. In this way, endpoint components such as modems rely on the AP to tell them when to use the PCIe channel links for data packet transfer (“DMA”) and when to enter a low-power sleep state.

[0005] As understood by those skilled in the art, according to the PCIe protocol, the establishment of a PCIe channel link between the master AP and the slave modem is triggered by an action of the AP, which transitions the AP to a sleep state or exits a sleep state (such as D3 hot or D3 cold). Unless the AP performs a state transition, the PCIe protocol does not allow the modem to establish a communication link with the AP. Therefore, if a backflow of downlink data packets is queued for processing by the modem, and the master AP does not take any action to transition from its own MHI state, the modem will not be allowed to establish a PCIe communication link with the AP to handle the workload. The modem remains in its own low-power state. Consequently, the backflow of unprocessed data packets may overwhelm the limited amount of memory available to the modem, leading to unintended modem failure.

[0006] Therefore, there is a need in the art for methods and systems to address the aforementioned situations and prevent modem crashes. More specifically, what is needed in the art is a system and method for stabilizing an endpoint modem while it awaits the reconstruction of an AP-driven PCIe link. Summary of the Invention

[0007] Various embodiments of methods and systems for stabilizing a modem in a SoC of a portable computing device (“PCD”) while waiting for an application processor (“AP”) to rebuild a PCIe communication link are disclosed. An exemplary method includes determining that the AP is in a sleep state. The AP and modem are operable to communicate over a PCIe channel, but it is determined that there is no active link available over the PCIe channel. Data packets are identified in a workload queue that are available for the modem to process. The modem determines the available queue capacity in a memory component associated with the modem, and if the available queue capacity is sufficient to store the data packets, it stores the data packets in the available queue capacity for later processing; however, if the available queue capacity is insufficient to store the data packets, the data packets are discarded from the workload queue. After discarding the data packets from the workload queue, the SoC can transition to a low-power state.

[0008] An exemplary method may also include monitoring a PCIe link recovery timer, such that even if the available queue capacity is sufficient to store data packets, if the timer has exceeded a predefined threshold, the data packets are dropped from the workload queue, or if the timer has not exceeded the predefined threshold, the data packets are stored in the available queue capacity for later processing. Additionally, if the available queue capacity is insufficient to store data packets, the exemplary method may drive one of a WAKE# signal (as defined in the PCIe specification) or a GPIO toggle from the modem to the AP before dropping the data packets from the workload queue. However, if the wake-up signal (i.e., WAKE#) or the GPIO toggle causes the link to be rebuilt over the PCIe channel, the modem may transition to an active processing state to handle the data packets. In the absence of a PCIe link being rebuilt, the method may drive multiple WAKE# signals or multiple GPIO toggles from the modem to the AP before dropping the data packets from the workload queue.

[0009] Additionally, if the available queue capacity is sufficient to store data packets and the timer has exceeded a predefined threshold, the method can drive either the WAKE# signal or a GPIO switch from the modem to the AP before discarding data packets from the workload queue. Furthermore, if the WAKE# signal or GPIO switch results in the link being re-established over the PCIe channel, the method can switch the modem to an active processing state and process the data packets. Attached Figure Description

[0010] In the accompanying drawings, unless otherwise specified, the same reference numerals refer to the same parts in the various views. For reference numerals with letter character names (such as "102A" or "102B"), the letter character names can distinguish two similar parts or elements in the same figure. When the reference numerals cover all parts with the same reference numerals in all figures, the letter character names of the reference numerals may be omitted.

[0011] Figure 1 This is a functional block diagram of an exemplary non-limiting aspect of a PCD in the form of a wireless telephone, which is used for a method and system for achieving modem stabilization while waiting for the recovery of an AP-driven PCIe link;

[0012] Figure 2 This is a functional block diagram illustrating an embodiment of an on-chip system performing a method for stabilizing a modem while waiting for the PCIe link to be rebuilt or restored by an AP driver;

[0013] Figure 3 It demonstrates that it can be made by Figure 2The diagram shows a functional block diagram of exemplary PCIe interfaces at relative levels within the protocol stack used by the AP and MDM of the system-on-a-chip.

[0014] Figure 4 It's a diagram. Figure 3 A functional block diagram of the functional gap in the protocol stack;

[0015] Figure 5 It is illustrated in Figure 4 Functional block diagram of the modem host interface (“MHI”) deployed within the functional gap shown.

[0016] Figure 6 This is an MHI power state machine diagram that identifies a state scenario in which an embodiment of a solution for stabilizing the modem while waiting for the PCIe link driven by the AP to recover can be adopted.

[0017] Figure 7 This is a flowchart illustrating a first exemplary method for stabilizing a modem in a SoC while waiting for the PCIe communication link driven by an AP to be rebuilt;

[0018] Figure 8 This is a flowchart illustrating a second exemplary method for stabilizing a modem in a SoC while waiting for the reconstruction of a PCIe communication link driven by an AP;

[0019] Figure 9 This is a flowchart illustrating a third exemplary method for stabilizing a modem in a SoC while waiting for the reconstruction of a PCIe communication link driven by an AP; and

[0020] Figure 10 This is a flowchart illustrating a fourth exemplary method for stabilizing a modem in a SoC while waiting for the reconstruction of a PCIe communication link driven by an AP. Detailed Implementation

[0021] The word “exemplary” is used in this document to mean “serving as an example, instance, or illustration.” Any aspect described as “exemplary” in this document is not necessarily to be construed as exclusive, preferred, or advantageous over other aspects.

[0022] In this specification, the term "application" may also include files with executable content, such as object code, scripts, bytecode, markup language files, and patches. Additionally, "application" as used herein may also include files that are not inherently executable, such as documents that may need to be opened or other data files that require access.

[0023] As used herein, the terms “component,” “database,” “module,” “system,” “processing component,” “processing engine,” “modem,” “application processor,” etc., are intended to refer to computer-related entities, hardware, firmware, combinations of hardware and software, or software, software in execution, and represent exemplary means for providing functionality and performing certain steps of the processes or process flows described herein. For example, a component can be, but is not limited to, a process, processor, object, executable file, execution thread, program, and / or computer running on a processor. For example, an application running on a computing device and the computing device itself can be components. One or more components may reside within an execution process and / or thread, and components may be located on a single computer and / or distributed across two or more computers. Additionally, these components may be executable from various computer-readable media on which various data structures are stored. Components can communicate via local and / or remote processes, such as according to signals having one or more data packets (e.g., data from a component interacting with a local system, another component in a distributed system, and / or interacting with other systems via a network such as the Internet).

[0024] In this specification, the terms “central processing unit ('CPU'),” “digital signal processor ('DSP'),” “application processor ('AP'),” “chip,” and “chipset” are non-limiting examples of processing components that may reside in a PCD, and are used interchangeably unless otherwise stated. Furthermore, as described in this specification, a CPU, DSP, AP, or chip or chipset may consist of one or more different processing components commonly referred to herein as “(one or more) cores.”

[0025] In this specification, references to "external memory device," etc., refer to a broader range of non-volatile (i.e., data that is retained after power loss) programmable memories and do not limit the scope of the disclosed solutions. Therefore, it should be understood that the use of the term contemplates any programmable read-only memory or field-programmable non-volatile memory suitable for a given application of the solution, such as, but not limited to, embedded multimedia card ("eMMC") memory, EEPROM, flash memory, etc.

[0026] In this specification, the term "portable computing device" ("PCD") is used to describe any device that operates on a limited-capacity power source, such as a battery. While battery-powered PCDs have been in use for decades, advancements in rechargeable battery technology, coupled with the emergence of third-generation ("3G"), fourth-generation ("4G"), and fifth-generation ("5G") wireless technologies, have enabled many PCDs to have multiple functions. Therefore, a PCD can be a cellular phone, satellite phone, pager, PDA, smartphone, navigation device, tablet computer, smartbook or e-reader, media player, a combination of the above devices, a laptop computer with wireless connectivity, etc.

[0027] In this specification, the term "DMA engine" refers to the Direct Memory Access component of a SoC, which allows certain hardware or subsystems (such as, for example, modems) to access system and / or peripheral memory independently of the central processing unit or application processor.

[0028] In this specification, the term "GPIO" refers to a general-purpose input / output communication or signal and / or a physical connection within a SoC designated for handling GPIO communication. GPIO connections are a common pin type on integrated circuits without a specified function. While most pins on a SoC have dedicated purposes, such as sending signals to a component, the functionality of GPIO pins is customizable and can be controlled by software. In some cases, embodiments of this solution may utilize GPIO connections to enable communication between a slave modem and a master AP in certain scenarios.

[0029] For ease of describing exemplary embodiments of the solution, the description refers to the low-power states "D3hot" and "D3cold" as sub-states of the D3 power state. However, embodiments of the solution are applicable to scenarios that include other low-power states, such as, but not limited to, D1 and / or D2 low-power states. D0 is understood in the art to be an active processing state.

[0030] As those skilled in the art recognize, a processor can transition between various power states in response to workload demands, heat generation / dissipation levels, and power consumption targets. D3 is generally understood in the art as the lowest power device low-power state. The D3 state is typically divided into two distinct sub-states, D3hot and D3cold. If the processor is in the D3 state and the system is in the active S0 system power state, the processor is in the D3hot sub-state. In D3hot, the processor is connected to power (but the processor can be configured to draw low current), and the presence of the processor on the PCIe bus can be detected. Conversely, if the processor is in the D3 state and the system is in a low-power state (a state other than S0), the processor can be in the D3cold sub-state. In the D3cold sub-state, the processor may receive trickle current, but the processor and system are effectively shut down until a wake-up event occurs.

[0031] The processor can directly transition from the D0 state to D3hot. As understood in the art, the transition from D0 to D3hot is performed under the software control of the driver. The modem in D3hot can be detected on its connected PCIe bus. When the modem is in the D3hot sub-state, the bus must remain in the D0 state. From D3hot, the modem can return to D0 or enter D3cold. D3cold can only be entered from D3hot.

[0032] In D3cold, a modem can be physically connected to the PCIe bus, but its presence on the bus cannot be detected (i.e., until the modem is turned on again). In D3cold, the PCIe bus to which the modem is connected is in a low-power state, and / or the modem is in a low-power state, so the modem cannot respond when the PCIe bus driver attempts to detect its presence.

[0033] A modem transition from D3hot to D3cold can occur without driver interaction. Conversely, the driver can indicate whether it is ready for a D3cold transition before initiating a transition from D0 to D3hot. Subsequently, a transition from D3hot to D3cold may or may not occur, depending on whether all conditions are suitable for the transition.

[0034] When a modem enters D3cold, the AP may cause a power outage (i.e., the modem PMIC). Switching to D3cold requires only inputting D0. There is no direct switch from D3cold to D3hot. In the D3cold substate, the processor may be able to trigger a wake-up signal to wake the sleeping AP.

[0035] In this specification, the term PCIe refers to Peripheral Component Interconnect Fast. PCIe is a serial I / O interconnect between on-board components, such as between a master application processor (“AP”) and an endpoint slave modem (“MDM”). PCIe connections are typically used for memory-mapped transactions and interrupts. A PCIe bus is multi-channel, with each channel having a pair of connections (one for incoming communication traffic and one for outgoing communication traffic). Note that PCIe is also an interface standard or protocol used to connect high-speed components via PCIe interconnect. Therefore, the use of the term “PCIe” in this specification can refer to both the physical interconnect between the master AP and the slave modem and the protocol used for controlling the interconnect.

[0036] In this specification, the term "MHI" refers to the Modem Host Interface. MHI is a protocol commonly used by host processors (such as APs) to control and communicate with modem devices via a high-speed peripheral bus or shared memory (such as PCIe). While MHI can be easily adapted to any peripheral bus, it is primarily used with PCIe-based devices. MHI provides logical channels over the physical bus and allows modem protocols, such as IP data packets, modem control messages, and diagnostics, to be transmitted through at least one of these logical channels. Furthermore, the MHI protocol provides data acknowledgment features and manages the power status of the modem via one or more logical channels.

[0037] In this specification, the term "root complex" refers to the component that connects a modem and its memory subsystem to a PCIe switch architecture consisting of one or more switching devices. The root complex is implemented by the AP.

[0038] In certain application scenarios, when the application processor (“AP”) is “stuck” in its own low-power state, the modem processor (“MDM”) may be unable to exit the D3cold state and, while waiting for the D3hot / cold state, may be unable to exit the M3 to process incoming data packets. As mentioned above, the PCIe protocol prevents the MDM from transitioning out of the D3cold state unless or until the AP transitions out of its own inactive state. In this situation, the MDM may be at risk of crashing and adversely affect the user experience. A review of the following figures and related detailed description will make it clearer that new methods can be employed to stabilize the modem and avoid such crashes without violating the MHI / PCIe protocol hierarchy.

[0039] Now from Figure 1 start, Figure 1A functional block diagram illustrating an exemplary, non-limiting aspect of a PCD in the form of a wireless telephone is shown, illustrating a method and system for achieving modem stabilization while awaiting the recovery of an AP-driven PCIe link. As shown, PCD 100 includes a system-on-a-chip 102, which includes a heterogeneous multi-core central processing unit (“CPU”) 110 and an analog signal processor 126 coupled together. As understood by those skilled in the art, CPU 110 may include a zeroth core 222, a first core 224, and an Nth core 230. Furthermore, as understood by those skilled in the art, a digital signal processor (“DSP”) may also be used instead of CPU 110. Moreover, as understood in the field of heterogeneous multi-core processors, each of cores 222, 224, and 230 can handle workloads at different maximum voltage frequencies, exhibit different static power current (“IDDq”) leakage rates at a given temperature and operating state, and have different delays in transitioning from a given idle operating state to an active state, etc. CPU 110 communicates with multiple operational sensors (e.g., temperature sensor 157) and components distributed in the system-on-a-chip 102 of PCD 100, such as modem 101.

[0040] Typically, modem 101 may be responsible for monitoring paging and / or other downlink data requests requiring action, and processing these requests in conjunction with application processor (“AP”) 111 and its DRAM 112B via a PCIe communication link. AP 111 may be a heterogeneous multi-core processor. In some embodiments, AP 111 may receive GPIO signals from modem 101.

[0041] like Figure 1 As shown, display controller 128 and touchscreen controller 130 are coupled to CPU 110. A touchscreen display 132 external to the system-on-chip 102 is coupled to display controller 128 and touchscreen controller 130. PCD 100 may also include video decoder 134, such as a Phase Alternating Line (“PAL”) decoder, Sequential Coulomb Memory (“SECAM”) decoder, National Television System Committee (“NTSC”) decoder, or any other type of video decoder 134. Video decoder 134 is coupled to multi-core central processing unit (“CPU”) 110. Video amplifier 136 is coupled to video decoder 134 and touchscreen display 132. Video port 138 is coupled to video amplifier 136. Figure 1As shown, a Universal Serial Bus (“USB”) controller 140 is coupled to a CPU 110. Additionally, a USB port 142 is coupled to the USB controller 140. Memory 112 (on-chip DRAM 112B associated with AP 111 and off-chip flash memory and / or DRAM 112A associated with MDM 101) and a Subscriber Identity Module (SIM) card 146 can also be coupled to the CPU 110 and / or AP 111. Furthermore, as... Figure 1 As shown, digital camera 148 can be coupled to CPU 110. In one exemplary aspect, digital camera 148 is a charge-coupled device (“CCD”) camera or a complementary metal-oxide-semiconductor (“CMOS”) camera.

[0042] like Figure 1 As further shown, the stereo audio CODEC 150 can be coupled to the analog signal processor 126. Additionally, the audio amplifier 152 can be coupled to the stereo audio CODEC 150. In an exemplary aspect, the first stereo speaker 154 and the second stereo speaker 156 are coupled to the audio amplifier 152. Figure 1 Microphone amplifier 158 is shown to also be coupled to stereo audio CODEC 150. Additionally, microphone 160 can be coupled to microphone amplifier 158. In one particular aspect, FM radio tuner 162 can be coupled to stereo audio CODEC 150. Furthermore, FM antenna 164 is coupled to FM radio tuner 162. Additionally, stereo headphones 166 can be coupled to stereo audio CODEC 150.

[0043] Figure 1 Further indications are made that the radio frequency (“RF”) transceiver 168 can be coupled to the analog signal processor 126. An RF switch 170 can be coupled to the RF transceiver 168 and the RF antenna 172. Figure 1 As shown, keyboard 174 can be coupled to analog signal processor 126. Additionally, a mono headset with microphone 176 can be coupled to analog signal processor 126. Furthermore, vibrator device 178 can be coupled to analog signal processor 126. Figure 1 A power source 188, such as a battery, is also shown coupled to the system-on-chip 102 via a power management integrated circuit (“PMIC”) 180. Multiple instances of the PMIC 180 may be dedicated to one or more given components of the SoC, such as a PMIC 180A for modem 101 and a PMIC 180 for AP 111. In one particular aspect, the power source 188 includes a rechargeable DC battery or DC power derived from an AC-DC transformer connected to an AC power source.

[0044] CPU 110 may also be coupled to one or more internal on-chip temperature sensors 157A and 157B and one or more external off-chip temperature sensors 157C. The on-chip temperature sensors 157A and 157B may include one or more sensors proportional to absolute temperature (“PTAT”) temperature, which are based on a vertical PNP structure and are typically dedicated to complementary metal-oxide-semiconductor (“CMOS”) very large-scale integration (“VLSI”) circuits. The off-chip thermal sensor 157C may include one or more thermistors. The temperature sensor 157 may generate a voltage drop, which is converted into a digital signal using an analog-to-digital converter (“ADC”) controller 103. However, other types of temperature sensors 157 may be used without departing from the scope of the invention.

[0045] In addition to being controlled and monitored by the ADC controller 103, the temperature sensor 157 can also be controlled and monitored by one or more modems 101 and / or (one or more) monitoring modules. The modem 101 and / or (one or more) monitoring modules may include software executed by the CPU 110. However, without departing from the scope of the invention, the modem 101 and / or (one or more) monitoring modules may also be formed by hardware and / or firmware.

[0046] return Figure 1 The touchscreen display 132, video port 138, USB port 142, camera 148, first stereo speaker 154, second stereo speaker 156, microphone 160, FM antenna 164, stereo headphones 166, RF switch 170, RF antenna 172, keyboard 174, mono headphone 176, vibrator 178, thermal sensor 157C, PMIC 180, Flash 112A, power supply 188, and ADC controller 103 are located external to the system-on-a-chip 102. However, it should be understood that the modem 101 and AP 111 can also receive one or more indications or signals from one or more of these external devices via analog signal processor 126 and CPU 110 to aid in real-time management of operable resources on PCD 100.

[0047] In one particular aspect, one or more method steps described herein can be implemented using executable instructions and parameters stored in memory 112. Processors 110, 111, 126, modem 101, and DMA engine ( Figure 1 (Not shown in the text), memory controller and associated memory 112, instructions or combinations thereof stored therein can be used as means to perform one or more method steps described herein.

[0048] Figure 2 This is a functional block diagram illustrating an embodiment of an on-chip system that performs a method for stabilizing a modem while waiting for a PCIe link driven by an AP to be rebuilt or restored. Figure 2 As shown, modem 101 communicates with multi-core application processor 111. The AP 111 shown includes four cores 271A, 271B, 271C, and 271D; however, it should be understood that AP 111 is not limited to any specific number of cores 271. Each core may have an associated temperature sensor 157, which monitors the heat generated by the corresponding core and triggers MHI state changes to manage heat generation, power consumption, etc.

[0049] Modem 101 can communicate with a flash / DRAM controller and its associated DMA engine. The controller controls and manages access to data images stored in external memory, such as flash / NAND memory or MDM DRAM 112A. As will be understood by those skilled in the art, modem 101 may also include internal memory registers. Furthermore, as will be understood by those skilled in the art, AP 111 can also communicate with DRAM memory 112B via and by means of a DRAM controller. DRAM 112B may contain execution images, as will be understood by those skilled in the art. System-on-chip 102 may include clock component 217.

[0050] Modem 101 can communicate with AP 111 via PCIe bus 211 and according to the PCIe protocol. According to an embodiment, modem 101 can also send control signals to and receive control signals from AP 111 via GPIO connection 213. As will be understood by those skilled in the art, modem 101 can receive data requests and process them by working with AP 111 and AP DRAM 112B via PCIe link 211. The local memory of the MDM may be quite limited in size and capacity, making it unable to queue incoming data requests. As will be better understood from the following figures and their related description, Figure 2 The SoC system 102 shown can be configured and operable to perform a method for stabilizing modem 101 when modem 101 is unable to process incoming data requests due to unavailability or delayed reconstruction of the AP-driven PCIe link.

[0051] Figure 3 It shows that it can be made by Figure 2A functional block diagram 300 of an exemplary PCIe interface 211 at a relative level within the protocol stack used by AP 111 and MDM 101 of the System-on-Chip 102 shown is illustrated. As previously described, AP 111 can load a boot image from its AP RAM 112B and transfer it to MDM modem 101, which can then store it in its device memory for execution. The boot image transfer between AP 111 and modem 101 can be performed between a USB host (at AP 111) and a USB device, providing a low-level transfer mechanism over which higher-level software can use the device's upper-layer protocol to implement the boot image transfer. A Controller Interface (HCI) layer within the AP stack for the Universal Serial Bus (USB) interface is also shown. The modem's upper-layer protocol can control the transmission of messages and packets over the logical channel.

[0052] PCIe devices with CPUs, such as modem 101, require executable software images, which can be stored in a boot ROM chip or a persistent file storage mechanism (e.g., NAND / NOR flash 112A). Both of these alternatives can be inefficient in terms of cost and time. An alternative is to have the device driver on AP 111's memory map the device RAM and copy the software image directly into the device RAM. This method requires the application processor and may result in suboptimal AP CPU throughput.

[0053] Figure 3 The relative hierarchy of the PCIe interface 211 within the protocol stack is also described. As those skilled in the art will understand, PCIe does not provide all the low-level support offered by USB. USB supports the transmission of message and data packets over serial links and endpoints. However, one advantage of PCIe is that it can provide faster throughput than USB and can scale as the system architecture expands. Therefore, in some cases, it may be desirable to implement the PCIe interface 211 between the host processor 111 and the MDM 101 while avoiding the need for a USB interface.

[0054] Figure 4 It's a diagram. Figure 3 Functional block diagram 400 of the functional gap in the protocol stack. Figure 4The illustration depicts a computing device such as System-on-a-Chip 102, which uses PCIe interface 211 as a memory-mapped communication path between a host processor such as AP 111 and modem 101. As shown, there is a functional gap between the low-level PCIe interface 211 and the upper-layer protocol. For example, without significant involvement from the core of AP 111, the standard PCIe interface 211 may not provide sufficient support for data transfer from AP 111 to modem 101.

[0055] Figure 5 It is illustrated in Figure 4 The diagram shows a functional block diagram 500 of a modem host interface (“MHI”) deployed within the functional gap. Typically, the modem host interface provides logical channels via memory-mapped communication paths such as PCIe links. These logical channels enable the transmission of upper-layer cellular modem communication protocols (e.g., 2G, 3G, 4G, 5G, and LTE protocols) from modem 101 to host AP 111. Furthermore, commands can be issued between host AP 111 and cellular modem (MDM) 101, and power status can also be communicated and managed via one or more logical channels. Additionally, the modem host interface functions to offload the task of downloading software executable images to a PCIe device, such as modem 101. Modem 101 can implement software image downloading using data buffers allocated in RAM 112 via hardware acceleration mechanisms (e.g., enhanced direct memory access (DMA) engine 114). That is, shared memory space can be used to transfer boot images between host AP 111 and MDM modem 101.

[0056] The communication link (e.g., PCIe 211) device driver enumerates MDM 101 and allocates a direct memory access data buffer in AP RAM 112B. As will be understood by those skilled in the art, the location (address) of the DMA buffer list can be transferred to modem 101 via a memory-mapped configuration register. Furthermore, a doorbell located in the application logic of modem 101 can be utilized by host AP 111 to trigger modem 101 to process a new transaction (see reference 112). Figure 6 (The illustration returns to that specific operational scenario). Upon completion, modem 101 triggers an interrupt (e.g., a PCIe interrupt) toward host AP 111 for further processing.

[0057] In operation, upon reset / power-on, modem 101 executes its primary bootloader (PBL) from the hardware boot ROM (small read-only on-chip memory). The PBL then downloads executable code from APRAM 112B to MDM RAM 112A via a memory-mapped communication path 211 (e.g., PCIe) using a hardware-accelerated DMA mechanism that uses a data buffer programmed in the configuration register by AP 111. DMA engine 114 relays read / write completion information back to AP 111 via events / interrupts. DMA buffer reclamation can be handled by host AP 111 upon receiving a read / write completion event. Once the MDM 101 executable image has been downloaded to MDM RAM 112A and verified, the MDM boot ROM code jumps to that image and begins execution of the main MDM bootloader from RAM. Similarly, for RAM dumps, MDM 101 uses a similar hardware-accelerated mechanism to upload RAM dump regions from MDM RAM 112A to host AP RAM 112B. In one exemplary implementation, the modem host protocol (flash-free booting on high-speed inter-chip HSIC) can be implemented using the proposed hardware acceleration mechanism as the transmission medium. In the case where the MDM 101 is implemented by a modem chip, the application logic can be a modem subsystem or a packet processing component.

[0058] Figure 6 This is the MHI power state machine diagram 600 for state scenario 610, in which an embodiment of a solution for stabilizing the modem while waiting for the PCIe link driven by the AP to recover can be adopted. Simply return to the reference. Figure 5As described, a doorbell within the application logic of modem 101 can be used by host AP 111 to trigger modem 101 to process a new transaction. Upon completion, modem 101 triggers a PCIe interrupt toward host AP 111 for further processing. However, it is worth noting that a problem may arise in state scenario 610 when host AP 111 is unavailable to change its state and provide a PCIe link to modem 101 to process a new transaction. In such a scenario, while modem 101 waits on AP 111 to rebuild the PCIe link, modem 101 may be "stuck" in the D3cold state and unable to transition back to the operating state shown in 610. Simultaneously, data packets associated with the new transaction may continue to queue in the limited memory associated with modem 101 (as required by the PCIe protocol, modem 101 will not process transactions without being triggered by AP 111). This overflow of data packets may cause unintended crashes of modem 101, resulting in a poor user experience. Advantageously, embodiments of this solution are designed to address this situation within state scenario 610 without violating the PCIe protocol.

[0059] Figure 7 This is a flowchart illustrating a first exemplary method 700 for stabilizing a modem in a SoC while awaiting the re-establishment of a PCIe communication link driven by an AP. Beginning at block 705, method 700 determines that AP 111 is in an MHI sleep state. Modem 101 may also be in a sleep state, such as a D3cold state. In this case, as previously described, data packets may arrive at modem 101 for processing; however, modem 101 may not be available for processing unless and until AP 111 transitions out of its current state and establishes (or more likely re-establishes) a PCIe communication link with modem 101. With the PCIe communication link 211 established, modem 101 can transition from state D3 to state D0 according to the PCIe protocol to handle workloads.

[0060] Method 700 continues to decision box 710. At decision box 710, method 700 can determine whether a downlink data packet has arrived at modem 101 for processing. If no downlink data packet has arrived, the "No" branch can be followed to box 725, and the system safely transitions to X0 sleep mode (system "disconnected"). From here, method 700 returns. However, if it is determined at decision box 710 that a downlink data packet has arrived at modem 101 for processing, the "Yes" branch can be followed to the subsequent decision box 715.

[0061] At decision box 715, method 700 determines whether there is modem-dependent memory capacity available to store data packets. If available capacity exists, the "yes" branch proceeds to box 720, and data packets are queued for future processing when PCIe link 211 is re-established. Method 700 returns, and modem 101 continues to wait for AP 111 to establish a communication link. However, if decision box 715 determines that there is insufficient modem-dependent memory capacity to store incoming data packets, the "no" branch proceeds to box 730, and data packets are discarded before the system is switched to X0 at box 725. In this way, method 700 prevents data overflow into modem-dependent memory when modem 101 is unavailable to process workloads due to the lack of an available PCIe link. Advantageously, modem 101 crashes can be avoided.

[0062] Figure 8 This is a flowchart illustrating a second exemplary method 800 for stabilizing a modem in a SoC while awaiting the re-establishment of a PCIe communication link driven by an AP. Beginning at block 805, method 800 determines that AP 111 is in an MHI sleep state. Modem 101 may also be in a sleep state, such as a D3cold state. In this case, as previously described, data packets may arrive at modem 101 for processing; however, modem 101 may not be available for processing unless and until AP 111 transitions out of its current state and establishes (or more likely re-establishes) a PCIe communication link with modem 101. With the PCIe communication link 211 established, modem 101 can transition from state D3 to state D0 to process workloads according to the PCIe protocol.

[0063] Method 800 continues to decision box 810. At decision box 810, method 800 can determine whether a downlink data packet has arrived at modem 101 for processing. If no downlink data packet has arrived, the "No" branch can be followed to box 825, and the system safely transitions to X0 sleep mode (system "shutdown"). From here, method 800 returns. However, if it is determined at decision box 810 that a downlink data packet has arrived at modem 101 for processing, the "Yes" branch can be followed to the subsequent decision box 815.

[0064] At decision box 815, method 800 determines whether there is modem-associated memory capacity available to store data packets. If, at decision box 815, it is determined that there is insufficient modem-associated memory capacity to store incoming data packets, the "No" branch is followed to box 830 and the data packets are discarded before the system transitions to X0 at box 825. If available capacity exists at decision box 815, the "Yes" branch is followed to decision box 817, and method 800 determines whether the link recovery threshold timer 217 has expired. If the timer has expired, the "Yes" branch is followed to box 830, and the packets are discarded before the system transitions to X0 at box 825, even if pending queue capacity in the modem-associated memory is available. However, if the timer has not expired, method 800 follows the "No" branch from decision box 817 to box 820. At box 820, when PCIe link 211 is rebuilt, data packets are queued for future processing. Method 800 returns and modem 101 continues to wait for AP 111 to establish a communication link. In this way, when modem 101 is unavailable for processing workloads due to the lack of a usable PCIe link, method 800 avoids data overflow into the modem-related memory. Furthermore, advantageously, it prevents modem 101 from crashing.

[0065] Figure 9 This is a flowchart illustrating a third exemplary method 900 for stabilizing a modem in a SoC while awaiting the re-establishment of a PCIe communication link driven by an AP. Beginning at block 905, method 900 determines that AP 111 is in an MHI sleep state. Modem 101 may also be in a sleep state, such as a D3cold state. In this case, as previously described, data packets may arrive at modem 101 for processing; however, modem 101 may not be available for processing unless and until AP 111 transitions out of its current state and establishes (or more likely re-establishes) a PCIe communication link with modem 101. With the PCIe communication link 211 established, modem 101 can transition from state D3 to state D0 to handle workloads according to the PCIe protocol.

[0066] Method 900 continues to decision box 910. At decision box 910, method 900 can determine whether a downlink data packet has arrived at modem 101 for processing. If no downlink data packet has arrived, the "No" branch can be followed to box 925, and the system safely transitions to X0 sleep mode (system "shutdown"). From here, method 900 returns. However, if it is determined at decision box 910 that a downlink data packet has arrived at modem 101 for processing, the "Yes" branch can be followed to the subsequent decision box 915.

[0067] At decision box 915, method 900 determines whether there is modem-dependent memory capacity available to store data packets. If, at decision box 915, it is determined that there is insufficient modem-dependent memory capacity to store incoming data packets, the "No" branch is followed to box 935, and a wake-up interrupt is driven to AP 111. Next, at decision box 940, it is determined whether the PCIe communication link has been rebuilt. If the link has not been rebuilt, the "No" branch is followed to box 945, and a threshold counter for the maximum number of wake-up attempts (WAKE# signal) to establish connection to AP 111 is consulted. If the wake-up threshold counter indicates that the maximum allowed number of wake-up attempts has not yet been reached, the "No" branch is followed and returns from decision box 945 to box 935, where the next WAKE# is driven to AP 111. Method 900 may continue to cycle through boxes 935, 940, and 945 in this manner until the PCIe link is restored or the wake-up threshold is reached.

[0068] If the wake-up threshold is reached at decision box 945, the "Yes" branch is followed, proceeding to box 930, and the data packet is discarded before the system transitions to X0 at box 925. Alternatively, if the PCIe link is rebuilt by AP 111 in response to a WAKE# signal driven to AP 111, the "Yes" branch is followed, proceeding from decision box 940 to box 950, where modem 101 transitions to task mode D0 for processing workloads. With modem 101 in task mode, method 900 can proceed to box 955 to retrieve data packets for processing.

[0069] Returning to decision box 915, if there is available pending queue capacity in the modem-related memory, method 900 can follow the "Yes" branch to reach decision box 917. At decision box 917, method 900 determines whether the link recovery threshold timer 217 has expired. If the timer has expired, it follows the "Yes" branch to reach box 935, and WAKE# is driven to AP 111, and method 900 proceeds from box 935 as previously described. However, if the timer has not expired, method 900 can follow the "No" branch to reach box 920 from decision box 917. At box 920, when PCIe link 211 is re-established, data packets are queued for future processing. Method 900 returns, and modem 101 continues to wait for AP 111 to establish a communication link. In these modes, method 900 avoids data overflow into the modem-related memory when modem 101 is unavailable to process workloads due to the lack of an available PCIe link. Furthermore, this can help prevent the modem 101 from crashing.

[0070] Figure 10 This is a flowchart illustrating a fourth exemplary method 1000 for stabilizing a modem in a SoC while awaiting the re-establishment of a PCIe communication link driven by an AP. Beginning at block 1005, method 1000 may determine that AP 111 is in an MHI sleep state. Modem 101 may also be in a sleep state, such as a D3cold state. In this case, as previously described, data packets may arrive at modem 101 for processing; however, modem 101 may not be available for processing unless and until AP 111 transitions out of its current state and establishes (or more likely re-establishes) a PCIe communication link with modem 101. With the PCIe communication link 211 established, modem 101 can transition from state D3 to state D0 to handle workloads according to the PCIe protocol.

[0071] Method 1000 continues to decision box 1010. At decision box 1010, method 1000 can determine whether a downlink data packet has arrived at modem 101 for processing. If no downlink data packet has arrived, the "No" branch can be followed to reach box 1025, and the system safely transitions to X0 sleep mode (system "shutdown"). From here, method 1000 returns. However, if it is determined at decision box 1010 that a downlink data packet has arrived at modem 101 for processing, the "Yes" branch can be followed to reach subsequent decision box 1015.

[0072] At decision box 1015, method 1000 determines whether there is modem-related memory capacity available to store data packets. If, at decision box 1015, it is determined that there is insufficient modem-related memory capacity to store incoming data packets, the "No" branch is followed to box 1036 and a GPIO switch is driven to AP 111. Next, at decision box 1040, it is determined whether the PCIe communication link has been rebuilt. If the link has not been rebuilt, the "No" branch is followed to decision box 1045, and a threshold counter for the maximum number of GPIO switch attempts to establish a connection to AP 111 is consulted. If the switch threshold counter indicates that the maximum allowed number of GPIO switch attempts has not yet been reached, the "No" branch is followed and returns from decision box 1045 to box 1036, where the next GPIO switch is driven to AP 111. Method 1000 may continue to cycle through boxes 1036, 1040, and 1045 in this manner until the PCIe link is restored or the switch threshold is reached.

[0073] If the GPIO switching threshold is reached at decision box 1045, the "Yes" branch is followed, proceeding to box 1030, and the data packet is discarded before the system transitions to X0 at box 1025. Alternatively, if the PCIe link is rebuilt by AP 111 in response to a GPIO switch driven to AP 111, the "Yes" branch is followed, proceeding from decision box 1040 to box 1050, where modem 101 transitions to task mode D0 for handling workloads. With modem 101 in task mode, method 1000 can move to box 1055 to retrieve data packets for processing.

[0074] Returning to decision box 1015, if there is available pending queue capacity in the modem-related memory, method 1000 can follow the "Yes" branch to reach decision box 1017. At decision box 1017, method 1000 determines whether the link recovery threshold timer 217 has expired. If the timer has expired, the "Yes" branch is followed to reach box 1036, and a GPIO switch is driven to AP 111, as previously described, and method 1000 continues from box 1036. However, if the timer has not expired, method 1000 can follow the "No" branch to reach box 1020 from decision box 1017. At box 1020, when PCIe link 211 is rebuilt, data packets are queued for future processing. Method 1000 returns, and modem 101 continues to wait for AP 111 to establish a communication link. In these ways, method 1000 avoids data overflow into the modem-related memory when modem 101 is unavailable to process workloads due to the lack of an available PCIe link. Furthermore, this can help prevent the modem 101 from crashing.

[0075] Some steps in the process or process flow described in this specification naturally precede other steps in order for the invention to function as described. However, the invention is not limited to the order of the steps if such an order or sequence does not alter the function of the invention. That is, some steps may be performed before, after, or in parallel (substantially simultaneously) with other steps without departing from the scope and spirit of the invention. In some cases, certain steps may be omitted or not performed without departing from the invention. Furthermore, words such as "then," "furthermore," and "next step" are not intended to limit the order of steps. These words are only used to guide the reader through the description of the exemplary method.

[0076] Additionally, those skilled in the art of programming can easily write computer code or identify suitable hardware and / or circuitry to implement the disclosed invention based on, for example, the flowcharts and related descriptions in this specification. Therefore, it is not necessary to disclose a specific set of program code instructions or detailed hardware devices for a full understanding of how to make and use the invention. The inventive function of the claimed computer implementation process has been explained in more detail in the foregoing description and in conjunction with the accompanying drawings, which may illustrate various process flows.

[0077] In one or more exemplary aspects, the described functionality can be implemented using hardware, software, firmware, or any combination thereof. If implemented in software, the functionality can be stored on a computer-readable medium or transmitted as one or more instructions or code. Computer-readable media include computer storage media and communication media, with communication media including any medium that facilitates the transfer of a computer program from one place to another. Storage media can be any available medium that is accessible to a computer. By way of example and not limitation, such computer-readable media can include random access memory (“RAM”), read-only memory (“ROM”), EEPROM, CD-ROM or other optical disc storage devices, magnetic disk storage devices or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that is accessible to a computer.

[0078] Furthermore, any connection is properly referred to as a computer-readable medium. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (“DSL”), or wireless technologies such as infrared, radio, and microwave, then coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium.

[0079] The terms "disk" and "optical disk" as used herein include optical discs ("CDs"), laser discs, optical discs, digital versatile optical discs ("DVDs"), floppy disks, and Blu-ray discs, wherein disks typically reproduce data magnetically, while optical discs reproduce data optically using lasers. Combinations of the above should also be included within the scope of computer-readable media.

[0080] Examples of implementation methods are described in the following numbered clauses:

[0081] 1. A method for stabilizing a modem in a SoC of a portable computing device (“PCD”) while waiting for an application processor (“AP”) to rebuild a PCIe communication link, the method comprising:

[0082] The AP is determined to be in a sleep state, wherein the AP and the modem are operable to communicate via the PCIe channel;

[0083] It was determined that there were no active links available over the PCIe channel;

[0084] Identify data packets in the workload queue that are available for modem processing; and

[0085] Determine the available queue capacity in the memory component associated with the modem, where:

[0086] If the available queue capacity is sufficient to store the data packet, then store the data packet in the available queue capacity for later processing; and

[0087] If the available queue capacity is insufficient to store the data packets, the data packets are discarded from the workload queue.

[0088] 2. The method for stabilizing a modem as described in Clause 1 further includes switching the SoC to a low-power state after dropping data packets from the workload queue.

[0089] 3. The method for stabilizing a modem as described in Clause 1 further includes:

[0090] Monitor the PCIe link recovery timer, where the available queue capacity is sufficient to store data packets:

[0091] If the timer has exceeded a predefined threshold, data packets are discarded from the workload queue; and

[0092] If the timer does not exceed the predefined threshold, the data packets are stored in the available queue capacity for later processing.

[0093] 4. The method for stabilizing a modem according to Clause 1 further includes:

[0094] If the available queue capacity is insufficient to store data packets, one of the WAKE# signal and GPIO switching is driven from the modem to the AP before dropping data packets from the workload queue. If the WAKE# signal or GPIO switching causes the link to be rebuilt over the PCIe channel, the modem is switched to active processing state and processes the data packets.

[0095] 5. The method for stabilizing a modem as described in Clause 4 further includes: switching multiple WAKE# signals or multiple GPIOs from the modem driver to the AP before discarding data packets from the workload queue.

[0096] 6. The method for stabilizing a modem as described in Clause 3 further includes:

[0097] If the available queue capacity is sufficient to store data packets and the timer has exceeded a predefined threshold, then either the WAKE# signal or a GPIO switch is driven from the modem to the AP before dropping data packets from the workload queue. If the WAKE# signal or GPIO switch results in the re-establishment of the link over the PCIe channel, the modem is switched to active processing state and processes the data packets.

[0098] 7. The method for stabilizing a modem as described in Clause 6 further includes: switching multiple WAKE# signals or multiple GPIOs from the modem driver to the AP before discarding data packets from the workload queue.

[0099] 8. The method for stabilizing a modem as described in Clause 1, wherein the PCD is in the form of a wireless mobile phone.

[0100] 9. A system for stabilizing a modem in a SoC of a portable computing device (“PCD”) while waiting for an application processor (“AP”) to rebuild a PCIe communication link, the method comprising:

[0101] A means for determining whether an AP is in a sleep state, wherein the AP and the modem are operable to communicate via a PCIe channel;

[0102] A means for determining that no active link is available over a PCIe channel;

[0103] A means for identifying data packets available for modem processing in a workload queue; and

[0104] A means for determining the available queue capacity in a memory component associated with a modem, wherein:

[0105] If the available queue capacity is sufficient to store the data packets, then means for storing the data packets in the available queue capacity for later processing; and

[0106] A means for discarding data packets from the workload queue if the available queue capacity is insufficient to store the data packets.

[0107] 10. The system for stabilizing a modem as described in Clause 9 further includes means for transitioning the SoC to a low-power state after dropping data packets from the workload queue.

[0108] 11. The system for stabilizing a modem as described in Clause 9 further includes:

[0109] A device for monitoring PCIe link recovery timers, wherein if the available queue capacity is sufficient to store data packets:

[0110] If the timer has exceeded a predefined threshold, data packets are discarded from the workload queue; and

[0111] If the timer does not exceed the predefined threshold, the data packets are stored in the available queue capacity for later processing.

[0112] 12. The system for stabilizing a modem as described in Clause 9 further includes:

[0113] If the available queue capacity is insufficient to store data packets, means for driving one of the WAKE# signal and GPIO switching from the modem to the AP before discarding data packets from the workload queue, wherein if the WAKE# signal or GPIO switching results in the re-establishment of the link on the PCIe channel, means for switching the modem to an active processing state and processing data packets.

[0114] 13. The system for stabilizing a modem as described in Clause 12 further includes means for switching multiple WAKE# signals or multiple GPIOs from the modem to the AP before discarding data packets from the workload queue.

[0115] 14. The system for stabilizing a modem as described in Clause 11 further includes:

[0116] If the available queue capacity is sufficient to store data packets and the timer has exceeded a predefined threshold, then means for driving one of the WAKE# signal or GPIO switching from the modem to the AP before discarding data packets from the workload queue, wherein if the WAKE# signal or GPIO switching results in the re-establishment of the link over the PCIe channel, means for switching the modem to an active processing state and processing data packets.

[0117] 15. The system for stabilizing a modem as described in Clause 14 further includes means for switching multiple WAKE# signals or multiple GPIOs from the modem to the AP before discarding data packets from the workload queue.

[0118] 16. The system for stabilizing a modem as described in Clause 9, wherein the PCD is in the form of a wireless mobile phone.

[0119] 17. A system for stabilizing a modem in a SoC of a portable computing device (“PCD”) while waiting for an application processor (“AP”) to rebuild a PCIe communication link, the system comprising:

[0120] The modem and access point are connected via PCIe channel communication. The modem is configured as follows:

[0121] Confirm that the AP is in a sleep state;

[0122] It was determined that there were no active links available over the PCIe channel;

[0123] Identify data packets in the workload queue that are available for modem processing; and

[0124] Determine the available queue capacity in the memory component associated with the modem, where:

[0125] If the available queue capacity is sufficient to store the data packet, then store the data packet in the available queue capacity for later processing; and

[0126] If the available queue capacity is insufficient to store the data packets, the data packets are discarded from the workload queue.

[0127] 18. The system for stabilizing a modem as described in Clause 17, wherein the modem is further configured to transition the SoC to a low-power state after dropping data packets from the workload queue.

[0128] 19. A system for stabilizing a modem as described in Clause 17, wherein the modem is further configured to:

[0129] Monitor the PCIe link recovery timer, where the available queue capacity is sufficient to store data packets:

[0130] If the timer has exceeded a predefined threshold, data packets are discarded from the workload queue; and

[0131] If the timer does not exceed the predefined threshold, the data packets are stored in the available queue capacity for later processing.

[0132] 20. A system for stabilizing a modem as described in Clause 17, wherein the modem is further configured to:

[0133] If the available queue capacity is insufficient to store data packets, one of the WAKE# signal and GPIO switching is driven to the AP before dropping data packets from the workload queue. If the WAKE# signal or GPIO switching causes the link to be rebuilt over the PCIe channel, the process transitions to active processing state and processes the data packets.

[0134] 21. A system for stabilizing a modem as described in Clause 20, wherein the modem is further configured to drive multiple WAKE# signals or multiple GPIO switches to the AP before dropping data packets from the workload queue.

[0135] 22. The system for stabilizing a modem as described in Clause 19, wherein the modem is further configured to:

[0136] If the available queue capacity is sufficient to store data packets and the timer has exceeded a predefined threshold, then either the WAKE# signal or a GPIO switch is driven to the AP before dropping data packets from the workload queue. If the WAKE# signal or GPIO switch causes the link to be rebuilt on the PCIe channel, then the process transitions to active processing state and processes the data packets.

[0137] 23. The system for stabilizing a modem as described in Clause 22, wherein the modem is further configured to drive multiple WAKE# signals or multiple GPIO switches to the AP before dropping data packets from the workload queue.

[0138] 24. A computer program product comprising a computer-usable medium embodying computer-readable program code adapted to perform a method of implementing a stable modem in a portable computing device (“PCD”) SoC while waiting for an application processor (“AP”) to rebuild a PCIe communication link, the method comprising:

[0139] The AP is determined to be in a sleep state, wherein the AP and the modem are operable to communicate via the PCIe channel;

[0140] It was determined that there were no active links available over the PCIe channel;

[0141] Identify data packets in the workload queue that are available for modem processing; and

[0142] Determine the available queue capacity in the memory component associated with the modem, where:

[0143] If the available queue capacity is sufficient to store the data packet, then store the data packet in the available queue capacity for later processing; and

[0144] If the available queue capacity is insufficient to store the data packets, the data packets are discarded from the workload queue.

[0145] 25. The computer program product as described in Clause 24 further includes switching the SoC to a low-power state after discarding data packets from the workload queue.

[0146] 26. The computer program product described in Clause 24 further includes:

[0147] Monitor the PCIe link recovery timer, where the available queue capacity is sufficient to store data packets:

[0148] If the timer has exceeded a predefined threshold, data packets are discarded from the workload queue; and

[0149] If the timer does not exceed the predefined threshold, the data packets are stored in the available queue capacity for later processing.

[0150] 27. The computer program product pursuant to Clause 24 further includes:

[0151] If the available queue capacity is insufficient to store data packets, one of the WAKE# signal and GPIO switching is driven from the modem to the AP before dropping data packets from the workload queue. If the WAKE# signal or GPIO switching causes the link to be rebuilt over the PCIe channel, the modem is switched to active processing state and processes the data packets.

[0152] 28. The computer program product as described in Clause 27 further includes switching multiple WAKE# signals or multiple GPIOs from the modem driver to the AP before discarding data packets from the workload queue.

[0153] 29. The computer program product pursuant to Clause 26 further includes:

[0154] If the available queue capacity is sufficient to store data packets and the timer has exceeded a predefined threshold, then either the WAKE# signal or a GPIO switch is driven from the modem to the AP before dropping data packets from the workload queue. If the WAKE# signal or GPIO switch results in the re-establishment of the link over the PCIe channel, then the modem is switched to active processing state and processes the data packets.

[0155] 30. The computer program product as described in Clause 29 further includes switching multiple WAKE# signals or multiple GPIOs from the modem driver to the AP before discarding data packets from the workload queue.

[0156] Therefore, although selected aspects have been illustrated and described in detail, it should be understood that various substitutions and modifications may be made without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. A method for stabilizing a modem, the method comprising: The application processor (AP) is determined to be in a sleep state, wherein the AP and the modem are operable to communicate via a peripheral component interconnect fast PCIe channel; It was determined that there were no active links available over the PCIe channel; Identify data packets in the workload queue that are available for modem processing; as well as Determine the available queue capacity in the memory component associated with the modem, wherein: If the available queue capacity is sufficient to store the data packet, then the data packet is stored in the available queue capacity for later processing; and If the available queue capacity is insufficient to store the data packet, multiple WAKE# signals or multiple GPIO switches are driven from the modem to the AP before the data packet is discarded from the workload queue. If the WAKE# signals or GPIO switches cause the link to be re-established over the PCIe channel, the modem is switched to an active processing state and the data packet is processed. If the link is not established, the data packet is discarded.

2. The method for stabilizing a modem according to claim 1, further comprising: After the data packets are discarded from the workload queue, the system-on-chip (SoC) with the AP is switched to a low-power state.

3. The method for stabilizing a modem according to claim 1, further comprising: Monitor the PCIe link recovery timer, wherein if the available queue capacity is sufficient to store the data packets: If the timer has exceeded a predefined threshold, the data packet is discarded from the workload queue; and If the timer does not exceed the predefined threshold, the data group is stored in the available queue capacity for later processing.

4. The method for stabilizing a modem according to claim 3, further comprising: If the available queue capacity is sufficient to store the data packet and the timer has exceeded the predefined threshold, then one of the WAKE# signal or GPIO switching is driven from the modem to the AP before the data packet is dropped from the workload queue. If the WAKE# signal or GPIO switching results in the link being rebuilt over the PCIe channel, the modem is switched to an active processing state and processes the data packet.

5. The method for stabilizing a modem according to claim 1, wherein the portable computing device housing the AP is in the form of a wireless mobile phone.

6. A system for stabilizing a modem for a portable computing device "PCD", the system comprising: A means for determining that an application processor (AP) is in a sleep state, wherein the AP and the modem are operable to communicate via a peripheral component interconnect fast PCIe channel; A means for determining that no active link is available over the PCIe channel; A means for identifying data packets in a workload queue that are available for processing by a modem; as well as A means for determining the available queue capacity in a memory component associated with the modem, wherein: If the available queue capacity is sufficient to store the data packet, then means for storing the data packet in the available queue capacity for later processing; as well as If the available queue capacity is insufficient to store the data packet, means for switching multiple WAKE# signals or multiple GPIOs from the modem to the AP before discarding the data packet from the workload queue, wherein if the WAKE# signal or GPIO switching causes the link to be re-established on the PCIe channel, means for switching the modem to an active processing state and processing the data packet, and if the link is not established, discarding the data packet.

7. The system for stabilizing a modem according to claim 6, further comprising means for switching the system-on-chip (SoC) containing the AP to a low-power state after discarding the data packets from the workload queue.

8. The system for stabilizing a modem according to claim 6, further comprising: A means for monitoring PCIe link recovery timers, wherein if the available queue capacity is sufficient to store the data packets: If the timer has exceeded a predefined threshold, the data packet is discarded from the workload queue; and If the timer does not exceed the predefined threshold, the data group is stored in the available queue capacity for later processing.

9. The system for stabilizing a modem according to claim 8, further comprising: If the available queue capacity is sufficient to store the data packet and the timer has exceeded the predefined threshold, then means for driving one of the WAKE# signal or GPIO switching from the modem to the AP before discarding the data packet from the workload queue, wherein if the WAKE# signal or GPIO switching results in the re-establishment of the link over the PCIe channel, means for switching the modem to an active processing state and processing the data packet.

10. The system for stabilizing a modem according to claim 6, wherein the PCD is in the form of a wireless mobile phone.

11. A system for stabilizing a modem for a portable computing device "PCD", comprising: The modem and application processor (AP) are interconnected via peripheral components for high-speed PCIe channel communication, and the modem is configured to: It is determined that the AP is in a sleep state; It was determined that there were no active links available over the PCIe channel; Identify data packets in the workload queue that are available for modem processing; as well as Determine the available queue capacity in the memory component associated with the modem, where: If the available queue capacity is sufficient to store the data packet, then the data packet is stored in the available queue capacity for later processing; and If the available queue capacity is insufficient to store the data packet, multiple WAKE# signals or multiple GPIO switches are driven to the AP before the data packet is discarded from the workload queue. If the WAKE# signal or GPIO switch causes the link to be re-established over the PCIe channel, the AP switches to an active processing state and processes the data packet. If the link is not established, the data packet is discarded.

12. The system for stabilizing a modem according to claim 11, wherein the modem is further configured to: switch the system-on-chip (SoC) containing the AP to a low-power state after discarding the data packets from the workload queue.

13. The system for stabilizing a modem according to claim 11, wherein the modem is further configured to: Monitor the PCIe link recovery timer, wherein if the available queue capacity is sufficient to store the data packets: If the timer has exceeded a predefined threshold, the data packet is discarded from the workload queue; and If the timer does not exceed the predefined threshold, the data group is stored in the available queue capacity for later processing.

14. The system for stabilizing a modem according to claim 13, wherein the modem is further configured to: If the available queue capacity is sufficient to store the data packet and the timer has exceeded the predefined threshold, then either a WAKE# signal or a GPIO switch is driven to the AP before the data packet is dropped from the workload queue. If the WAKE# signal or GPIO switch results in the link being rebuilt on the PCIe channel, then the process transitions to an active processing state and the data packet is processed.

15. A computer program product comprising a computer-usable medium embodying computer-readable program code adapted to be executed to implement a method for stabilizing a modem, the method comprising: The application processor (AP) is determined to be in a sleep state, wherein the AP and the modem are operable to communicate via a peripheral component interconnect fast PCIe channel; It was determined that there were no active links available over the PCIe channel; The workload queue is identified as containing data packets available for processing by the modem. as well as Determine the available queue capacity in the memory component associated with the modem, wherein: If the available queue capacity is sufficient to store the data packet, then the data packet is stored in the available queue capacity for later processing; and If the available queue capacity is insufficient to store the data packet, multiple WAKE# signals or multiple GPIO switches are driven from the modem to the AP before the data packet is discarded from the workload queue. If the WAKE# signals or GPIO switches cause the link to be re-established over the PCIe channel, the modem is switched to an active processing state and the data packet is processed. If the link is not established, the data packet is discarded.

16. The computer program product of claim 15, further comprising switching the system-on-chip (SoC) containing the AP to a low-power state after discarding the data packet from the workload queue.

17. The computer program product according to claim 15, further comprising: Monitor the PCIe link recovery timer, wherein if the available queue capacity is sufficient to store the data packets: If the timer has exceeded a predefined threshold, the data packet is discarded from the workload queue; and If the timer does not exceed the predefined threshold, the data group is stored in the available queue capacity for later processing.

18. The computer program product according to claim 17, further comprising: If the available queue capacity is sufficient to store the data packet and the timer has exceeded the predefined threshold, then one of the WAKE# signal or the GPIO switch is driven from the modem to the AP before the data packet is dropped from the workload queue. If the WAKE# signal or the GPIO switch results in the link being rebuilt over the PCIe channel, then the modem is switched to an active processing state and the data packet is processed.

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