Subscriber station for a serial bus system and method of communication in a serial bus system

Abstract

A subscriber station (10; 30) for a serial bus system (1) and a method for communicating in a serial bus system (1) are provided. The subscriber station (10; 30) has a communication control device (11; 31) for controlling the communication of the subscriber station (10; 20; 30) with at least one further subscriber station (10; 20; 30) of the bus system (1) and for generating a transmission signal (TXD) such that for messages (45) exchanged between subscriber stations (10, 20, 30) of the bus system (1) a bit time (t_bt1) of the signal transmitted onto the bus (40) in a first communication phase (451) is distinguishable from a bit time (t_bt2) of the signal transmitted in a second communication phase (452); wherein the communication control device (11; 31) is configured to generate the transmission signal (TxD) in accordance with a frame (450) and to insert a field (DAS) with an edge into the frame (450) after the second communication phase (452); wherein the field (DAS) has a predetermined length before the edge corresponding to a duration (T_RB) which is longer than a duration of the bit time (t_bt1) of the first communication phase (451); and wherein a communication control device (21; 31; 11) of at least one further subscriber station (10; 20; 30) of the bus system (1) is provided with an edge for synchronizing to the communication on the bus (40), a transmission / reception device (22; 32; 12) of the at least one further subscriber station (10; 20; 30) switching into an operating mode (B_451) for transmitting and receiving the frame (450) in the first communication phase (451) before the predetermined duration (T_RB).

Description

Technical Field

[0001] The invention relates to a subscriber station for a serial bus system and a method for communication in a serial bus system, which operates at a high data rate and with great flexibility and error robustness. Background Art

[0002] Depending on the number of technical installations or vehicle functions, bus systems used for communication between sensors and control units (e.g., in a vehicle) must be able to transmit large amounts of data. This often requires that data be transmitted from sender to receiver faster than before, and that large data packets be transmitted if necessary.

[0003] Bus systems in vehicles are currently in the introduction phase, in which data is transmitted as messages in the ISO 11898-1:2015 standard, which specifies the CAN protocol with CAN FD. These messages are transmitted between bus users of the bus system, such as sensors, control units, and transmitters. Messages are sent on the bus in frames, which switch between two communication phases. In the first communication phase (arbitration), the bus system negotiates which user station is allowed to send its frame on the bus in the subsequent second communication phase (data phase, or sending useful data). CAN FD is initially used in vehicles by most manufacturers with an arbitration bit rate of 500 kbit / s and a data bit rate of 2 Mbit / s. Consequently, transmission on the bus involves switching back and forth between slow and fast operating modes.

[0004] To enable even higher data rates in the second communication phase, a successor bus system to CAN FD is currently being developed. This successor bus system, called CAN XL, is currently being standardized by the CAN in Automation (CiA) organization. In addition to pure data transmission via the CAN bus, CAN XL is also intended to support additional features such as functional safety, data security, and quality of service (QoS). These are essential features required in autonomous vehicles.

[0005] When data is transmitted in frames via a channel (CAN bus), errors can occur. Bits can be manipulated, in particular due to external influences, especially radiation. The CAN XL communication protocol must detect and respond to errors.

[0006] In CAN XL, errors can be handled either with or without error signaling. With error signaling, a user station that detects an error sends an error frame (error flag) to the bus to inform other user stations that an error has been detected. Without error signaling, a user station that detects an error does not send an error frame (error flag) to the bus. As a result, the sending user station (sending node) does not receive any feedback from the receiving user station (receiving node), which could potentially receive the frame incorrectly. This type of communication is also called "fire and forget," or "send and forget."

[0007] If no error frames are sent to the bus, the transmitting subscriber station (sending node) sends the complete frame onto the bus, since no error feedback occurs. If the transmitting / receiving device (transceiver) of the receiving subscriber station (receiving node) that could have incorrectly received the frame was not previously in slow mode, the receiving subscriber station (receiving node) switches the transmitting / receiving device from fast mode (FAST) back to slow mode (SLOW) and then attempts to reintegrate into the ongoing communication on the bus. These subscriber stations therefore continuously wait for a sequence of 11 recessive bits, the so-called bus idle sequence, which may only occur at the end of a frame. This sequence is also waited for by subscriber stations that have been switched back on or have been switched active again after an inactive switchover and subsequently wish to participate in communication on the bus.

[0008] It is important that all participating subscriber stations recognize the 11 recessive bits at the end of the frame simultaneously. This synchronization is necessary because all subscriber stations must be ready to send or receive a frame at the same time in the next bit (i.e., the bit following the 11 recessive bits).

[0009] To achieve this synchronization of the user stations, there is a synchronization edge in the DAS field in the CAN XL frame, to which all receiving nodes should synchronize. After this, reintegration can be synchronized.

[0010] The problem, however, is that all receiving nodes have already seen an error during the data phase. In this case, no receiving node sends a dominant ACK bit as confirmation of correct reception of the frame. Consequently, the synchronization edge in the DAS field is the last possible edge for synchronization before the bus idle sequence. This demonstrates that correct synchronization is not possible in all cases using the DAS field in the current CAN XL frame format. Summary of the Invention

[0011] The object of the present invention is therefore to provide a subscriber station for a serial bus system and a method for communicating in a serial bus system, which solve the aforementioned problems. In particular, a subscriber station for a serial bus system and a method for communicating in a serial bus system are to be provided, wherein during ongoing bus communication, after an error or after a connection, the reintegration of the receiving node can always be performed correctly, so as to achieve high error robustness of the communication even at high data rates and increased amounts of useful data per frame.

[0012] This object is achieved by a subscriber station for a serial bus system having the features of claim 1. The subscriber station comprises a communication control device for controlling communication with at least one other subscriber station of the bus system such that, for messages exchanged between the subscriber stations of the bus system, the bit time of a signal transmitted on the bus in a first communication phase can be distinguished from the bit time of a signal transmitted in a second communication phase; and the subscriber station comprises a transmit / receive device for transmitting a transmit signal on a bus of the bus system; wherein the communication control device is designed to generate a transmit signal according to a frame and to insert a field with an edge into the frame after the second communication phase, wherein the field has a predetermined length before the edge that corresponds to a duration that is longer than the duration of the bit time in the first communication phase, and wherein the edge is provided for the communication control device of at least one other subscriber station of the bus system for synchronizing with the communication on the bus, the transmit / receive device of the at least one other subscriber station being switched to an operating mode for transmitting and receiving frames in the first communication phase before the predetermined duration.

[0013] By configuring this user station so that it has a modified DAS field, it ensures that all user stations reintegrating into the bus communication are synchronized within the DAS field. This allows for safe error handling even in the event of errors due to illumination. Furthermore, fairness is ensured because all user stations (nodes) are simultaneously ready to send or receive. Furthermore, subsequent errors in communication within the bus system can be avoided.

[0014] This allows, firstly, robust communication with the CAN XL using this subscriber station.

[0015] With this subscriber station, it is therefore possible in the bus system to maintain the arbitration known from CAN in the first communication phase and nevertheless to increase the transmission rate again considerably compared to CAN or CAN FD.

[0016] If at least one CAN subscriber station and / or at least one CAN FD subscriber station is also present in the bus system, a method performed by a subscriber station can also be used, which transmits messages according to the CAN protocol and / or the CAN FD protocol.

[0017] Advantageous further embodiments of the subscriber station are described in the dependent claims.

[0018] It is possible that the field of predetermined length has at least three bits with the bit time of the first communication phase.

[0019] The edge may be a falling edge.

[0020] The communication control device may be designed to insert a bit sequence with the logical value 11 in this field before the edge.

[0021] The communication control device may be designed to insert this field as a bit sequence having the logical value 1101 .

[0022] According to one exemplary embodiment, the communication control device is designed to signal the transmitting / receiving device by means of pulse width modulation in the transmission signal that the transmitting / receiving device must switch its operating mode.

[0023] It is conceivable that the user station further has a transmit / receive device for sending a transmit signal to a bus of the bus system, wherein the transmit / receive device is designed to switch its operating mode from the operating mode of the second communication phase to a different operating mode of the first communication phase after expiration of a predetermined time period in which the transmit / receive device has not received any edge in the transmit signal.

[0024] According to one exemplary embodiment, the communication control device is designed to insert a PWM symbol with a logical value of 0 as the last symbol in the transmission signal before the start of the predetermined time duration.

[0025] According to one exemplary embodiment, the communication control device is designed to insert a PWM symbol having a logical value of 1 as the last symbol in the transmit signal before the start of a predetermined time duration.

[0026] According to one embodiment, the communication control device is designed to insert a PWM symbol with a logical value of 0 as the second-to-last symbol in the transmit signal before the start of a predetermined time duration, and to insert the following PWM symbol into the transmit signal as the last symbol in the transmit signal before the start of the predetermined time duration: the PWM symbol has a logical value of 0 but does not have a terminal edge.

[0027] The communication control device can be designed to check the signal at the terminal at which the transmitting / receiving device sends and receives signals to the communication control device as to whether the transmitting / receiving device has switched its operating mode from the operating mode of the second communication phase to a different operating mode of the first communication phase.

[0028] According to a further exemplary embodiment, the transmitting / receiving device is designed to transmit the entire frame onto the bus in an operating mode for transmitting and receiving frames in a first communication phase.

[0029] It is possible to create a message-forming frame compatible with CAN FD, wherein in a first communication phase it is negotiated which of the subscriber stations of the bus system receives at least temporarily exclusive, conflict-free access to the bus in a subsequent second communication phase.

[0030] The user station described above may be part of a bus system that further comprises a bus and at least two user stations that are interconnected via the bus so that the at least two user stations can communicate with each other serially. In this case, at least one of the at least two user stations is the user station described above.

[0031] Furthermore, the aforementioned object is achieved by a method for communication in a serial bus system according to claim 15. The method is carried out using a subscriber station of the bus system, the subscriber station having a communication control device and a transmitting / receiving device. The method comprises the steps of: controlling communication between the subscriber station and at least one other subscriber station of the bus system using the communication control device so that, for messages exchanged between the subscriber stations of the bus system, the bit time of a signal transmitted on the bus in a first communication phase can be distinguished from the bit time of a signal transmitted in a second communication phase; and transmitting a transmit signal onto the bus of the bus system using the transmitting / receiving device. The communication control device generates the transmit signal based on a frame and inserts a field with an edge into the frame after the second communication phase. The field has a predetermined length before the edge that corresponds to a duration that is longer than the duration of the bit time in the first communication phase. The communication control device of the at least one other subscriber station of the bus system is provided with an edge for synchronization with the communication on the bus, and the transmitting / receiving device of the at least one other subscriber station is switched to an operating mode for transmitting and receiving frames in the first communication phase before the predetermined duration.

[0032] This method offers the same advantages as mentioned above with respect to the user station.

[0033] Other possible embodiments of the present invention are also included in the above or below about the combination of the features or embodiments not explicitly mentioned. At this, those skilled in the art will also add individual aspects as improvements or supplements to the corresponding basic forms of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The present invention will now be described in more detail based on embodiments with reference to the accompanying drawings, in which:

[0035] Figure 1 FIG. 1 shows a simplified block circuit diagram of a bus system according to a first embodiment;

[0036] Figure 2 A diagram is shown for illustrating the structure of a message that can be sent by a subscriber station of a bus system according to a first exemplary embodiment;

[0037] Figure 3 A simplified schematic block circuit diagram of a user station of a bus system according to a first embodiment is shown;

[0038] Figure 4 1 shows the time course of the bus signals CAN-XL H and CAN-XL L in the subscriber station according to the first exemplary embodiment;

[0039] Figure 5 1 shows the time course of the differential voltage VDIFF of the bus signals CAN-XL H and CAN-XL L in the subscriber station according to the first embodiment;

[0040] Figures 6 to 8 The time course of the following signals is respectively shown: If the subscriber station according to the first exemplary embodiment is the sender of the message, the signal occurs when a frame is transmitted at the terminal of the subscriber station;

[0041] Figure 9 The differential voltage VDIFF of the bus signals CAN-XL H and CAN-XL L is shown by Figures 6 to 8 The time variation process caused by the signal;

[0042] Figure 10 The following state at the receiving terminal of the receiving node is shown in FIG. Figure 9 The differential voltage VDIFF is generated;

[0043] Figures 11 to 13 The time course of the following signals is respectively shown: If the subscriber station according to the second exemplary embodiment is the sender of the message, the signal occurs when a frame is transmitted at the terminal of the subscriber station;

[0044] Figure 14 The differential voltage VDIFF of the bus signals CAN-XL H and CAN-XL L is shown by Figures 11 to 13 The time variation process caused by the signal;

[0045] Figure 15 The following state at the receiving terminal of the receiving node is shown in FIG. Figure 14 The differential voltage VDIFF is generated;

[0046] Figures 16 to 18 The time course of the following signals is respectively shown: If the subscriber station according to the third exemplary embodiment is the sender of the message, the signal occurs when a frame is transmitted at the terminal of the subscriber station;

[0047] Figure 19 The differential voltage VDIFF of the bus signals CAN-XL H and CAN-XL L is shown by Figures 16 to 18 the time variation of the signal; and

[0048] Figure 20 The following state at the receiving terminal of the receiving node is shown in FIG. Figure 19 The differential voltage VDIFF is generated.

[0049] In the figures, identical or functionally identical elements are provided with the same reference symbols unless otherwise indicated. DETAILED DESCRIPTION

[0050] As an example, Figure 1 A bus system 1 is shown, which is designed in particular essentially for a CAN bus system, a CAN FD bus system, a CAN XL bus system, and / or their variants, as described below. The bus system 1 can be used in vehicles, in particular motor vehicles, aircraft, etc., or in hospitals, etc.

[0051] exist Figure 1 In the embodiment, the bus system 1 has a plurality of user stations 10, 20, 30, each of which is connected to a bus 40 having a first bus cable core 41 and a second bus cable core 42. The bus cable cores 41, 42 may also be referred to as CAN_H and CAN_L, or as CAN-XL_H and CAN-XL_L, and are used for electrical signal transmission after coupling in a dominant level or generating a recessive level or another level for a signal in a sending state. Via the bus 40, messages 45, 46 can be transmitted serially between the individual user stations 10, 20, 30 in the form of signals. If an error occurs in the communication on the bus 40, such as in Figure 1 As indicated by the jagged thick black arrow in FIG. 4 , an error frame 47 (Error Flag) can optionally be sent. The subscriber stations 10 , 20 , 30 are, for example, control units, sensors, display units, etc. of a motor vehicle.

[0052] As in Figure 1 As shown in FIG, the user station 10 has a communication control device 11, a transmitting / receiving device 12 and an error handling module 15. The user station 20 has a communication control device 21, a transmitting / receiving device 22 and, optionally, an error handling module 25. The user station 30 has a communication control device 31, a transmitting / receiving device 32 and an error handling module 35. The transmitting / receiving devices 12, 22, 32 of the user stations 10, 20, 30 are each directly connected to the bus 40, even if this is Figure 1 The same is true for what is not explained in the text.

[0053] The communication control devices 11 , 21 , 31 are each used to control the communication of the corresponding subscriber station 10 , 20 , 30 with at least one other subscriber station of the subscriber stations 10 , 20 , 30 connected to the bus 40 via the bus 40 .

[0054] The communication control device 11, 31 creates and reads first messages 45, which are, for example, modified CAN messages 45. In this case, the modified CAN messages 45 are established on the basis of the CAN XL format, which is described with respect to Figure 2 In more detail, and in the case of the CAN XL format, a corresponding error handling module 15, 35 is employed. Furthermore, the communication control device 11, 31 can be implemented so as to provide or receive CAN XL messages 45 or CAN FD messages 46, as required, with respect to the sending / receiving device 32. In this case, too, a corresponding error handling module 15, 35 is employed. The communication control device 11, 31 thus creates and reads first messages 45 or second messages 46, which are distinguished by their data transmission standard, namely, in this case, by CAN XL or CAN FD.

[0055] The communication control device 21 can be implemented as a conventional CAN controller as per ISO 11898-1:2015, that is to say as a Classical CAN-Controller or CAN FD Controller which tolerates CAN FD. In addition, there is optionally an error handling module 25, which has the same functionality as the error handling module 15, 35. The communication control device 21 creates and reads second messages 46, for example CAN FD messages 46. In the case of the CAN FD messages 46, a number of 0 to 64 data bytes can be included, which are also transmitted at a significantly faster data rate than in the case of classical CAN messages. In particular, the communication control device 21 is implemented as a conventional CAN FD controller.

[0056] The sending / receiving device 22 can be implemented as a conventional CAN transceiver as per ISO 11898-1:2015 or as a CAN FD transceiver. The sending / receiving device 12, 32 can be implemented so as to provide or receive, as required, messages 45 according to the CAN XL format or messages 46 according to the now CAN FD format, with respect to the associated communication control device 11, 31.

[0057] With the two subscriber stations 10, 30, the formation and subsequent transmission of messages 45 having the CAN XL format can be implemented, and such messages 45 can be received.

[0058] Figure 2 A CAN XL frame 450 is shown for the message 45, as it is provided by the communication control device 11 to the transmitting / receiving device 12 for transmission onto the bus 40. In this case, the communication control device 11 creates the frame 450 in this exemplary embodiment to be compatible with CAN FD, as also described in Figure 2 The same applies analogously to the communication control device 31 and the transmitting / receiving device 32 of the user station 30.

[0059] according to Figure 2 CAN XL frame 450 is divided into different communication phases 451 and 452 for CAN communication on bus 40, namely, an arbitration phase 451 and a data phase 452. Frame 450 includes an arbitration field 453, a control field 454 with an ADS field for switching between communication phases 451 and 452, a data field 455, a checksum field 456, and an end-of-frame field 457, which contains a DAS field for switching between communication phases 452 and 451. This is followed by an end-of-frame field, EOF.

[0060] In arbitration phase 451, using an identifier (ID) in arbitration field 453, which includes, for example, bits ID28 to ID18, a bit-by-bit negotiation is conducted between user stations 10, 20, 30 as to which user station 10, 20, 30 wishes to send message 45, 46 with the highest priority and, therefore, to receive exclusive access to bus 40 of bus system 1 for transmission in the subsequent data phase 452. In arbitration phase 451, the physical layer is used, as in CAN and CAN-FD. The physical layer corresponds to the bit transmission layer, or layer 1, of the known OSI model (Open Systems Interconnection Model 1).

[0061] During phase 451, it is important to use the known CSMA / CR method, which allows user stations 10, 20, 30 to access bus 40 simultaneously without destroying messages 45, 46 that have a higher priority. This makes it relatively easy to add further bus user stations 10, 20, 30 to bus system 1, which is very advantageous.

[0062] A consequence of the CSMA / CR method is that a so-called recessive state is necessary on bus 40, which can be rewritten by another subscriber station 10, 20, 30 using a dominant state. In the recessive state, a high-resistance condition prevails at each subscriber station 10, 20, 30, which, combined with parasitics in the bus wiring, results in longer time constants. This limits the maximum bit rate of the current CAN FD physical layer to approximately 2 megabits per second in real-world vehicle use.

[0063] In data phase 452, in addition to parts of control field 454, the useful data of CAN-XL frame or message 45, consisting of data field 455, and checksum field 456 are transmitted. This is followed by the DAS field, which is used to switch from data phase 452 back to data phase 451.

[0064] Only when subscriber station 10 as sender has won the arbitration and thus has exclusive access to bus 40 of bus system 1 for sending does the sender of message 45 begin sending the bits of data phase 452 onto bus 40 .

[0065] In general, the following deviating properties can be achieved in a bus system with CAN XL compared to CAN or CAN FD:

[0066] a) take over and, if necessary, adapt proven features that are responsible for the robustness and user-friendliness of CAN and CAN FD, in particular the frame structure with identifiers and arbitration according to the CSMA / CR method,

[0067] b) increasing the net data transmission rate, in particular increasing the net data transmission rate to about 10 megabits per second,

[0068] c) Increasing the size of the useful data per frame, in particular increasing the size of the useful data per frame to approximately 2 kbytes or any other value.

[0069] As in Figure 2 As shown in FIG, in arbitration phase 451 as the first communication phase, subscriber station 10 partially uses the format known from CAN / CAN-FD according to ISO 11898-1:2015, in particular up to and including the FDF bit. From the FDF bit onwards, subscriber station 10 uses the CAN XL format described below in the first communication phase and in the second communication phase (data phase 452).

[0070] In this embodiment, CAN XL and CAN FD are compatible. In this case, the res bit (hereinafter referred to as the XLF bit), known in CAN FD, is used to convert from the CAN FD format to the CAN XL format. Therefore, the frame formats of CAN FD and CAN XL are identical up to the res bit or the XLF bit. The receiver only recognizes the format in which frame 450 is transmitted using the res bit. CAN XL user stations (i.e., user stations 10 and 30 in this example) also support CAN FD.

[0071] Alternative to Figure 2 In the frame 450 shown in FIG, 11 identifiers ID28 to ID18 are used. A CAN XL extended frame format is optionally possible in which a 29-bit identifier is used. This is identical to the known CAN FD extended frame format from ISO 11898-1:2015, up to the FDF bit.

[0072] according to Figure 2 , from the SOF bit up to and including the FDF bit, the frame 450 is identical to the CAN FD base frame format (Base Frame Format) according to ISO 11898-1:2015. Therefore, the known structure will not be further elaborated here. Figure 2 The bits shown with bold lines on their lower lines in FIG are sent as dominant or '0' in frame 450. Figure 2 The bits shown with bold lines on their upper lines are sent as recessive or '1' in the frame 450. In the CAN XL data phase 452, symmetrical '1' and '0' levels are used instead of recessive and dominant levels.

[0073] Generally speaking, two different stuffing rules are applied when generating frame 450. Up to the FDF bit in arbitration field 453, the CAN FD dynamic bit stuffing rule applies, with inverted stuffing bits inserted consecutively after five identical bits. In the data phase 452, up to the FCP field, a fixed stuffing rule applies, with fixed stuffing bits inserted after a fixed number of bits. Alternatively, instead of inserting just one stuffing bit, two or more bits can be inserted as fixed stuffing bits.

[0074] In frame 450, the FDF bit is immediately followed by the XLF bit, which corresponds in position to the "res bit" in the CAN FD basic frame format, as previously mentioned. If the XLF bit is transmitted as 1 (i.e., recessive), it identifies frame 450 as a CAN XL frame. For CAN FD frames, communication control device 11 sets the XLF bit to 0 (i.e., dominant).

[0075] In frame 450, the XLF bit is followed by the resXL bit, which is a dominant bit for future use. For frame 450, resXL must be sent as 0 (i.e., dominant). However, if a subscriber station 10 receives the resXL bit as 1 (i.e., recessive), the receiving subscriber station 10 enters a protocol exception state (Protocol Exception State), as is implemented in a CAN FD message 46 for res=1. Alternatively, the resXL bit could be defined in the opposite way, i.e., the resXL bit must be sent as 1 (i.e., recessive). In this case, the receiving subscriber station enters a protocol exception state with a dominant resXL bit.

[0076] In frame 450, the resXL bit is followed by the ADS (Arbitration Data Switch) sequence, in which a predetermined bit sequence is encoded. This bit sequence allows for a simple and secure switch from the bit rate of arbitration phase 451 (arbitration bit rate) to the bit rate of data phase 452 (data bit rate). For example, the bit sequence of the ADS sequence includes the AL1 bit, which is transmitted as a logical 1 at least in the last part. The AL1 bit is the last bit of arbitration phase 451. Within the AL1 bit, the physical layer is switched in the transmitter / receiver devices 12, 22, 32. Therefore, during the ADS sequence, the operating mode of the transmitter / receiver devices 12, 32 is also switched. The following bits DH1, DH2, and DL1 are already transmitted at the data bit rate. Therefore, in CAN XL, bits DH1, DH2, and DL1 are the shortest bits in the data phase 452. The ADS field is used to transition from the first communication phase 451 to the second communication phase 452.

[0077] In frame 450, the sequence ADS is followed by an SDT field, which indicates the contents of data field 455. The contents of the SDT field indicate what type of information is contained in data field 455. For example, the SDT field indicates whether data field 455 contains an Internet Protocol (IP) frame, a tunneled Ethernet frame, or another frame.

[0078] Following the SDT field is the SEC field, which specifies whether the CAN safety protocol is used to secure the frame 450. The SEC field is one bit wide and, like the SDT field, must specify the function of what type of information is contained in the data field 455.

[0079] The SEC field is followed by a DLC field, in which a data length code (DLC=Data Length Code) is inserted, which indicates the number of data bytes in the data field 455 of the frame 450. The data length code (DLC) can take any value from 1 up to the maximum number of bytes or the data field length of the data field 455. If the maximum data field length is, in particular, 2048 bits, the data length code (DLC) requires 11 bits, assuming that DLC=0 means a data field length with a byte number of 1 and DLC=2047 means a data field length with a byte number of 2048. Alternatively, a data field 455 of length 0 may be allowed, as in CAN, for example. In this case, DLC=0 may, for example, encode a data field length with a byte number of 0. The maximum encodable data field length is then, for example, 11 bits (2 11 )-1=2047.

[0080] In frame 450, the DLC field is followed by an SBC bit count field (Stuff-Bit-Count). This field specifies the number of dynamic stuff bits sent in the arbitration field 453. The receiving node uses the information in the SBC bit count field to check whether it has received the correct number of dynamic stuff bits.

[0081] Following the SBC bit count field is the preamble checksum and PCRC, also known as the Preface-CRC. The preamble checksum and PCRC are checksums used to ensure the frame format of frame 450. Specifically, they are checksums of all variable bits (including all dynamic padding bits and optional fixed padding bits) from the start of the SOF bit in frame 450 to the start of the preamble checksum and PCRC. The length of the preamble checksum and PCRC, which are based on the cyclic redundancy check (CRC), and the resulting checksum polynomial, is selected based on the desired Hamming distance.

[0082] In frame 450, the preamble checksum and PCRC are followed by a VCID (Virtual CAN Bus ID) field. The VCID field has a length of 1 byte and contains the number of the virtual CAN bus.

[0083] In frame 450, the VCID field is followed by the AF field (Acceptance Field). The AF field has a length of 32 bits and contains an address or another value used for acceptance filtering.

[0084] In frame 450, the AF field is followed by a data field 455 (DataField). The data field 455 consists of P bytes B, where P is encoded in the DLC field as described above. P is a natural number greater than or equal to 1.

[0085] In frame 450, the data field 455 is followed by a checksum field 456 having a frame checksum FCRC and an FCP field. The frame checksum FCRC is composed of the bits of the frame checksum FCRC. The frame checksum FCRC and the length of the resulting CRC polynomial are selected based on the desired Hamming distance. The frame checksum FCRC secures the entire frame 450. Alternatively, only the data field 455 can be secured using the frame checksum FCRC.

[0086] In frame 450, the frame checksum (FCRC) is followed by the FCP field, where FCP = Frame Check Pattern applies. The FCP field consists of four bits, specifically the bit sequence 1100. The receiving node uses the FCP field to check whether it is bit-synchronized with the transmit data stream. Furthermore, the receiving node synchronizes to a falling edge in the FCP field.

[0087] Following the FCP field follows the end-of-frame field 457. The end-of-frame field 457 consists of two fields, namely, a DAS field and an acknowledgement field or ACK field having at least one bit ACK and a bit ACK-Dlm.

[0088] The DAS field contains the sequence DAS (Data Arbitration Switch) in which a predetermined bit sequence is encoded. Figure 2 In the DAS field, the predetermined bit sequence includes bits DAH, AH1, and AL2. Furthermore, bit AH2 is optionally provided at the end of the DAS field to maintain a distance from the acknowledgment field (ACK). The DAS field has at least three bits. The bit sequence DAH, AH1, and AL2 allows for a simple and secure switch from the data bit rate of the data phase 452 to the arbitration bit rate of the arbitration phase 451. Furthermore, during the DAS field, the operating mode of the transmitting / receiving device 12, 32 is switched, optionally from the FAST operating mode to the SLOW operating mode. For example, the bit sequence of the DAS sequence includes arbitration bits DAH and AH1, each having a logical value of 1. Within bit DAH or bit AH1, the physical layer (i.e., operating mode) of the transmitting / receiving device 12, 32 is switched from FAST_TX or FAST_RX to SLOW. Bit AH1 is followed by bit AL2 (logical 0) and bit AH2 (logical 1). These three bits DAH, AH1, AL2 have the following function: at the end of the frame, they ensure the synchronization of the user stations of the bus system. This also ensures the synchronization of those receiving nodes that have detected an error during reception.

[0089] In the frame end field 457, the sequence of DAS fields is followed by an acknowledgement field (ACK). In the acknowledgement field, a bit is set for acknowledging or not acknowledging the correct reception of the frame 450. Figure 2 In the example, an ACK bit and an ACK-dlm bit are provided. Optionally, a NACK bit and a NACK-dlm bit may additionally be present. If the receiving user station 10, 30 has correctly received the frame 450, the receiving user station 10, 30 sends the ACK bit as an explicit bit. The transmitting user station sends the ACK bit as a recessive bit. Thus, the bits originally sent to the bus 40 in the frame 450 can be rewritten by the receiving user station 10, 30. The ACK-dlm bit is sent as a recessive bit that is used to separate it from other fields. The NACK bit and the NACK-dlm bit are used so that the receiving user station can signal an incorrect reception of the frame 450 on the bus 40. The functions of these bits are the same as those of the ACK bit and the ACK-dlm bit.

[0090] In frame 450, the end-of-frame field 457 is followed by the end field (EOF = End of Frame). The bit sequence in the end field (EOF) is used to indicate the end of frame 450. The end field (EOF) is responsible for transmitting eight recessive bits at the end of frame 450. This bit sequence cannot occur within frame 450. This allows user stations 10, 20, and 30 to reliably identify the end of frame 450.

[0091] The End of Field (EOF) has a length that differs depending on whether a dominant or recessive bit was seen in the ACK bit. If the transmitting subscriber station received the ACK bit as dominant, the End of Field (EOF) has seven recessive bits. Otherwise, the End of Field (EOF) is only five recessive bits long.

[0092] In frame 450, the end field (EOF) is followed by an inter-frame space (IFS). Figure 2 This interframe space (IFS) is constructed as in CAN FD according to ISO 11898-1:2015.

[0093] Figure 3 The basic structure of the following user station 10 is shown: the user station 10 has a communication control device 11, a transmission / reception device 12 and an error handling module 15, which is part of the communication control device 11. The user station 30 is set up in a similar way, as in Figure 3 As shown in FIG, the communication control device 31 and the sending / receiving device 32 are arranged separately according to Figure 1 The error handling module 35. Therefore, the user station 30 is not described separately.

[0094] according to Figure 3In addition to a communication control unit 11 and a transceiver 12, the subscriber station 10 also includes a microcontroller 13 to which the communication control unit 11 is assigned, and a system ASIC 16 (ASIC = Application Specific Integrated Circuit). Alternatively, the system ASIC 16 may be a system basis chip (SBC) on which multiple functions required for the electronic components of the subscriber station 10 are integrated. In addition to the transceiver 12, a power supply 17 is incorporated into the system ASIC 16, which supplies the transceiver 12 with electrical energy. The power supply 17 typically supplies a voltage CAN_Supply of 5V. However, depending on requirements, the power supply 17 can also supply a different voltage with a different value. Additionally or alternatively, the power supply 17 can be designed as a current source.

[0095] The error handling module 15 has an insertion block 151, which inserts a predetermined DAS field 1511 into the frame 450, and a signaling block 152. The blocks 151, 152 will be described in more detail later.

[0096] Furthermore, the transmitting / receiving device 12 includes a transmitting module 121 and a receiving module 122. Although reference is made to the transmitting / receiving device 12 below, it is alternatively possible to provide the receiving module 122 in a separate device external to the transmitting module 121. The transmitting module 121 and the receiving module 122 can be configured similarly to conventional transmitting / receiving devices 22. The transmitting module 121 can, in particular, include at least one operational amplifier and / or transistor. The receiving module 122 can, in particular, include at least one operational amplifier and / or transistor.

[0097] Transmitter / receiver 12 is connected to a bus 40, more precisely to a first bus core 41 of bus 40 for CAN H or CAN-XL H and a second bus core 42 of bus 40 for CAN L or CAN-XL L. A power supply 17 for supplying electrical energy, in particular the supply voltage CAN-Supply, to first and second bus cores 41, 42 is provided via at least one terminal 43. Connection to ground or CAN GND is provided via terminal 44. First and second bus cores 41, 42 are terminated by a terminating resistor 49.

[0098] In the transmitting / receiving device 12, the first bus cable core 41 and the second bus cable core 42 are connected not only to the transmitting module 121, also called a transmitter, but also to the receiving module 122, also called a receiver. Figure 3 This is also not shown for simplicity.

[0099] When the bus system 1 is in operation, the transmitting module 121 converts the transmit signal TXD or TxD of the communication control device 11 into corresponding signals CAN-XL H and CAN-XL L for the bus cable cores 41 and 42 and transmits these signals CAN-XL H and CAN-XL L to the bus 40 at the terminals for CAN H and CAN L.

[0100] The receiving module 122 receives Figure 4 The signals CAN-XL H and CAN-XL L received by the bus 40 are converted into a reception signal RXD or RxD and the reception signal RXD or RxD is forwarded to the communication control device 11, as in Figure 3 Except in the idle or standby state (Idle or Standby), the transceiver 12 with the receiving module 122 always listens to the transmission of data or messages 45, 46 on the bus 40 during normal operation, more precisely, regardless of whether the transceiver 12 is the sender of the message 45.

[0101] according to Figure 4 In the example of FIG. 4 , the signals CAN-XL H and CAN-XL L have a dominant bus level 401 and a recessive bus level 402 at least in the arbitration phase 451 , as is known from CAN. Figure 5 The differential signal VDIFF = CAN-XL H - CAN-XL L is shown for the arbitration phase 451. In the arbitration phase 451, the individual bits of the signal VDIFF with the bit time t bt1 can be detected using a reception threshold Ta of, for example, 0.7 V. In the data phase 452, the bits of the signals CAN-XL H and CAN-XL L are sent faster than in the arbitration phase 451, i.e., with a shorter bit time t bt2. This is based on Figures 6 to 10 The signals CAN-XLH and CAN-XL L therefore differ from the conventional signals CANH and CANL in the data phase 452 at least in terms of their faster bit rate.

[0102] Figure 4 The order of states 401 and 402 for signals CAN-XL H and CAN-XL L in Figure 5 The resulting profile of voltage VDIFF serves only to clarify the function of subscriber station 10. The order of the data states for bus states 401, 402 can be selected as required.

[0103] In other words, if the sending module 121 switches to the first operating mode B451 (SLOW), the sending module 121 Figure 4 A first data state 402 is generated as a bus state, which has different bus levels for the two bus wires 41 , 42 of the bus line of the bus 40 , and a second data state 401 is generated as a bus state, which has the same bus level for the two bus wires 41 , 42 of the bus line of the bus 40 .

[0104] Furthermore, for the time course of the signals CAN-XL H, CAN-XL L in the second operating mode B 452TX (FAST TX) included in the data phase 452, transmit module 121 transmits these bits onto bus 40 at a higher bit rate. Furthermore, in data phase 452, the CAN-XL H and CAN-XL L signals can be generated using a different physical layer than in CAN FD. This allows the bit rate in data phase 452 to be increased even further compared to CAN FD. A subscriber station that is not the sender of frame 450 in data phase 452 sets the third operating mode B 452RX (FASTRX) in its transmit / receive device.

[0105] To signal the transition from operating mode B 451 to operating mode B 452TX (FAST TX) or operating mode B 452RX (FAST RX), communications control device 11 performs pulse width modulation (PWM) of transmit signal TxD. To this end, communications control device 11 uses one or more PWM symbols for each logical bit of CAN XL frame 450. In principle, a PWM symbol consists of two phases: phase 0 and phase 1. Furthermore, the PWM symbol is bounded by two identical edges, for example, two rising edges.

[0106] Figure 3 The error handling module 15 (in particular its insertion block 151) is configured to insert a DAS field 1511 into the frame 450 if the subscriber station 10 acts as the transmitter of the frame 450. Furthermore, the error handling module 15 (in particular its signaling block 152) can perform pulse width modulation (PWM), as will be described later for the switchover between the operating modes B 452TX (FAST TX) and B 451 (SLOW).

[0107] Figure 6The resulting digital transmit signal TxD is shown at the end of the data phase 452 of the frame 450 at time t. In the frame 450, the DAS field 1511 is inserted after the bits FCP3 to FCP0. The transmit signal TxD is transmitted serially by the communication control device 11 as the sender of the frame 450 to the transmit / receive device 12, as will be described in more detail below. Up to the bit DAH, the bits of the frame 450 have a bit duration tbt2. From the bit DAH onwards, the bits of the frame 450 have a bit duration tbt1. Figure 6 In the example of , the bit duration t b2 is shorter than the bit duration t bt1 .

[0108] Figure 7 The state resulting from the transmit signal TxD during the time t is shown, which occurs serially at the terminal TXD between the communication control device 11 and the transmitting / receiving device 12. For this purpose, the communication control device 11 (for example, the error handling module 15, in particular the signaling block 152) executes in the data phase 452 Figure 6 The transmit signal TxD is pulse width modulated (PWM). Figure 7 In the example shown in FIG4 , in the PWM symbol SB D0, the phase of 0 is longer than the phase of 1, which corresponds to a bit with a logic value of 0 in the transmission signal TxD. In contrast, in the PWM symbol SB D1, the phase of 1 is longer than the phase of 0, which corresponds to a bit with a logic value of 1. Of course, the PWM symbols SB D0 and SB D1 can be defined differently, in particular, in the opposite manner to that described above. After the data phase 452, the pulse width modulation (PWM) of the transmission signal TxD ends, as shown in FIG4 . Figure 6 In the arbitration phase 451 , no pulse width modulation (PWM) of the transmit signal TxD is performed. The switch from operating mode B 452 TX (FAST TX) or operating mode B 452 RX (FAST RX) to operating mode B 451 (SLOW) is signaled by stopping the PWM coding and thus by the absence of multiple edges.

[0109] At the end of arbitration phase 451, transceiver 12 detects based on the high frequency of edges in transmit signal TxD that it is to transition from operating mode B 451 during the arbitration phase to one of fast operating modes B 452TX (FASTTX) or B 452RX (FASTRX), or to remain in that mode. Transceiver 12 detects based on the value of the first PWM symbol or the first M symbols whether it is to transition to operating mode B 452TX (FASTTX) or operating mode B 452RX (FASTRX). M is a natural number greater than or equal to 1.

[0110] Figure 8 It shows that the sending / receiving device 12 has received Figure 7 The time variation of the state decoded signal TxD TC at the terminal TXD. Figure 8 The operating modes of the transceiver 12 are shown. In bit DAH, the transceiver 12 switches from operating mode B 452TX, in which frame 450 has bits with a bit duration t_bt2, to operating mode B 451, in which frame 450 has bits with a bit duration t_bt1. Furthermore, the bits of frame 450 can be transmitted to bus 40 in operating mode B_451 using a different physical layer than in operating mode B_452_TX (as described above). In particular, using an RC link, the transceiver 12 can detect, after a predetermined duration T_TO (TimeOut) has expired, that no edge has arrived within the predetermined time T_TO. If the transceiver 12 detects the expiration of the predetermined duration T_TO (TimeOut), it switches to operating mode B_451 (SLOW).

[0111] The transmitting / receiving device 12 will therefore Figure 7 The status at terminal TXD is decoded according to Figure 8 Each of the PWM symbols SB_D0, SB_D1 at the terminal TXD can be decoded only at the end of the PWM symbol SB_D0, SB_D1. Therefore, the decoding in the transmitting / receiving device 12 inserts a delay duration T_VZ into the signal TxD_TC to be serially transmitted on the bus 40. The delay duration T_VZ is equal to the length of the symbol length of one of the PWM symbols SB_D0, SB_D1, as shown in Figure 8 As shown in .

[0112] The sending / ending device 12 will Figure 7 The state at the terminal TXD has been decoded into the transmission / reception device 12 according to Figure 8 After the signal TxD_TC is received, the transmitting / receiving device 12 takes the signal TxD_TC as Figure 9 The differential voltage VDIFF shown in FIG is sent to bus 40 .

[0113] Figure 10The course of the signal at the RXD terminal of the transceiver 12 is shown over time t. As long as the transceiver 12 is in the operating mode B_452_TX, the transceiver 12 transmits the receive signal RxD as 1 via the RXD terminal. The duration of the transceiver 12 in the operating mode B_452_TX corresponds to the duration of the transceiver 12 in the operating mode B_452_TX. Figure 10 In operating mode B_452_TX (FAST_TX), RXD=1 applies. In operating mode B_452, transceiver 12 transmits via terminal RXD a state corresponding to the state of digital receive signal RxD generated by transceiver 12 from differential voltage VDIFF received from bus 40.

[0114] As in Figures 6 to 10 As shown in Figure 3 The error handling module 15 is therefore designed in the present exemplary embodiment such that the DAS field has two bits (DAH, AH1) with the value 1, followed by a bit (AL2) with the value 0 (dominant).

[0115] The DAH bit is a transition bit in DAS field 1151. The DAH bit is transmitted by the transmitting node or by the transmitting / receiving device 12 at least in the last part at a recessive level. The transmitting node is a subscriber station that is the transmitter of frame 450 in the ongoing data phase 452 and therefore transmits frame 450 to bus 40. It is assumed that subscriber station 10 is the transmitting node of frame 450 and subscriber station 30 is the receiving node.

[0116] In user station 10, which is the transmitting node of frame 450, communication control device 11 uses the start of the DAH bit to signal that transceiver 12 must switch its operating mode from operating mode B_452_TX (FAST_TX) to B_451 (SLOW). For example, the start of the DAH bit corresponds to up to 50% of the DAH bit. After the expiration of a predetermined time T_TO, transceiver 12 switches its operating mode from operating mode B_452_TX (FAST_TX) to B_451 (SLOW) based on the signaling in the DAH bit, as in Figure 7 and Figure 8 During the duration T_TO, according to Figure 9 The bus level (ie, the value of VDIFF) is not reliably recessive.

[0117] according to Figure 6 and Figure 7, the user station 10 (more precisely, the transmitting / receiving device 12) as the transmitting node of the frame 450 transmits the DAH bit at a recessive level in the last part. For example, this last part also corresponds to 50%. Thereafter, the user station 10 transmits the AH1 bit completely at a recessive level. Thereafter, the user station 10 transmits the AL2 bit completely at a dominant level. Thus, a recessive bus state is generated on the bus 40 within the predetermined duration T_RB. Figures 6 to 9 In the example of , the predetermined duration T_RB corresponds to a number of bits having a bit duration t_bt1 of 1.5.

[0118] Therefore, according to Figures 6 to 10 The FCP0 bit is the last bit transmitted to the transceiver 12 in a manner encoded with the aid of a PWM symbol. During the DAH bit, the communication control device 11 (in particular the error handling module 15) transmits the TxD signal as 1. Since the FCP0 bit has a logical 0 as value, a logical 0 is driven by the device 12 as a differential voltage with a value of +1V onto the bus 40. After a duration T_TO (TimeOut), which is, for example, 500 ns or another value, the transceiver 12 detects that no edge has occurred at the terminal TXD. The transceiver 12 therefore switches its operating mode to the operating mode B451 (SLOW), as shown in Figure 8 . Since 1 is present on the TxD signal, the transmitting-receiving device 12 now drives a recessive level onto the bus 40. The next AH1 bit is also driven at a recessive level onto the bus 40. Therefore, immediately before the AL2 bit, the transmitting node generates a recessive level with a duration T_RB, which is significantly longer than the arbitration bit time t_bt1.

[0119] As a result, the DAS field contains a bit sequence 110 that provides a safe synchronization edge before the transition from data phase 452 to arbitration phase 451. This ensures that immediately before the falling edge of the AL2 bit (dominant) in the DAS field, each receiving node (i.e., a subscriber station that is not the transmitter of frame 450 and therefore only the receiver of frame 450 in the ongoing data phase 452) sees a recessive level for the duration t_bt1 of at least one arbitration bit. This also applies if these bits arrive at the receiver shortened, which can occur due to bit asymmetry. Bit asymmetry is caused by non-ideal components such as transmit / receive devices 12, 22, 32 (transceivers), terminating resistors, stubs, etc. Therefore, each receiving node sees at least one recessive bit before the edge between AH1 and AL1, which is a necessary prerequisite for synchronization.

[0120] This allows for error handling in which the receiving node does not send an error frame 47. Instead, when the receiving node detects an error, it takes the following actions. If an error is detected, the receiving node (e.g., user station 30) switches its transceiver 32 to the arbitration phase 451 operating mode (SLOW operating mode), if not already in this mode. The receiving node then waits for the bus idle sequence consisting of 11 recessive bits in the arbitration phase 451, as described above. The DAS field with bit sequence 110 then prepares the required safety synchronization edge before the bus idle sequence begins.

[0121] According to a modification of this exemplary embodiment, communication control device 11 (e.g., error handling module 15, in particular, signaling block 152) does not signal transceiver 12 to switch transceiver 12 to operating mode B_452_TX (FAST_TX). Alternatively, in subscriber station 10, a transceiver, in particular transceiver 22, may be present for communication control device 11 that does not have operating modes B_452_TX (FAST_TX) or B_452_RX (FAST_RX). In both alternatives, the transmitting node transmits the DAH bit as a recessive bit because it is a logical '1'.

[0122] Even for this modification and its alternatives, it is ensured that each receiving node sees the recessive level immediately before the falling edge of the AL2 bit (dominant) in the DAS field for at least the duration t_b1 , which is the duration of the arbitration bit.

[0123] Figures 11 to 15 The time course according to the second exemplary embodiment is shown, which differs from the time course according to the second exemplary embodiment in the following respects. Figures 6 to 10 time change process.

[0124] As in Figure 12 As shown in , at least one PWM symbol is sent at the beginning of the DAH bit, and the at least one PWM symbol corresponds to a logic value of 1. Figure 12 In the example, the PWM symbol SB_D1 is transmitted. To this end, the communication control device 11 (e.g., the error handling module 15, in particular, the signaling block 152) performs a corresponding pulse width modulation (PWM) of the DAH bit. Subsequently, the communication control device 11 (e.g., the error handling module 15, in particular, the signaling block 152) transmits the TxD signal as 1 during the DAH bit.

[0125] Because the last PWM symbol of logic 1 has been sent, Figure 13 The signal TxD_TC is also logic 1 at the start of the DAH bit. Therefore, during the duration T_TO (TimeOut) of the DAH bit ( Figure 12 ), the differential voltage VDIFF has a value of -1V, as in Figure 14 As shown in .

[0126] For a duration T_TO (TimeOut) of, for example, 500 ns or another value ( Figure 12 ) After that, the transmitting-receiving device 12 recognizes that no edge has occurred at the terminal TXD. Therefore, the transmitting-receiving device 12 switches its operating mode to the operating mode B_451 (SLOW), as shown in Figure 13 As shown in . Since 1 is present on the TxD signal, the transmit-receive device 12 now drives a recessive level onto the bus 40. The next AH1 bit is also driven onto the bus 40 at a recessive level.

[0127] Therefore, even in this embodiment, the transmitting node generates a recessive level immediately before the AL2 bit, and the recessive level is significantly longer than the arbitration bit time tbt1.

[0128] Otherwise, the bus system 1 functions in the same manner in both exemplary embodiments.

[0129] Figures 16 to 20 The time course according to the third exemplary embodiment is shown, which differs from the time course according to the third exemplary embodiment in the following respects. Figures 6 to 10 time change process.

[0130] As in Figure 17 As shown in FIG, the communication control device 11 (eg, the error handling module 15, in particular the signaling block 152) sends a PWM symbol at the beginning of the DAH bit, which corresponds to a logical value of 0, but has no ending edge. Figure 17 In the example, a PWM symbol SB_D0 without an ending edge is sent. Subsequently, the communication control device 11 (e.g., the error handling module 15, in particular the signaling block 152) sends the TxD signal as 0 until the transceiver 12 switches its operating mode to or has switched to the operating mode B_451 (SLOW) during the DAH bit, as in Figure 18 As shown in .

[0131] For a duration T_TO (TimeOut) of, for example, 500 ns or another value ( Figure 17 ) After that, the transmitting-receiving device 12 recognizes that no edge has occurred at the terminal TXD. Therefore, the transmitting-receiving device 12 switches its operating mode to the operating mode B_451 (SLOW), as shown in Figure 18 As shown in Figure 17 The signal at terminal TXD still has the value 0 at this moment, so the transmitting-receiving device 12 drives the dominant level onto the bus 40. The differential voltage VDIFF thus has the value +2 V, as shown in FIG. Figure 19 As shown in .

[0132] The communication control device 11 (eg, the error handling module 15, in particular the signaling block 152) recognizes the operating mode B_451 (SLOW) based on the value at the RXD terminal, as in Figure 20 In operating mode B 452TX (FAST TX), RXD=1 applies, as shown by Figure 20 In operating mode B 451 (SLOW), the value at the RXD terminal is the logical value of the differential voltage VDIFF on bus line 40, as indicated by the duration TS in FIG. Figure 19 and Figure 20 As shown in .

[0133] As soon as the communication control device 11 (e.g. the error handling module 15, in particular the signaling block 152) recognizes from the value of RXD (RXD=0) that the transceiver device 12 has been switched to operating mode B 451 (SLOW), the communication control device 11 (e.g. the error handling module 15, in particular the signaling block 152) switches the remaining portion of the DAH bit to the same as the value of the RXD value. Figure 17 At terminal TXD, the Figure 16 The TxD signal of AH1 is sent as 1. The next AH1 bit is also driven onto bus 40 at a recessive level.

[0134] Therefore, even in this embodiment, the transmitting node generates a recessive level immediately before the AL2 bit, and the recessive level is significantly longer than the arbitration bit time t bt1 .

[0135] Otherwise, the bus system 1 functions in the same manner as the bus systems of the other exemplary embodiments.

[0136] Furthermore, the three exemplary embodiments differ in the difference in the differential voltage VDIFF from which the transition to the differential voltage VDIFF = 0 for the recessive level occurs. In this case, there are three possibilities for operating mode switching using the transmitting / receiving device, because in addition to the recessive level of the differential voltage VDIFF = 0, there are three other possibilities: VDIFF = +2 V for the dominant level, VDIFF = +1 V for a logical 0 in the data phase, and VDIFF = -1 V for a logical 1 in the data phase 452.

[0137] All previously described embodiments of user stations 10, 20, 30, bus system 1, and the methods implemented therein can be used individually or in all possible combinations. In particular, all features of the previously described exemplary embodiments and / or all features of their modifications can be combined as desired. Additionally or alternatively, the following modifications are particularly conceivable.

[0138] Although the present invention has been described above using a CAN bus system as an example, it can also be used in any communication network and / or communication method in which two different communication phases are used and in which different bus states are generated for the different communication phases. In particular, the present invention can be used when developing other serial communication networks (such as Ethernet and / or 100Base-T1 Ethernet, fieldbus systems, etc.).

[0139] In particular, the bus system 1 according to these exemplary embodiments can be a communication network in which data can be transmitted serially at two different bit rates. Advantageously, but not necessarily, it is a prerequisite that exclusive, conflict-free access to a common channel is guaranteed to the user stations 10, 20, 30 in the bus system 1, at least for a specific period of time.

[0140] Of course, the DAS field can have more than three bits as described in the three embodiments. In this case, the field (DAS) only needs to have a predetermined length before the edge, with a duration T RB that is longer than the duration of the bit time t bt1 of the arbitration phase 451 (the first communication phase). Preferably, the duration T RB is equal to or greater than the duration of 1.5 bits of the arbitration phase 451, as described above.

[0141] The number and arrangement of subscriber stations 10, 20, and 30 in bus system 1 of these exemplary embodiments are arbitrary. In particular, subscriber station 20 can be omitted from bus system 1. It is possible for one or more subscriber stations 10 or 30 to be present in bus system 1. It is also conceivable for all subscriber stations in bus system 1 to be identical, i.e., for only subscriber station 10 or only subscriber station 30 to be present.

Claims

1. A user station (10; 30) for a serial bus system (1), comprising: A communication control device (11; 31) for controlling the communication of the user station (10; 20; 30) with at least one further user station (10; 20; 30) of the bus system (1) and for generating a transmit signal (TXD) such that, for messages (45) exchanged between the user stations (10, 20, 30) of the bus system (1), a bit time (t_bt1) of the signal transmitted onto the bus (40) in a first communication phase (451) can be distinguished from a bit time (t_bt2) of the signal transmitted in a second communication phase (452), The communication control device (11; 31) is designed to generate the transmission signal (TxD) according to a frame (450) and to insert a field (DAS) with an edge into the frame (450) after the second communication phase (452). wherein the field (DAS) has a predetermined length before the edge corresponding to a duration (T_RB) that is longer than the duration of a bit time (t_bt1) of the first communication phase (451), and in, The communication control device (21; 31; 11) of the at least one further user station (10; 20; 30) of the bus system (1) is provided with the edge for synchronizing to the communication on the bus (40), the sending / receiving device (22; 32; 12) of the at least one further user station (10; 20; 30) switching to an operating mode (B_451) for sending and receiving the frame (450) in the first communication phase (451) before a predetermined duration (T_RB).

2. The user station (10; 30) according to claim 1, wherein The field (DAS) of the predetermined length has at least three bits with the bit time (t_bt1) of the first communication phase (451).

3. The user station (10; 30) according to claim 1 or 2, wherein The edge is a falling edge.

4. The user station (10; 30) according to any one of the preceding claims, wherein The communication control device (11) is designed to insert a bit sequence with the logical value 11 in the field (DAS) before the edge.

5. The user station (10; 30) according to any one of the preceding claims, wherein The communication control device (11) is designed to insert the field (DAS) as a bit sequence with the logical value 1101.

6. The user station (10; 30) according to any one of the preceding claims, wherein The communication control device (11) is designed to signal the transmitting / receiving device (12; 32) by means of pulse width modulation in the transmit signal (TXD) that the transmitting / receiving device (12; 32) must switch its operating mode.

7. The user station (10; 30) according to any one of the preceding claims, It further comprises the transmitting / receiving device (12; 32) for transmitting the transmit signal (TXD) to a bus (40) of the bus system (1), The transmitting / receiving device (12; 32) is designed to switch the operating mode of the transmitting / receiving device (12; 32) from the operating mode (B_452_TX) of the second communication phase (452) to a different operating mode (B_451) of the first communication phase (451) after expiration of a predetermined time period (T_TO) during which the transmitting / receiving device (12; 32) has not received an edge in the transmission signal (TXD).

8. The user station (10; 30) according to claim 7, wherein The communication control device (11; 31) is designed to insert a PWM symbol (SB_D0) having a logical value of 0 as the last symbol in the transmit signal (TxD, TXD) before the start of the predetermined time period (T_TO).

9. The user station (10; 30) according to claim 7, wherein The communication control device (11; 31) is designed to insert a PWM symbol (SB_D1) having a logical value of 1 as the last symbol in the transmit signal (TxD, TXD) before the start of the predetermined time period (T_TO).

10. The user station (10; 30) according to claim 7, wherein The communication control device (11; 31) is constructed to: insert a PWM symbol (SB_D0) with a logical value of 0 as the second-to-last symbol in the transmission signal (TxD, TXD) before the start of the predetermined time duration (T_TO); and insert the following PWM symbol (SB_D0) into the transmission signal (TxD, TXD) as the last symbol in the transmission signal (TxD, TXD) before the start of the predetermined time duration (T_TO): the PWM symbol (SB_D0) has a logical value of 0 but does not have an end edge.

11. The user station (10; 30) according to any one of the preceding claims, wherein The communication control device (11; 31) is designed to check the signal at the terminal (RXD) at which the transmitting / receiving device (12; 32) transmits a receive signal (RxD) to the communication control device (11; 31) as to whether the transmitting / receiving device (12; 32) has switched its operating mode from the operating mode (B_452_TX) of the second communication phase (452) to a different operating mode (B_451) of the first communication phase (451).

12. The user station (10; 30) according to any one of claims 1 to 4, It further comprises the transmitting / receiving device (22) for transmitting the transmit signal (TXD) to the bus (40) of the bus system (1), The transmitting / receiving device (22) is designed to transmit the entire frame (450) to the bus (40) in the operating mode (B_452_TX) for transmitting and receiving the frame (450) in the first communication phase (451).

13. The user station (10; 30) according to any one of the preceding claims, in, said frame (450) formed for said message (45) is established in compliance with CAN FD, and In this case, in the first communication phase (451), it is negotiated which of the user stations (10, 20, 30) of the bus system (1) is to receive at least temporarily exclusive, conflict-free access to the bus (40) in the subsequent second communication phase (452).

14. A bus system (1) comprising: bus (40), and At least two user stations (10; 20; 30), the at least two user stations (10; 20; 30) being connected to one another via the bus (40) such that the at least two user stations (10; 20; 30) can communicate with one another serially, and at least one user station (10; 30) of the at least two user stations (10; 20; 30) is a user station (10; 30) according to any one of the above claims.

15. A method for communicating in a serial bus system (1), wherein the method is carried out using a user station (10; 30) of the bus system (1), the user station (10; 30) having a communication control device (11; 31) and a transmitting / receiving device (12; 22; 32), wherein the method comprises the steps of: The communication between the user station (10; 30) and at least one further user station (10; 20; 30) of the bus system (1) is controlled by means of the communication control device (11; 31) so that, for messages (45) exchanged between the user stations (10, 20, 30) of the bus system (1), the bit time (t_bt1) of the signal sent to the bus (40) in a first communication phase (451) can be distinguished from the bit time (t_bt2) of the signal sent in a second communication phase (452), and Using the transmitting / receiving device (12; 32) to transmit a transmit signal (TXD) to a bus (40) of the bus system (1), wherein the communication control device (11; 31) generates the transmission signal (TxD) based on a frame (450) and inserts a field (DAS) with an edge into the frame (450) after the second communication phase (452), wherein the field (DAS) has a predetermined length before the edge corresponding to a duration (T_RB) that is longer than the duration of a bit time (t_bt1) of the first communication phase (451), and in, The communication control device (21; 31; 11) of the at least one further user station (10; 20; 30) of the bus system (1) is provided with the edge for synchronizing to the communication on the bus (40), the sending / receiving device (22; 32; 12) of the at least one further user station (10; 20; 30) switching to an operating mode (B_451) for sending and receiving the frame (450) in the first communication phase (451) before a predetermined duration (T_RB).

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