A wideband digital array radar high-speed data processing method based on polyphase filtering

Abstract

The application discloses a kind of wideband digital array radar high-speed data processing methods based on polyphase filtering, comprising the following specific steps: obtaining the data rate f of data output link channel M And signal frequency conversion to baseband data rate f N , rate conversion is carried out to sampling data;Frequency control word of the sampling data after rate conversion is calculated, and N-way digital mixing signal of each frequency point is generated according to the frequency control word;N-way digital mixing signal is filtered based on the filter with left-right symmetric coefficients, and the mixing signal is converted to the required data rate of baseband.The data rate of data output link channel is obtained, and the sampling data is rate converted to match the sampling rate of the later stage baseband data, so that the signal is not distorted, N-way digital mixing signal of each frequency point is generated by frequency control word, and N-way digital mixing signal is filtered based on the filter with left-right symmetric coefficients, and the mixing signal is converted to the required data rate of baseband, so that the signal matching rate is improved, and resource consumption is reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of digital signal processing, and particularly relates to a wideband digital array radar high-speed data processing method based on polyphase filtering. BACKGROUND

[0002] The digital array radar can realize the rapid change of beam shape and beam pointing, and its performance can be greatly improved compared with the mechanical scanning radar, and has strong adaptability in the case of change of working environment and observed target, and is widely and maturely applied at present. Meanwhile, the software radio theory and application are increasingly mature, and the software radio has been widely concerned in various fields in the world.

[0003] In the signal reconnaissance field, in order to more flexibly process the reconnaissance signal, the programmable logic device becomes more and more important in the preprocessing of the phased array reconnaissance radar adopting the software radio architecture.

[0004] The digital array reconnaissance radar adopting the software radio architecture, after sampling the wideband signal, due to the high data rate, and the clock frequency of the FPGA for digital signal processing is usually far lower than the data rate, the polyphase filtering technology must be used for digital down conversion, and for the case of many channels and many processing frequency points, the resource consumption of the FPGA is very large. Conventionally, the high-speed data is extracted and interpolated according to the baseband signal rate to realize the matching of the rate, and the data rate matched by the polyphase filtering is approximately obtained, which will inevitably lead to the distortion of the signal.

[0005] Specifically includes the following problems:

[0006] 1. The signal distortion problem caused by the mismatch between the data rate after sampling and the data rate required after down conversion caused by the self limitation of JESD204B protocol;

[0007] 2. When simultaneously extracting multiple narrowband signals, the resource consumption of the digital local oscillator signal generated by using the conventional method such as DDS or CORDIC is high when the working frequency band is wide;

[0008] 3. When polyphase filtering, the filter coefficients mapped to each path lose symmetry, which leads to the doubling of the number of multipliers. SUMMARY

[0009] The technical problem to be solved by the present application is that the prior art has the problems of mismatching of sampling data rate and baseband signal data rate, signal distortion, and high resource consumption when performing digital down-conversion processing, and the purpose is to provide a wideband digital array radar high-speed data processing method based on polyphase filtering, by acquiring the data rate of the data output link channel, and performing rate conversion on the sampling data to match the sampling rate of the subsequent baseband data, while ensuring that the signal is not distorted, by generating N-way digital mixing signals for each frequency point through the frequency control word, and based on the filter with left-right symmetric coefficients, filtering the N-way digital mixing signals to convert the mixing signals to the required data rate of the baseband, improving the signal matching rate and reducing resource consumption.

[0010] The present application is realized by the following technical solutions:

[0011] A wideband digital array radar high-speed data processing method based on polyphase filtering, comprising the following specific steps:

[0012] S1, acquiring the data rate f of the data output link channel M and frequency converting the signal to the baseband data rate f N , performing rate conversion on the sampling data;

[0013] S2, calculating the frequency control word of the rate-converted sampling data, and generating N-way digital mixing signals for each frequency point according to the frequency control word;

[0014] S3, based on the filter with left-right symmetric coefficients, filtering the N-way digital mixing signals to convert the mixing signals to the required data rate of the baseband.

[0015] The present application is realized by the following technical solutions:

[0016] Further, the data rate f of the data output link channel is acquired M , specifically comprising:

[0017] Selecting an AD device integrated with a JESD204B interface, and configuring the JESD204B interface according to the sampling rate:

[0018] Acquiring the sampling data to obtain the AD sampling rate and the decimation rate, and determining the data output rate f out ;

[0019] Acquiring the number of channels and the data bit width of each channel, and combining the data output rate fout determining a data rate f of a data output link channel M .

[0020] Further, the specific calculation steps include:

[0021]

[0022]

[0023] wherein M represents the number of channels, N' represents the data bit width per channel, L represents the number of links, f out represents the data output rate.

[0024] Further, the rate conversion of the sampling data specifically includes:

[0025] obtaining the data rate f N after frequency conversion of the signal to baseband, obtaining the ratio relationship between the data rate f M and the data rate f N , determining whether f M / f N is an integer;

[0026] If it is not an integer, obtaining the least common multiple f M of f N and f x , determining a rate conversion coefficient k x according to the least common multiple f i ;

[0027] rate converting the sampling data according to the rate conversion coefficient k i .

[0028] Further, the rate conversion of the sampling data according to the rate conversion coefficient k i specifically includes:

[0029] transmitting the sampling data to an FPGA through a JESD204B interface;

[0030] the FPGA writes M channel data into a cache at a rate of k1 f M , reads out k2 data at a rate of f N , and determines that the rate of the read-out data is converted to f N and the number of channels is converted to N.

[0031] Further, the determination of the rate conversion coefficient k x according to the least common multiple f i specifically includes:

[0032] f x =k1fM

[0033] f x =k2f N

[0034] Among them, f M Indicates the data rate of each link when transmitting data, f N Indicates the data rate after the signal is converted to baseband, f x represents f M With f N k1 and k2 represent the rate conversion coefficients, which are positive integers.

[0035] Furthermore, the S2 specifically includes:

[0036] Obtaining a single-sideband signal spectrum;

[0037] Get the intermediate frequency starting frequency f1 and the intermediate frequency ending frequency f2, and determine the intermediate frequency carrier frequency f c and bandwidth B;

[0038] Determine the number of sample points per cycle of a single-channel mixed digital local oscillator signal based on the signal sampling rate and the intermediate frequency carrier frequency;

[0039] Determine the phase control word input to a single-channel cordic according to the number of sample points;

[0040] The single-channel phase control word is extracted to obtain the phase control words of N-channel cordic.

[0041] Furthermore, the intermediate frequency carrier frequency calculation formula is:

[0042] f c ∈(f1,f2)

[0043] The bandwidth calculation formula is:

[0044] f2-f1=B

[0045] Among them, f1 represents the intermediate frequency starting frequency, f2 represents the intermediate frequency ending frequency, and f c represents the intermediate frequency carrier frequency, and B represents the bandwidth.

[0046] Furthermore, the calculation formula for the phase control word input to a single cordic is:

[0047]

[0048] Among them, f c Indicates the intermediate frequency carrier frequency, f s Indicates the signal sampling rate.

[0049] Furthermore, the S3 specifically includes:

[0050] The order of filter coefficient is designed as even number, and the length is an integer multiple of N;

[0051] The logic device stores half of the coefficients, and the filtering logic reorganizes and caches i N-way signals;

[0052] The cached data is added symmetrically left and right, and after addition, the sequence is multiplied by the filter coefficient, and then the coefficient product is accumulated to obtain the baseband data at the current time.

[0053] Compared with the prior art, the present application has the following advantages and beneficial effects:

[0054] 1. By acquiring the data rate of the data output link channel, and performing rate conversion on the sampling data to match the sampling rate of the subsequent baseband data, while ensuring that the signal is not distorted, the N-way digital mixing signal of each frequency point is generated through the frequency control word, the N-way digital mixing signal is filtered based on the left and right symmetric filter, the mixing signal is converted into the required data rate of the baseband, the signal matching rate is improved, and the resource consumption is reduced;

[0055] 2. The signal is not distorted when the FPGA uses multiple filtering algorithms to process high-speed data;

[0056] 3. A relatively small amount of FPGA resources can be used to complete the multi-frequency point synchronous processing of the wideband radar. BRIEF DESCRIPTION OF DRAWINGS

[0057] In order to more clearly illustrate the technical solutions of the exemplary embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments, and it should be understood that the following drawings only show some embodiments of the present application, and therefore should not be regarded as a limitation on the scope, and for those skilled in the art, other related drawings can also be obtained without creative labor. In the drawings:

[0058] Figure 1 The radar signal preprocessing flow in the embodiment of the present application;

[0059] Figure 2 The ADC sampling data and transmission process schematic diagram in the embodiment of the present application;

[0060] Figure 3 The channel and rate conversion schematic diagram in the embodiment of the present application;

[0061] Figure 4 The digital mixing unit implementation block diagram in the embodiment of the present application. DETAILED DESCRIPTION

[0062] In order to make the purpose, technical scheme and advantages of the present application more clear, the present application is further described in detail below with examples and drawings, the illustrative embodiments of the present application and the description thereof are only used to explain the present application, and do not limit the present application.

[0063] Embodiment 1

[0064] As Figure 1 shown, the embodiment provides a wideband digital array radar high-speed data processing method based on polyphase filtering, comprising the following specific steps:

[0065] S1, acquiring the data rate f of the data output link channel M and frequency conversion of the signal to baseband data rate f N , rate conversion is performed on the sampling data;

[0066] S2, calculating the frequency control word of the sampling data after rate conversion, and generating N-way digital mixing signals of each frequency point according to the frequency control word;

[0067] S3, filtering and processing the N-way digital mixing signals based on the filter with left-right symmetric coefficients, and converting the mixing signals to the required data rate of baseband.

[0068] By acquiring the data rate of the data output link channel and performing rate conversion on the sampling data, the sampling rate of the subsequent baseband data is matched, while the signal is not distorted, N-way digital mixing signals of each frequency point are generated according to the frequency control word, and the N-way digital mixing signals are filtered and processed based on the filter with left-right symmetric coefficients, the mixing signals are converted to the required data rate of baseband, the signal matching rate is improved, and the resource consumption is reduced.

[0069] As Figure 1 shown, the present application respectively through the design of the four links of rate conversion, digital local oscillator generation, polyphase mixing and polyphase filtering of high-speed data to expound the method of saving hardware resources when the radar signal is not distorted in digital down-conversion in FPGA.

[0070] As Figure 2 shown, the data rate f of the data output link channel is determined according to the sampling rate f M , specifically comprising:

[0071] acquiring the data rate f of the data output link channel f M , specifically comprising:

[0072] selecting an AD device integrated with JESD204B interface, and configuring the JESD204B interface according to the sampling rate:

[0073] acquiring the sampling data, obtaining the AD sampling rate and the decimation rate, and determining the data output rate fout ;

[0074] Obtaining the number of channels and the data bit width per channel, and combining the data output rate f out , to determine the data rate f M of the data output link channel.

[0075] The specific calculation steps include:

[0076]

[0077]

[0078] Wherein, M represents the number of channels, N' represents the data bit width per channel, L represents the number of links, f out represents the data output rate.

[0079] Because the signal bandwidth is large, the ADC sampling rate is high, and the clock frequency of the logic device (such as FPGA) in the later stage has an upper limit, which is lower than the ADC output data rate, so the sampling data cannot be directly processed. Here, the ADC performs multi-phase decimation on the data and then matches it in the form of multi-channel parallel transmission. High-speed ADC usually has a JESD204B interface integrated internally, and its transmission mode can be configured to be limited to x1, x2, x4 or x8. In the AD, the JESD204B interface high-speed serial interface is configured to be M-link combination transmission.

[0080] As shown in Figure 3 , the rate conversion of the sampling data specifically includes:

[0081] Obtaining the data rate f N after the signal is frequency-converted to baseband, obtaining the ratio relationship between the data rate f M and the data rate f N , and determining whether f M / f N is an integer;

[0082] If it is not an integer, obtain the least common multiple f M of f N and f x , determine the rate conversion coefficient k i according to the least common multiple f x ;

[0083] According to the rate conversion coefficient k i , the rate conversion of the sampling data is performed.

[0084] The data rate of the ADC through the M-link combination transmission of the JESD204B interface is usually not matched with the data rate of the narrowband signal required by the logic device to extract from the wideband signal in real time. For example:

[0085] After the ADC samples the wideband analog data, the data rate is 1.2 Gbps. The narrowband signal rate extracted by the logic device is 200 Mbps. 1.2 Gbps / 200 Mbps = 6. Since JESD204B does not have a x6 transmission mode, a suitable intermediate rate must be used to transmit the data to the logic device. The logic device then performs a secondary conversion on the rate to match the back-end rate requirements.

[0086] The present invention adopts the following method:

[0087] If the ADC does not extract the data after sampling the analog signal and directly transmits the original data, the AD sampling rate is f s , the sampled data is transmitted to the FPGA through the JESD204B interface. The JESD204B high-speed serial output is configured as xM mode, that is, it is transmitted through a combination of M 204B physical links. The corresponding data rate of each link channel is f M =f s / M; suppose the data rate after the signal is converted to baseband is f N , if f M / f N If it is not an integer, the FPGA cannot obtain the required baseband data through equal-interval sampling after down-conversion, and non-equal-interval data sampling will inevitably lead to signal distortion.

[0088] The present invention uses segmented reorganization and secondary splitting to achieve secondary conversion of ADC data rate to match the sampling rate of the subsequent baseband data while ensuring that the signal is not distorted. The details are as follows:

[0089] If f M / f N If it is not an integer, then f M With f N The least common multiple f x , f x =k1f M , f x =k2f N , where k1 and k2 are rate conversion coefficients, which are positive integers. The logic device conversion process is as follows:

[0090] FPGA with k1 f M Write M channel data into the cache at the same time at a rate of f N The rate of reading out k2 data is converted to f N , the number of channels is transformed into N, which is the number of polyphase filtering channels. At this time, the rate of the transformed data matches the data rate required by the subsequent stage.

[0091] like Figure 4 As shown, S2 specifically includes:

[0092] Obtaining a signal spectrum of a single sideband of the sampling signal;

[0093] Obtaining an intermediate frequency start frequency f1 and an intermediate frequency end frequency f2, and determining an intermediate frequency carrier frequency f c and a bandwidth B;

[0094] According to the signal sampling rate and the intermediate frequency carrier frequency, the number of sample points per cycle of the single-path mixing digital local oscillator signal is determined;

[0095] According to the number of sample points, the phase control word input to the single-path cordic is determined.

[0096] The single-path phase control word is decimated to obtain the phase control word of the N-path cordic.

[0097] Since the antenna receives a wideband signal, the system needs to extract multiple narrow-band and small-bandwidth signals at the same time. The shift of the logical processing signal relative to the center frequency of the front-end signal changes at any time. If the table lookup method is used to store all digital local oscillator signals or the real-time calculation of the DDS phase control word to generate the mixing signal, the resource consumption is large and not flexible.

[0098] In this paper, the signal processing device is used to calculate the frequency control word in real time and then send it to the logic device. The logic device generates N-path digital mixing signals for each frequency point according to the frequency control word. The processing block diagram is shown in Figure 4

[0099] In this paper, the phase control word of the cordic is controlled to generate the digital local oscillator signal. The complete process includes two steps:

[0100] 1. Single-path mixing signal phase control word operation

[0101] If the signal spectrum after ADC sampling is single sideband, the intermediate frequency carrier frequency is f c ∈(f1,f2), where f1 is the intermediate frequency start frequency, f2 is the intermediate frequency end frequency, f2-f1=B (B is the bandwidth), and the signal sampling rate is f s According to the single-path mixing digital local oscillator signal, there are f s / f c sample points per cycle, and the phase control word input to the single-path cordic is

[0102] 2. N-path cordic phase control word generation

[0103] The single-path phase control word is decimated to obtain the phase control word of the N-path cordic.

[0104] ​In some possible embodiments, when digital pre-frequency conversion is performed, a FIR filter is used for low-pass filtering, when the filter order is even, the filter coefficients are symmetric, direct filtering can be performed by half addition to reduce half of the multiplier resources, but when a polyphase filtering algorithm is used, since the filter coefficients also need to be polyphase extracted, the coefficients of each channel no longer have symmetry, if direct filtering is performed using an IP core, the logic device multiplier resources will be used to the maximum;

[0105] The application uses basic logic resources to build filtering logic, and restores the symmetry of the filter coefficients by recombining the multiple data, S3 specifically includes:

[0106] 1. The order of the filter coefficients is designed to be even so that it is symmetric on the left and right, and the length thereof is an integer multiple of N, i.e. i·N (i is an integer greater than 0), the logic device stores half of the coefficients;

[0107] 2. The filtering logic recombines i N-way signals (length = i·N) for caching;

[0108] 3. The data in the cache are added symmetrically on the left and right;

[0109] 4. The sequences after addition are respectively multiplied by the filter coefficients;

[0110] 5. The data and the coefficient products are accumulated to obtain the baseband data at the current time.

[0111] The above-described specific embodiments further explain the purpose, technical solutions and advantages of the application, and it should be understood that the above-described embodiments are only specific embodiments of the application and are not used to limit the protection scope of the application, any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the application should be included in the protection scope of the application.

Claims

1. A high-speed data processing method for broadband digital array radar based on polyphase filtering, characterized in that: The specific steps include: S1. Get the data rate of the data output link channel f M The data rate after the signal is converted to baseband f N , perform rate conversion on the sampled data; S2. Calculate the frequency control word of the sampled data after rate conversion, and generate N-channel digital mixed signals at each frequency point according to the frequency control word; S3, filtering the N-channel digital mixed signals based on a filter with bilaterally symmetrical coefficients, and converting the mixed signals to the data rate required by the baseband; The S3 specifically includes: The order of the filter coefficient is designed to be an even number, and its length is an integer multiple of N; The logic device stores half of the coefficients, and the filter logic reorganizes and caches the N signals. The buffered data is added symmetrically on the left and right sides, and the added sequences are multiplied by the filter coefficients respectively, and then accumulated with the coefficient products to obtain the baseband data at the current moment.

2. The method for high-speed data processing of broadband digital array radar based on polyphase filtering according to claim 1, characterized in that: The data rate of the acquired data output link channel f M , specifically including: Select an AD device with an integrated JESD204B interface and configure the JESD204B interface according to the sampling rate: Get the sampled data, get the AD sampling rate and decimation rate, and determine the data output rate f out ; Get the number of channels and the data bit width per channel, combined with the data output rate f out , determines the data rate of the data output link channel f M .

3. The method for high-speed data processing of broadband digital array radar based on polyphase filtering according to claim 2, characterized in that: The data output rate f out The calculation formula is: ; The data rate of the data output link channel f M The expression is: ; in, M Indicates the number of channels, Indicates the data bit width of each channel, L Indicates the number of links, f out Indicates the data output rate.

4. The method for high-speed data processing of broadband digital array radar based on polyphase filtering according to claim 1, characterized in that: The rate conversion of the sampled data specifically includes: Get the data rate after the signal is converted to baseband f N , get the data rate f M and data rate f N The ratio relationship, judge f M / f N Is it an integer? If not an integer, get f M and f N The least common multiple of f x , according to the least common multiple f x Determine the rate conversion factor k i ; According to the rate conversion coefficient k i Perform rate conversion on sampled data.

5. The method for high-speed data processing of broadband digital array radar based on polyphase filtering according to claim 4, characterized in that: The rate conversion coefficient k i Perform rate conversion on the sampled data, including: The sampled data is transmitted to the FPGA via the JESD204B interface; the FPGA writes M channel data into the cache at the rate of k1fM at the same time. f N Rate readout k 2 data, determine the rate of reading data is converted to f N , the number of channels is transformed into N.

6. The method for high-speed data processing of broadband digital array radar based on polyphase filtering according to claim 5, characterized in that: According to the least common multiple f x Determine the rate conversion factor k i The specific calculation steps include: f x ＝ k 1 f M ； f x = k 2 f N ;in, f M Indicates the data rate of each link when transmitting data, f N Indicates the data rate after the signal is converted to baseband. f x express f M and f N The least common multiple of k 1, k 2 represents the rate conversion coefficient, which is a positive integer.

7. The method for high-speed data processing of broadband digital array radar based on polyphase filtering according to claim 1, characterized in that: The S2 specifically includes: Obtaining a single-sideband signal spectrum; Get the intermediate frequency starting frequency f 1 and the intermediate frequency end frequency f 2. Determine the intermediate frequency carrier frequency f c and bandwidth B; Determine the number of sample points per cycle of a single-channel mixed digital local oscillator signal based on the signal sampling rate and the intermediate frequency carrier frequency; Determine the phase control word input to a single-channel cordic according to the number of sample points; The single-channel phase control word is extracted to obtain the phase control words of N-channel cordic.

8. The method for high-speed data processing of broadband digital array radar based on polyphase filtering according to claim 7, characterized in that: The intermediate frequency carrier frequency calculation formula is: f c ∈( f 1, f 2); The bandwidth calculation formula is: f 2- f 1=B; where f 1 indicates the intermediate frequency starting frequency, f 2 represents the intermediate frequency end frequency, f c represents the intermediate frequency carrier frequency, and B represents the bandwidth.

9. The method for high-speed data processing of broadband digital array radar based on polyphase filtering according to claim 8, characterized in that: The calculation formula for the phase control word input to a single cordic is: ,in, f c Indicates the intermediate frequency carrier frequency, f s Indicates the signal sampling rate.

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