Liquid crystal display device

Abstract

A liquid crystal display device includes a liquid crystal panel comprising a first substrate provided with thin film transistors, a second substrate provided with a color filter layer, and a liquid crystal layer positioned between the first and second substrates; and a backlight unit positioned below the liquid crystal panel. The second substrate is positioned between the backlight unit and the first substrate, and an organic buffer layer may be positioned between the first substrate and the thin film transistors. This minimizes the width of the border region and improves the mechanical durability of the device.

Description

Technical Field

[0001] The present disclosure relates to a liquid crystal display (LCD) device, and particularly, to a borderless LCD device having a narrow bezel. Background Art

[0002] With the development of the information society, there are various demands on image display devices, and thus, flat panel display devices such as liquid crystal display (LCD) devices and organic light emitting diode (OLED) display devices have been developed and applied to various fields.

[0003] In particular, an LCD device as one of such display devices has various technical advantages such as light weight, thinness, and low power consumption, and is widely used.

[0004] LCD devices are configured to utilize the optical and dielectric anisotropy of liquid crystals and include two substrates, a liquid crystal layer located between the two substrates, and pixels and common electrodes configured to drive the liquid crystal molecules in the liquid crystal layer. In LCD devices, the orientation of the liquid crystal molecules is controlled by an electric field generated by applying voltage to the pixels and common electrodes. This process is used to change the optical transmittance in each pixel of the LCD device, thereby displaying an image on the LCD device. LCD devices are used in a wide variety of devices, from portable devices such as cellular phones and multimedia devices to laptop computers, computer monitors, and large televisions.

[0005] Electronic products with such LCD devices include a frame area in addition to a display area for displaying images. Recently, various efforts have been made to provide borderless products that minimize the width of the frame area (i.e., have narrow frames or maximize the area of ​​the display area within a given area of ​​the display device).

[0006] For example, a flip panel structure has been proposed in which an array substrate is arranged adjacent to a display surface. However, the array substrate includes multiple inorganic layers that are susceptible to cracking when subjected to external impact. In other words, the flip panel structure is susceptible to problems such as low strength and panel damage.

[0007] In addition, attempts have been made to reduce the weight and thickness of LCD devices by reducing the thickness of substrates. However, this makes the LCD device more susceptible to external impact and stress. Summary of the Invention

[0008] Accordingly, the present disclosure is directed to an LCD device that substantially obviates one or more problems due to limitations and disadvantages of the related art.

[0009] An object of the present disclosure is to provide an LCD device having improved mechanical strength or durability.

[0010] Other features and advantages of the present disclosure will be set forth in the following description, and in part will be apparent from the description, or may be learned through practice of the present disclosure. The advantages of the present disclosure may be realized and obtained through the structures particularly pointed out in the written description and claims as well as the drawings.

[0011] To achieve these and other advantages and in accordance with the purposes of the present disclosure, a liquid crystal display device, as embodied and broadly described herein, includes: a liquid crystal panel including a first substrate having thin film transistors disposed thereon, a second substrate having a color filter layer disposed thereon, and a liquid crystal layer disposed therebetween; and a backlight unit disposed below the liquid crystal panel. The second substrate is disposed between the backlight unit and the first substrate, and an organic buffer layer is disposed between the first substrate and the thin film transistors.

[0012] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The accompanying drawings are included to provide a further understanding of the present disclosure, and are incorporated in and constitute a part of this specification, illustrate embodiments of the present disclosure and together with the description serve to explain the principles of the present disclosure. In the drawings:

[0014] Figure 1 is a cross-sectional view schematically illustrating an LCD device according to a first embodiment of the present disclosure.

[0015] Figure 2 is a plan view schematically illustrating a liquid crystal panel of an LCD device according to a second embodiment of the present disclosure.

[0016] Figure 3 is a cross-sectional view schematically illustrating a sub-pixel of a liquid crystal panel of an LCD device according to a second embodiment of the present disclosure.

[0017] Figure 4 is a cross-sectional view schematically illustrating a gate driving part of a liquid crystal panel of an LCD device according to a second embodiment of the present disclosure.

[0018] Figure 5 is a cross-sectional view schematically illustrating a link portion of a liquid crystal panel of an LCD device according to a second embodiment of the present disclosure.

[0019] Figure 6 is a plan view schematically illustrating a liquid crystal panel of an LCD device according to a third embodiment of the present disclosure.

[0020] Figure 7is a cross-sectional view schematically illustrating a sub-pixel of a liquid crystal panel of an LCD device according to a third embodiment of the present disclosure.

[0021] Figure 8 is a cross-sectional view schematically illustrating a gate driving part of a liquid crystal panel of an LCD device according to a third embodiment of the present disclosure.

[0022] Figure 9 is a cross-sectional view schematically illustrating a link portion of a liquid crystal panel of an LCD device according to a third embodiment of the present disclosure.

[0023] Figure 10 is a cross-sectional view schematically illustrating a liquid crystal panel of an LCD device according to a fourth embodiment of the present disclosure.

[0024] Figure 11 is a cross-sectional view schematically illustrating a liquid crystal panel of an LCD device according to a fifth embodiment of the present disclosure.

[0025] Figure 12 is a cross-sectional view schematically illustrating a liquid crystal panel of an LCD device according to a sixth embodiment of the present disclosure.

[0026] Figure 13 is a cross-sectional view schematically illustrating a liquid crystal panel of an LCD device according to a seventh embodiment of the present disclosure.

[0027] Figure 14 is a cross-sectional view schematically illustrating a liquid crystal panel of an LCD device according to an eighth embodiment of the present disclosure.

[0028] Figure 15 is a plan view schematically illustrating an example of a liquid crystal panel of an LCD device according to a ninth embodiment of the present disclosure.

[0029] Figure 16 is a plan view schematically illustrating another example of a liquid crystal panel of an LCD device according to a ninth embodiment of the present disclosure. DETAILED DESCRIPTION

[0030] Reference will now be made in detail to embodiments, examples of which are illustrated in the accompanying drawings. The same or similar reference numerals may be used throughout the drawings to refer to the same or similar parts.

[0031] [First embodiment]

[0032] Figure 1 is a diagram schematically illustrating an LCD device according to a first embodiment of the present disclosure.

[0033] like Figure 1As shown in , the LCD device according to the first embodiment of the present disclosure may include a liquid crystal panel 100 configured to display an image and a backlight unit 185 configured to provide light to the liquid crystal panel 100 .

[0034] The liquid crystal panel 100 may include an array substrate 110, a color filter substrate 160, and a liquid crystal layer 170 between the two substrates 110 and 160. In addition, a display area DA for displaying an image and a non-display area NDA disposed around the display area DA may be defined in the liquid crystal panel 100.

[0035] Here, the color filter substrate 160 may be disposed between the array substrate 110 and the backlight unit 185 .

[0036] The array substrate 110 may include a first substrate 112 , an organic buffer layer 141 , a thin film transistor T1 , a pixel electrode 132 , and a common electrode 134 , and the color filter substrate 160 may include a second substrate 162 , a black matrix 164 , a color filter layer 165 , and an overcoat layer 166 .

[0037] In detail, the display area DA and the non-display area NDA may be defined in the first substrate 112 of the array substrate 110 and the second substrate 162 of the color filter substrate 160. The first substrate 112 and the second substrate 162 may be formed of at least one of glass or plastic materials. The first substrate 112 and the second substrate 162 may be configured to have a thickness of 0.5 mm or less, preferably 0.3 mm or less, but the inventive concept of the present disclosure is not limited to this example.

[0038] An organic buffer layer 141 may be formed on the inner surface of the first substrate 112. The organic buffer layer 141 may be formed of an organic insulating material and may function as a buffer or shock absorbing element to improve the mechanical strength or durability of the liquid crystal panel 100. As an example, the organic buffer layer 141 may be formed of polyimide (PI), polyamide (PA), photoacrylic, or benzocyclobutene (BCB), but the inventive concept of the present disclosure is not limited to this example.

[0039] By forming the organic buffer layer 141 in the display area DA and the non-display area NDA through a coating method and then removing a portion of the organic buffer layer 141 from the non-display area NDA through a photoetching process, the organic buffer layer 141 may be partially formed only in the display area DA. However, the inventive concept of the present disclosure is not limited to this example, and the organic buffer layer 141 may be disposed in both the display area DA and the non-display area NDA.

[0040] The thickness of the organic buffer layer 141 may range from to 50 μm, preferably from to 20 μm, and more preferably from To 1μm.

[0041] The inorganic buffer layer 142 may be formed on the organic buffer layer 141. The inorganic buffer layer 142 may be formed of silicon nitride (SiNx) or silicon oxide (SiO2).

[0042] The inorganic buffer layer 142 may be disposed in both the display area DA and the non-display area NDA. In the case where the organic buffer layer 141 is disposed only in the display area DA, the inorganic buffer layer 142 may be in contact with the organic buffer layer 141 in the display area DA, may be in contact with the first substrate 112 in the non-display area NDA, and may have a step difference near the boundary between the display area DA and the non-display area NDA.

[0043] The inorganic buffer layer 142 can prevent impurities in the organic buffer layer 141 from entering the thin film transistor T1. In addition, the inorganic buffer layer 142 can have a high adhesive strength to the first substrate 112 compared with the organic buffer layer 141, and in this case, it is possible to prevent the organic buffer layer 141 from being separated from the first substrate 112.

[0044] In contrast, when the organic buffer layer 141 is also disposed in the non-display area NDA, the inorganic buffer layer 142 may contact the organic buffer layer 141 in the non-display area NDA. However, the disclosed inventive concept is not limited to this example, and the inorganic buffer layer 142 may be omitted.

[0045] In addition, an inorganic buffer layer may be disposed between the first substrate 112 and the organic buffer layer 141 .

[0046] Next, a gate electrode 122 made of a conductive material may be formed on the inorganic buffer layer 142 in the display area DA. The gate electrode 122 may be formed of aluminum (Al), molybdenum (Mo), nickel (Ni), chromium (Cr), copper (Cu), neodymium (Nd), titanium (Ti), or alloys thereof, and may have a single-layer or multi-layer structure.

[0047] Although not shown, a gate line made of the same material as the gate electrode 122 may be formed on the inorganic buffer layer 142. The gate line may extend in the first direction and may be connected to the gate electrode 122.

[0048] The gate insulating layer 143 may be formed on the gate 122 to cover substantially the entire surface of the first substrate 112. Accordingly, the gate insulating layer 143 may be disposed in both the display area DA and the non-display area NDA. The gate insulating layer 143 may be made of silicon nitride (SiN x ) or silicon oxide (SiO2) is formed.

[0049] The semiconductor layer 124 may be formed on the gate insulating layer 143 corresponding to the gate electrode 122. The semiconductor layer 124 may be formed of an oxide semiconductor material. As an example, the semiconductor layer 124 may be formed of indium gallium zinc oxide (IGZO), but the inventive concepts disclosed herein are not limited to this example. Here, an etch stop layer may also be formed on the semiconductor layer 124 to correspond to the gate electrode 122.

[0050] Alternatively, the semiconductor layer 124 may be formed of amorphous silicon. In this case, the semiconductor layer 124 may include an active layer made of intrinsic amorphous silicon and an ohmic contact layer made of doped amorphous silicon, and here, the ohmic contact layer may be divided into two parts to expose the top surface of the active layer.

[0051] Next, a source electrode 126 and a drain electrode 128 made of a conductive material may be formed on the semiconductor layer 124. The source electrode 126 and the drain electrode 128 on the semiconductor layer 124 may be spaced apart from each other with the gate 122 interposed therebetween, and a portion of the semiconductor layer 124 between the source electrode 126 and the drain electrode 128 may be exposed.

[0052] In addition, although not shown, a data line made of the same material as the source electrode 126 and the drain electrode 128 may be formed on the gate insulating layer 143. The data line may extend in the second direction to cross the gate line, and in this case, a sub-pixel may be defined by the data line and the gate line. The data line may be connected to the source electrode 126.

[0053] The source electrode 126 and the drain electrode 128 may be formed of aluminum (Al), molybdenum (Mo), nickel (Ni), chromium (Cr), copper (Cu), neodymium (Nd), titanium (Ti), or alloys thereof, and may have a single-layer or multi-layer structure.

[0054] The gate 122 , the semiconductor layer 124 , the source 126 , and the drain 128 may constitute a thin film transistor T1 , and an exposed portion of the semiconductor layer 124 between the source 126 and the drain 128 may be used as a channel region of the thin film transistor T1 .

[0055] Here, the semiconductor layer 124 and the source electrode 126 and the drain electrode 128 may be formed by a photolithography process using a single mask. Accordingly, the semiconductor layer 124, excluding a portion located between the source electrode 126 and the drain electrode 128, may have substantially the same shape as the source electrode 126 and the drain electrode 128. Here, although not shown, a semiconductor pattern made of the same material as the semiconductor layer 124 may be formed between the gate insulating layer 143 and the data line.

[0056] In an embodiment, the semiconductor layer 124 and the source electrode 126 and the drain electrode 128 may be formed by two photolithography processes performed using respective masks. In this case, the side surfaces of the semiconductor layer 124 may be covered with the source electrode 126 and the drain electrode 128, and the semiconductor pattern between the gate insulating layer 143 and the data line may be omitted.

[0057] A protective layer 144 made of an insulating material may be formed on the source electrode 126 and the drain electrode 128. The protective layer 144 may be formed on substantially the entire surface of the first substrate 112 and may be disposed in both the display area DA and the non-display area NDA. The protective layer 144 may be made of an inorganic insulating material (e.g., silicon oxide (SiO2) or silicon nitride (SiN x ))form.

[0058] A planarization layer 145 made of an insulating material may be formed on the protective layer 144. The planarization layer 145 may be formed on substantially the entire surface of the first substrate 112, and may be disposed in both the display area DA and the non-display area NDA.

[0059] The planarization layer 145 may be formed of an organic insulating material. The planarization layer 145 may have a substantially flat top surface and may remove step differences that may be formed by underlying layers. As an example, the planarization layer 145 may be formed of photoacrylic having photosensitive properties. Alternatively, the planarization layer 145 may be formed of benzocyclobutene (BCB), polyimide (PI), or polyamide (PA), but the inventive concepts of the present disclosure are not limited to this example.

[0060] In addition, the planarization layer 145 may have a first contact hole 145a formed at a position corresponding to a portion of the drain electrode 128. Here, a top surface of the protection layer 144 may be exposed through the first contact hole 145a.

[0061] In addition, the planarization layer 145 may be formed to have a groove 145 b in the non-display area NDA, and an edge portion of the planarization layer 145 may be removed to expose the top surface of the protection layer 144 thereunder.

[0062] A common electrode 134 made of a conductive material may be formed on the planarization layer 145. The common electrode 134 may be formed of a transparent conductive material, for example, indium tin oxide (ITO) or indium zinc oxide (IZO).

[0063] A passivation layer 148 made of an insulating material may be formed on the common electrode 134. The passivation layer 148 may be made of an inorganic insulating material (eg, silicon oxide (SiO2) or silicon nitride (SiN x ))form.

[0064] The passivation layer 148 may be formed on substantially the entire surface of the first substrate 112 and may be disposed in both the display area DA and the non-display area NDA.

[0065] In the display area DA, the passivation layer 148 may be in contact with the side surface of the planarization layer 145 and may have a second contact hole 148a exposing the drain electrode 128. Here, the second contact hole 148a may also be formed in the protective layer 144. In addition, in the non-display area NDA, the passivation layer 148 may be in contact with the side surface of the planarization layer 145 and the top surface of the protective layer 144.

[0066] A pixel electrode 132 made of a conductive material may be formed on the passivation layer 148. The pixel electrode 132 may be provided in each sub-pixel and may be formed of a transparent conductive material (eg, ITO or IZO).

[0067] The pixel electrode 132 can contact the drain electrode 128 through a second contact hole 148a formed in the first contact hole 145a. In the present embodiment, the second contact hole 148a has been described as being separated from the first contact hole 145a, but the inventive concept of the present disclosure is not limited to this example. For example, the second contact hole 148a and the first contact hole 145a can be arranged to form a single hole. In other words, a single contact hole formed to expose the drain electrode 128 can be provided in the passivation layer 148, the planarization layer 145, and the protective layer 144, and in this case, the pixel electrode 132 can contact the side surface of the planarization layer 145.

[0068] The pixel electrode 132 may include a plurality of patterns and may overlap with the common electrode 134. Accordingly, when a voltage is applied to the pixel electrode 132 and the common electrode 134, an electric field substantially parallel to the first substrate 112 may be generated between the plurality of patterns of the pixel electrode 132 and the common electrode 134, and in this case, the liquid crystal molecules in the liquid crystal layer 170 may be driven by the electric field.

[0069] In addition, a plurality of driving lines 152 may be provided in the non-display area NDA. The driving lines 152 may include a plurality of patterns formed in the same layer and of the same material as the gate 122 or the source 126 and drain 128. The driving lines 152 may include signal lines and a gate driver provided in the form of a gate in panel (GIP).

[0070] Here, the gate driving part may be disposed between the inorganic buffer layer 142 and the protective layer 144 , and the inorganic buffer layer 142 may have a step difference between the display area DA and the gate driving part.

[0071] Next, the second substrate 162 may be provided to be spaced apart from the first substrate 112, and a black matrix 164 may be formed on the inner surface of the second substrate 162. The black matrix 164 may be formed in an area corresponding to the boundary of each sub-pixel in the display area DA and may be formed throughout the non-display area NDA. When viewed in a plan view, the black matrix 164 may have a lattice shape.

[0072] The black matrix 164 can be formed of a black resin. Alternatively, the black matrix 164 can be formed of an optically reflective metal. When the black matrix 164 is formed of a metal material, it is possible to increase the brightness of each pixel through photon recycling. For example, light emitted from the backlight unit 185 can be reflected by the black matrix 164, and the reflected light can be reflected again by the backlight unit 185 to propagate toward the liquid crystal panel 100 and can be used to display an image. Therefore, as described above, the brightness of the liquid crystal panel 100 can be increased.

[0073] The color filter layer 165 may be formed on the black matrix 164 in the display area DA. The color filter layer 165 may include red, green, and blue color filters, and each of the color filters may be disposed to correspond to one of the sub-pixels.

[0074] An overcoat layer 166 made of an insulating material may be formed on the color filter layer 165. The overcoat layer 166 may be formed on substantially the entire surface of the second substrate 162 and may be disposed in the display area DA and the non-display area NDA. In the non-display area NDA, the overcoat layer 166 may be in contact with the black matrix 164.

[0075] A column spacer 167 made of an insulating material may be formed on the overcoat layer 166. The column spacer 167 may be formed to correspond to the black matrix 164 in the display area DA and may be configured to maintain a cell gap between the array substrate 110 and the color filter substrate 160. The column spacer 167 may also be formed on the array substrate 110.

[0076] In addition, an electrostatic discharge (ESD) prevention layer 168 made of a conductive material may be formed on an outer surface of the second substrate 162 to cover substantially the entire surface of the second substrate 162. The ESD prevention layer 168 may be formed of a transparent conductive material such as ITO or IZO.

[0077] The liquid crystal layer 170 may be disposed between the array substrate 110 and the color filter substrate 160. Although not shown, alignment layers may be formed between the array substrate 110 and the liquid crystal layer 170 and between the color filter substrate 160 and the liquid crystal layer 170 to determine the initial alignment direction of the liquid crystal molecules.

[0078] Next, a seal pattern 180 may be formed between the array substrate 110 and the color filter substrate 160, particularly in the non-display area NDA between the passivation layer 148 and the overcoat layer 166. The seal pattern 180 may be provided to surround the display area DA and prevent liquid crystal from leaking from the display area DA. The seal pattern 180 may be formed at a position corresponding to the groove 145b of the planarization layer 145, and in this case, the presence of the groove 145b may increase the contact area between the seal pattern 180 and the array substrate 110.

[0079] In addition, although not shown, upper and lower polarizing plates may be disposed on the array substrate 110 and under the color filter substrate 160 , respectively, and in an embodiment, may be disposed to have transmission axes crossing each other.

[0080] The backlight unit 185 may be disposed under the liquid crystal panel 100 including the array substrate 110 and the color filter substrate 160 , and here, the backlight unit 185 may be configured to transmit photons to the liquid crystal panel 100 .

[0081] In the LCD device according to the first embodiment of the present disclosure, the color filter substrate 160 may be disposed between the array substrate 110 and the backlight unit 185. That is, the second substrate 162 may be disposed between the first substrate 112 and the backlight unit 185, and in this case, the outer surface of the first substrate 112 may be used as a display surface.

[0082] Therefore, by reducing an area for connection between a driving part provided in the array substrate 110 and an external circuit, it may be possible to reduce a width of the bezel region, thereby realizing a borderless LCD device having a minimized area of ​​the bezel region.

[0083] In addition, since the organic buffer layer 141 is disposed between the first substrate 112 of the array substrate 110 and the thin film transistor T1 , cracking of the organic buffer layer 141 during the manufacturing process may be prevented, and thus, mechanical strength or durability of the liquid crystal panel 100 may be improved.

[0084] Tables 1 and 2 show the mechanical strength characteristics of the liquid crystal panel of the LCD device according to the present disclosure. The tables specifically show the test results obtained by varying the thickness of the organic buffer layer made of polyimide in the Ball-on-Ring (BOR) and Ball-Drop (BD) tests. Table 1 shows the results when 0.3 mm thick glass substrates were used as the first and second substrates, and Table 2 shows the results when 0.2 mm thick glass substrates were used as the first and second substrates.

[0085] In the BOR test, the LCD panel is placed on a 40mm diameter ring fixture. A 30mm diameter metal ball probe is then used to apply force to the LCD panel until it cracks. The force applied when the LCD panel cracks is measured as the panel's mechanical strength, with the maximum applied force being 90kgf. In the BD test, a 22g metal ball is positioned relative to the LCD panel until the panel cracks due to the free fall of the 22g metal ball. The position of the metal ball is measured when the LCD panel cracks. The highest position of the metal ball is 1400mm.

[0086] [Table 1]

[0087]

[0088] [Table 2]

[0089]

[0090] As shown in Table 1 and Table 2, when the organic buffer layer is disposed between the first substrate of the array substrate and the thin film transistor, the mechanical durability of the liquid crystal panel is improved.

[0091] In addition, there is an increasing demand for LCD devices including touch screens configured to receive commands from a user while displaying an image on a liquid crystal panel. In particular, some LCD devices are being developed to include in-cell touch screens in which touch electrodes and touch lines constituting a touch panel are integrated as part of an array substrate of a liquid crystal panel. Figures 2 to 5 A liquid crystal panel including a touch electrode and a touch line according to a second embodiment of the present disclosure is described in more detail.

[0092] [Second embodiment]

[0093] Figure 2 is a plan view schematically illustrating a liquid crystal panel of an LCD device according to a second embodiment of the present disclosure.

[0094] like Figure 2 As shown in , the liquid crystal panel of the LCD device according to the second embodiment of the present disclosure may include a display area DA for displaying an image and a non-display area NDA disposed to surround the display area DA.

[0095] In the display area DA, a plurality of sub-pixels SP may be arranged in a matrix shape. Each of the sub-pixels SP may be configured to receive signals through a gate line (not shown), a data line (not shown), and a power line (not shown). Each of the sub-pixels SP may include a thin film transistor and a liquid crystal capacitor, and the detailed structure of the sub-pixels SP will be described in more detail below.

[0096] In addition, a touch line (not shown) may be provided in the display area DA and may be used to transmit a touch driving voltage and a touch sensing voltage.

[0097] The gate driving part GD and the first and second driving parts DIC1 and DIC2 may be disposed in the non-display area NDA to generate signals or receive signals from an external driving printed circuit board (PCB) and apply the signals to each of the subpixels SP in the display area DA.

[0098] The gate drive section GD can be set separately Figure 2 The gate driver GD may be configured to generate a gate signal and apply the gate signal to the gate line. In an embodiment, the gate driver GD may be formed on the same substrate as the thin film transistors in the display area DA, or may be provided in the form of a GIP.

[0099] The first driving part DIC1 and the second driving part DIC2 can be arranged in Figure 2 The non-display area NDA shown in FIG is located in a lower portion thereof and may be provided in the form of an integrated circuit (IC).

[0100] The first driving part DIC1 may generate a data signal and then output the data signal to the data line. In addition, the first driving part DIC1 may be configured to apply a touch driving voltage to the touch line and receive a touch sensing voltage from the touch electrode through the touch line.

[0101] The second driving part DIC2 may be connected to the gate driving part GD and the signal lines SL to transmit a power voltage and a control signal required to operate the LCD device.

[0102] In addition, a plurality of signal lines SL, at least one data link line 254 , and at least one touch link line 237 may be provided in the non-display area NDA.

[0103] The plurality of signal lines SL may include common lines and test lines for transmitting a common voltage and a test voltage to the display area DA, and may be formed to surround the display area DA.

[0104] The data link line 254 can be set in the lower portion of the non-display area NDA to connect the data line in the display area DA to the first driving part DIC1, and the touch link line 237 can be set in the lower portion of the non-display area NDA to connect the touch line in the display area DA to the first driving part DIC1.

[0105] In addition, a seal pattern 280 may be formed in the non-display area NDA to surround the display area DA, and in this case, it may be possible to prevent liquid crystal from leaking from the display area DA. Here, the gate driver GD may be arranged in an area located inside the seal pattern 280 (i.e., toward the center of the liquid crystal panel) (e.g., between the seal pattern 280 and the display area DA), and the first driver DIC1 and the second driver DIC2 may be arranged in an area located outside the seal pattern 280. That is, the seal pattern 280 may be arranged between the display area DA and the first driver DIC1 and the second driver DIC2.

[0106] In addition, at least one of the signal lines SL may overlap the seal pattern 280 , and the data link line 254 and the touch link line 237 may be disposed to cross the seal pattern 280 .

[0107] Silver (Ag) dots 290 may be provided at opposite ends of the lower portion of the non-display area (NDA). The silver dots 290 may be provided by forming a metal paste using a dotting method, and the silver dots may connect the ESD prevention layer of the color filter substrate to the pads of the array substrate. In this case, electrostatic current that may be generated in the color filter substrate may be discharged to the outside through the silver dots 290.

[0108] Will refer to Figures 3 to 5 A cross-sectional structure of a liquid crystal panel of an LCD device according to a second embodiment of the present disclosure is described.

[0109] Figure 3 、 Figure 4 and Figure 5 is a cross-sectional view schematically illustrating a liquid crystal panel of an LCD device according to a second embodiment of the present disclosure. For example, Figure 3 Illustrated with Figure 2 The cross-sectional structure of the sub-pixel area corresponding to the area "A1" of the display area, Figure 4 Illustrated with Figure 2 The cross-sectional structure of the area "A2" corresponding to the gate driving portion in the non-display area is shown in FIG. Figure 5 Illustrated with Figure 2 . The cross-sectional structure of area "A3" corresponding to the link portion in the non-display area is shown. Aside from the structural differences associated with the touch lines, the buffer layer, and the touch insulation layer, the liquid crystal panel of the LCD device according to the second embodiment of the present disclosure can be configured to have substantially the same structure as the liquid crystal panel of the LCD device of the first embodiment. To avoid repeated overlapping descriptions, the same elements as those in the first embodiment will be identified by the same reference numerals.

[0110] like Figure 3 、 Figure 4 and Figure 5As shown in , the liquid crystal panel of the LCD device according to the second embodiment of the present disclosure may include an array substrate 210, a color filter substrate 260, and a liquid crystal layer 270 located between the two substrates 210 and 260, and the color filter substrate 260 may be located between the array substrate 210 and the backlight unit (not shown).

[0111] The array substrate 210 may include a first substrate 212 , an organic buffer layer 241 , a thin film transistor T2 , a pixel electrode 232 , a common electrode 234 and a touch line 236 , and the color filter substrate 260 may include a second substrate 262 , a black matrix 264 , a color filter layer 265 and an overcoat layer 266 .

[0112] In detail, the display area DA and the non-display area NDA may be defined in the first substrate 212 of the array substrate 210 and the second substrate 262 of the color filter substrate 260. The first substrate 212 and the second substrate 262 may be formed of at least one of glass or plastic material.

[0113] An organic buffer layer 241 may be formed on the inner surface of the first substrate 212. The organic buffer layer 241 may be formed of an organic insulating material and may be disposed in the display area DA. As an example, the organic buffer layer 241 may be formed of polyimide (PI), polyamide (PA), photoacrylic, or benzocyclobutene (BCB), but the inventive concept of the present disclosure is not limited to this example.

[0114] The thickness of the organic buffer layer 241 can be in the range of to 50 μm, preferably to 20 μm, and more preferably To 1μm.

[0115] The inorganic buffer layer 242 may be formed on the organic buffer layer 241. The inorganic buffer layer 242 may be formed on substantially the entire surface of the first substrate 212 and may be disposed in both the display area DA and the non-display area NDA. The inorganic buffer layer 242 may be made of silicon nitride (SiN x ) or silicon oxide (SiO2) is formed.

[0116] The inorganic buffer layer 242 may contact the organic buffer layer 241 in the display area DA, may contact the first substrate 212 in the non-display area NDA, and may have a step difference near a boundary between the display area DA and the non-display area NDA.

[0117] Next, a gate electrode 222 made of a conductive material may be formed on the inorganic buffer layer 242 in the display area DA.

[0118] A gate insulating layer 243 made of an inorganic insulating material may be formed on the gate electrode 222 and may be disposed in both the display area DA and the non-display area NDA.

[0119] The semiconductor layer 224 may be formed on the gate insulating layer 243 corresponding to the gate electrode 222. The semiconductor layer 224 may be formed of an oxide semiconductor material. Alternatively, the semiconductor layer 224 may be formed of amorphous silicon.

[0120] Next, a source electrode 226 and a drain electrode 228 formed of a conductive material may be formed on the semiconductor layer 224 .

[0121] The gate electrode 222 , the semiconductor layer 224 , the source electrode 226 , and the drain electrode 228 may constitute a thin film transistor T2 .

[0122] The data line 229 made of the same material as the source electrode 226 and the drain electrode 228 may be formed on the gate insulating layer 243. In addition, a semiconductor pattern made of the same material as the semiconductor layer 224 may be formed between the gate insulating layer 243 and the data line 229.

[0123] A protective layer 244 made of an inorganic insulating material may be formed on the source electrode 226 and the drain electrode 228 and may be disposed in both the display area DA and the non-display area NDA.

[0124] A planarization layer 245 made of an organic insulating material may be formed on the protective layer 244 and may be disposed in both the display area DA and the non-display area NDA. The planarization layer 245 may have a flat top surface.

[0125] The planarization layer 245 may have a first contact hole 245a formed at a position corresponding to a portion of the drain electrode 228. Here, the first contact hole 245a may be formed to expose a portion of the top surface of the protection layer 244.

[0126] In addition, the planarization layer 245 may have a groove 245 b in the non-display area NDA, and an edge portion of the planarization layer 245 may be removed to expose the top surface of the protection layer 244 thereunder.

[0127] A buffer layer 246 made of an insulating material may be formed on the planarization layer 245. The buffer layer 246 may be formed on substantially the entire surface of the first substrate 212 and may be disposed in both the display area DA and the non-display area NDA. In the display area DA, the buffer layer 246 may be in contact with the side surface of the planarization layer 245. In addition, in the non-display area NDA, the buffer layer 246 may be in contact with the side surface of the planarization layer 245 and the top surface of the protective layer 244. The buffer layer 246 may be made of an inorganic insulating material (e.g., silicon nitride (SiN x) or silicon oxide (SiO2)) is formed.

[0128] A touch line 236 made of a conductive material may be formed on the buffer layer 246. The touch line 236 may overlap the data line 229. The touch line 236 may be formed of aluminum (Al), molybdenum (Mo), nickel (Ni), chromium (Cr), copper (Cu), neodymium (Nd), titanium (Ti), or an alloy thereof. For example, the touch line 236 may have a double-layer structure including molybdenum titanium (MoTi) and copper (Cu) layers. However, the inventive concepts of the present disclosure are not limited to this example. For example, in an embodiment, the touch line 236 may be configured to have a single-layer or triple-layer structure.

[0129] A touch insulating layer 247 made of an insulating material may be formed on the touch line 236. The touch insulating layer 247 may be formed on substantially the entire surface of the first substrate 212 and may be disposed in both the display area DA and the non-display area NDA. The touch insulating layer 247 may be made of an inorganic insulating material (e.g., silicon nitride (SiN x ) or silicon oxide (SiO2)) is formed.

[0130] The touch insulation layer 247 may have a touch contact hole 247 a formed to expose the touch wire 236 .

[0131] The common electrode 234 may be formed on the touch insulating layer 247. The common electrode 234 may be formed of a transparent conductive material (e.g., ITO or IZO). The common electrode 234 may contact the touch line 236 through the touch contact hole 247a. The common electrode 234 may be patterned to include a plurality of patterns respectively arranged in corresponding touch blocks, and may be used as a touch electrode that receives a touch drive voltage through the touch line 236 and transmits a touch sensing voltage to the touch line 236.

[0132] A passivation layer 248 made of an inorganic insulating material may be formed on the common electrode 234 and may be disposed in both the display area DA and the non-display area NDA.

[0133] In the display area DA, the passivation layer 248 may have a second contact hole 248a formed to expose the drain electrode 228. Here, the second contact hole 248a may be formed not only in the touch insulation layer 247 but also in the buffer layer 246 and the protection layer 244.

[0134] A pixel electrode 232 made of a conductive material may be formed on the passivation layer 248. The pixel electrode 232 may be formed of a transparent conductive material such as ITO or IZO.

[0135] The pixel electrode 232 may include a plurality of patterns and may overlap the common electrode 234. The pixel electrode 232 may contact the drain electrode 228 through a second contact hole 248a formed in the first contact hole 245a.

[0136] In the present embodiment, the second contact hole 248a has been described as being separated from the first contact hole 245a, but in an embodiment of the present disclosure, the second contact hole 248a and the first contact hole 245a may be provided to form a single hole.

[0137] Bump 249 may be formed on pixel electrode 232. Bump 249 may be formed of an organic insulating material. As an example, bump 249 may be formed of photoacrylic, benzocyclobutene (BCB), polyimide (PI), or polyamide (PA), but the inventive concept of the present disclosure is not limited to this example. In an embodiment, bump 249 may be omitted.

[0138] In addition, a plurality of driving lines 252 , at least one data link line 254 , and at least one touch link line 237 may be provided in the non-display area NDA.

[0139] The driving line 252 may include a plurality of patterns formed in the same layer and of the same material as the gate 222 or the source 226 and drain 228. The driving line 252 may include a common line, a test line, and a gate driving part provided in the form of a GIP.

[0140] Here, the gate driving part may be disposed between the inorganic buffer layer 242 and the protective layer 244 , and the inorganic buffer layer 242 may have a step difference between the display area DA and the gate driving part.

[0141] The data link line 254 may include a plurality of patterns formed in the same layer and of the same material as the gate 222 or the source and drain electrodes 226 and 228 and may be connected to the data line 329 in the display area DA.

[0142] In addition, the touch link line 237 may be formed in the same layer and of the same material as the touch line 236 in the display area DA, and may be connected to the touch line 236 .

[0143] Next, the second substrate 262 may be disposed to be spaced apart from the first substrate 212, and a black matrix 264 may be formed on an inner surface of the second substrate 262. The black matrix 264 may be formed in an area corresponding to a boundary of each sub-pixel in the display area DA and may be formed in the entire non-display area NDA.

[0144] The black matrix 264 may be formed of a black resin or an optically reflective metal.

[0145] The color filter layer 265 may be formed on the black matrix 264 in the display area DA. The color filter layer 265 may include red, green, and blue color filters, and here, each of the color filters may be disposed to correspond to one of the sub-pixels.

[0146] An overcoat layer 266 made of an insulating material may be formed on the color filter layer 265 and may be disposed in the display area DA and the non-display area NDA. In the non-display area NDA, the overcoat layer 266 may contact the black matrix 264.

[0147] A column spacer 267 made of an insulating material may be formed on the overcoat layer 266. The column spacer 267 may be formed to correspond to the black matrix 264 in the display area DA and may be configured to maintain a cell gap between the array substrate 210 and the color filter substrate 260. The column spacer 267 may be formed at a position corresponding to the bump 249 of the array substrate 210 and may be in contact with the bump 249.

[0148] In addition, an ESD prevention layer 268 made of a transparent conductive material (eg, ITO or IZO) may be formed on the outer surface of the second substrate 262 to cover substantially the entire surface of the second substrate 262 .

[0149] The liquid crystal layer 270 may be disposed between the array substrate 210 and the color filter substrate 260 .

[0150] In addition, a seal pattern 280 may be formed between the array substrate 210 and the color filter substrate 260, particularly in the non-display area NDA between the passivation layer 248 and the overcoat layer 266. The seal pattern 280 may be formed to surround the display area DA and prevent liquid crystal leakage. The seal pattern 280 may be formed at a position corresponding to the groove 245b of the planarization layer 245, and in this case, the contact area between the seal pattern 280 and the array substrate 210 may be increased by the groove 245b.

[0151] Although not shown, a backlight unit (not shown) may be disposed under the color filter substrate 260 and may be configured to transmit photons to the liquid crystal panel.

[0152] In the LCD device according to the second embodiment of the present disclosure, it is possible to implement an integrated touch screen by providing the touch line 236 in the first substrate 212 of the array substrate 210 and connecting the touch line 236 to the touch electrode (eg, the common electrode 234 ).

[0153] In addition, the structure of the touch line and the touch electrode can be changed. Figures 6 to 9 Such a liquid crystal panel according to the third embodiment of the present disclosure is described in more detail.

[0154] [Third embodiment]

[0155] Figure 6 is a plan view schematically illustrating a liquid crystal panel of an LCD device according to a third embodiment of the present disclosure.

[0156] like Figure 6 As shown in , the liquid crystal panel of the LCD device according to the third embodiment of the present disclosure may include a display area DA for displaying an image and a non-display area NDA disposed to surround the display area DA.

[0157] In the display area DA, a plurality of sub-pixels SP may be arranged in a matrix shape. Each of the sub-pixels SP may be configured to receive signals through a gate line (not shown), a data line (not shown), and a power line (not shown). Each of the sub-pixels SP may include a thin film transistor and a liquid crystal capacitor, and the detailed structure of the sub-pixels SP will be described in more detail below.

[0158] In addition, a touch line (not shown) may be provided in the display area DA and may be used to transmit a touch driving voltage and a touch sensing voltage.

[0159] The gate driving part GD and the touch display driving part DIC may be disposed in the non-display area NDA to generate a signal or receive a signal from an external driving printed circuit board (PCB) and / or apply a signal to each of the subpixels SP in the display area DA.

[0160] The gate drive section GD can be set to Figure 6 The gate driver GD may be configured to generate a gate signal and apply the gate signal to the gate line. In an embodiment, the gate driver GD may be formed on the same substrate as the thin film transistors in the display area DA, or may be provided in the form of a GIP.

[0161] The touch display driver DIC can be placed in Figure 6 The non-display area NDA is shown in the lower part and can be provided in the form of an integrated circuit (IC).

[0162] The touch display driver DIC can be configured to generate and apply data signals to the data lines, apply touch drive voltages to the touch lines, and receive touch sensing voltages transmitted from the touch electrodes via the touch lines. Furthermore, the touch display driver DIC can be connected to the gate driver GD and signal lines SL to transmit power voltages and control signals required to operate the LCD device.

[0163] In addition, a plurality of signal lines SL, at least one data link line 354 , and at least one touch link line 337 may be provided in the non-display area NDA.

[0164] The plurality of signal lines SL may include common lines and test lines for transmitting a common voltage and a test voltage to the display area DA, and may be formed to surround the display area DA.

[0165] The data link line 354 can be set in the lower part of the non-display area NDA to connect the data line in the display area DA to the touch display driving part DIC, and the touch link line 337 can be set in the lower part of the non-display area NDA to connect the touch line in the display area DA to the touch display driving part DIC.

[0166] In addition, a seal pattern 380 may be formed in the non-display area NDA to surround the display area DA, and in this case, it may be possible to prevent liquid crystal from leaking from the display area DA. Here, the gate driver GD may be arranged in an area located inside the seal pattern 380 (e.g., between the seal pattern 380 and the display area DA), and the touch display driver DIC may be arranged in an area located outside the seal pattern 380. That is, the seal pattern 380 may be arranged between the display area DA and the touch display driver DIC.

[0167] In addition, at least one of the signal lines SL may overlap the seal pattern 380 , and the data link line 354 and the touch link line 337 may be disposed to cross the seal pattern 380 .

[0168] Silver dots 390 may be provided at opposite ends of the lower portion of the non-display area (NDA). The silver dots 390 may be formed by forming a metal paste using a dotting method, and may connect the ESD prevention layer of the color filter substrate to the pads of the array substrate. In this case, electrostatic current generated in the color filter substrate may be discharged to the outside through the silver dots 390.

[0169] Will refer to Figures 7 to 9 A cross-sectional structure of a liquid crystal panel of an LCD device according to a third embodiment of the present disclosure is described.

[0170] Figure 7 、 Figure 8 and Figure 9 : is a cross-sectional view schematically illustrating a liquid crystal panel of an LCD device according to a third embodiment of the present disclosure. For example, Figure 7 Illustrated with Figure 6 The cross-sectional structure of the area "B1" corresponding to the sub-pixel in the display area, Figure 8 Illustrated with Figure 6The cross-sectional structure of the region "B2" corresponding to the gate driving portion in the non-display region is shown in FIG. Figure 9 Illustrated with Figure 6 FIG3 is a cross-sectional structure of an area "B3" corresponding to a link portion in a non-display area of ​​FIG3 . Aside from structural differences associated with the touch lines, the buffer layer, and the touch insulation layer, the liquid crystal panel of the LCD device according to the third embodiment of the present disclosure can be configured to have a structure substantially the same as that in the first embodiment. To avoid repeated overlapping descriptions, the same elements as in the first embodiment will be identified by the same reference numerals.

[0171] like Figure 7 、 Figure 8 and Figure 9 As shown in , the liquid crystal panel of the LCD device according to the third embodiment of the present disclosure may include an array substrate 310, a color filter substrate 360, and a liquid crystal layer 370 located between the two substrates 310 and 360, and the color filter substrate 360 ​​may be arranged between the array substrate 310 and the backlight unit (not shown).

[0172] The array substrate 310 may include a first substrate 312 , an organic buffer layer 341 , a thin film transistor T3 , a pixel electrode 332 , a common electrode 334 and a touch line 336 , and the color filter substrate 360 ​​may include a second substrate 362 , a black matrix 364 , a color filter layer 365 and an overcoat layer 366 .

[0173] In detail, the display area DA and the non-display area NDA may be defined in the first substrate 312 of the array substrate 310 and the second substrate 362 of the color filter substrate 360. The first substrate 312 and the second substrate 362 may be formed of at least one of glass or plastic material.

[0174] An organic buffer layer 341 may be formed on the inner surface of the first substrate 312. The organic buffer layer 341 may be formed of an organic insulating material and may be disposed in the display area DA. As an example, the organic buffer layer 341 may be formed of polyimide (PI), polyamide (PA), photoacrylic, or benzocyclobutene (BCB), but the inventive concept of the present disclosure is not limited to this example.

[0175] The thickness of the organic buffer layer 341 may range from to 50 μm, preferably from to 20 μm, and more preferably from To 1μm.

[0176] The inorganic buffer layer 342 may be formed on the organic buffer layer 341. The inorganic buffer layer 342 may be formed on substantially the entire surface of the first substrate 312 and may be disposed in both the display area DA and the non-display area NDA. The inorganic buffer layer 342 may be made of silicon nitride (SiN x ) or silicon oxide (SiO2) is formed.

[0177] The inorganic buffer layer 342 may contact the organic buffer layer 341 in the display area DA, may contact the first substrate 312 in the non-display area NDA, and may have a step difference near a boundary between the display area DA and the non-display area NDA.

[0178] Next, a gate electrode 322 made of a conductive material may be formed on the inorganic buffer layer 342 of the display area DA.

[0179] A gate insulating layer 343 made of an inorganic insulating material may be formed on the gate electrode 322 and may be disposed in both the display area DA and the non-display area NDA.

[0180] The semiconductor layer 324 may be formed on the gate insulating layer 343 corresponding to the gate electrode 322. The semiconductor layer 324 may be formed of an oxide semiconductor material. Alternatively, the semiconductor layer 324 may be formed of amorphous silicon.

[0181] Next, a source electrode 326 and a drain electrode 328 formed of a conductive material may be formed on the semiconductor layer 324 .

[0182] The gate electrode 322 , the semiconductor layer 324 , the source electrode 326 , and the drain electrode 328 may constitute a thin film transistor T3 .

[0183] The data line 329 made of the same material as the source electrode 326 and the drain electrode 328 may be formed on the gate insulating layer 343. In addition, a semiconductor pattern made of the same material as the semiconductor layer 324 may be formed between the gate insulating layer 343 and the data line 329.

[0184] A protective layer 344 made of an inorganic insulating material may be formed on the source electrode 326 and the drain electrode 328 , and may be disposed in both the display area DA and the non-display area NDA.

[0185] A planarization layer 345 made of an inorganic insulating material may be formed on the protective layer 344 and may be disposed in both the display area DA and the non-display area NDA. The planarization layer 345 may have a flat top surface.

[0186] The planarization layer 345 may have a first contact hole 345a formed at a position corresponding to a portion of the drain electrode 328. In an embodiment, the first contact hole 345a may be formed to expose a portion of the top surface of the protection layer 344.

[0187] In addition, the planarization layer 345 may be formed to have a groove 345 b in the non-display area NDA, and an edge portion of the planarization layer 345 may be removed to expose a top surface of the protection layer 344 thereunder.

[0188] The common electrode 334 may be formed on the planarization layer 345. The common electrode 334 may be formed of a transparent conductive material (eg, ITO or IZO). The common electrode 334 may be patterned to include a plurality of patterns respectively disposed in corresponding touch blocks and may be used as a touch electrode.

[0189] In addition, a buffer layer made of an inorganic insulating material may be further formed between the planarization layer 345 and the common electrode 334 .

[0190] A touch insulating layer 347 made of an inorganic insulating material may be formed on the common electrode 334 and may be disposed in both the display area DA and the non-display area NDA. In the display area DA, the touch insulating layer 347 may contact the side surfaces of the planarization layer 345. Furthermore, in the non-display area NDA, the touch insulating layer 347 may contact the side surfaces of the planarization layer 345 and the top surface of the protective layer 344.

[0191] A touch line 336 made of a conductive material may be formed on the touch insulation layer 347. The touch line 336 may overlap the data line 329.

[0192] A passivation layer 348 made of an inorganic insulating material may be formed on the touch line 336 and may be disposed in both the display area DA and the non-display area NDA.

[0193] In the display area DA, the passivation layer 348 may have a second contact hole 348a formed to expose the drain electrode 328. Here, the second contact hole 348a may also be formed in the touch insulation layer 347 and the protective layer 344. In addition, the passivation layer 348 may have a touch contact hole 348b formed to expose the touch line 336 and the common electrode 334. The touch contact hole 348b may also be formed in the touch insulation layer 347.

[0194] A pixel electrode 332 made of a conductive material may be formed on the passivation layer 348. The pixel electrode 332 may be formed of a transparent conductive material such as ITO or IZO.

[0195] The pixel electrode 332 may include a plurality of patterns and may overlap the common electrode 334. The pixel electrode 332 may contact the drain electrode 328 through a second contact hole 348a formed in the first contact hole 345a.

[0196] In addition, a touch connection electrode 338 made of the same material as the pixel electrode 332 may be formed on the passivation layer 348. The touch connection electrode 338 may make contact with the common electrode 334 and the touch line 336 through the touch contact hole 348b.

[0197] Accordingly, the common electrode 334 may be connected to the touch line 336 and may be used as a touch electrode that receives a touch driving voltage through the touch line 336 and transmits a touch sensing voltage to the touch line 336 .

[0198] In addition, a plurality of driving lines 352 , at least one data link line 354 , and at least one touch link line 337 may be provided in the non-display area NDA.

[0199] The driving line 352 may include a plurality of patterns formed in the same layer and of the same material as the gate 322 or the source 326 and drain 328. The driving line 352 may include a common line, a test line, and a gate driver provided in the form of a GIP.

[0200] Here, the gate driving part may be disposed between the inorganic buffer layer 342 and the protective layer 344 , and the inorganic buffer layer 342 may have a step difference between the display area DA and the gate driving part.

[0201] The data link line 354 may include a plurality of patterns formed in the same layer and of the same material as the source electrode 326 and the drain electrode 328. The data link line 354 may be connected to the data line 329 in the display area DA.

[0202] In addition, the touch link line 337 may be formed in the same layer and of the same material as the touch line 336 in the display area DA, and may be connected to the touch line 336 .

[0203] Next, the second substrate 362 may be disposed to be spaced apart from the first substrate 312, and a black matrix 364 may be formed on an inner surface of the second substrate 362. The black matrix 364 may be formed in an area corresponding to a boundary of each sub-pixel in the display area DA and may be formed in the entire non-display area NDA.

[0204] The black matrix 364 may be formed of a black resin or an optically reflective metal.

[0205] The color filter layer 365 may be formed on the black matrix 364 in the display area DA. The color filter layer 365 may include red, green, and blue color filters, and each of the color filters may be disposed to correspond to one of the sub-pixels.

[0206] An overcoat layer 366 made of an insulating material may be formed on the color filter layer 365 and may be disposed in the display area DA and the non-display area NDA. In the non-display area NDA, the overcoat layer 366 may contact the black matrix 364.

[0207] Column spacers 367 made of an insulating material may be formed on the overcoat layer 366. The column spacers 367 may be formed to correspond to the black matrix 364 in the display area DA and may be configured to maintain a cell gap between the array substrate 310 and the color filter substrate 360.

[0208] In addition, an ESD prevention layer 368 made of a transparent conductive material (eg, ITO or IZO) may be formed on the outer surface of the second substrate 362 to cover substantially the entire surface of the second substrate 362 .

[0209] The liquid crystal layer 370 may be disposed between the array substrate 310 and the color filter substrate 360 ​​.

[0210] In addition, a seal pattern 380 may be formed between the array substrate 310 and the color filter substrate 360, particularly in the non-display area NDA between the passivation layer 348 and the overcoat layer 366. The seal pattern 380 may be provided to surround the display area DA and prevent liquid crystal leakage. The seal pattern 380 may be formed at a position corresponding to the groove 345b of the planarization layer 345, and in this case, the contact area between the seal pattern 380 and the array substrate 310 may be increased by the groove 345b.

[0211] Although not shown, a backlight unit (not shown) may be disposed under the color filter substrate 360 ​​to transmit photons to the liquid crystal panel.

[0212] In the LCD device according to the third embodiment of the present disclosure, it is possible to implement an integrated touch screen by providing a touch line 336 in the first substrate 312 of the array substrate 310 and connecting the touch line 336 to a touch electrode (eg, the common electrode 334 ).

[0213] According to the above-mentioned embodiments of the present disclosure, the black matrix 164, 264 or 364 may be formed of an optically reflective metal, and this may make it possible to increase the brightness of the panel. Here, the electromagnetic coupling caused by the metal black matrix may induce an additional electric field in the liquid crystal layer, or may affect the electric field induced in the liquid crystal layer, and in this case, the brightness of the pixel that should be in the black state may increase, resulting in a decrease in the contrast of the pixel. Hereinafter, reference will be made to Figures 10 to 16 The fourth to ninth embodiments are described in more detail. In each of the fourth to ninth embodiments, the LCD device is configured to shield an electric field caused by a metallic black matrix.

[0214] [Fourth embodiment]

[0215] Figure 10 is a cross-sectional view schematically illustrating a liquid crystal panel of an LCD device according to a fourth embodiment of the present disclosure, and except for a structure for applying a voltage to a black matrix, the liquid crystal panel of the LCD device according to the fourth embodiment of the present disclosure can be configured to have substantially the same features as those in the first embodiment. In the following description, for the sake of brevity, previously described elements will be identified by the same reference numerals without repeating their overlapping descriptions.

[0216] like Figure 10 As shown in , the liquid crystal panel of the LCD device according to the fourth embodiment of the present disclosure may include an array substrate 410, a color filter substrate 460, and a liquid crystal layer 470 located between the two substrates 410 and 460, and the color filter substrate 460 may be arranged between the array substrate 410 and the backlight unit (not shown).

[0217] The array substrate 410 may include a first substrate 412, an organic buffer layer 441, a thin film transistor (not shown), a pixel electrode (not shown) and a common electrode (not shown), and the color filter substrate 460 may include a second substrate 462, a black matrix 464, a color filter layer 465 and an outer coating layer 466.

[0218] In detail, the display area DA and the non-display area NDA may be defined in the first substrate 412 of the array substrate 410 and the second substrate 462 of the color filter substrate 460. The first substrate 412 and the second substrate 462 may be formed of at least one of glass or plastic material.

[0219] An organic buffer layer 441 may be formed on the inner surface of the first substrate 412. The organic buffer layer 441 may be formed of an organic insulating material and may be disposed in the display area DA. As an example, the organic buffer layer 441 may be formed of polyimide (PI), polyamide (PA), photoacrylic, or benzocyclobutene (BCB), but the inventive concept of the present disclosure is not limited to this example.

[0220] The thickness of the organic buffer layer 441 may range from to 50 μm, preferably from to 20 μm, and more preferably from To 1μm.

[0221] The inorganic buffer layer 442 may be formed on the organic buffer layer 441. The inorganic buffer layer 442 may be formed on substantially the entire surface of the first substrate 412 and may be disposed in both the display area DA and the non-display area NDA. The inorganic buffer layer 442 may be made of silicon nitride (SiN x ) or silicon oxide (SiO2) is formed.

[0222] The inorganic buffer layer 442 may contact the organic buffer layer 441 in the display area DA, may contact the first substrate 412 in the non-display area NDA, and may have a step difference near a boundary between the display area DA and the non-display area NDA.

[0223] Next, a gate insulating layer 443 made of an inorganic insulating material may be formed on the inorganic buffer layer 442 and may be disposed in both the display area DA and the non-display area NDA.

[0224] A protective layer 444 made of an inorganic insulating material may be formed on the gate insulating layer 443 and may be disposed in both the display area DA and the non-display area NDA.

[0225] Although not shown, a thin film transistor may be formed between the inorganic buffer layer 442 and the protective layer 444 provided in the display area DA.

[0226] In addition, a plurality of driving lines 452 may be provided in the non-display area NDA. The driving lines 452 may include a plurality of patterns provided in the display area DA and formed in the same layer and from the same material as the gate electrode (not shown) between the inorganic buffer layer 442 and the gate insulating layer 443, or formed in the same layer and from the same material as the source electrode and drain electrode (not shown) between the gate insulating layer 443 and the protective layer 444. The driving lines 452 may include a signal line and a gate driver provided in the form of a GIP.

[0227] Here, the gate driving part may be disposed between the inorganic buffer layer 442 and the protective layer 444 , and the inorganic buffer layer 442 may have a step difference between the display area DA and the gate driving part.

[0228] In addition, the auxiliary pad 492 may be disposed in the non-display area NDA and may include a plurality of patterns formed in the same layer and of the same material as the gate or source and drain electrodes.

[0229] Next, a planarization layer 445 made of an organic insulating material may be formed on the protective layer 444 and may be disposed in both the display area DA and the non-display area NDA. The planarization layer 445 may have a flat top surface.

[0230] The planarization layer 445 may be formed to have a groove 445 b in the non-display area NDA, and an edge portion of the planarization layer 445 may be removed to expose a top surface of the protection layer 444 thereunder.

[0231] A passivation layer 448 made of an inorganic insulating material may be formed on the planarization layer 445 and may be disposed in both the display area DA and the non-display area NDA. In the non-display area NDA, the passivation layer 448 may have an auxiliary contact hole 448b exposing the auxiliary pad 492. Here, the auxiliary contact hole 448b may also be formed in the planarization layer 445 and the protective layer 444.

[0232] Although not shown, a common electrode made of a conductive material may be formed between the planarization layer 445 and the passivation layer 448 in the display area DA. In addition, a pixel electrode made of a conductive material may be formed on the passivation layer 448. The common electrode and the pixel electrode may be formed of a transparent conductive material (e.g., ITO or IZO).

[0233] In addition, an auxiliary electrode 494 made of the same material as the pixel electrode may be formed in the non-display area NDA on the passivation layer 448. The auxiliary electrode 494 may contact the auxiliary pad 492 through the auxiliary contact hole 448b.

[0234] Next, a second substrate 462 may be disposed to be spaced apart from the first substrate 412, and a black matrix 464 may be formed on an inner surface of the second substrate 462. The black matrix 464 may be formed in an area corresponding to a boundary of each sub-pixel in the display area DA and may be formed in the entire non-display area NDA.

[0235] The black matrix 464 may be formed of an optically reflective metal. For example, the black matrix 464 may be formed of aluminum (Al) or silver (Ag) having a relatively high reflectivity, but the inventive concept of the present disclosure is not limited to this example.

[0236] The color filter layer 465 may be formed on the black matrix 464 in the display area DA. The color filter layer 465 may include red, green, and blue color filters, and each of the color filters may be disposed to correspond to one of the sub-pixels.

[0237] An overcoat layer 466 made of an insulating material may be formed on the color filter layer 465 and may be disposed in the display area DA and the non-display area NDA. In the non-display area NDA, the overcoat layer 466 may be in contact with the black matrix 464.

[0238] In addition, an ESD prevention layer 468 made of a transparent conductive material (e.g., ITO or IZO) may be formed on the outer surface of the second substrate 462 in both the display area DA and the non-display area NDA. In an embodiment, a portion of the ESD prevention layer 468 may be removed from an edge portion of the non-display area NDA to expose the outer surface of the second substrate 462.

[0239] The liquid crystal layer 470 may be disposed between the array substrate 410 and the color filter substrate 460 .

[0240] In addition, a seal pattern 480 may be formed between the array substrate 410 and the color filter substrate 460, particularly in the non-display area NDA between the passivation layer 448 and the overcoat layer 466. The seal pattern 480 may be provided to surround the display area DA and prevent liquid crystal from leaking from the display area DA. The seal pattern 480 may be formed at a position corresponding to the groove 445b of the planarization layer 445, and in this case, the contact area between the seal pattern 480 and the array substrate 410 may be increased by the groove 445b.

[0241] The connection pattern 490 can be formed in an area located outside the seal pattern 480. The connection pattern 490 can contact the auxiliary electrode 494 of the array substrate 410 and the black matrix 464 of the color filter substrate 460. Accordingly, the connection pattern 490 can electrically connect the auxiliary pad 492 to the black matrix 464, and in this case, a specific voltage (e.g., a fixed DC voltage) can be applied to the black matrix 464 through the auxiliary pad 492. As an example, the common voltage of the common electrode can be applied to the black matrix 464, but the inventive concept of the present disclosure is not limited to this example. The connection pattern 490 can be composed of silver dots. The connection pattern 490 can contact the side surface and outer surface of the second substrate 462, and can contact the outer coating 466 and the side surface of the black matrix 464. The connection pattern 490 can be spaced apart from the ESD prevention layer 468.

[0242] Although not shown, a backlight unit (not shown) may be disposed under the color filter substrate 460 and may be configured to transmit photons to the liquid crystal panel.

[0243] In the above-mentioned LCD device according to the fourth embodiment of the present disclosure, by forming the black matrix 464 with a metal material, it is possible to increase the brightness of the device, and further by applying a specific voltage to the black matrix 464, it is possible to shield the influence of the electric field that may be caused by the black matrix 464.

[0244] [Fifth embodiment]

[0245] Figure 11 is a cross-sectional view schematically illustrating a liquid crystal panel of an LCD device according to a fifth embodiment of the present disclosure, and except for some differences associated with an overcoat layer and a connection pattern, the liquid crystal panel of the LCD device according to the fifth embodiment of the present disclosure can be configured to have the same features as the liquid crystal panel of the LCD device in the fourth embodiment. In the following description, for the sake of brevity, previously described elements will be identified by the same reference numerals, and overlapping descriptions thereof will not be repeated.

[0246] like Figure 11 As shown in , the liquid crystal panel of the LCD device according to the fifth embodiment of the present disclosure may include an array substrate 410, a color filter substrate 460, and a liquid crystal layer 470 located between the two substrates 410 and 460, and the color filter substrate 460 may be arranged between the array substrate 410 and the backlight unit (not shown).

[0247] An organic buffer layer 441, an inorganic buffer layer 442, a gate insulating layer 443, a protective layer 444, a planarization layer 445, and a passivation layer 448 may be sequentially formed on the inner surface of the first substrate 412 in the array substrate 410. In addition, a plurality of driving lines 452, at least one auxiliary pad 492, and at least one auxiliary electrode 494 may be formed on the first substrate 412 in the non-display area NDA.

[0248] A black matrix 464 , a color filter layer 465 , and an overcoat layer 566 may be sequentially formed on an inner surface of a second substrate 462 in the color filter substrate 460 , and an ESD prevention layer 468 may be formed on an outer surface of the second substrate 462 .

[0249] Here, an edge portion of the overcoat layer 566 may be removed to partially expose a top surface of the black matrix 464 in the non-display area NDA.

[0250] A liquid crystal layer 470 may be disposed between the array substrate 410 and the color filter substrate 460 , and a seal pattern 480 may be formed between the array substrate 410 and the color filter substrate 460 in the non-display area NDA.

[0251] The connection pattern 590 may be formed outside the seal pattern 480. The connection pattern 590 may contact the auxiliary electrode 494 of the array substrate 410 and the black matrix 464 of the color filter substrate 460. Here, the connection pattern 590 may contact the side surface and outer surface of the second substrate 462, may contact the overcoat layer 566 and the side surface of the black matrix 464, and may also contact the top surface of the black matrix 464 exposed by the overcoat layer 566.

[0252] Accordingly, the connection pattern 590 may electrically connect the auxiliary pad 492 to the black matrix 464, and a specific voltage may be applied to the black matrix 464 through the auxiliary pad 492. As an example, a common voltage may be applied to the black matrix 464, but the inventive concept of the present disclosure is not limited to this example.

[0253] The connection pattern 590 may be formed of silver dots.

[0254] In the LCD device according to the fifth embodiment of the present disclosure, by increasing the contact area between the black matrix 464 and the connection pattern 590 , it may be possible to stably apply a voltage to the black matrix 464 .

[0255] [Sixth embodiment]

[0256] Figure 12 is a cross-sectional view schematically illustrating a liquid crystal panel of an LCD device according to a sixth embodiment of the present disclosure, and except for the connection structure between the shielding electrode and the conductive seal pattern, the liquid crystal panel of the LCD device according to the sixth embodiment of the present disclosure can be configured to have substantially the same features as the liquid crystal panel of the LCD device in the fourth embodiment. In the following description, for the sake of brevity, previously described elements will be identified by the same reference numerals, and overlapping descriptions thereof will not be repeated.

[0257] like Figure 12 As shown in , the liquid crystal panel of the LCD device according to the sixth embodiment of the present disclosure may include an array substrate 410, a color filter substrate 460, and a liquid crystal layer 470 located between the two substrates 410 and 460, and the color filter substrate 460 may be arranged between the array substrate 410 and the backlight unit (not shown).

[0258] An organic buffer layer 441, an inorganic buffer layer 442, a gate insulating layer 443, a protective layer 444, a planarization layer 445, and a passivation layer 448 may be sequentially formed on the inner surface of the first substrate 412 in the array substrate 410. In addition, a plurality of driving lines 452, at least one auxiliary pad 692, and at least one auxiliary electrode 694 may be formed on the first substrate 412 in the non-display area NDA, and here, the auxiliary electrode 694 may contact the auxiliary pad 692 through the first auxiliary contact hole 648b.

[0259] A black matrix 464 , a shielding electrode 696 , a color filter layer 465 , and an overcoat layer 666 may be sequentially formed on an inner surface of a second substrate 462 in the color filter substrate 460 , and an ESD prevention layer 468 may be formed on an outer surface of the second substrate 462 .

[0260] Here, the shielding electrode 696 may overlap and contact the black matrix 464. The shielding electrode 696 may be formed of a transparent conductive material and may be formed on substantially the entire surface of the second substrate 462. Alternatively, the shielding electrode 696 may be formed of a metal material, and in this case, the shielding electrode 696 may have the same shape as the black matrix 464 (i.e., a grid shape).

[0261] The overcoat layer 666 may have a second auxiliary contact hole 666 a formed to expose the shielding electrode 696 in the non-display area NDA.

[0262] A liquid crystal layer 470 may be disposed between the array substrate 410 and the color filter substrate 460 , and a seal pattern 480 may be formed between the array substrate 410 and the color filter substrate 460 in the non-display area NDA.

[0263] In addition, a conductive seal pattern 690 may be formed in an area located inside the seal pattern 480 and between the array substrate 410 and the color filter substrate 460 in the non-display area NDA. Here, an auxiliary pad 692 and an auxiliary electrode 694 may also be disposed inside the seal pattern 480.

[0264] The conductive seal pattern 690 may contact the auxiliary electrode 694 of the array substrate 410 and the shielding electrode 696 of the color filter substrate 460. Here, the conductive seal pattern 690 may contact the shielding electrode 696 through the second auxiliary contact hole 666a.

[0265] Thus, the conductive seal pattern 690 may be provided to electrically connect the auxiliary pad 692 to the shielding electrode 696 , and may be used to apply a specific voltage to the shielding electrode 696 through the auxiliary pad 692 .

[0266] In the above-mentioned LCD device according to the sixth embodiment of the present disclosure, by additionally providing a shielding electrode 696 on the black matrix 464 (particularly, between the black matrix 464 and the outer coating 666, or more particularly, between the black matrix 464 and the color filter layer 465) and applying a specific voltage to the shielding electrode 696 through the conductive sealing pattern 690, it is possible to shield the influence of the electric field that may be caused by the black matrix 464.

[0267] [Seventh embodiment]

[0268] Figure 13is a cross-sectional view schematically illustrating a liquid crystal panel of an LCD device according to a seventh embodiment of the present disclosure, and except for the difference in the position of the shielding electrode, the liquid crystal panel of the LCD device according to the seventh embodiment of the present disclosure can be configured to have substantially the same features as the liquid crystal panel of the LCD device in the sixth embodiment. In the following description, for the sake of brevity, previously described elements will be identified by the same reference numerals, and overlapping descriptions thereof will not be repeated.

[0269] like Figure 13 As shown in , the liquid crystal panel of the LCD device according to the seventh embodiment of the present disclosure may include an array substrate 410, a color filter substrate 460, and a liquid crystal layer 470 located between the two substrates 410 and 460, and the color filter substrate 460 may be arranged between the array substrate 410 and the backlight unit (not shown).

[0270] An organic buffer layer 441, an inorganic buffer layer 442, a gate insulating layer 443, a protective layer 444, a planarization layer 445, and a passivation layer 448 may be sequentially formed on the inner surface of the first substrate 412 in the array substrate 410. In addition, a plurality of driving lines 452, at least one auxiliary pad 692, and at least one auxiliary electrode 694 may be formed on the first substrate 412 in the non-display area NDA, and here, the auxiliary electrode 694 may contact the auxiliary pad 692 through the first auxiliary contact hole 648b.

[0271] A black matrix 464 , a color filter layer 465 , a shielding electrode 796 , and an overcoat layer 666 may be sequentially formed on an inner surface of a second substrate 462 in the color filter substrate 460 , and an ESD prevention layer 468 may be formed on an outer surface of the second substrate 462 .

[0272] In the non-display area NDA, the shielding electrode 796 may overlap and contact the black matrix 464. The shielding electrode 796 may be formed of a transparent conductive material and may be formed on substantially the entire surface of the second substrate 462. Alternatively, the shielding electrode 796 may be formed of metal, and in this case, the shielding electrode 796 may have the same shape as the black matrix 464 (e.g., a grid shape).

[0273] The overcoat layer 666 may have a second auxiliary contact hole 666 a formed to expose a portion of the shielding electrode 796 in the non-display area NDA.

[0274] A liquid crystal layer 470 may be disposed between the array substrate 410 and the color filter substrate 460 , and a seal pattern 480 may be formed between the array substrate 410 and the color filter substrate 460 in the non-display area NDA.

[0275] In addition, a conductive seal pattern 690 may be formed in an area located inside the seal pattern 480 and between the array substrate 410 and the color filter substrate 460 in the non-display area NDA. Here, an auxiliary pad 692 and an auxiliary electrode 694 may also be disposed inside the seal pattern 480.

[0276] The conductive seal pattern 690 may contact the auxiliary electrode 694 of the array substrate 410 and the shielding electrode 796 of the color filter substrate 460. Here, the conductive seal pattern 690 may contact the shielding electrode 796 through the second auxiliary contact hole 666a.

[0277] Accordingly, the conductive seal pattern 690 may be provided to electrically connect the auxiliary pad 692 to the shielding electrode 796 , and may be used to apply a specific voltage to the shielding electrode 796 through the auxiliary pad 692 .

[0278] In the above-mentioned LCD device according to the seventh embodiment of the present disclosure, by additionally providing a shielding electrode 796 on the black matrix 464 (particularly, between the black matrix 464 and the outer coating 666, and more particularly, between the color filter layer 465 and the outer coating 666) and applying a specific voltage to the shielding electrode 796 through the conductive sealing pattern 690, it is possible to shield the influence of the electric field that may be caused by the black matrix 464.

[0279] [Eighth Embodiment]

[0280] Figure 14 is a cross-sectional view schematically illustrating a liquid crystal panel of an LCD device according to an eighth embodiment of the present disclosure, and except for the difference in the positions of the overcoat layer and the shielding electrode, the liquid crystal panel of the LCD device according to the eighth embodiment of the present disclosure can be configured to have substantially the same features as the liquid crystal panel of the LCD device in the sixth embodiment. In the following description, for the sake of brevity, previously described elements will be identified by the same reference numerals, and overlapping descriptions thereof will not be repeated.

[0281] like Figure 14 As shown in , the liquid crystal panel of the LCD device according to the eighth embodiment of the present disclosure may include an array substrate 410, a color filter substrate 460, and a liquid crystal layer 470 located between the two substrates 410 and 460, and the color filter substrate 460 may be arranged between the array substrate 410 and the backlight unit (not shown).

[0282] An organic buffer layer 441, an inorganic buffer layer 442, a gate insulating layer 443, a protective layer 444, a planarization layer 445, and a passivation layer 448 may be sequentially formed on the inner surface of the first substrate 412 in the array substrate 410. In addition, a plurality of driving lines 452, at least one auxiliary pad 692, and at least one auxiliary electrode 694 may be formed on the first substrate 412 in the non-display area NDA, and here, the auxiliary electrode 694 may contact the auxiliary pad 692 through the first auxiliary contact hole 648b.

[0283] A black matrix 464 , a color filter layer 465 , an overcoat layer 866 , and a shielding electrode 896 may be sequentially formed on an inner surface of a second substrate 462 in the color filter substrate 460 , and an ESD prevention layer 468 may be formed on an outer surface of the second substrate 462 .

[0284] In the non-display area NDA, the overcoat layer 866 may overlap and contact the black matrix 464 .

[0285] In addition, the shielding electrode 896 on the overcoat layer 866 may be formed of a transparent conductive material and may be formed on substantially the entire surface of the second substrate 462. Alternatively, the shielding electrode 896 may be formed of a metal material, and in this case, the shielding electrode 896 may have the same shape as the black matrix 464 (i.e., a grid shape).

[0286] A liquid crystal layer 470 may be disposed between the array substrate 410 and the color filter substrate 460 , and a seal pattern 480 may be formed between the array substrate 410 and the color filter substrate 460 in the non-display area NDA.

[0287] In addition, a conductive seal pattern 690 may be formed in an area located inside the seal pattern 480 and between the array substrate 410 and the color filter substrate 460 in the non-display area NDA. Here, an auxiliary pad 692 and an auxiliary electrode 694 may also be disposed inside the seal pattern 480.

[0288] The conductive seal pattern 690 may make contact with the auxiliary electrode 694 of the array substrate 410 and the shielding electrode 896 of the color filter substrate 460 .

[0289] Accordingly, the conductive seal pattern 690 may be provided to electrically connect the auxiliary pad 692 to the shielding electrode 896 , and may be used to apply a specific voltage to the shielding electrode 896 through the auxiliary pad 692 .

[0290] In the above-mentioned LCD device according to the eighth embodiment of the present disclosure, by additionally providing a shielding electrode 896 on the black matrix 464 (in particular, on the outer coating 866) and applying a specific voltage to the shielding electrode 896 through the conductive sealing pattern 690, it is possible to shield the influence of the electric field that may be caused by the black matrix 464.

[0291] Will refer to Figure 15 and Figure 16 The structure of the conductive seal pattern 690 is described in more detail.

[0292] [Ninth embodiment]

[0293] Figure 15 is a plan view schematically illustrating an example of a liquid crystal panel of an LCD device according to a ninth embodiment of the present disclosure, and Figure 16 1 is a plan view schematically illustrating another example of a liquid crystal panel of an LCD device according to a ninth embodiment of the present disclosure. Figure 15 and Figure 16 Some elements except the seal pattern and the conductive seal pattern are omitted.

[0294] like Figure 15 and Figure 16 As shown in , the liquid crystal panel of the LCD device according to the ninth embodiment of the present disclosure may include a display area DA for displaying an image and a non-display area NDA disposed to surround the display area DA.

[0295] In the display area DA, a plurality of sub-pixels may be arranged in a matrix shape, and the gate driving part GD may be provided in left and right portions of the non-display area NDA.

[0296] A seal pattern 980 may be formed in the non-display area NDA to surround the display area DA, and in this case, it may be possible to prevent liquid crystal from leaking from the display area DA. Here, the gate driver GD may be disposed in an area located inside the seal pattern 980 or between the seal pattern 980 and the display area DA.

[0297] In addition, a conductive seal pattern 990 may be provided in the non-display area NDA and inside the seal pattern 980, and the conductive seal pattern 990 may be arranged between the seal pattern 980 and the display area DA. The conductive seal pattern 990 may be provided in at least a portion of the non-display area NDA.

[0298] like Figure 15As shown in FIG, the conductive seal pattern 990a may be formed in the left, right, upper, and lower portions of the non-display area NDA to surround the display area DA. Therefore, it may be possible to stably apply a voltage to the color filter substrate.

[0299] Alternatively, if Figure 16 As shown in FIG, the conductive seal pattern 990b may be provided in the upper and lower portions of the non-display area NDA. In this case, it may be possible to increase the area of ​​the display area DA within the same area.

[0300] As described above, in the LCD device of the present disclosure, a color filter substrate may be disposed between the array substrate and the backlight unit to minimize the width or area of ​​the border region, and an organic buffer layer may be disposed between the thin film transistor in the array substrate and the first substrate to improve the mechanical durability of the liquid crystal panel.

[0301] In addition, touch lines connected to the common electrodes may be provided on the array substrate, and this may make it possible to form a touch screen in an integral shape, thereby reducing the weight and thickness of the LCD device.

[0302] Furthermore, by forming the black matrix with a metal material, it may be possible to increase the brightness of the LCD device, and by applying a specific voltage to the black matrix, it may be possible to improve the black brightness characteristics of the LCD device.

[0303] It will be clear to those skilled in the art that various modifications and variations can be made in the display device of the present disclosure without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure is intended to cover modifications and variations of the present disclosure, provided that they fall within the scope of the appended claims and their equivalents.

[0304] CROSS-REFERENCE TO RELATED APPLICATIONS

[0305] This patent application claims the benefit of priority to Korean Patent Application No. 10-2021-0189587 filed in Korea on December 28, 2021, the entire contents of which are incorporated by reference for all purposes as if fully set forth herein.

Claims

1. A liquid crystal display device, comprising: A liquid crystal panel comprising a first substrate provided with a thin film transistor, a second substrate provided with a color filter layer, and a liquid crystal layer located between the first substrate and the second substrate; as well as a backlight unit, the backlight unit being located below the liquid crystal panel, Wherein, the second substrate is arranged between the backlight unit and the first substrate, Wherein, the organic buffer layer is provided between the first substrate and the thin film transistor, A display area and a non-display area surrounding the display area are defined in the first substrate and the second substrate. Wherein, the organic buffer layer is only located in the display area, and Wherein, in the display area, the first substrate is in contact with only the organic buffer layer.

2. The liquid crystal display device according to claim 1, wherein A pixel electrode connected to the thin film transistor, a common electrode overlapping the pixel electrode, a planarization layer between the common electrode and the thin film transistor, and a touch line connected to the common electrode are further provided on the inner surface of the first substrate.

3. The liquid crystal display device according to claim 1, in, The organic buffer layer is partially disposed in the display area.

4. The liquid crystal display device according to claim 1, wherein An inorganic buffer layer is further provided between the organic buffer layer and the thin film transistor.

5. The liquid crystal display device according to claim 4, in, A gate driving portion is further provided in the non-display area of ​​the first substrate, and The inorganic buffer layer has a step difference formed between the display area and the gate driving part.

6. The liquid crystal display device according to claim 1, wherein The thin film transistor includes a gate electrode, a semiconductor layer, a source electrode, and a drain electrode, and Wherein, the semiconductor layer is formed of an oxide semiconductor material.

7. The liquid crystal display device according to claim 1, wherein A black matrix is ​​further provided between the second substrate and the color filter layer, and Wherein, the black matrix is ​​formed of optically reflective metal.

8. The liquid crystal display device according to claim 7, wherein An auxiliary pad is further provided over the inner surface of the first substrate, and the auxiliary pad is electrically connected to the black matrix.

9. The liquid crystal display device according to claim 8, wherein The black matrix is ​​electrically connected to the auxiliary pad through a connection pattern in contact with a side surface and an outer surface of the second substrate.

10. The liquid crystal display device according to claim 9, wherein An overcoat layer is further provided on the color filter layer of the second substrate to expose the top surface of the black matrix, and The connection pattern contacts the top surface and the side surface of the black matrix.

11. The liquid crystal display device according to claim 8, wherein The liquid crystal panel further includes a seal pattern disposed between the first substrate and the second substrate and a conductive seal pattern disposed inside the seal pattern, and The black matrix is ​​electrically connected to the auxiliary pad through the conductive sealing pattern.

12. The liquid crystal display device according to claim 11, wherein A shielding electrode is further provided on the black matrix, and Wherein, the conductive sealing pattern contacts the shielding electrode.

13. The liquid crystal display device according to claim 12, wherein The shielding electrode is located between the black matrix and the color filter layer.

14. The liquid crystal display device according to claim 12, wherein The shielding electrode is located on the color filter layer.

15. The liquid crystal display device according to claim 7, wherein The liquid crystal panel further includes a seal pattern disposed between the first substrate and the second substrate and a conductive seal pattern disposed inside the seal pattern. Wherein, an outer coating layer is further provided on the color filter layer of the second substrate, Wherein, a shielding electrode is further provided on the outer coating layer, and Wherein, the conductive sealing pattern contacts the shielding electrode.

16. The liquid crystal display device according to claim 11, in, The conductive seal pattern is disposed in at least a portion of the non-display area.

17. The liquid crystal display device according to claim 2, wherein: A touch insulating layer disposed between the common electrode and the planarizing layer and a passivation layer disposed between the common electrode and the pixel electrode are further disposed on the inner surface of the first substrate, and Wherein, the touch line is arranged between the planarization layer and the touch insulation layer.

18. The liquid crystal display device according to claim 2, wherein A touch insulating layer disposed between the common electrode and the planarizing layer and a passivation layer disposed between the touch insulating layer and the pixel electrode are further disposed above the inner surface of the first substrate, and Wherein, the touch line is arranged between the touch insulation layer and the passivation layer.

19. The liquid crystal display device according to claim 18, wherein A touch connection electrode is further provided on the inner surface of the first substrate and is formed of the same material as the pixel electrode. wherein a touch contact hole for exposing the touch line and the common electrode is formed in the passivation layer and the touch insulating layer, and The touch connection electrode contacts the common electrode and the touch line through the touch contact hole.

20. The liquid crystal display device according to claim 1, wherein The liquid crystal panel further includes a black matrix disposed above the second substrate, and The organic buffer layer above the first substrate overlaps with the black matrix and the color filter layer above the second substrate.

Images