A low power design method and apparatus for adaptive voltage scaling
By adjusting the critical path and delay margin of analog-digital circuits, and using the sampling clock signal to detect and adjust the supply voltage, the problem of low voltage regulation accuracy in existing technologies is solved, and efficient energy management of digital circuits at the lowest power consumption is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SPL ELECTRONICS TECH CO LTD
- Filing Date
- 2023-03-31
- Publication Date
- 2026-06-02
AI Technical Summary
Existing technologies have low voltage regulation control accuracy when the minimum power consumption voltage of digital circuits is determined, and cannot achieve optimal results under different temperature, process and operating conditions.
By simulating the critical path of the digital circuit, a test clock signal and a sampling clock signal are generated. The output signal of the critical path is sampled using the sampling clock. The power supply voltage of the digital circuit is controlled according to the sampling results to determine the minimum operating voltage. A delay margin adjustment circuit is set before the critical path to adapt to environmental changes.
It improves the control precision and efficiency of voltage regulation, ensuring that digital circuits operate normally with minimal power consumption, thus achieving energy savings.
Smart Images
Figure CN116360537B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of low-power technology, specifically relating to a low-power design method and device with adaptive voltage regulation. Background Technology
[0002] With the rapid development of the Internet of Things (IoT), battery-powered embedded electronic devices are widely used. The functionality of mobile handheld devices, such as smartphones, is also increasing. However, due to the limited battery capacity, the battery life of these electronic devices is gradually attracting attention. Furthermore, for high-performance processors used in applications such as desktop computers and servers, their power consumption under full load has reached its limit, thus restricting further performance improvements and leading to significant heat dissipation costs and energy consumption.
[0003] The main sources of power consumption in CMOS digital circuits include three parts: dynamic power consumption caused by the charging and discharging of parasitic capacitances; short-circuit current power consumption caused by the conduction and short-circuiting of P-type and N-type transistors; and static power consumption caused by leakage current and subthreshold current. These three functions can be abstracted into the following power consumption model:
[0004] P=αC L fV dd 2 +V dd I short +V dd I leakage
[0005] Where f is the operating frequency of the CMOS digital circuit, and C L For the load capacitance, V dd For the operating voltage, I short For short-circuit current, I leakage This is the leakage current.
[0006] According to the classic power consumption formula for CMOS digital circuits, the dynamic power consumption of a chip is proportional to the square of the voltage, and the overall static power consumption is also proportional to the voltage. Therefore, reducing the operating voltage should have the most significant effect on overall power consumption. When the chip's maximum frequency exceeds the predetermined specifications, reducing the voltage can achieve lower power consumption while maintaining performance.
[0007] Current mainstream dynamic voltage regulation technology uses a pre-set table corresponding to frequency and voltage. When power consumption needs to be reduced, the lowest voltage at which the circuit can operate normally, or the lowest frequency at which the circuit can operate normally, is found by looking up the table. Although this technology can dynamically find the lowest frequency and voltage, it still uses a table lookup method for adjustment. The corresponding table cannot contain all optimal situations, so it cannot achieve the optimal voltage regulation effect under different temperature, process, and operating conditions. Summary of the Invention
[0008] The purpose of this invention is to provide a low-power design method and apparatus with adaptive voltage regulation to solve the problem of low voltage regulation control accuracy in the prior art when determining the minimum power consumption voltage of digital circuits.
[0009] To address the aforementioned technical problems, this invention provides a low-power design method with adaptive voltage regulation, comprising the following steps:
[0010] 1) The critical path of an analog-to-digital circuit, whereby the critical path refers to the path with the longest delay in the digital circuit;
[0011] 2) Generate a test clock signal and a sampling clock signal, and input the generated test clock signal into the critical path. Each sampling clock signal is delayed by the test clock signal, and the rising edge of one of the sampling clock signals is the falling edge of the test clock signal. This sampling clock signal is used as the first sampling clock.
[0012] 3) Sample the output signal of the critical path at the rising edge of each sampling clock signal, and control and adjust the power supply voltage of the digital circuit according to the sampling results to determine the minimum operating voltage to ensure the normal operation of the digital circuit, thereby achieving the minimum system power consumption.
[0013] Its beneficial effects are as follows: The method for determining the minimum power consumption voltage of digital circuits in this invention uses the path with the longest simulated delay as the critical path, and uses a simple critical path to characterize complex loads. Its structure is simple and its application range is wide. By using a sampling clock to detect the voltage output of the critical path and controlling and adjusting the circuit power supply voltage according to the detection result, the control accuracy can be improved, the adjustment efficiency can be increased, the minimum voltage to ensure the normal operation of the circuit can be determined, and energy saving can be achieved.
[0014] Furthermore, when sampling the output signal of the critical path signal, sampling nodes with different delays are set, and the power supply of the current digital circuit is determined based on the sampling results of each sampling node, and corresponding adjustments are made.
[0015] Its beneficial effects are as follows: by setting up multiple sampling nodes behind the critical path to sample the voltage, it can determine whether the voltage of the current circuit rises or falls, thereby improving control accuracy, increasing regulation efficiency, determining the minimum voltage to ensure the normal operation of the circuit, and achieving energy savings.
[0016] Furthermore, if the sampling clock with the shortest delay can sample the test clock signal on its rising edge, it indicates that the current power supply voltage of the digital circuit is too high and needs to be stepped down.
[0017] Its beneficial effects are as follows: if the test clock signal is sampled at the rising edge of the sampling clock with the least delay, it indicates that the current power supply voltage of the digital circuit is very high and needs to be stepped down for adjustment. This process can quickly determine the situation of high power supply voltage, improve control accuracy, and increase adjustment efficiency.
[0018] Furthermore, the adjustment process based on the sampling results of each sampling node is as follows:
[0019] Set up n sampling nodes, where the first sampling node is the critical path output signal without delay, the second sampling node is the critical path output signal after one level of delay, and the nth sampling node is the critical path output signal after n-1 levels of delay.
[0020] If the output signal of the first sampling node can be sampled at the rising edge of the first sampling clock, but the output signal of the second sampling node cannot be sampled, it indicates that the timing of the digital circuit meets the requirements, the current voltage is in a critical state, and the current voltage should be boosted. If the output signals of the first and second sampling nodes can be sampled, but the output signal of the third sampling node cannot be sampled, it indicates that the current voltage is just right and no adjustment is needed. If the output signals of the first, second, and third sampling nodes can be sampled, it indicates that the current voltage is high and bucking adjustment is needed. If no output signal is sampled at any sampling node, it indicates that the current voltage is low and boosting adjustment is needed.
[0021] Its beneficial effects are: at the same sampling time, voltage adjustment based on the detection results of each sampling node can improve control accuracy, increase regulation efficiency, determine the minimum voltage to ensure normal circuit operation, and achieve energy saving.
[0022] Furthermore, before inputting the generated test clock signal into the critical path, the method also adjusts the delay margin of the test clock signal so that the test clock signal is input into the critical path after a delay; when adjusting the delay margin, different delay margins are adjusted, and the corresponding delay margin is adaptively selected according to environmental changes.
[0023] Its beneficial effects are as follows: adjusting the delay margin of the test clock signal before the critical path can add a safety margin to the critical path. When adjusting the delay margin, the appropriate delay margin can be selected according to the environmental changes, which can improve the circuit's adaptability, thereby improving control accuracy, increasing regulation efficiency, determining the minimum voltage to ensure the normal operation of the circuit, and achieving energy saving.
[0024] To address the aforementioned technical problems, this invention also provides a low-power design device with adaptive voltage regulation, comprising a pulse generator, a critical path simulation unit, a phase difference detection unit, and a control unit. The critical path simulation unit simulates the critical path of a digital circuit, where the critical path refers to the path with the longest delay in the circuit. The pulse generator generates a test clock signal and a sampling clock signal, and inputs the generated test clock signal into the critical path. Each sampling clock signal is delayed by the test clock signal, and the rising edge of one of the sampling clock signals is the falling edge of the test clock signal; this sampling clock signal is used as the first sampling clock. The phase difference detection unit samples the output signal of the critical path at the rising edge of each sampling clock signal. The control unit controls and adjusts the power supply voltage of the digital circuit based on the sampling results, enabling the power management unit to provide the digital circuit with the lowest power consumption operating voltage.
[0025] Its beneficial effects are as follows: The low-power design device for adaptive voltage regulation of the present invention inputs the test clock signal generated by the pulse generator into the critical path, and uses a simple critical path simulation unit to characterize complex loads. Its structure is simple and its application range is wide. The phase difference detection unit detects the output voltage of the critical path according to the sampling clock signal generated by the pulse generator. The control unit controls the power management unit to adjust the output voltage according to the detection result, which can improve control accuracy, improve regulation efficiency, determine the minimum voltage to ensure the normal operation of the circuit, and achieve energy saving.
[0026] Furthermore, the phase difference detection unit sets sampling nodes with different delays when sampling the output signal of the critical path signal, and determines the current power supply voltage of the digital circuit based on the sampling results of each sampling node, and makes corresponding adjustments.
[0027] Its beneficial effects are as follows: the phase difference detection unit performs voltage sampling on multiple sampling nodes set behind the critical path to determine whether the voltage of the current circuit increases or decreases, which can improve control accuracy, improve regulation efficiency, determine the minimum voltage to ensure the normal operation of the circuit, and achieve energy saving.
[0028] Furthermore, the control unit adjustment criteria include: if the sampling clock with the smallest delay can sample the test clock signal on its rising edge, it indicates that the current power supply voltage of the digital circuit is high and needs to be stepped down.
[0029] Its beneficial effects are as follows: if the test clock signal is sampled at the rising edge of the sampling clock with the least delay, it indicates that the current power supply voltage of the digital circuit is very high and needs to be stepped down for adjustment. This process can quickly determine the situation of high power supply voltage, improve control accuracy, and increase adjustment efficiency.
[0030] Furthermore, the process by which the control unit controls the output voltage of the power management unit based on the detection results is as follows:
[0031] There are n sampling nodes, where the first sampling node is the critical path output signal without delay, the second sampling node is the critical path output signal after one level of delay, and the nth sampling node is the critical path output signal after n-1 levels of delay.
[0032] If the output signal of the first sampling node can be sampled at the rising edge of the first sampling clock, but the output signal of the second sampling node cannot be sampled, it indicates that the timing of the digital circuit meets the requirements, the current voltage is in a critical state, and the current voltage should be boosted. If the output signals of the first and second sampling nodes can be sampled, but the output signal of the third sampling node cannot be sampled, it indicates that the current voltage is just right and no adjustment is needed. If the output signals of the first, second, and third sampling nodes can be sampled, it indicates that the current voltage is high and bucking adjustment is needed. If no output signal is sampled at any sampling node, it indicates that the current voltage is low and boosting adjustment is needed.
[0033] Its beneficial effects are: at the same sampling time, voltage adjustment based on the detection results of each sampling node can improve control accuracy, increase regulation efficiency, determine the minimum voltage to ensure normal circuit operation, and achieve energy saving.
[0034] Furthermore, the device also includes a delay margin adjustment circuit disposed between the pulse generator and the critical path simulation unit. The delay margin adjustment circuit is used to adjust the delay margin of the generated test clock signal before inputting it into the critical path, so that the test clock signal is input into the critical path after a delay. The delay margin adjustment circuit includes a delay line and a selector. The delay line uses inverters in series to simulate different delay lines, and the selector is used to select the corresponding delay margin according to environmental changes.
[0035] Its beneficial effects are as follows: The delay margin adjustment circuit adjusts the delay margin of the test clock signal before the critical path, which can add a safety margin to the critical path. When adjusting the delay margin, the selector selects the corresponding delay margin according to the environmental changes, which can improve the circuit's adaptability, thereby improving control accuracy, increasing adjustment efficiency, determining the minimum voltage to ensure the normal operation of the circuit, and achieving energy saving. Attached Figure Description
[0036] Figure 1 This is a schematic diagram of the digital circuit of the present invention;
[0037] Figure 2 This is a circuit diagram of the pulse generator of the present invention;
[0038] Figure 3 This is a phase relationship diagram of the pulse signal output by the pulse generator of the present invention;
[0039] Figure 4 This is a schematic diagram of multiple critical paths based on delay line load of the present invention;
[0040] Figure 5 This is the phase detection relationship diagram of the present invention when the voltage is too low or too high. Detailed Implementation
[0041] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.
[0042] Examples of low-power design devices with adaptive voltage regulation:
[0043] The present invention provides a low-power design device with adaptive voltage regulation, such as... Figure 1As shown, the system includes a pulse generator, a delay margin adjustment circuit, a critical path simulation unit, a phase difference detection unit, a phase encoding unit, a control unit, and a power management unit. The pulse generator generates a test clock signal and a sampling clock signal, and inputs the generated test clock signal into the critical path. Each sampling clock signal is delayed by the test clock signal, and the rising edge of one of the sampling clock signals is the falling edge of the test clock signal. This sampling clock signal is used as the first sampling clock. The delay margin adjustment circuit adds a safety margin to the critical path. The critical path simulation unit simulates the critical path of the digital circuit, which refers to the path with the longest delay in the circuit. The phase difference detection unit samples the output signal of the critical path using sampling clock signals with the same sampling time and / or different sampling times. The phase encoding unit completes the signal encoding after phase detection. The control unit controls the output voltage of the power management unit in the digital circuit according to the detection result, so that the power management unit provides the lowest power consumption operating voltage for the digital circuit. The power management unit generates the lowest power consumption operating voltage according to the control signal output by the control unit.
[0044] A pulse generator is used to generate the delay line test clock and the sampling clock. The circuit principle of a pulse generator is as follows: Figure 2 As shown, the module includes multiple flip-flops and inverters, capable of generating a clock cycle pulse signal at regular intervals (e.g., 8 clock cycles). This signal serves as the test clock Ctest. Under stable operating conditions, the test clock pulse width is half the target clock frequency. Simultaneously, the module also outputs clock signals with different delays relative to the pulse signal. For example, in this embodiment, the output sampling clock signals include Csample05, Csample10, Csample15, and Csample20. The phase relationship of the output pulse signals is as follows: Figure 3 As shown. To avoid excessive delay in the critical path simulation unit, exceeding one clock cycle, which could cause incorrect voltage adjustment, the pulse generator of this invention employs a periodic pulse generation circuit. Csample05 is mainly used for determining when the voltage is too high, while Csample15 and Csample20 are mainly used for determining when the voltage is too low.
[0045] The delay margin adjustment circuit is mainly used to add a safety margin to the delay of the critical path simulation unit. This is primarily because, in real-world scenarios, factors such as process differences, temperature variations, and noise interference can all affect the critical path, increasing the delay or creating new critical paths. Therefore, to ensure proper replication, a certain margin needs to be left relative to the actual critical path. Figure 1As shown, the delay margin adjustment circuit includes several inverters and a selector. The inverters are connected in series, and the output of each inverter is connected to the selector. Different inverter outputs represent different delay margins, and the selector adjusts the delay margin accordingly based on environmental changes. This requires a comprehensive adjustment strategy. For example, regarding process technology, such changes generally lead to a normal distribution adjustment in the voltage required for different chips to achieve the same performance, as described in the supplementary materials. Temperature also plays a role; chip packaging and long-term circuit operation cause temperature changes at various nodes of the integrated circuit. Higher temperatures result in poorer timing of the chip circuit, requiring increased voltage to ensure chip performance, while lower temperatures require reduced voltage to minimize system power consumption. The critical path simulation unit replicates the critical path of the load using delay lines. Since the critical path directly affects the highest operating frequency of the entire circuit and determines the electrical performance of the entire circuit, the operation of the delay line reflects the critical path and the overall circuit operation. Generally, a delay line consists of multiple identical delay units, which are used to replicate the critical path. Typically, there can be one or more critical paths. When there are multiple critical paths, simply adding an AND gate will select the critical path with the highest latency. Figure 4 The diagram illustrates multiple critical paths based on delay line load. A typical delay line consists of multiple identical delay units, which are used to replicate the critical path. There can usually be one or more critical paths. When there are multiple critical paths, simply adding an AND gate after the path will select the critical path with the longest delay.
[0046] The phase difference detection unit primarily performs phase shifting on the input test clock, then samples the signal at each rising edge using a trigger. This completes phase detection processing for the critical path simulation unit, determining whether the transmission speed of the delayed test signal in the delay line meets the requirements. Figure 1 As shown, the phase difference detection unit in this embodiment includes n-1 inverters connected in series and N flip-flops. The n inverters connected in series form n sampling nodes, where the first sampling node ND1 is the output of the critical path, and the remaining sampling nodes are the outputs of the respective inverters after different delays. The flip-flops are D flip-flops, with the D input connected to the sampling node and the trigger input connected to the sampling clock. When the rising edge of the sampling clock arrives, the Q terminal outputs the phase detection result.
[0047] The phase encoding unit mainly performs the signal encoding function after phase detection, and encodes the signal based on the delayed phase line detected by the FF1 to FFn flip-flops. Figure 5 This diagram illustrates the phase detection relationship between the current voltage being too low or too high according to the present invention.
[0048] The control unit primarily determines the current voltage value of the power management unit based on the delayed phase detected by each monitored unit. Simultaneously, the control unit is also responsible for performing delay selection control on the delay margin adjustment circuit based on the detected delayed phase information, generating a safety margin for the delay line to ensure the circuit can operate normally under different environments; if the voltage does not meet the requirements, the output clock is gated to prevent circuit errors due to timing discrepancies.
[0049] The power management unit is used to generate the lowest power consumption operating voltage based on the control signal output by the control unit.
[0050] This invention utilizes a trigger to detect whether the transmission speed of the delay test signal in the delay line meets the requirements, thereby indirectly detecting whether the critical path in the load can work normally under this power supply voltage, and then uses a power management unit to regulate the voltage.
[0051] The specific work process is described as follows:
[0052] 1. When the system is working normally, the frequency Cclk generated by the system to operate under load.
[0053] 2. First, input the operating frequency Cclk into the pulse generator circuit to generate a pulse signal Ctest for one clock cycle. This signal serves as the test clock. Under stable operating conditions, the width of the test clock pulse is half of the target clock frequency. At the same time, clock signals with different delays relative to the pulse signal are also generated: Csample05, Csample10, Csample15, and Csample20.
[0054] 3. Then, the test clock signal Ctest is used as the input signal to the delay margin adjustment circuit before entering the critical path simulation unit. Changes in the working environment can often alter the length of the critical path. Therefore, a certain margin needs to be left during the replication of the critical path using delay lines. Specifically, this is achieved by adjusting the delay margin adjustment circuit according to environmental changes, adding a safe margin to the critical path simulation unit.
[0055] 4. The system sampling clock signal is sent to the trigger input terminal of the flip-flop in the phase difference detection unit. Then, the test clock signal passing through the critical path simulation unit is input to each sampling node of the phase difference detection unit. The signal of each sampling node is input to the D input terminal of the flip-flop to output the phase detection result.
[0056] 5. The signal after phase detection is input into the phase encoding unit. The encoding circuit encodes the signal based on the delayed phase line detected by the FF1 to FFn flip-flops. The encoding criteria are as follows:
[0057] (1) If the delayed phase line output by the FFn flip-flop can sample the pulse signal, it proves that the current voltage is too high and the current voltage can be adjusted downward by a large amount.
[0058] (2) If the output of FF3 is high and the output of FF4 is low, it proves that the timing meets the requirements, but the current voltage is in a critical state, and the current voltage can be appropriately boosted.
[0059] (3) If the outputs of FF3 and FF4 are both high and the output of FF5 is low, it means that the current voltage is just right and there is no need to adjust the current voltage.
[0060] (4) If the outputs of FF3, FF4 and FF5 are all high, it means that the current voltage is too high and the current voltage can be adjusted by reducing the voltage appropriately.
[0061] (5) If the output of FF1 to FFn flip-flops does not sample pulses, it means that the voltage is too low and the current voltage needs to be significantly boosted.
[0062] 6. The phase-encoded information enters the control unit, which mainly performs the following control processes:
[0063] a. Determine the current voltage value of the power management unit based on the delayed phase detected by each monitored unit. Specific criteria are as follows:
[0064] ① If the software requires a boost voltage from the power management chip, the current voltage output by the power management unit will be immediately adjusted to its maximum value.
[0065] ② If any processor suddenly has a major hardware adjustment requirement, the current output voltage of the power management unit is immediately increased by a predefined voltage unit value; after waiting for the boost time of several power management units, if any processor still has a major hardware adjustment requirement, the current output voltage of the power management unit continues to be increased by a predefined voltage unit value; until no processor detects a major hardware adjustment requirement.
[0066] ③ If all processors in the monitored processor require hardware fine-tuning, the current output voltage of the power management unit will only be adjusted downward according to the predefined voltage unit value if all processors are adjusting downward. Otherwise, the current output voltage of the power management unit will be adjusted upward according to the predefined voltage unit value.
[0067] ④ If only one processor among the monitored processors needs hardware fine-tuning, and if this processor is adjusting upwards, the current output voltage of the power management unit will be adjusted upwards according to the predefined voltage unit value; otherwise, the current output voltage of the power management chip will not be adjusted.
[0068] b. Based on the detected delay phase information, delay margin adjustment circuit is subjected to delay selection control to generate a safety margin for the delay line, ensuring that the circuit can work normally under different environments.
[0069] c. If the voltage does not meet the requirements, the output clock is gated to prevent the processor and other circuits from malfunctioning due to timing discrepancies.
[0070] 7. Finally, the power management unit is used to generate the lowest power consumption operating voltage based on the control signal output by the control unit.
[0071] It should be noted that this embodiment detects multiple sampling nodes at the same or different sampling times. In other implementations, there can be only one sampling node, sampled using sampling clock signals at different sampling times. Sampling clock signals of different phases are used to sample the rising edge of the output signal of the critical path. If the sampling clock with the smallest delay can sample the test clock signal at the rising edge, it indicates that the current power supply voltage of the digital circuit is higher. In summary, this invention has the following characteristics:
[0072] (1) The method for determining the minimum power consumption voltage of the digital circuit of the present invention uses the path with the longest simulated delay as the critical path, and uses a simple critical path to characterize a complex load. It has a simple structure and a wide range of applications. The voltage output of the critical path is detected by sampling clock, and the circuit power supply voltage is controlled and adjusted according to the detection result. This can improve control accuracy, increase adjustment efficiency, determine the minimum voltage to ensure the normal operation of the circuit, and achieve energy saving.
[0073] (2) By performing voltage detection on at least three sampling nodes set behind the critical path, the voltage rise or fall of the current circuit can be determined, thereby improving control accuracy, increasing regulation efficiency, determining the minimum voltage to ensure normal operation of the circuit, and achieving energy saving.
[0074] (3) At the same sampling time, voltage adjustment is performed based on the detection results of each sampling node; at different sampling times, the higher the sampling time of the sampling clock of the detected output signal, the greater the current power supply voltage of the digital circuit is determined. Through the above method, control accuracy can be improved, regulation efficiency can be enhanced, the minimum voltage to ensure normal circuit operation can be determined, and energy savings can be achieved.
[0075] (4) Adjusting the delay margin of the test clock signal before the critical path can add a safety margin to the critical path. When adjusting the delay margin, the corresponding delay margin can be selected according to the environmental changes, which can improve the circuit's adaptability, thereby improving control accuracy, increasing regulation efficiency, determining the minimum voltage to ensure the normal operation of the circuit, and achieving energy saving.
[0076] Examples of low-power design methods with adaptive voltage regulation:
[0077] The adaptive voltage regulation low-power design method of the present invention is consistent with the method described in the embodiment of the adaptive voltage regulation low-power design device. Since the adaptive voltage regulation low-power design device embodiment has been described in detail, it will not be repeated here.
Claims
1. A low-power design method with adaptive voltage regulation, characterized in that, Includes the following steps: 1) The critical path of an analog-to-digital circuit, where the critical path refers to the path with the longest delay in the digital circuit; 2) Generate a test clock signal and a sampling clock signal. Adjust the delay margin of the test clock signal so that the test clock signal is input into the critical path after a delay. Each sampling clock signal is delayed compared to the test clock signal, and the rising edge of one of the sampling clock signals is the falling edge of the test clock signal. This sampling clock signal is used as the first sampling clock. The delay margin is determined according to changes in the external environment. 3) Set up n sampling nodes. The first sampling node is the critical path output signal without delay, the second sampling node is the critical path output signal after one level of delay, and the nth sampling node is the critical path output signal after n-1 levels of delay. At the rising edge of the first sampling clock, if the output signal of the first sampling node can be sampled, but the output signal of the second sampling node cannot be sampled, it indicates that the timing of the digital circuit meets the requirements, the current voltage is in a critical state, and a boost adjustment is performed on the current voltage. If the output signals of the first and second sampling nodes can be sampled, but the output signal of the third sampling node cannot be sampled, no adjustment is needed for the current voltage. If the output signals of the first, second, and third sampling nodes can be sampled, a buck adjustment is needed. If no output signal is sampled at any sampling node, a boost adjustment is needed. When the voltage does not meet the requirements and needs to be adjusted, the output clock is gated to avoid circuit errors caused by timing discrepancies, and the voltage is adjusted accordingly to determine the minimum operating voltage to ensure the normal operation of the digital circuit, thereby minimizing system power consumption.
2. The low-power design method with adaptive voltage regulation according to claim 1, characterized in that, If the sampling clock with the shortest delay can sample the test clock signal on its rising edge, it indicates that the current power supply voltage of the digital circuit is too high and needs to be stepped down.
3. The low-power design method with adaptive voltage regulation according to claim 1, characterized in that, The method also includes delay selection control based on the phase information detected at each sampling point to generate a safety margin for the delay line.
4. The low-power design method with adaptive voltage regulation according to claim 1, characterized in that, At different sampling times, the gate determines whether to adjust the voltage based on the sampling time of the sampling clock of the output signal at each sampling point detected. The earlier the sampling time, the higher the current power supply voltage.
5. The low-power design method with adaptive voltage regulation according to any one of claims 1-4, characterized in that, The aforementioned changes in the external environment include process differences, temperature changes, and noise interference.
6. A low-power design device with adaptive voltage regulation, characterized in that, The system includes a pulse generator, a critical path simulation unit for delay margin adjustment circuit, a phase difference detection unit, and a control unit. The critical path simulation unit simulates the critical path of the digital circuit, where the critical path refers to the path with the longest delay. The pulse generator generates a test clock signal and a sampling clock signal, and inputs the generated test clock signal to the delay margin adjustment circuit to adjust the delay margin of the test clock signal. The delayed test clock signal is then input into the critical path, where the delay margin is determined based on changes in the external environment. Each sampling clock signal is delayed compared to the test clock signal, and the rising edge of one sampling clock signal is the falling edge of the test clock signal; this sampling clock signal is used as the first sampling clock. The phase difference detection unit sets n sampling nodes, with the first sampling node being the one without delay. The critical path output signal is determined by the nth sampling point, which is the critical path output signal after an n-1 level delay. If the output signal of the first sampling node can be sampled at the rising edge of the first sampling clock but not the output signal of the second sampling node, the timing of the digital circuit meets the requirements, and the current voltage is boosted. If the output signals of the first and second sampling nodes can be sampled but not the output signal of the third sampling node, no adjustment is needed. If the output signals of the first, second, and third sampling nodes can be sampled, a buck adjustment is required. If no output signal is sampled at any sampling node, a boost adjustment is required. When the voltage does not meet the requirements and adjustment is needed, the control unit gates the output clock to prevent circuit errors due to timing discrepancies and adjusts the voltage accordingly.
7. The low-power design device with adaptive voltage regulation according to claim 6, characterized in that, The control unit adjustment criteria include: if the sampling clock with the smallest delay can sample the test clock signal on its rising edge, it indicates that the current power supply voltage of the digital circuit is too high and needs to be reduced.
8. The low-power design device with adaptive voltage regulation according to claim 6, characterized in that, The control unit is also used to perform delay selection control based on the phase information detected at each sampling point to generate a safety margin for the delay line.
9. The low-power design device with adaptive voltage regulation according to claim 6, characterized in that, The control unit is used to determine whether to adjust the voltage based on the sampling time of the sampling clock of the output signal of each sampling point detected at different sampling times. The earlier the sampling time, the higher the current power supply voltage.
10. The low-power design device with adaptive voltage regulation according to any one of claims 6-9, characterized in that, The delay margin adjustment circuit includes a delay line and a selector. The delay line uses inverters in series to simulate different delay lines. The selector is used to select the corresponding delay margin according to changes in the external environment, including process differences, temperature changes, and noise interference.