A wafer-level chip and a method for waking up a dormant computing die

Abstract

The present invention discloses a wafer-level chip, which includes a number of homogeneous computing dies arranged in an array. Each computing die is configured to be able to maintain continuous communication with its adjacent dies during power-on, and thus can wake up its adjacent dormant computing dies through the computing die when needed, so as to reduce the time required for the system to wake up the dormant computing dies and improve the overall efficiency of the chip.

Description

Technical Field

[0001] The present invention relates to the technical field of cloud computing, and particularly to a wafer-level chip and a method for waking up a sleeping computing die thereof. Background Art

[0002] In order to save the time and power consumption wasted by data transfer between chips, wafer-scale chips are currently used in some high-performance computing, large computing power, and cloud computing tasks to achieve super computing power. A large number of dies are included in the wafer-scale chip, among which some dies are used for communication with the outside and can be called interface dies (IO-Die), and the rest of the dies are used for computing and are called computing dies (C-Die, Compute Die).

[0003] Since the power consumption of the cloud wafer-scale chip is very large, when the task load is low, the main control HOST can control some computing dies to enter the sleep mode through the IO-DIE to reduce the overall power consumption. When the main control detects that the load of the currently running computing die is insufficient, it wakes up the sleeping computing die through the IO-DIE. This process is too dependent on the main control's scheduling of the existing task volume, and the waiting running program and data path are long, so the time required to wake up the C-DIE in the sleep mode is relatively long. Summary of the Invention

[0004] In view of some or all of the problems in the prior art, a first aspect of the present invention provides a wafer-level chip, including:

[0005] A plurality of computing dies arranged in an array, wherein the computing dies are all of the same type, and each computing die is configured to be able to maintain continuous communication with its adjacent dies during the power-on of the chip.

[0006] Further, the wafer-level chip further includes:

[0007] An interface die communicatively connected to the computing dies; and

[0008] A power management and microcontroller module for power and task management of each computing die.

[0009] Further, the computing dies are communicatively connected through a die-to-die (D2D) sub-module, and the die-to-die sub-module adopts an extremely short serial interconnect (XSR) or UCIE protocol.

[0010] Further, the die-to-die sub-module and the power management and microcontroller module are disposed in a voltage domain that is always turned on.

[0011] Further, the computing die includes a data reception buffer (RX-BUFFER) for receiving and storing data required for tasks.

[0012] Further, the wafer-level chip includes N interface dies, and each interface die is connected to any one of the computing dies in each row of computing dies.

[0013] The second invention of the present invention provides a method for waking up a sleeping computing die of the wafer-level chip as described above, including:

[0014] A first computing die in a working state predicts a load trend within a specified duration. When the load trend is equal to or greater than a threshold, it wakes up an adjacent second computing die in a sleep mode and reports to the main control;

[0015] The main control sends the data required by the second computing die to the data reception buffer of the second computing die through the first computing die. At the same time, the second computing die sends an interrupt to the power management and microcontroller module for power-on; and

[0016] After the second computing die completes power-on, it reads the data from the data reception buffer and enters the working state.

[0017] Further, the method further includes:

[0018] Regular handshakes are performed between the first computing die and the second computing die.

[0019] Further, waking up an adjacent second computing die in a sleep mode includes:

[0020] The first computing die sends a fixed wake-up command to the second computing die through the die interconnection sub-module.

[0021] Further, the specified duration is set by software; and / or

[0022] The specified duration is within the range of 3 to 5 time periods, where the time period is equal to the sum of the power-on and power-off durations.

[0023] A wafer-level chip and a method for waking up its sleeping computing die provided by the present invention can keep the interconnection path between the computing dies in a normal working mode. Thus, when needed, a computing die can wake up its adjacent sleeping computing die, which can reduce the time required for the system to wake up the sleeping computing die and improve the overall efficiency of the chip. Description of the Drawings

[0024] To further clarify the above and other advantages and features of the embodiments of the present invention, a more specific description of the embodiments of the present invention will be presented with reference to the accompanying drawings. It is understood that these drawings only depict typical embodiments of the present invention and thus will not be considered as limiting its scope. In the drawings, for clarity, the same or corresponding components will be denoted by the same or similar reference numerals.

[0025] Figure 1 Schematic structural diagram of a wafer-level chip showing an embodiment of the present invention;

[0026] Figure 2 Schematic connection diagram of two adjacent computing dies in a wafer-level chip showing an embodiment of the present invention; and

[0027] Figure 3 Schematic flowchart of a method for waking up a dormant computing die in a wafer-level chip showing an embodiment of the present invention. Detailed implementation manners

[0028] In the following description, the present invention is described with reference to the embodiments. However, those skilled in the art will recognize that the embodiments can be implemented without one or more specific details or in conjunction with other alternative and / or additional methods, materials, or components. In other instances, well-known structures, materials, or operations have not been shown or described in detail to avoid obscuring the inventive points of the present invention. Similarly, for purposes of explanation, specific quantities, materials, and configurations are set forth in order to provide a thorough understanding of the embodiments of the present invention. However, the present invention is not limited to these specific details. In addition, it should be understood that the embodiments shown in the drawings are illustrative representations and not necessarily drawn to scale.

[0029] In this specification, the reference to "an embodiment" or "the embodiment" means that the specific features, structures, or characteristics described in connection with that embodiment are included in at least one embodiment of the present invention. The phrase "in an embodiment" appearing throughout this specification does not necessarily refer to the same embodiment.

[0030] It should be noted that the embodiments of the present invention describe the method steps in a specific order, but this is only for the purpose of explaining the specific embodiment and not for limiting the order of the steps. On the contrary, in different embodiments of the present invention, the order of the steps can be adjusted according to actual requirements.

[0031] In existing wafer-level chips, once a computing die enters the sleep state, it will be powered off, and the communication link with the remaining computing dies will also be interrupted. When it is necessary to wake up the sleeping computing die, on the one hand, it needs to be powered on, and on the other hand, it is also necessary to re-establish the communication link between it and other computing dies. However, re-establishing the communication link requires a certain amount of training and calibration time. In addition, data transmission can only be carried out after the communication link is re-established. Therefore, in the prior art, the time required to wake up a sleeping computing die is relatively long, which has a certain impact on the overall efficiency of the chip. Based on this, in order to improve the chip efficiency and reduce the wake-up duration of the sleeping computing die, the present invention provides a wafer-level chip and a method for waking up its sleeping computing die, by keeping the communication link between the computing dies always normal, so that the sleeping die can be woken up by the adjacent working die prior to the master HOST, without the need to re-establish the communication link. In addition, during the power-on period, the required data can be pre-transferred to the die to be woken up by the adjacent working die, thereby reducing the waiting time for data distribution, and thus greatly reducing the wake-up duration.

[0032] In the present invention, the term "continuous communication" means maintaining communication continuously within the specified time period, and outside this time period, communication can be maintained continuously, intermittently, or not at all.

[0033] The following further describes the solution of the present invention in conjunction with the accompanying drawings of the embodiments.

[0034] Figure 1 The structural schematic diagram of a wafer-level chip showing an embodiment of the present invention is as follows Figure 1 As shown, a wafer-level chip includes computing dies 101, interface dies 102, and a power management (PMU, Power Management Unit) and microcontroller module (MCU, Micro Control Unit) 103.

[0035] Among them, the computing die 101 (C-DIE, Compute DIE) is used to execute computing tasks. It is arranged in an array, including N rows and M columns, where N and M are natural numbers. Each computing die is communicatively connected to its adjacent computing dies, that is, the upper computing die, the lower computing die in the same column, the previous computing die, and the subsequent computing die in the same row. It should be understood that in the embodiments of the present invention, all computing dies are homogeneous dies, that is, all computing dies are of the same type.

[0036] Since in a wafer-level chip, the execution of computing tasks usually adopts a pipelining method, and the computing dies in the sleep state are marked as sleep computing dies CO-DIE 111, then as Figure 1 shown, the computing tasks are preferentially executed by the computing dies C-DIE 101 in the first row and the first column. When the load is insufficient, the sleep computing dies 111 in the second row and the second column are woken up, and so on. This makes the previous computing die in the same column and / or the previous computing die in the same row of the computing die of the next executable task necessarily in the working state, and thus can be woken up by the previous computing die in the same column and / or the previous computing die in the same row. Based on this, in order to shorten the wake-up time, during the power-on of the chip, the computing dies still maintain continuous communication with their adjacent computing dies even after entering the sleep state. In an embodiment of the present invention, the sleep computing die and its adjacent computing die in the working state keep having regular handshakes all the time, thereby ensuring that the communication link clock is normally maintained.

[0037] In an embodiment of the present invention, the computing dies are communicatively connected through a die-to-die (D2D) interconnect sub-module. In an embodiment of the present invention, the die interconnect sub-module realizes the communication connection between the computing dies based on the extremely short serial interconnect (XSR SerDes) or the UCIe protocol. Among them, the serial interconnect technology (SerDes) adopts a differential signal transmission method to achieve high-speed data transmission, and has the advantages of few IO numbers, long transmission distance, and high speed. Currently, it is widely used in high-speed interconnections between systems or chips. The extremely short serial interconnect (XSR SerDes) refers to a serial interconnect with a relatively small distance between the transmitter and the receiver. Its optical internetworking forum-common electrical interface specification (OIF-CEI 4.0) is specifically for the interconnection between dies, and has the characteristics of low power consumption, small area, and flexible communication protocol. UCIe 1.0 uses the high-speed serial computer expansion bus standard (PCIe) and the computer interconnect standard (CXL) as the low-power D2D interconnect physical layer (PHY), and it can be compatible with multiple protocols, including PCIe, CXL, and Raw Mode, etc. Figure 2 shows a connection schematic diagram of two adjacent computing dies in a wafer-level chip according to an embodiment of the present invention. As Figure 2 shown is a connection schematic diagram of a computing die C-DIE in the working state and a sleep computing die CO-DIE. As Figure 2 shown, in an embodiment of the present invention, the computing die includes a control module Controller, an interconnect physical layer PHY, and a data reception buffer RX BUFFER. Among them, the control module is used to execute the computing tasks of the computing die, the interconnect physical layer is used for the interconnect communication between two computing dies, and the data reception buffer is used to receive and store the data required for the tasks.Figure 2 As shown, in order to ensure the maintenance of the communication link clock, in an embodiment of the present invention, the die interconnect sub-module and the power management and microcontroller module 103 are configured to be in an always-on power domain.

[0038] The interface die (IO-Die) 102 is communicatively connected to the computing die 101 to implement the communication connection between the computing die and the main control HOST and / or other external chips, units, modules, etc. Since it works in a pipelined form, in an embodiment of the present invention, there are N interface dies provided in the wafer-level chip, where N is the number of rows of the computing die array. As Figure 1 shown, each interface die is connected to any one of the computing dies in each row of computing dies, preferably the first computing die in each row.

[0039] The power management (PMU, Power Management Unit) and the microcontroller module (MCU, MicroControl Unit) 103 are in an always-on power domain and are used for the power supply and task management of each computing die. For example, after receiving an interrupt, it starts the power-on program of the sleeping computing die, etc.

[0040] Figure 3 The flowchart shows the wake-up method for a sleeping computing die in a wafer-level chip according to an embodiment of the present invention. As Figure 3 shown, the wake-up method for the sleeping computing die of the wafer-level chip as described above includes:

[0041] First, in step 301, the load trend is predicted. While the first computing die in the working state is working, it predicts the load trend of itself or the overall system. Once it is predicted that the load after a specified duration will be greater than or equal to the threshold, it enters step 302 to wake up the sleeping computing die. In practical applications, the specified duration can be set according to the product usage scenario and working conditions. However, if the specified duration is too short, it may lead to frequent power-on and power-off processes. In a situation where the load trend drops sharply, for example, it may cause the connected DIE to shut down, affecting the system stability. Therefore, in an embodiment of the present invention, the specified duration is preferably set within the range of 3 to 5 time cycles, where the time cycle is equal to the sum of the power-on and power-off durations. In an embodiment of the present invention, the specified duration can be set by software, and the hardware provides a configuration register to set the time window;

[0042] In step 302, a wake-up command is sent. When the predicted load trend is equal to or greater than the threshold, the first computing die wakes up its adjacent second computing die in the sleep mode and reports to the main control HOST. In an embodiment of the present invention, the first computing die sends a fixed wake-up command to the second computing die through the die interconnection sub-module;

[0043] Next, in step 303, the power-on procedure is started. After receiving the fixed wake-up command, the second computing die sends an interrupt to the MCU in the always-on power domain to start the power-on procedure of the second computing die;

[0044] Meanwhile, in step 304, data is sent down. After receiving the report from the first computing die, the main control HOST sends the data required by the second computing die. Since the second computing die may not be fully woken up at this time and thus cannot communicate with the HOST yet, the data is sent to the first computing die. As described above, the communication link between the first computing die and the second computing die is always kept normal through regular handshakes. Therefore, after receiving the data, the first computing die can directly send it to the data reception buffer of the second computing die without waiting for the second computing die to complete the power-on completely; and

[0045] Finally, in step 305, the computing task is executed. After the second computing die completes the power-on, it reads the data from the data reception buffer and enters the working state to execute the corresponding computing task.

[0046] The wafer-level chip keeps the interconnection paths between the computing dies in the normal working mode, and thus can wake up its adjacent sleeping computing dies through the computing dies when needed, reducing the time required for the system to wake up the sleeping computing dies and improving the overall efficiency of the chip.

[0047] Although the embodiments of the present invention have been described above, it should be understood that they are presented only as examples and not as limitations. It is obvious to those skilled in the relevant art that various combinations, variations and changes can be made to them without departing from the spirit and scope of the present invention. Therefore, the width and scope of the present invention disclosed herein should not be limited by the above-disclosed exemplary embodiments, but should be defined only by the appended claims and their equivalents.

Claims

1. A method for waking up a dormant computing die of a wafer-level chip, characterized in that, the wafer-level chip includes a plurality of computing dies arranged in an array, N interface dies, and a power management and microcontroller module, where N is the number of rows of the computing die array. The computing dies are all of the same type, and each computing die includes a data reception buffer configured to receive and store data required for tasks. Each computing die is configured to be able to continuously communicate with its adjacent computing dies through a die interconnect sub-module during chip power-on. The die interconnect sub-module uses a very short serial interconnect or UCIE protocol and is set in a voltage domain that is always powered on. The interface dies are communicatively connected to the computing dies. Each interface die is connected to any one of the computing dies in each row of computing dies, and the interface dies are configured to implement communication connections between the computing dies and the main control and / or external chips and units. The power management and microcontroller module is configured to perform power and task management of the computing dies; the waking-up method includes the steps of: a first computing die in the working state predicts the load trend within a specified duration. When the load trend is equal to or greater than a threshold, it wakes up an adjacent second computing die in the sleep mode and reports to the main control; the main control sends the data required by the second computing die to the data reception buffer of the second computing die through the first computing die. At the same time, the second computing die sends an interrupt to the power management and microcontroller module for power-on; and after the second computing die completes power-on, it reads the data from the data reception buffer and executes the task.

2. The waking-up method according to claim 1, characterized in that, it further includes the step of: performing regular handshakes between the first computing die and the second computing die.

3. The waking-up method according to claim 1, characterized in that, waking up an adjacent second computing die in the sleep mode includes the steps of: the first computing die sends a fixed wake-up command to the second computing die through the die interconnect sub-module.

4. The waking-up method according to claim 1, characterized in that, the specified duration is set by software; and / or the specified duration is within the range of 3 to 5 time periods, where the time period is equal to the sum of the power-on and power-off durations.

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