PCIe topology acquisition method and apparatus

Abstract

The application provides a PCIe topology acquisition method and device, the method comprising: in the process of PCIe device enumeration of a target electronic device, obtaining original information comprising original device information of each PCIe device in the target electronic device; analyzing the original information to obtain target information comprising target device information of each PCIe device, the target device information of each PCIe comprising identity information of each PCIe device; based on the target information, constructing a PCIe topology of the target electronic device, and displaying the PCIe topology on a BIOS setup interface of the target electronic device. The PCIe topology acquisition method and device provided by the application can acquire the PCIe topology without relying on a Linux operating system, and can display the PCIe topology on the BIOS setup interface, so that the user can more conveniently and efficiently view the PCIe topology, and the user experience can be improved.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and in particular to a method and apparatus for obtaining PCIe topology. Background Technology

[0002] PCIe (Peripheral Component Interconnect Express) topology refers to the connection relationship between PCIe devices and the CPU (central processing unit). In different application scenarios, PCIe devices are connected to different CPU interfaces, thus forming different PCIe topologies. Obtaining PCIe topology information is crucial for hardware development, design, and testing.

[0003] In existing technologies, the PCIe topology can be obtained using the `lspci` command under the Linux operating system. However, it is difficult to obtain the PCIe topology using the `lspci` command when the Linux operating system malfunctions, cannot access the Linux operating system, or does not have a Linux system installed. Therefore, how to obtain the PCIe topology without relying on the Linux operating system is a technical problem that urgently needs to be solved in this field. Summary of the Invention

[0004] This invention provides a PCIe topology acquisition method and apparatus to address the shortcomings of existing technologies where it is difficult to obtain PCIe topology information through the operating system when the operating system malfunctions, and the PCIe topology information obtained through the operating system is not very intuitive. This invention enables the acquisition of PCIe topology information even when the operating system malfunctions, and provides a more intuitive display of the PCIe topology information.

[0005] This invention provides a PCIe topology acquisition method, comprising:

[0006] During the process of enumerating PCIe devices in the target electronic device, the original information is obtained, which includes the original device information of each PCIe device in the target electronic device.

[0007] Parse the original information to obtain target information. The target information includes target device information for each PCIe device. The target device information for each PCIe device is the parsed original device information of each PCIe device. The target device information for each PCIe device includes the identity information of each PCIe device.

[0008] Based on the target information, the PCIe topology of the target electronic device is constructed, and the PCIe topology is displayed in the BIOS setup interface of the target electronic device.

[0009] According to a PCIe topology acquisition method provided by the present invention, the original information further includes: the original port information of each CPU root port and the original port information of each PCIe port in the target electronic device.

[0010] Accordingly, the target information further includes: target port information for each CPU root port and target port information for each PCIe port; the target port information for each CPU root port is the original port information parsed from each CPU root port; the target port information for each CPU root port includes the identity information of each CPU root port; the target port information for each PCIe port is the original port information parsed from each PCIe port; the target port information for each PCIe port includes the identity information of each PCIe port.

[0011] The step of constructing the PCIe topology of the target electronic device based on the target information includes:

[0012] Based on the target information, obtain the first connection relationship between the CPU root port and the PCIe port, the second connection relationship between the CPU root port and the PCIe device, and the third connection relationship between the PCIe port and the PCIe device;

[0013] The PCIe topology is constructed based on the first connection relationship, the second connection relationship, and the third connection relationship.

[0014] According to a PCIe topology acquisition method provided by the present invention, the step of constructing the PCIe topology structure of the target electronic device based on the first connection relationship, the second connection relationship, and the third connection relationship includes:

[0015] Each CPU root port is defined as a root node in the PCIe topology;

[0016] Based on the first connection relationship and the second connection relationship, each PCIe port connected to any CPU root port is determined as a first-level child node under the root node corresponding to any CPU root port, and each PCIe device connected to any CPU root port is determined as a first-level child node under the root node corresponding to any CPU root port.

[0017] Based on the third connection relationship, each PCIe device connected to any PCIe port is determined as a second-level sub-node under the first-level sub-node corresponding to any PCIe port, thereby obtaining the PCIe topology.

[0018] According to a PCIe topology acquisition method provided by the present invention, the step of constructing the PCIe topology of the target electronic device based on the target information includes:

[0019] Based on the target information, each PCIe device is identified as a node in the PCIe topology, thereby constructing the PCIe topology;

[0020] Accordingly, displaying the PCIe topology in the BIOS setup interface of the target electronic device includes:

[0021] In the BIOS setup interface, a first control is created for each node, and the identity information of the PCIe device corresponding to each node is used as the identifier of the first control and displayed in the BIOS setup interface.

[0022] According to a PCIe topology acquisition method provided by the present invention, the step of displaying the PCIe topology in the BIOS setup interface of the target electronic device includes:

[0023] In the BIOS setup interface, a second control is created corresponding to each node, and the identity information of the CPU root port corresponding to each node is used as the identifier of the second control and displayed in the BIOS setup interface.

[0024] In the BIOS setup interface, a third control is created corresponding to each level-one child node, and the identity information of the PCIe port corresponding to each level-one child node or the identity information of the PCIe device corresponding to each level-one child node is used as the identifier of the third control and displayed in the BIOS setup interface.

[0025] In the BIOS setup interface, a fourth control is created corresponding to each second-level child node, and the identity identifier of the PCIe device corresponding to each second-level child node is used as the identifier of the fourth control and displayed in the BIOS setup interface.

[0026] According to a PCIe topology acquisition method provided by the present invention, the method further includes: creating a first control corresponding to each node in the BIOS setup interface, and displaying the identification information of the PCIe device corresponding to each node as the identifier of the first control in the BIOS setup interface; the method further includes:

[0027] The target device information of the PCIe corresponding to each node is displayed as the corresponding content of the first control, and the device information of the PCIe device is displayed in the BIOS setup interface when a first operation is received on the first control.

[0028] According to a PCIe topology acquisition method provided by the present invention, the method further includes using the identity identifier of the CPU root port corresponding to each node as the identifier of the second control and displaying it on the BIOS setup interface.

[0029] The target port information of the CPU root port corresponding to each node is determined as the display content corresponding to the second control, and the target port information of the CPU root port corresponding to each node is displayed in the BIOS setup interface when the second operation on the second control is received.

[0030] The method of using the identity identifier of the PCIe port corresponding to each first-level child node or the identity identifier of the PCIe device corresponding to each first-level child node as the identifier of the third control and displaying it on the BIOS setup interface further includes:

[0031] When the identifier of the third control is the identity identifier of the PCIe port corresponding to each first-level child node, the target port information of the PCIe port corresponding to each first-level child node is determined as the display content of the third control. Upon receiving a third operation on the third control, the target port information of the PCIe port corresponding to each first-level child node is displayed on the BIOS setup interface.

[0032] When the identifier of the third control is the identity identifier of the PCIe device corresponding to each first-level child node, the target device information of the PCIe device corresponding to each first-level child node is determined as the display content of the third control, and when a third operation is received on the third control, the target device information of the PCIe device corresponding to each first-level child node is displayed on the BIOS setup interface.

[0033] The method further includes using the identity identifier of the PCIe device corresponding to each secondary child node as the identifier of the fourth control and displaying it on the BIOS setup interface:

[0034] The target device information of the PCIe device corresponding to each secondary sub-node is determined as the display content corresponding to the fourth control, and the target device information of the PCIe device corresponding to each secondary sub-node is displayed on the BIOS setup interface upon receiving the fourth operation on the fourth control.

[0035] The present invention also provides a PCIe topology acquisition device, comprising:

[0036] The data acquisition module is used to acquire raw information during the PCIe device enumeration process of the target electronic device, the raw information including the raw device information of each PCIe device in the target electronic device;

[0037] The data parsing module is used to parse the original information to obtain target information. The target information includes target device information for each PCIe device. The target device information for each PCIe device is the parsed original device information of each PCIe device. The target device information for each PCIe device includes the identity information of each PCIe device.

[0038] The topology display module is used to construct the PCIe topology of the target electronic device based on the target information, and display the PCIe topology in the BIOS setup interface of the target electronic device.

[0039] The present invention also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement any of the PCIe topology acquisition methods described above.

[0040] The present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the PCIe topology acquisition method as described above.

[0041] The present invention also provides a computer program product, including a computer program that, when executed by a processor, implements any of the PCIe topology acquisition methods described above.

[0042] The PCIe topology acquisition method and apparatus provided by this invention, during the process of enumerating the target electronic device, obtains original information including the original device information of each PCIe device in the target electronic device, parses the original information to obtain target information including the target device information of each PCIe device, and then constructs the PCIe topology of the target electronic device based on the target information and displays the PCIe topology on the BIOS setup interface of the target electronic device. It can acquire the PCIe topology without relying on the Linux operating system and display the PCIe topology on the BIOS setup interface, making it more convenient and efficient for users to view the PCIe topology and improving user experience. Attached Figure Description

[0043] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0044] Figure 1 This is one of the flowcharts illustrating the PCIe topology acquisition method provided by the present invention;

[0045] Figure 2 This is the second flowchart illustrating the PCIe topology acquisition method provided by the present invention;

[0046] Figure 3 This is a schematic diagram of the PCIe topology acquisition device provided by the present invention;

[0047] Figure 4 This is a schematic diagram of the structure of the electronic device provided by the present invention. Detailed Implementation

[0048] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0049] In the description of the invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0050] It should be noted that server scalability is an important performance characteristic of servers.

[0051] Server scalability refers to the ability to flexibly configure server hardware as needed, such as memory, adapters, solid-state drives (SSDs), processors, etc.

[0052] Server scalability can be achieved by adding PCIe (Peripheral Component Interconnect Express, a high-speed serial computer expansion bus standard slot).

[0053] After the CPU is connected to the PCIe slot, each PCIe slot can connect to at least one PCIe device, thereby expanding the server's functionality based on these PCIe devices. For example, connecting a graphics processing unit (GPU) to the PCIe slot can expand the server's video processing capabilities, and connecting an SSD to the PCIe slot can expand the server's storage capabilities.

[0054] Typically, the `lspci` command in the Linux operating system can be used to view and analyze the server's PCIe topology. The `lspci` command can read the server's PCIe topology, PCIe configuration space, and parsing results. Viewing the server's PCIe topology using `lspci` is not limited by the complexity of the topology and provides convenient information retrieval.

[0055] Specifically, developers can use the lspci command to check the connection status of PCIe devices, whether PCIe devices are properly recognized, and whether PCIe devices are malfunctioning, analyze the operating status of PCIe devices, view the resources required by PCIe devices, adapt the PCIe topology to the corresponding devices, and also perform whole-machine resource adaptation and fault device location by viewing the PCIe topology.

[0056] Testers can use the `lspci` command to determine if there are missing or faulty PCIe devices, or if there is a reduction in speed or bandwidth. The `lspci` command is frequently used in stability testing.

[0057] Operations and maintenance personnel can add the lspci command to the operations and maintenance script to check for faults such as card loss, speed reduction and bandwidth reduction.

[0058] However, it is difficult to obtain the server's PCIe topology using the lspci command when the Linux operating system malfunctions, cannot access the Linux operating system, or has not installed the Linux system.

[0059] Typically, the UEFI shell allows you to view the server's PCIe topology in UEFI mode. UEFI stands for Unified Extensible Firmware Interface, and the UEFI shell provides an interactive command-line shell environment for UEFI.

[0060] However, when the UEFI shell is unavailable, it is difficult to view device information of PCIe devices and port information of PCIe ports on the server through the UEFI shell.

[0061] The device information and port information of PCIe devices in the server that can be viewed through the UEFI shell are in code form, which makes it difficult to show the topological relationship between PCIe devices. In scenarios where PCIe topology needs to be obtained quickly or for non-professional users, the readability of the above code information is poor.

[0062] The PCIe topology seen through the UEFI shell is not a multi-level tree structure, making it difficult for users to intuitively understand and experience.

[0063] To address this issue, the present invention provides a PCIe topology acquisition method. Based on the PCIe topology acquisition method provided by the present invention, the PCIe topology can be acquired without relying on the Linux operating system and displayed in the BIOS setup interface, making it more convenient and efficient for users to view the PCIe topology and improving user experience.

[0064] Furthermore, the PCIe topology acquisition method provided by this invention can also overcome the shortcomings of UEFI shell, which can only view the device information of PCIe devices and the port information of PCIe ports in UEFI mode. It can enable the viewing of PCIe topology when the Linux operating system is unavailable and UEFI shell is unavailable in legacy mode.

[0065] Figure 1 This is one of the flowcharts illustrating the PCIe topology acquisition method provided by this invention. The following is in conjunction with... Figure 1 This invention describes the PCIe topology acquisition method. For example... Figure 1 As shown, the method includes: Step 101, during the process of enumerating PCIe devices in the target electronic device, obtaining original information, which includes the original device information of each PCIe device in the target electronic device.

[0066] It should be noted that the execution subject of this embodiment of the invention is a PCIe topology acquisition device.

[0067] Specifically, the target electronic device is the object of acquisition in the PCIe topology acquisition method provided by this invention. Based on the PCIe topology acquisition method provided by this invention, the PCIe topology in the target electronic device can be acquired.

[0068] It should be noted that the target electronic device in the embodiments of the present invention can be an electronic device such as a computer or server. The specific type of the target electronic device is not limited in the embodiments of the present invention.

[0069] Since the device information of PCIe devices is dynamic, unlike the common fixed static option menus, this embodiment of the invention reads the original device information of each PCIe device, the original port information of each PCIe port, and the original port information of each CPU root port from the code during the PCIe device enumeration process of the target electronic device.

[0070] After obtaining the above information, the original device information of each PCIe device in the target electronic device can be filtered out from the above original information and used as the original information.

[0071] It should be noted that the original device information of the PCIe device in the embodiments of the present invention may include the BDF (Bus Device Function) information of the PCIe device, the vendor ID (VID) of the PCIe device, the device ID (DID) of the PCIe device, the I / O (Input / Output) resources and MMIO (Memory-mapped I / O) resources required by the PCIe device, the link capability information of the PCIe device, the link control information of the PCIe device, and the link status information of the PCIe device.

[0072] Among them, the BDF information of the PCIe device is the unique identifier of the PCIe device, which can be used to reflect the physical location of the PCIe device.

[0073] The vendor ID and device ID of a PCIe device are stored in the PCIe configuration space, which refers to a physical space unique to a PCIe device.

[0074] I / O stands for input / output, and it is divided into two parts: I / O devices and I / O interfaces.

[0075] MMIO refers to Memory Mapped I / O;

[0076] The link performance information, link control information, and link status information of a PCIe device can be used to represent the connection function, configuration, and status of the PCIe device. All of the above information is stored in the PCIe configuration space.

[0077] Step 102: Parse the original information to obtain the target information. The target information includes the target device information of each PCIe device. The target device information of each PCIe device is the original device information parsed from each PCIe device. The target device information of each PCIe device includes the identity information of each PCIe device.

[0078] Specifically, after obtaining the above-mentioned original information, it can be saved and parsed to obtain the target information.

[0079] It should be noted that, in this embodiment of the invention, by saving and parsing the above-mentioned original information, the original device information parsed by each PCIe device in the target electronic device can be used as the target device information of each PCIe device. The readability of the target device information is stronger, thereby better meeting the viewing needs of scenarios that require quick acquisition of PCIe topology and non-professional users.

[0080] Step 103: Based on the target information, construct the PCIe topology of the target electronic device and display the PCIe topology in the BIOS setup interface of the target electronic device.

[0081] Specifically, after obtaining the target information, the PCIe topology of the target electronic device can be constructed in various ways based on the target information. For example, the PCIe topology of the target electronic device can be constructed using parallel, tree, or exhaustive methods based on the target information. This embodiment of the invention does not limit the specific method for constructing the PCIe topology of the target electronic device based on the target information.

[0082] Based on the above target information, after constructing the PCIe topology of the target electronic device, the PCIe topology can be displayed in the BIOS setup interface of the target electronic device. BIOS stands for Basic Input Output System; the BIOS setup interface is the interface within the BIOS where configuration functions can be modified.

[0083] This invention, in the process of enumerating target electronic devices, obtains raw information including the original device information of each PCIe device in the target electronic device, parses the raw information to obtain target information including the target device information of each PCIe device, and then constructs the PCIe topology of the target electronic device based on the target information and displays the PCIe topology on the BIOS setup interface of the target electronic device. This allows the PCIe topology to be obtained without relying on the Linux operating system and displayed on the BIOS setup interface, making it more convenient and efficient for users to view the PCIe topology and improving user experience.

[0084] Based on the above embodiments, constructing a PCIe topology for a target electronic device based on target information includes: determining each PCIe device as a node in the PCIe topology based on the target information, thereby constructing the PCIe topology.

[0085] Specifically, after obtaining the target information, which includes the parsed device information of each PCIe device in the target electronic device, each PCIe device can be identified as a node based on the target information, thereby constructing the PCIe topology of the target electronic device. The nodes in the PCIe topology are in a parallel relationship.

[0086] Accordingly, the PCIe topology is displayed in the BIOS setup interface of the target electronic device, including: creating a first control corresponding to each node in the BIOS setup interface, and using the identity information of the PCIe device corresponding to each node as the identifier of the first control, and displaying it in the BIOS setup interface.

[0087] Specifically, after constructing the PCIe topology in which the nodes are in parallel relationship, for each node in the PCIe topology, a first control corresponding to the node can be created in the BIOS setup interface of the target electronic device, and the identity information of the PCIe device corresponding to the node can be used as the identifier of the first control and displayed in the BIOS setup interface.

[0088] As an optional embodiment, a first control corresponding to each node is created in the BIOS setup interface, and the identity information of the PCIe device corresponding to each node is used as the identifier of the first control and displayed in the BIOS setup interface. The method further includes: displaying the target device information of the PCIe device corresponding to each node as the corresponding content of the first control, and displaying the device information of the PCIe device in the BIOS setup interface when a first operation on the first control is received.

[0089] Specifically, for each node in a PCIe topology where the nodes are in parallel, a first control corresponding to the node is created in the BIOS setup interface of the target electronic device. After the identity information of the PCIe device corresponding to the node is displayed in the BIOS setup interface as the identifier of the first control, the device information parsed by the PCIe device corresponding to the node can be used as the display content of the first control.

[0090] Upon receiving the user's first operation on the aforementioned first control, it indicates that the user requests to view the content displayed corresponding to the aforementioned first control. The device information parsed by the PCIe device corresponding to the aforementioned node can be displayed on the aforementioned BIOS setup interface.

[0091] It should be noted that the first operation described above may include, but is not limited to, clicking, double-clicking, or dragging to a preset area. This embodiment of the invention does not specifically limit the first operation described above.

[0092] This invention, based on target information, identifies each PCIe device in a target electronic device as a node in the PCIe topology of the target electronic device, thereby constructing a PCIe topology with parallel relationships between the nodes. By creating a first control corresponding to each node in the PCIe topology in the BIOS setup interface, and using the identification information of the PCIe device corresponding to each node as the identifier of the first control, the PCIe topology of the target electronic device can be displayed more simply and intuitively in the BIOS setup interface of the target electronic device. Furthermore, upon receiving a user's first operation on the first control, the parsed device information of the PCIe device corresponding to each node can be displayed. This parsed device information is more readable, better meeting the user's needs for viewing and analyzing PCIe device information, and improving user experience.

[0093] Based on the content of the above embodiments, the original information also includes: the original port information of each CPU root port and the original port information of each PCIe port in the target electronic device.

[0094] Accordingly, the target information also includes target port information for each CPU root port and target port information for each PCIe port; the target port information for each CPU root port is the original port information parsed from each CPU root port; the target port information for each CPU root port includes the identity information of each CPU root port; the target port information for each PCIe port is the original port information parsed from each PCIe port; the target port information for each PCIe port includes the identity information of each PCIe port.

[0095] Specifically, in the process of enumerating PCIe devices in the target electronic device, the original device information of each PCIe device, the original port information of each PCIe port, and the original port information of each CPU root port in the target electronic device are read from the code as the original information.

[0096] It should be noted that the original port information of the PCIe port in the embodiments of the present invention may include the BDF information of the PCIe device, the VID and DID of the PCIe port, the I / O resources and MMIO resources required by the PCIe port, the link performance information of the PCIe port, the link control information of the PCIe port, and the link status information of the PCIe device.

[0097] The original port information of the CPU root port in this embodiment of the invention may include the VID and DID of the CPU root port, the I / O resources and MMIO resources required by the CPU root port, the link performance information of the CPU root port, the link control information of the CPU root port, and the link status information of the CPU root port.

[0098] Accordingly, after obtaining the above-mentioned original information, by saving and parsing the above-mentioned target information, the original port information parsed from each CPU root port in the target electronic device can be used as the target device information of each CPU root port, and the original port information parsed from each PCIe port in the target electronic device can be determined as the target port information of each PCIe port. The target port information of each CPU root port and the target frame information of each PCIe port are more readable, thus better meeting the viewing needs of scenarios that require quick acquisition of PCIe topology and non-professional users.

[0099] Based on the target information, construct the PCIe topology of the target electronic device, including:

[0100] Based on the target information, obtain the first connection relationship between the CPU root port and the PCIe port, the second connection relationship between the CPU root port and the PCIe device, and the third connection relationship between the PCIe port and the PCIe device.

[0101] It is understandable that the CPU root port can be connected to a PCIe port or a PCIe device, and a PCIe port can be connected to a PCIe device.

[0102] Therefore, after obtaining the target information, including the target device information of each PCIe device, the target port information of each PCIe port, and the target port information of each CPU port in the target electronic device, the first connection relationship between the CPU root port and the PCIe port, the second connection relationship between the CPU root port and the PCIe device, and the third connection relationship between the PCIe port and the PCIe device in the target electronic device can be obtained based on the above target information.

[0103] Based on the first connection relationship, the second connection relationship, and the third connection relationship, construct the PCIe topology.

[0104] Specifically, after obtaining the first connection relationship, the second connection relationship, and the third connection relationship, the PCIe topology of the target electronic device can be constructed based on the first connection relationship, the second connection relationship, and the third connection relationship.

[0105] As an optional embodiment, the PCIe topology of the target electronic device is constructed based on the first connection relationship, the second connection relationship and the third connection relationship, including: determining each CPU root port as a root node in the PCIe topology.

[0106] Specifically, for each CPU root port in the target electronic device, the aforementioned CPU root port can be determined as a root node in the PCIe topology of the target electronic device.

[0107] Based on the first connection relationship and the second connection relationship, each PCIe port connected to any CPU root port is determined as a first-level child node under the root node corresponding to any CPU root port, and each PCIe device connected to any CPU root port is determined as a first-level child node under the root node corresponding to any CPU root port.

[0108] Specifically, for any CPU root port in the target electronic device, based on the first connection relationship and the second connection relationship mentioned above, each PCIe port connected to the CPU root port can be determined as a first-level child node under the root node corresponding to the CPU root port, and each PCIe device connected to the CPU root port can also be determined as a first-level child node under the root node corresponding to the CPU root port.

[0109] Based on the third connection relationship, each PCIe device connected to any PCIe port is identified as a second-level sub-node under the first-level sub-node corresponding to any PCIe port, thereby obtaining the PCIe topology.

[0110] Specifically, for any PCIe port in the target electronic device, based on the aforementioned third connection relationship, each PCIe device connected to the aforementioned PCIe port can be identified as a second-level sub-node under the first-level sub-node corresponding to the aforementioned PCIe port, thereby obtaining the PCIe topology of the target electronic device, which has a multi-level tree structure.

[0111] This invention, based on target information, obtains a first connection relationship between the CPU root port and the PCIe port in the target electronic device, a second connection relationship between the CPU root port and the PCIe device, and a third connection relationship between the PCIe port and the PCIe device. Based on these connection relationships, each CPU root port can be identified as a root port in the PCIe topology of the target electronic device. Each PCIe port connected to any CPU root port is identified as a first-level child node under the root node corresponding to the CPU root port. Each PCIe device connected to any CPU root port is identified as a first-level child node under the root node corresponding to the CPU root port. Each PCIe device connected to any PCIe port is identified as a second-level child node under the first-level child node corresponding to the PCIe port. This results in a PCIe topology with a multi-level tree structure. The structure of this PCIe topology is clearer and more intuitive, enabling more efficient and convenient PCIe topology analysis and improving user experience.

[0112] Based on the above embodiments, displaying the PCIe topology in the BIOS setup interface of the target electronic device includes: creating a second control corresponding to each node in the BIOS setup interface, and displaying the identification information of the CPU root port corresponding to each node as the identifier of the second control in the BIOS setup interface.

[0113] Specifically, for each node in the PCIe topology with the above multi-level tree structure, a second control of the root node can be created in the BIOS setup interface of the target electronic device, and the identification information of the CPU root port corresponding to the root node can be used as the identifier of the second control and displayed in the BIOS setup interface.

[0114] Create a third control corresponding to each level of child node in the BIOS setup interface, and use the identification information of the PCIe port corresponding to each level of child node or the identification information of the PCIe device corresponding to each level of child node as the identifier of the third control and display it in the BIOS setup interface.

[0115] Specifically, for each first-level child node in the PCIe topology with the above-mentioned multi-level tree structure, a third control corresponding to the first-level child node can be created in the above-mentioned BIOS setup interface, and the identity information of the PCIe port corresponding to the first-level child node or the identity information of the PCIe device corresponding to the first-level child node can be determined as the identifier of the third control and displayed in the above-mentioned BIOS setup interface.

[0116] In the BIOS setup interface, create a fourth control corresponding to each second-level child node, and use the identity identifier of the PCIe device corresponding to each second-level child node as the identifier of the fourth control, which is then displayed in the BIOS setup interface.

[0117] Specifically, for each second-level child node in the PCIe topology with the above-mentioned multi-level tree structure, a fourth control corresponding to the second-level child node can be created in the above-mentioned BIOS setup interface, and the identity information of the PCIe device corresponding to the above-mentioned second-level child node can be determined as the identifier of the above-mentioned fourth control and displayed in the above-mentioned BIOS setup interface.

[0118] It should be noted that Depth-First Search (DFS) is a type of graph algorithm. In short, it delves into every possible branch path until it can go as far as it can, and each node can only be visited once.

[0119] Optionally, in this embodiment of the invention, a depth-first traversal mechanism can be used to traverse each first-level child node and each second-level child node on the link where each of the above-mentioned nodes is located, and sequentially create a second control, a third control, and a fourth control on each link in the BIOS setup interface of the target electronic device, and display the identifier of the second control, the identifier of each third control, and the identifier of each fourth control.

[0120] This invention creates a second control corresponding to each node in a multi-level tree-structured PCIe topology within the BIOS setup interface of the target electronic device. The identification information of the CPU root port corresponding to each node is used as the identifier of the second control and displayed in the BIOS setup interface. A third control is created within the BIOS setup interface for each first-level child node in the PCIe topology. The identification information of the PCIe port or the PCIe device corresponding to each first-level child node is used as the identifier of the third control and displayed in the BIOS setup interface. A fourth control is created within the BIOS setup interface for each second-level child node in the PCIe topology. The identification information of the PCIe device corresponding to each second-level child node is used as the identifier of the fourth control and displayed in the BIOS setup interface. This allows for a more intuitive display of the multi-level tree-structured PCIe topology within the BIOS setup interface, enabling users to view the PCIe topology of the target electronic device more clearly and intuitively, thus improving user perception.

[0121] Based on the above embodiments, the method further includes: using the identity identifier of the CPU root port corresponding to each node as the identifier of the second control and displaying it on the BIOS setup interface; determining the target port information of the CPU root port corresponding to each node as the display content of the second control; and displaying the target port information of the CPU root port corresponding to each node on the BIOS setup interface upon receiving a second operation on the second control.

[0122] Specifically, for each node in the PCIe topology with the above multi-level tree structure, a second control corresponding to the root node is created in the BIOS setup interface of the target electronic device, and the identity information of the CPU root port corresponding to the root node is used as the identifier of the second control. After the BIOS setup interface is displayed, the target port information of the CPU root port corresponding to the root node can be determined as the display content corresponding to the second control.

[0123] Upon receiving a second operation from the user on the second control, indicating that the user requests to view the content displayed by the second control, the target port information of the CPU root port corresponding to the root node can be displayed on the BIOS setup interface.

[0124] It should be noted that the second operation described above may include, but is not limited to, clicking, double-clicking, or dragging to a preset area. This embodiment of the invention does not specifically limit the second operation described above.

[0125] The method further includes: when the identifier of the third control is the identifier of the PCIe port corresponding to each level-one child node or the identifier of the PCIe device corresponding to each level-one child node, the target port information of the PCIe port corresponding to each level-one child node is determined as the display content of the third control, and upon receiving a third operation on the third control, the target port information of the PCIe port corresponding to each level-one child node is displayed on the BIOS setup interface; when the identifier of the third control is the identifier of the PCIe device corresponding to each level-one child node, the target device information of the PCIe device corresponding to each level-one child node is determined as the display content of the third control, and upon receiving a third operation on the third control, the target device information of the PCIe device corresponding to each level-one child node is displayed on the BIOS setup interface.

[0126] Specifically, for each first-level child node in the PCIe topology with the above-mentioned multi-level tree structure, a third control corresponding to the first-level child node is created in the BIOS setup interface of the target electronic device, and the identity information of the PCIe port corresponding to the first-level child node is used as the identifier of the third control. After the BIOS setup interface is displayed, the target port information of the PCIe port corresponding to the first-level child node can be determined as the display content corresponding to the third control.

[0127] Upon receiving a third operation from the user on the aforementioned third control, it indicates that the user requests to view the corresponding display content of the aforementioned third control. The target port information of the PCIe port corresponding to the aforementioned first-level child node can be displayed on the aforementioned BIOS setup interface.

[0128] For each first-level child node in the PCIe topology with the above multi-level tree structure, a third control corresponding to the first-level child node is created in the BIOS setup interface of the target electronic device. The identity information of the PCIe device corresponding to the first-level child node is used as the identifier of the third control. After the BIOS setup interface is displayed, the target device information of the PCIe device corresponding to the first-level child node can be determined as the display content corresponding to the third control.

[0129] Upon receiving a third operation from the user on the aforementioned third control, it indicates that the user requests to view the corresponding display content of the aforementioned third control. The target device information of the PCIe device corresponding to the aforementioned first-level sub-node can be displayed on the aforementioned BIOS setup interface.

[0130] It should be noted that the aforementioned third operation may include, but is not limited to, clicking, double-clicking, or dragging to a preset area. This embodiment of the invention does not specifically limit the aforementioned third operation.

[0131] The method further includes: using the identity identifier of the PCIe device corresponding to each secondary child node as the identifier of the fourth control and displaying it on the BIOS setup interface; determining the target device information of the PCIe device corresponding to each secondary child node as the display content of the fourth control; and displaying the target device information of the PCIe device corresponding to each secondary child node on the BIOS setup interface upon receiving a fourth operation on the fourth control.

[0132] Specifically, for each secondary child node in the PCIe topology with the above multi-level tree structure, a fourth control corresponding to the above secondary child node is created in the BIOS setup interface of the target electronic device, and the identity information of the PCIe device corresponding to the above secondary child node is used as the identifier of the above fourth control. After the above BIOS setup interface is displayed, the target device information of the PCIe device corresponding to the above secondary child node can be determined as the display content corresponding to the above fourth control.

[0133] Upon receiving a third operation from the user on the fourth control, it indicates that the user requests to view the content displayed on the fourth control. The target device information of the PCIe device corresponding to the second-level sub-node can be displayed on the BIOS setup interface.

[0134] It should be noted that the fourth operation described above may include, but is not limited to, clicking, double-clicking, or dragging to a preset area. This embodiment of the invention does not specifically limit the fourth operation described above.

[0135] It should be noted that, in order to balance performance and speed, when constructing the PCIe topology of the target electronic device based on the above target information in this invention, whether the PCIe topology has a multi-level tree structure or the nodes in the PCIe topology are in a parallel relationship, it is necessary to ignore the PCIe configuration space information of some PCIe devices and only display the identification information, more readable target device information, and target port information in the above BIOS setup interface.

[0136] This invention uses the target port information of the CPU root port corresponding to the root node in the PCIe topology of the target electronic device as the display content of the second control corresponding to the root node, the target port information of the PCIe port corresponding to the first-level child node or the target device information of the corresponding PCIe device as the display content of the third control corresponding to the first-level child node, and the target device information of the PCIe port corresponding to the second-level child node as the display content of the fourth control corresponding to the second-level child node. This allows for the display of corresponding content upon receiving user-related operations, better meeting the user's needs for viewing and analyzing PCIe device information, and improving user experience.

[0137] To facilitate understanding of the PCIe topology acquisition method provided by this invention, an example is provided below to illustrate the PCIe topology acquisition method provided by this invention.

[0138] Figure 2 This is the second flowchart illustrating the PCIe topology acquisition method provided by this invention. For example... Figure 2As shown, after starting to obtain the PCIe topology of the target electronic device, during the process of enumerating PCIe devices in the target electronic device, the original device information of each PCIe device, the original port information of each PCIe port, and the original port information of each CPU root port can be obtained.

[0139] After obtaining the above information, it can be filtered to obtain the original device information of each PCIe device in the target electronic device as the original information; or the above information can be directly used as the original information.

[0140] After obtaining the original information including the original device information of each PCIe device in the target electronic device, the original information can be parsed to obtain the target information including the target device information of each PCIe device, wherein the target device information of each PCIe device includes the identity information of each PCIe device.

[0141] Each of the above PCIe devices is identified as a node, resulting in a PCIe topology where the nodes are in parallel.

[0142] For each node in the above PCIe topology, a first control corresponding to the node is created in the BIOS setup interface of the target electronic device, and the identity information of the PCIe device corresponding to the node is used as the identifier of the first control and displayed in the BIOS setup interface.

[0143] After obtaining the original information, including the original device information of each PCIe device, the original port information of each PCIe port, and the original port information of each CPU root port in the target electronic device, the original information can be parsed to obtain target information, including the target device information of each PCIe device, the target port information of each PCIe port, and the target port information of each CPU root port. The target device information of each PCIe device includes the identification information of each PCIe device, the target port information of each PCIe port includes the identification information of each PCIe port, and the target port information of each CPU root port includes the identification information of each CPU root port.

[0144] After obtaining the above target information, the first connection relationship between the CPU root port and the PCIe port, the second connection relationship between the CPU root port and the PCIe device, and the third connection relationship between the PCIe port and the PCIe device can be obtained based on the above target information. Then, the PCIe topology of the target electronic device can be constructed based on the above first connection relationship, the above second connection relationship, and the above third connection relationship. The above PCIe topology has a multi-level tree structure.

[0145] After constructing the above PCIe topology, it can be displayed in the BIOS setup interface of the target electronic device based on a depth-first traversal mechanism. The specific steps include:

[0146] Step S1: Create a second control corresponding to the i-th root node in the above PCIe topology, and determine the identity information of the CPU root port corresponding to the i-th root node as the identifier of the first control, display it in the BIOS setup interface, and determine the target port information of the CPU root port corresponding to the i-th root node as the display content of the first control; where i takes the values ​​1, 2, 3, ..., I in sequence; M is the total number of CPU root ports in the target electronic device;

[0147] Step S2: Create a third control corresponding to the nth first-level child node under the i-th root node in the BIOS setup interface, and determine the identity of the PCIe device or the identity of the PCIe port corresponding to the nth first-level child node as the identifier of the third control, and display it in the BIOS setup interface.

[0148] When the nth first-level child node corresponds to a PCIe port, the target port information of the PCIe port corresponding to the nth first-level child node is determined as the display content of the third control; when the nth first-level child node corresponds to a PCIe device, the target device information of the PCIe port corresponding to the nth first-level child node is determined as the display content of the third control; where n takes values ​​of 1, 2, 3, ..., N; and N is the total number of first-level child nodes under the i-th root node.

[0149] Step S3: In the BIOS setup interface, create a fourth control corresponding to the m-th second-level child node under the n-th first-level child node, and determine the identity identifier of the PCIe device corresponding to the m-th second-level child node as the identifier of the fourth control. Display the target device information of the PCIe device corresponding to the m-th second-level child node in the BIOS setup interface as the display content of the fourth control; where m takes the values ​​1, 2, 3, ..., M in sequence; M is the total number of second-level child nodes under the n-th first-level node.

[0150] Step S4: Determine if m is equal to M. If not, increment m by 1 and return to step S3. If yes, proceed to step S5.

[0151] Step S5: Determine if n is equal to N. If not, increment n by 1 and return to execute steps S2, S3, and S4. If yes, execute step S6.

[0152] In step S6, it can be determined whether i is equal to I; if yes, the acquisition of PCIe topology is completed; if no, i is incremented by 1, and the process returns to steps S1 to S5.

[0153] Figure 3 This is a schematic diagram of the PCIe topology acquisition device provided by the present invention. The following is in conjunction with... Figure 3 The PCIe topology acquisition device provided by this invention will be described below. The PCIe topology acquisition device described below can be referred to in correspondence with the PCIe topology acquisition method provided by this invention described above. For example... Figure 3 As shown, the device includes: a data acquisition module 301, a data parsing module 302, and a topology display module 303.

[0154] The data acquisition module 301 is used to acquire raw information during the process of enumerating PCIe devices in the target electronic device. The raw information includes the raw device information of each PCIe device in the target electronic device.

[0155] Data parsing module 302 is used to parse the original information to obtain target information. The target information includes target device information of each PCIe device. The target device information of each PCIe device is the original device information of each PCIe device after parsing. The target device information of each PCIe device includes the identity information of each PCIe device.

[0156] The topology display module 303 is used to construct the PCIe topology of the target electronic device based on the target information, and display the PCIe topology in the BIOS setup interface of the target electronic device.

[0157] Specifically, the data acquisition module 301, the data parsing module 302, and the topology display module 303 are electrically connected.

[0158] The PCIe topology acquisition device in this embodiment of the invention acquires original information including the original device information of each PCIe device in the target electronic device during the process of enumerating the target electronic device, parses the original information to obtain target information including the target device information of each PCIe device, and then constructs the PCIe topology of the target electronic device based on the target information and displays the PCIe topology on the BIOS setup interface of the target electronic device. It can acquire the PCIe topology without relying on the Linux operating system and display the PCIe topology on the BIOS setup interface, making it more convenient and efficient for users to view the PCIe topology and improving user experience.

[0159] Figure 4 An example is a schematic diagram of the physical structure of an electronic device, such as... Figure 4 As shown, the electronic device may include a processor 410, a communications interface 420, a memory 430, and a communication bus 440. The processor 410, communications interface 420, and memory 430 communicate with each other via the communication bus 440. The processor 410 can call logical instructions in the memory 430 to execute a PCIe topology acquisition method. This method includes: acquiring raw information during the PCIe device enumeration process of the target electronic device, the raw information including the raw device information of each PCIe device in the target electronic device; parsing the raw information to obtain target information, the target information including the target device information of each PCIe device, the target device information of each PCIe device being the parsed raw device information of each PCIe device, and the target device information of each PCIe device including the identification information of each PCIe device; constructing the PCIe topology of the target electronic device based on the target information, and displaying the PCIe topology on the BIOS setup interface of the target electronic device.

[0160] Furthermore, the logical instructions in the aforementioned memory 430 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, essentially, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0161] On the other hand, the present invention also provides a computer program product, which includes a computer program that can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can execute the PCIe topology acquisition method provided by the above methods. The method includes: acquiring original information during the PCIe device enumeration process of the target electronic device, the original information including the original device information of each PCIe device in the target electronic device; parsing the original information to obtain target information, the target information including the target device information of each PCIe device, the target device information of each PCIe device being the parsed original device information of each PCIe device, and the target device information of each PCIe device including the identification information of each PCIe device; constructing the PCIe topology of the target electronic device based on the target information, and displaying the PCIe topology on the BIOS setup interface of the target electronic device.

[0162] In another aspect, the present invention also provides a non-transitory computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements the PCIe topology acquisition method provided by the above methods. The method includes: during the process of enumerating PCIe devices in a target electronic device, acquiring original information, the original information including the original device information of each PCIe device in the target electronic device; parsing the original information to obtain target information, the target information including the target device information of each PCIe device, the target device information of each PCIe device being the parsed original device information of each PCIe device, and the target device information of each PCIe device including the identification information of each PCIe device; constructing the PCIe topology of the target electronic device based on the target information, and displaying the PCIe topology on the BIOS setup interface of the target electronic device.

[0163] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0164] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0165] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for obtaining PCIe topology, characterized in that, include: During the process of enumerating PCIe devices in the target electronic device, the original information is obtained, which includes the original device information of each PCIe device in the target electronic device. Parse the original information to obtain target information. The target information includes target device information for each PCIe device. The target device information for each PCIe device is the parsed original device information of each PCIe device. The target device information for each PCIe device includes the identity information of each PCIe device. Based on the target information, the PCIe topology of the target electronic device is constructed, and the PCIe topology is displayed in the BIOS setup interface of the target electronic device; The original information also includes: the original port information of each CPU root port and the original port information of each PCIe port in the target electronic device. Accordingly, the target information further includes: target port information for each CPU root port and target port information for each PCIe port; the target port information for each CPU root port is the original port information parsed from each CPU root port; the target port information for each CPU root port includes the identity information of each CPU root port; the target port information for each PCIe port is the original port information parsed from each PCIe port; the target port information for each PCIe port includes the identity information of each PCIe port. The step of constructing the PCIe topology of the target electronic device based on the target information includes: Based on the target information, obtain the first connection relationship between the CPU root port and the PCIe port, the second connection relationship between the CPU root port and the PCIe device, and the third connection relationship between the PCIe port and the PCIe device; The PCIe topology is constructed based on the first connection relationship, the second connection relationship, and the third connection relationship; The step of constructing the PCIe topology of the target electronic device based on the first connection relationship, the second connection relationship, and the third connection relationship includes: Each CPU root port is defined as a root node in the PCIe topology; Based on the first connection relationship and the second connection relationship, each PCIe port connected to any CPU root port is determined as a first-level child node under the root node corresponding to any CPU root port, and each PCIe device connected to any CPU root port is determined as a first-level child node under the root node corresponding to any CPU root port. Based on the third connection relationship, each PCIe device connected to any PCIe port is determined as a second-level sub-node under the first-level sub-node corresponding to any PCIe port, thereby obtaining the PCIe topology.

2. The PCIe topology acquisition method according to claim 1, characterized in that, The step of constructing the PCIe topology of the target electronic device based on the target information includes: Based on the target information, each PCIe device is identified as a node in the PCIe topology, thereby constructing the PCIe topology; Accordingly, displaying the PCIe topology in the BIOS setup interface of the target electronic device includes: In the BIOS setup interface, a first control is created for each node, and the identity information of the PCIe device corresponding to each node is used as the identifier of the first control and displayed in the BIOS setup interface.

3. The PCIe topology acquisition method according to claim 1, characterized in that, The display of the PCIe topology in the BIOS setup interface of the target electronic device includes: In the BIOS setup interface, a second control is created corresponding to each node, and the identity information of the CPU root port corresponding to each node is used as the identifier of the second control and displayed in the BIOS setup interface. In the BIOS setup interface, a third control is created corresponding to each level-one child node, and the identity information of the PCIe port corresponding to each level-one child node or the identity information of the PCIe device corresponding to each level-one child node is used as the identifier of the third control and displayed in the BIOS setup interface. In the BIOS setup interface, a fourth control is created corresponding to each second-level child node, and the identity identifier of the PCIe device corresponding to each second-level child node is used as the identifier of the fourth control and displayed in the BIOS setup interface.

4. The PCIe topology acquisition method according to claim 2, characterized in that, The method further includes: creating a first control corresponding to each node in the BIOS setup interface, and using the identity information of the PCIe device corresponding to each node as the identifier of the first control, and displaying it in the BIOS setup interface; The target device information of the PCIe device corresponding to each node is displayed as the corresponding content of the first control, and the device information of the PCIe device is displayed in the BIOS setup interface when a first operation is received on the first control.

5. The PCIe topology acquisition method according to claim 3, characterized in that, The method further includes using the identifier of the CPU root port corresponding to each node as the identifier of the second control and displaying it on the BIOS setup interface. The target port information of the CPU root port corresponding to each node is determined as the display content corresponding to the second control, and the target port information of the CPU root port corresponding to each node is displayed in the BIOS setup interface when the second operation on the second control is received. The method of using the identity identifier of the PCIe port corresponding to each first-level child node or the identity identifier of the PCIe device corresponding to each first-level child node as the identifier of the third control and displaying it on the BIOS setup interface further includes: When the identifier of the third control is the identity identifier of the PCIe port corresponding to each first-level child node, the target port information of the PCIe port corresponding to each first-level child node is determined as the display content of the third control. Upon receiving a third operation on the third control, the target port information of the PCIe port corresponding to each first-level child node is displayed on the BIOS setup interface. When the identifier of the third control is the identity identifier of the PCIe device corresponding to each first-level child node, the target device information of the PCIe device corresponding to each first-level child node is determined as the display content of the third control, and when a third operation is received on the third control, the target device information of the PCIe device corresponding to each first-level child node is displayed on the BIOS setup interface. The method further includes using the identity identifier of the PCIe device corresponding to each secondary child node as the identifier of the fourth control and displaying it on the BIOS setup interface: The target device information of the PCIe device corresponding to each secondary sub-node is determined as the display content corresponding to the fourth control, and the target device information of the PCIe device corresponding to each secondary sub-node is displayed on the BIOS setup interface upon receiving the fourth operation on the fourth control.

6. A PCIe topology acquisition device, characterized in that, The apparatus is used to implement the PCIe topology acquisition method as described in any one of claims 1 to 5.

7. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the program, it implements the PCIe topology acquisition method as described in any one of claims 1 to 5.

8. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the PCIe topology acquisition method as described in any one of claims 1 to 5.

9. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by the processor, it implements the PCIe topology acquisition method as described in any one of claims 1 to 5.

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