Circuit simulation verification method, verification device, electronic device and readable storage medium

Abstract

The present disclosure provides a circuit simulation verification method, a verification device, an electronic device and a readable storage medium, which relate to the field of memory technology. The circuit simulation verification method includes: obtaining simulation excitation information of the chip circuit to be verified, the simulation excitation information includes the input excitation of the chip to be verified, the output signal to be measured and the expected simulation result; performing timing simulation on the chip circuit to be verified based on the input excitation to obtain the timing simulation result of the chip to be verified; sampling the timing simulation result based on multiple groups of timing sampling moments to obtain multiple groups of simulation sampling results of the output signal to be measured; comparing the expected simulation result with the multiple groups of simulation sampling results respectively to generate multiple verification result record files; optimizing and adjusting the chip circuit to be verified based on the multiple verification result record files. Through the technical solution of the present disclosure, the obtained verification result has higher verification accuracy.

Description

Technical Field

[0001] The present disclosure relates to the field of memory technology, and in particular to a circuit simulation verification method, a circuit simulation verification device, an electronic device, and a computer-readable storage medium. Background Art

[0002] Simulation software is used to perform timing simulation verification of memory chips. The memory controller of the memory chip can convert a large number of test cases into simulation stimuli, input the stimuli into the memory chip's circuit under test (DUT), and capture the response of the DUT output. The captured response level data is compared with the expected level data output by the ideal reference model (golden model) at the center point of the half-clock cycle to check whether the levels are consistent. Based on the comparison results, a simulation verification result can be obtained. However, due to the limitation of the sampling point, this solution has a high probability of false errors in the comparison results, resulting in low accuracy of the output simulation verification results.

[0003] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to ordinary technicians in the field. Summary of the Invention

[0004] The purpose of the present disclosure is to provide a circuit simulation verification method, a verification device, an electronic device and a readable storage medium, which at least to some extent overcome the problem of low accuracy of simulation verification results outputted in related technologies.

[0005] Other features and advantages of the present disclosure will become apparent from the following detailed description, or may be learned in part by practice of the present disclosure.

[0006] According to one aspect of the present disclosure, a circuit simulation verification method is provided, comprising: obtaining simulation excitation information of a chip circuit to be verified, the simulation excitation information including an input excitation, an output signal to be measured, and an expected simulation result of the chip to be verified; performing a timing simulation on the chip circuit to be verified based on the input excitation to obtain a timing simulation result of the chip to be verified; sampling the timing simulation result based on multiple groups of sampling moment sequences to obtain multiple groups of simulation sampling results of the output signal to be measured; comparing the expected simulation result with the multiple groups of simulation sampling results respectively to generate multiple verification result record files; and optimizing and adjusting the chip circuit to be verified based on the multiple verification result record files.

[0007] In one embodiment of the present disclosure, the simulation excitation information also includes a reference clock signal. Before sampling the timing simulation results based on multiple groups of sampling moment sequences, it also includes: determining the multiple groups of sampling moment sequences based on the reference clock signal, wherein the sampling periods of the multiple groups of sampling moment sequences are the same, and the sampling periods are related to the period of the reference clock signal; sampling the timing simulation results based on multiple groups of sampling moment sequences includes: sampling the timing simulation results based on a sampling moment in each group of the sampling moment sequences within each sampling window of the reference clock signal, wherein the sampling intervals between the multiple sampling moments are equal, and the duration of the sampling window is equal to the duration of the sampling period.

[0008] In one embodiment of the present disclosure, the simulation expected results and the multiple groups of simulation sampling results are compared respectively to generate multiple verification result record files, including: obtaining simulation parameters of the chip to be verified; determining high and low level dividing values of the timing simulation results based on the simulation parameters; determining multiple groups of simulation sampling value sequences corresponding to the multiple groups of simulation sampling results based on the high and low level dividing values, and obtaining simulation expected value sequences corresponding to the simulation expected results; comparing the simulation expected value sequences with the multiple groups of simulation sampling value sequences respectively to generate the multiple verification result record files, wherein, in the verification result record files, the comparison results of the simulation expected results and the multiple groups of simulation sampling results are set corresponding to the simulation parameters.

[0009] In one embodiment of the present disclosure, the multiple groups of sampling moment sequences include a first sampling moment sequence, a second sampling moment sequence and a third sampling moment sequence, the sampling moments in the first sampling moment sequence are recorded as first sampling moments, and the first sampling moments are aligned with the center of the sampling window, the sampling moments in the second sampling moment sequence are recorded as second sampling moments, and the second sampling moments are left-deflected relative to the center of the sampling window, the sampling moments in the third sampling moment sequence are recorded as third sampling moments, and the third sampling moments are right-deflected relative to the center of the sampling window, wherein the relative left deviation or relative right deviation offset is determined based on the adjustment results of multiple rounds of tests, or the offset is determined based on the simulation parameters.

[0010] In one embodiment of the present disclosure, the simulation expected value sequence and the multiple groups of simulation sampling value sequences are compared respectively to generate the multiple verification result record files, including: comparing the first simulation expected value of each first sampling moment and the corresponding first simulation sampling value, the second simulation expected value of each second sampling moment and the corresponding second simulation sampling value, and the third simulation expected value of each third sampling moment and the corresponding third simulation sampling value, to obtain the multiple verification result record files; wherein, if the comparison results are consistent, the verification is recorded as passed in the corresponding verification result record file, and if the comparison results are inconsistent, the verification is recorded as failed in the corresponding verification result record file.

[0011] In one embodiment of the present disclosure, the optimizing and adjusting the circuit of the chip to be verified based on the multiple verification result record files includes: determining a target verification result record file from the multiple verification result record files, the target verification result record file being the verification result record file with the least verification failure records; optimizing and adjusting the circuit based on the target verification result record file.

[0012] In one embodiment of the present disclosure, it also includes: the simulation parameters include process angle data, PVT parameters, operating frequency and operating mode; the sampling interval is determined based on the sampling period and the number of groups of the sampling moment sequence, or the sampling interval is determined based on the number of groups of the sampling moment sequence and the error range in the standard specification file, or the sampling interval is determined based on at least one of the process angle data, the PVT parameters and the operating frequency; and the output pin of the output signal to be measured is determined based on the operating mode.

[0013] According to another aspect of the present disclosure, a circuit simulation verification device is provided, including: an acquisition module for acquiring simulation excitation information of a chip circuit to be verified, the simulation excitation information including input excitation, output signal to be measured and expected simulation result of the chip to be verified; a simulation module for performing timing simulation on the chip circuit to be verified based on the input excitation to obtain timing simulation results of the chip to be verified; a sampling module for sampling the timing simulation results based on multiple groups of sampling moment sequences to obtain multiple groups of simulation sampling results of the output signal to be measured; a comparison module for comparing the expected simulation result with the multiple groups of simulation sampling results respectively to generate multiple verification result record files; and an optimization module for optimizing and adjusting the chip circuit to be verified based on the multiple verification result record files.

[0014] According to another aspect of the present disclosure, an electronic device is provided, comprising: a processor; and a memory for storing executable instructions of the processor; wherein the processor is configured to perform any one of the above-mentioned circuit simulation verification methods by executing the executable instructions.

[0015] According to another aspect of the present disclosure, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the circuit simulation verification method described above is implemented.

[0016] The circuit simulation verification scheme provided by the embodiments of the present disclosure obtains simulation stimulus information of the chip to be verified, performs timing simulation on the chip to be verified based on the simulation stimulus information, and obtains timing simulation results. By configuring at least three groups of sampling moment sequences, the timing simulation results are sampled based on these sampling moment sequences to obtain corresponding multiple groups of simulation sampling results. Each group of simulation sampling results is compared with the expected simulation results to obtain multiple verification result record files, and then the circuit of the chip to be verified is optimized based on these verification result record files. The configuration of multiple groups of sampling moment sequences can make the sampling moments cover different moments within a clock cycle as much as possible, so that the sampling results can take into account different output working conditions, which is conducive to improving the reliability of the sampling operation. Accordingly, it is conducive to reducing the probability of false errors in the simulation results. By comparing the simulation sampling results with the expected simulation results, the obtained verification results have higher verification accuracy, so that when the circuit optimization adjustment is performed based on the verification result record file, the adjustment operation is more efficient and the reliability of the adjustment result is more reliable.

[0017] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0019] Figure 1 A schematic flow chart illustrating a circuit simulation verification method provided by an embodiment of the present disclosure is shown;

[0020] Figure 2 A schematic flow chart illustrating a circuit simulation verification method provided by another embodiment of the present disclosure is shown;

[0021] Figure 3A schematic flow chart showing a circuit simulation verification method provided by yet another embodiment of the present disclosure is shown;

[0022] Figure 4 A schematic diagram showing sampling of a simulation curve at a first sampling moment in an embodiment of the present disclosure is shown;

[0023] Figure 5 A schematic diagram illustrating sampling a simulation curve at a second sampling time in an embodiment of the present disclosure is shown;

[0024] Figure 6 A schematic diagram illustrating sampling of a simulation curve at a third sampling moment in an embodiment of the present disclosure is shown;

[0025] Figure 7 A schematic diagram showing a comparison window in an embodiment of the present disclosure;

[0026] Figure 8 A schematic flow chart illustrating a circuit simulation verification method provided by yet another embodiment of the present disclosure is shown;

[0027] Figure 9 A schematic block diagram of a circuit simulation verification device provided by one embodiment of the present disclosure;

[0028] Figure 10 A schematic diagram of the structure of a computer system provided for one embodiment of the present disclosure and suitable for implementing an electronic device of the present disclosure is provided. DETAILED DESCRIPTION

[0029] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be embodied in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0030] In addition, the accompanying drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale. Identical reference numerals in the figures denote identical or similar parts, and thus repetitive descriptions thereof will be omitted. Some of the block diagrams shown in the accompanying drawings are functional entities that do not necessarily correspond to physically or logically separate entities. These functional entities may be implemented in software, in one or more hardware modules or integrated circuits, or in different networks and / or processor devices and / or microcontroller devices.

[0031] like Figure 1 As shown, a circuit simulation verification method according to an embodiment of the present disclosure includes:

[0032] Step S102 : obtaining simulation stimulus information of the chip circuit to be verified, where the simulation stimulus information includes input stimulus, output signal to be measured, and expected simulation result of the chip to be verified.

[0033] Among them, test cases are collected to obtain simulation stimulus information through the test cases. The expected simulation results are generated by inputting the test cases into the standard model golden model. The output signal to be tested corresponds to the output pin to be tested. There can be multiple output signals to be tested. Accordingly, the expected simulation results include the expected value sequence corresponding to each output signal to be tested.

[0034] In addition, the simulation stimulus information also includes input stimulus as a simulation condition, a reference clock signal CLK, and the like.

[0035] Those skilled in the art will appreciate that the simulation result is expected to be aligned with the external clock signal CLK in terms of timing, or have a fixed delay.

[0036] Step S104 , performing timing simulation on the circuit of the chip to be verified based on the input stimulus to obtain a timing simulation result of the chip to be verified.

[0037] Among them, Fine sim is used to perform timing simulation verification, and the timing simulation results include the timing simulation result file of the output signal to be tested of the output pin to be tested.

[0038] Step S106 , sampling the timing simulation results based on the multiple sets of sampling time sequences to obtain multiple sets of simulation sampling results of the output signal to be measured.

[0039] The output signals to be tested include but are not limited to a data strobe signal DQS (data strobe signal) output by a data strobe pin of the chip to be verified and a readout data signal DQ (data signal) output by a data output port of the chip to be verified.

[0040] The multiple groups of sampling time sequences are specifically at least three groups of sampling time sequences.

[0041] The simulation sampling result of each output signal to be measured is a set of voltage values corresponding to the sampling time sequence. By setting the 0 / 1 dividing point of the voltage, the set of voltage values is converted into a set of numerical values, that is, the simulation sampling value sequence.

[0042] Since the timing relationship between the clock signal and the expected result of the standard model output is fixed, the simulation expected value used for comparison does not need to be sampled.

[0043] Step S108 : comparing the expected simulation results with the multiple groups of simulation sampling results respectively, and generating multiple verification result record files.

[0044] Among them, for multiple groups of simulation sampling results, multiple comparator checkers need to be configured, and each comparator is used to compare a group of simulation sampling results with the simulation expected results.

[0045] Step S110 , optimizing and adjusting the circuit of the chip to be verified based on the multiple verification result record files.

[0046] The circuit of the chip to be verified is optimized and adjusted based on multiple verification result record files. Specifically, a target verification result record file is selected to optimize and adjust the circuit based on the target verification result record file.

[0047] In this embodiment, by obtaining simulation excitation information of the chip to be verified, timing simulation is performed on the chip to be verified based on the simulation excitation information to obtain timing simulation results, and by configuring at least three groups of sampling moment sequences, the timing simulation results are sampled based on these sampling moment sequences to obtain corresponding multiple groups of simulation sampling results, and each group of simulation sampling results is compared with the expected simulation results to obtain multiple verification result record files, and then the circuit of the chip to be verified is optimized based on these verification result record files. The configuration of multiple groups of sampling moment sequences can make the sampling moments cover different moments within a clock cycle as much as possible, so that the sampling results can take into account different output conditions, which is conducive to improving the reliability of the sampling operation, and accordingly, it is conducive to reducing the probability of false errors in the simulation results. By comparing the simulation sampling results with the expected simulation results, the obtained verification results have higher verification accuracy, so that when the circuit optimization adjustment is performed based on the verification result record file, the adjustment operation is more efficient and the reliability of the adjustment result is higher.

[0048] like Figure 2 As shown, in one embodiment of the present disclosure, the simulation stimulus information further includes a reference clock signal.

[0049] Step S202 , performing timing simulation on the output signal to be tested based on the input stimulus to obtain a timing simulation result of the chip to be verified.

[0050] Step S204 : determining a plurality of sampling time sequences based on the reference clock signal, wherein the sampling periods of the plurality of sampling time sequences are the same, and the sampling periods are related to the period of the reference clock signal.

[0051] Among them, the sampling period is related to the period of the reference clock signal, specifically, the sampling period and the reference clock signal are in a proportional relationship. Specifically, the ratio between the sampling period and the reference clock signal can be 0.5, 1, and 2, etc. The specific value is determined based on the relationship between DQ data transmission and CLK in the actual circuit. For example, one DQ data is sampled every half CLK cycle, the ratio is 0.5, and one DQ data is sampled every CLK cycle, the ratio is 1.

[0052] Step S206 , sampling the timing simulation results based on a sampling moment in each group of sampling moment sequences in each sampling window of the reference clock signal, to obtain multiple groups of simulation sampling results of the output signal to be measured.

[0053] The sampling intervals between the multiple sampling moments are equal, and the duration of the sampling window is equal to the duration of the sampling period.

[0054] Specifically, it is assumed that there are three sets of sampling time sequences. Within one sampling period, that is, within one sampling window, there are three sampling times, and the intervals between any two of these three sampling times are equal.

[0055] Step S208 : comparing the expected simulation results with the multiple groups of simulation sampling results respectively, and generating multiple verification result record files.

[0056] Step S210 : optimizing and adjusting the circuit of the chip to be verified based on the multiple verification result record files.

[0057] In this embodiment, multiple groups of sampling moment sequences are determined based on a reference clock signal to ensure that the sampling moments in these multiple groups of sampling moment sequences are related to the period of the reference clock signal, thereby further achieving that multiple sampling moments can be evenly distributed within one clock cycle, so that the output signal to be measured can be sampled based on multiple sampling moments, and the sampling results can be further screened to obtain the sampling results with the least false errors as the target verification result record file to ensure the effectiveness of the optimization and adjustment operation.

[0058] like Figure 3 As shown, in one embodiment of the present disclosure, in step S208, a specific implementation method of comparing the simulation expected result and the multiple groups of simulation sampling results to generate multiple verification result record files includes:

[0059] Step S302 : obtaining simulation parameters of the chip to be verified, wherein the simulation parameters include process corner data, PVT parameters, operating frequency, operating mode, etc.

[0060] Specifically, simulation parameters are obtained from test cases.

[0061] Among them, for semiconductor devices such as chips, it is necessary to ensure that the performance of the device is within the required range during design. This range is given in the form of a "process angle". There are five process angles mentioned: TT, FF, SS, FS, and SF. T stands for Typical, F stands for Fast, and S stands for Slow. The two letters represent the driving current of the NMOS tube and the PMOS tube, respectively. For example, FS means that the driving current of the NMOS tube is the maximum value, and the driving current of the PMOS tube is the minimum value.

[0062] The PVT (process, voltage, temperature) parameters include P, V, and T. P refers to the process fluctuation parameter, V refers to the voltage parameter of the chip to be verified, and T is the operating temperature of the chip to be verified.

[0063] The operating frequency may specifically be the clock frequency at which the CPU core of the chip operates.

[0064] The working modes include x4 / x8 / x16, etc.

[0065] Step S304: determining a high-level and low-level boundary value of the timing simulation result based on the simulation parameters.

[0066] Step S306 , determining multiple groups of simulation sampling value sequences corresponding to the multiple groups of simulation sampling results based on the high and low level dividing values, and obtaining simulation expected value sequences corresponding to the simulation expected results.

[0067] Specifically, the expected simulation result is a set of sampled voltage values. If the sampled voltage value is greater than or equal to the high-low level dividing value, the sampled voltage value is regarded as a high level 1. If the sampled voltage value is less than the high-low level dividing value, the sampled voltage value is regarded as a low level 0. Through this processing operation, multiple sets of simulation sampled value sequences can be obtained, and accordingly, a simulation expected value sequence is obtained.

[0068] Step S308 : Compare the simulation expected value sequence and the multiple groups of simulation sampling value sequences respectively to generate multiple verification result record files, wherein the comparison results of the simulation expected results and the multiple groups of simulation sampling results are set correspondingly to the simulation parameters in the verification result record files.

[0069] In this embodiment, the high and low level boundary values of the timing simulation results are determined based on the simulation parameters, and based on the high and low level boundary values, multiple groups of timing simulation results representing voltage values are converted into multiple groups of 01 numerical values, and the expected simulation results are converted into a group of 01 numerical values. By comparing whether the numerical values at the same sampling moment are consistent, multiple verification result record files are obtained.

[0070] In one embodiment of the present disclosure, multiple groups of sampling moment sequences include a first sampling moment sequence, a second sampling moment sequence and a third sampling moment sequence. The sampling moments in the first sampling moment sequence are recorded as first sampling moments, and the first sampling moments are aligned with the center of the sampling window. The sampling moments in the second sampling moment sequence are recorded as second sampling moments, and the second sampling moments are offset to the left relative to the center of the sampling window. The sampling moments in the third sampling moment sequence are recorded as third sampling moments, and the third sampling moments are offset to the right relative to the center of the sampling window.

[0071] The relative left or right offset is determined based on adjustment results of multiple rounds of tests, or the offset is determined based on simulation parameters.

[0072] In this embodiment, the multiple groups of time series sampling moments are specifically three groups, namely a first sampling moment sequence, a second sampling moment sequence and a third sampling moment sequence. The first group of sampling moments is regarded as a reference sampling moment sequence, the second sampling moment sequence is left-biased relative to the first sampling moment sequence, and the third sampling moment sequence is right-biased relative to the first sampling moment sequence. In the sampling window, the first sampling moment in the first sampling moment sequence is at the center position, the second sampling moment in the second sampling moment sequence is to the left of the center, and the third sampling moment in the third sampling moment sequence is to the right of the center, wherein the left offset and the right offset are equal.

[0073] Furthermore, the left / right time offset can be gradually adjusted during multi-lane testing, that is, from the maximum range, which is half of the sampling window length, to the range required by the standard specification document, and then gradually reduced to a smaller range to meet the chip product yield and factory requirements.

[0074] Specifically, Tck is used to represent the clock period of the reference clock signal to determine multiple groups of sampling time sequences based on the reference clock signal. The multiple groups of sampling time sequences include a first sampling time sequence Ta, a second sampling time sequence and a third sampling time sequence. In addition, based on the obtained simulation parameters including process angle data, PVT parameters, operating frequency and operating mode, the high and low level boundary values are determined.

[0075] Figure 4 A timing diagram of the first sampling moment sequence is shown. The sampling period, that is, the sampling interval between two adjacent sampling moments, is 1 / 2Tck, and 1 / 2 Tck is determined as a sampling window. If the timing simulation results of the output signal DQ / DQS to be measured and the expected simulation results are relatively aligned in timing or the deviation is small, the 0.25Tck position and 0.75Tck position of each reference clock signal can be used as the first sampling moment, such as ta1, ta2, ta3, ta4, ..., tai, etc., to form the first sampling moment sequence Ta.

[0076] Based on the first sampling moment sequence Ta, the timing simulation results of the output signal DQ / DQS to be tested are sampled, and the first group of simulation sampling results are [0.7V, 0.6V, 0.68V, 0.55V, ..., 0.68V], and the high-low level dividing value = 0.5V. Based on the high-low level dividing value, the first group of simulation sampling value sequence corresponding to the first group of simulation sampling results is determined to be [1, 1, 1, 1, ..., 1]. Combined with the simulation expected value sequence corresponding to the simulation expected result is [1, 0, 1, 0, ..., 0], the target verification result record file is finally generated based on the simulation sampling results collected at the first sampling moment.

[0077] Figure 5 A timing diagram of the second sampling moment sequence is shown. The sampling interval between two adjacent sampling moments is 0.5Tck, and 1 / 2 Tck is determined as a sampling window. If the timing simulation result of the output signal DQ / DQS to be measured is left-shifted in timing relative to the expected simulation result, multiple second sampling moments can be determined based on the offset, where the maximum left-shift range is 0.25Tck. For example, the 0.0Tck position and 0.50Tck position of each reference clock signal are used as the second sampling moments, such as tb1, tb2, tb3, tb4, ..., tbi, etc., to form the second sampling moment sequence Tb.

[0078] The timing simulation results are sampled based on the second sampling time sequence Tb, and the second group of simulation sampling results are [0.6V, 0.7V, 0.58V, 0.75V, ..., 0.85V], and the high and low level dividing value = 0.5V. Then, based on the high and low level dividing value, the second group of simulation sampling value sequence corresponding to the second group of simulation sampling results is determined to be [1, 1, 1, 1, ..., 1]. Combined with the simulation expected value sequence corresponding to the expected result, it is [1, 1, 1, 1, ..., 1]. At this time, if the timing simulation result of the output signal DQ / DQS to be measured is relatively aligned with the simulation expected result, the target verification result record file is finally generated based on the simulation sampling result collected at the second sampling time.

[0079] Figure 6 A timing diagram of the third sampling moment sequence is shown. The sampling interval between two adjacent sampling moments is 0.5Tck, and 1 / 2 Tck is determined as a sampling window. If the timing simulation results of the output signal DQ / DQS to be measured are right-skewed in timing relative to the expected simulation results, multiple second sampling moments can be determined based on the offset, where the maximum right-skew range is 0.25Tck. For example, 0.49tCK or 0.99tCK of each reference clock signal is used as the third sampling moment, such as tc1, tc2, tc3, tc4, ..., tci, etc., to form the second sampling moment sequence Tc.

[0080] The timing simulation results are sampled based on the third sampling time sequence Tc, and the third group of simulation sampling results are [0.72V, 0.55V, 0.7V, 0.54V, ..., 0.6V], and the high-low level dividing value = 0.5V. Then, based on the high-low level dividing value, the first group of simulation sampling value sequence corresponding to the first group of simulation sampling results is determined to be [1, 1, 1, 1, ..., 1], and the simulation expected value sequence corresponding to the simulation expected result is [1, 0, 1, 0, ..., 0]. At this time, if the timing simulation results of the output signal DQ / DQS to be measured are relatively aligned with the simulation expected results, the target verification result record file is finally generated based on the simulation sampling results collected at the third sampling time.

[0081] Table 1 shows the comparison results between the simulation sampling value sequence obtained by sampling the simulation sampling results based on any sampling time sequence and the corresponding simulation expected value.

[0082] Table 1

[0083]

[0084] Table 2 shows the verification result record files obtained by combining different simulation parameters as input stimuli, where F refers to Fast, S refers to Slow, P refers to Pmos, FAIL refers to the comparison results in the verification result record file that show inconsistency between the expected simulation results and the simulation sampling results, and PASS refers to the comparison results in the verification result record file that show no inconsistency between the expected simulation results and the simulation sampling results.

[0085] Table 2

[0086]

[0087]

[0088] In this embodiment, the timing simulation results and the expected simulation results are sampled respectively to obtain corresponding first sampling points and second sampling points, and the timing offset of the timing simulation results of the output signal to be measured is obtained by comparing the first sampling point and the second sampling point. By detecting the timing offset, it is determined whether the status of the simulation result is successful or failed. The timing simulation results and the expected simulation results are sampled respectively by configuring multiple sampling moments within a half clock cycle based on the estimated position relationship of the timing simulation results relative to the clock signal, so that the obtained sampling points can cover different output working conditions based on the estimated position relationship, so as to improve the reliability of the sampling operation, help reduce the probability of false errors in the simulation results, and thus improve the accuracy of the simulation results and the efficiency of circuit debugging.

[0089] In one embodiment of the present disclosure, in step S308, a specific implementation method of comparing the simulation expected value sequence and the multiple groups of simulation sample value sequences to generate multiple verification result record files includes:

[0090] Compare the first simulation expected value and the corresponding first simulation sampling value at each first sampling moment, the second simulation expected value and the corresponding second simulation sampling value at each second sampling moment, and the third simulation expected value and the corresponding third simulation sampling value at each third sampling moment to obtain multiple verification result record files, wherein if the comparison results are consistent, the verification is recorded as passed in the corresponding verification result record file; if the comparison results are inconsistent, the verification failure is recorded in the corresponding verification result record file.

[0091] In this embodiment, for any one or more sets of simulation sampling value sequences, they are compared with the simulation expected value sequences, that is, for the same sampling moment, whether the corresponding simulation sampling values and simulation expected values are consistent is detected. If they are consistent, it means that the actual simulation results are consistent with the expected simulation results, and the simulation result of this point is determined to be passed. If they are inconsistent, it means that the actual simulation results are inconsistent with the expected simulation results, and the simulation result of this point is determined to be failed, that is, the verification failure is recorded, and a verification result record file is generated based on the recorded results, so as to further optimize and adjust the circuit based on the multiple sets of verification result record files.

[0092] In one embodiment of the present disclosure, optimizing and adjusting the circuit of a chip to be verified based on multiple verification result record files includes:

[0093] A target verification result record file is determined from multiple verification result record files, where the target verification result record file is a verification result record file with the least verification failure records, and the circuit is optimized and adjusted based on the target verification result record file.

[0094] Among them, the verification result record file with the least number of verification failures, that is, the simulation sampling results obtained by sampling using the corresponding sampling time sequence, produces fewer false errors than the expected simulation results. Therefore, the verification result record file generated by the sampling time sequence is used as the target verification result record file to optimize and adjust the circuit based on the target verification result record file to ensure the accuracy of the optimization and adjustment operation.

[0095] Specifically, the statistical results of the three sampling time series are printed separately. If one of the sampling time sequences does not report a fail point, that is, there is no failure record, the simulation result is considered to be PASS. When all three groups of sampling simulation results report a fail point, the results of the sampling time sequence with fewer fail points will be output to the file 0.err0.Real.

[0096] The circuit is adjusted based on the verification record, that is, the corresponding parameters such as Corner and speed are determined by the fail point, and the circuit is adjusted by adjusting these parameters.

[0097] In this embodiment, when performing Finesim timing simulation verification, there will be a large number of test cases. When the simulation is completed or during the simulation, a matrix table is generated corresponding to different sampling time sequences to record the pass / fail status of the DUT output under these conditions. This serves as a verification result record file. Based on this verification result record file, circuit modification and optimization can be carried out. By combining the use of more clocks for sampling, more possibilities can be covered. This solution can more effectively screen out false errors.

[0098] In one embodiment of the present disclosure, the simulation parameters include process corner data, PVT parameters, operating frequency, and operating mode.

[0099] The sampling interval, that is, the time interval between two adjacent sampling moments in a sampling period, can be determined in the following ways, but is not limited to.

[0100] The first method is to determine the sampling interval based on the sampling period and the number of groups of the sampling time sequence.

[0101] Specifically, assuming that the length of the sampling period is 1 / 2 of the length of the reference clock signal, that is, 1 / 2T, and the number of groups of sampling time sequences is 3, the time interval can be set to 0.24T.

[0102] The second method is to determine the sampling interval based on the number of groups in the sampling time series and the error range in the standard specification file.

[0103] The third method is to determine the sampling interval based on at least one of process angle data, PVT parameters, and operating frequency.

[0104] In addition, in order to obtain the output signal to be measured, it is also necessary to determine the output pin of the output signal to be measured, and the output pin of the output signal to be measured is determined based on the working mode.

[0105] Specifically, the chip output pins include data selection pins LDQS (Low DQS) and UDQS (Up DQS), where LDQS and LDQS# correspond to low bytes DQ0 to DQ7, which are output when reading and input when writing, and UDQS and UDQS# correspond to high bytes DQ8 to DQ15, which are output when reading and input when writing.

[0106] In one embodiment of the present disclosure, optimizing and adjusting the circuit based on the target verification result record file further includes: determining failed pins among chip pins based on the target verification result record file, and debugging the corresponding circuit based on the failed pins.

[0107] In this embodiment, by determining the chip pins for receiving simulation stimuli, after outputting the verification record, the connected circuits can be modified and optimized for the failed pins, thereby facilitating improved modification and optimization efficiency.

[0108] In one embodiment of the present disclosure, comparing the timing offset of the corresponding first sampling point relative to the second sampling point within the comparison window further includes: detecting the working state of the chip pin, and determining the comparison window when the working state is a data output state.

[0109] Specifically, the data output state is a data reading state.

[0110] like Figure 7 As shown, within the comparison window, the chip pins used to output the timing simulation results are in the output state, so as to compare the timing simulation results with the expected simulation results.

[0111] Taking Fine sim timing simulation verification as an example, a large number of test cases are required to perform timing simulation verification, where a test case includes process corner data of PVT combination, chip frequency and mode, etc.

[0112] The test cases generated at different process corners and frequency speeds are converted into stimulus inputs and simulated into the chip DUT to be verified to generate timing simulation results. Based on the statistical results of the timing offset between the timing simulation results and the expected waveform, the simulation status (i.e., valid or failed) record is determined, so that only the failed test cases need to be debugged and optimized.

[0113] Specifically, if Figure 8 As shown, based on the statistical results of the timing offset between the timing simulation results and the expected waveform, the process of determining the simulation status includes:

[0114] Step S802 : According to the timing delay range specified in the standard specification file corresponding to the chip to be verified, half a clock cycle is determined as a sampling cycle, so as to configure multiple timing sampling moments within the sampling cycle.

[0115] Among them, three sampling moments can be set within one clock cycle. Compared with the clock signal CKT, when the output signal DQ / DQS to be measured is right-skewed, 0.49tCK / 0.99tCK is used as the sampling moment. When the output signal DQ / DQS to be measured is left-skewed, 0.0tCK / 0.50tCK is used as the sampling moment. When the output signal DQ / DQS to be measured is aligned with the clock signal, 0.25tCK / 0.75tCK is used as the sampling moment.

[0116] Step S804 : determining a high-level and low-level boundary value based on simulation parameters of the chip to be verified.

[0117] The simulation parameters include process angle data, PVT parameters, operating frequency, and operating mode. The operating frequency can be determined according to the frequency of an externally set reference clock signal.

[0118] Step S806 , performing timing simulation on the circuit of the chip to be verified based on the simulation tool in combination with input stimulus to obtain a timing simulation result of the chip to be verified.

[0119] Step S808 , sampling the timing simulation results and the simulation expected results at multiple sampling moments within a sampling period to obtain multiple groups of simulation sampling results of the output signal to be measured.

[0120] Step S810 , determining a simulation expected value sequence corresponding to the simulation expected result and multiple groups of simulation sampling value sequences corresponding to the multiple groups of simulation sampling results based on the high and low level dividing values.

[0121] Step S812 : comparing the simulation expected value sequence and the multiple groups of simulation sampling value sequences respectively to compare whether the sampling values at the same sampling moment are consistent with the expected values, and generating multiple verification result record files.

[0122] Among them, since the timing delay ranges under different process angles are different, the output sampling points are also different.

[0123] Step S814: determining a target verification result record file from the plurality of verification result record files, where the target verification result record file has the least number of verification failures.

[0124] Step S816: Optimize and adjust the circuit based on the target verification result record file.

[0125] Specifically, after detecting whether the timing offset is within the timing delay range, the simulation stimulus includes the expected value at different times. By comparing it with the output signal to be tested in real time, three sampling moments are proposed for the three situations of DQS / DQ left deviation, right deviation and middle deviation compared with CKT. As long as the verification at one of the moments passes, the simulation verification is considered to have passed.

[0126] In this embodiment, by using more clocks for sampling, more possibilities can be covered, and false errors can be screened out more effectively. To improve debug efficiency, a table summarizing the status of each test case needs to be compiled. Design verification personnel will optimize and debug the chip circuit for failed cases.

[0127] It should be noted that the above figures are merely illustrative of the processes included in the method according to exemplary embodiments of the present invention and are not intended to be limiting. It is readily understood that the processes illustrated in the above figures do not indicate or limit the temporal order of these processes. Furthermore, it is readily understood that these processes may be executed synchronously or asynchronously, for example, in multiple modules.

[0128] Those skilled in the art will appreciate that various aspects of the present invention may be implemented as systems, methods, or program products. Therefore, various aspects of the present invention may be implemented in the following forms: a complete hardware implementation, a complete software implementation (including firmware, microcode, etc.), or a combination of hardware and software implementations, which may be collectively referred to herein as "circuits," "modules," or "systems."

[0129] Refer to the following Figure 9 A circuit simulation verification apparatus 900 according to this embodiment of the present invention will be described. Figure 9 The circuit simulation verification device 900 shown is merely an example and should not limit the functions and scope of use of the embodiments of the present invention.

[0130] The circuit simulation verification apparatus 900 is implemented as a hardware module. The components of the circuit simulation verification apparatus 900 may include, but are not limited to: an acquisition module 902 for acquiring simulation stimulus information for the circuit of the chip to be verified, the simulation stimulus information including the input stimulus, the output signal to be measured, and the expected simulation result of the chip to be verified; a simulation module 904 for performing timing simulation on the output signal to be measured based on the input stimulus to obtain the timing simulation result of the chip to be verified; a sampling module 906 for sampling the timing simulation result based on multiple sets of sampling time sequences to obtain multiple sets of simulation sampling results of the output signal to be measured; a comparison module 908 for comparing the expected simulation result with the multiple sets of simulation sampling results to generate multiple verification result record files; and an optimization module 910 for optimizing and adjusting the circuit of the chip to be verified based on the multiple verification result record files.

[0131] Reference below Figure 10 , which shows a structural diagram of a computer system 1000 suitable for implementing an electronic device of an embodiment of the present disclosure. Figure 10 The computer system 1000 of the electronic device shown is only an example and should not limit the functions and scope of use of the embodiments of the present disclosure.

[0132] like Figure 10As shown, computer system 1000 includes a central processing unit (CPU) 1001, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 1002 or a program loaded from a storage unit 1008 into a random access memory (RAM) 1003. Various programs and data required for system operation are also stored in RAM 1003. CPU 1001, ROM 1002, and RAM 1003 are connected to each other via a bus 1004. An input / output (I / O) interface 10010 is also connected to bus 1004.

[0133] The following components are connected to the I / O interface 1005: an input section 1006 including a keyboard, a mouse, and the like; an output section 1007 including devices such as a cathode ray tube (CRT), a liquid crystal display (LCD), and a speaker; a storage section 1008 including a hard disk; and a communication section 1009 including a network interface card such as a LAN card or a modem. The communication section 1009 performs communication processing via a network such as the Internet. A drive 1010 is also connected to the I / O interface 1005 as needed. A removable medium 1013, such as a magnetic disk, an optical disk, a magneto-optical disk, or a semiconductor memory, is installed in the drive 1010 as needed, so that computer programs read therefrom can be installed into the storage section 1008 as needed.

[0134] As another aspect, the present application also provides a computer-readable medium, which may be included in the electronic device described in the above embodiments, or may exist independently without being incorporated into the electronic device. The computer-readable medium carries one or more programs, and when the one or more programs are executed by the electronic device, the electronic device implements the defect assessment method described in the above embodiments.

[0135] For example, electronic devices can implement Figure 1 As shown in: Step S102, obtaining simulation stimulus information of the chip circuit to be verified, the simulation stimulus information including the input stimulus, the output signal to be measured and the expected simulation result of the chip to be verified; Step S104, performing timing simulation on the output signal to be measured based on the input stimulus to obtain the timing simulation result of the chip to be verified; Step S106, sampling the timing simulation result based on multiple groups of sampling time sequences to obtain multiple groups of simulation sampling results of the output signal to be measured; Step S108, comparing the expected simulation result with the multiple groups of simulation sampling results respectively to generate multiple verification result record files; Step S110, optimizing and adjusting the chip circuit to be verified based on the multiple verification result record files.

[0136] In particular, according to an embodiment of the present disclosure, the process described above with reference to the flowchart can be implemented as a computer software program. For example, an embodiment of the present disclosure includes a computer program product, which includes a computer program carried on a computer-readable medium, and the computer program includes a program code for executing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from a network through a communication part, and / or installed from a removable medium. When the computer program is executed by a central processing unit (CPU), the above-mentioned functions defined in the system of the present application are executed.

[0137] It should be noted that the computer-readable medium described in the present disclosure may be a computer-readable signal medium or a computer-readable storage medium, or any combination thereof. A computer-readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or component, or any combination thereof. More specific examples of computer-readable storage media may include, but are not limited to, an electrical connection having one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof. In the present disclosure, a computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, device, or component. In the present disclosure, a computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, which carries computer-readable program code. This propagated data signal may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A computer-readable signal medium may also be any computer-readable medium other than a computer-readable storage medium that can transmit, propagate, or transport a program for use by or in conjunction with an instruction execution system, apparatus, or device. Program code embodied on a computer-readable medium may be transmitted using any suitable medium, including but not limited to wireless, wireline, optical fiber cable, RF, or any suitable combination thereof.

[0138] The flowcharts and block diagrams in the accompanying drawings illustrate the possible implementation architecture, functions and operations of the systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each box in the flowchart or block diagram can represent a module, program segment, or a part of code, and the above-mentioned module, program segment, or a part of code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in an order different from that marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram or flowchart, and the combination of boxes in the block diagram or flowchart, can be implemented with a dedicated hardware-based system that performs the specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0139] The units involved in the embodiments described in this disclosure may be implemented in software or hardware, and the units described may also be provided in a processor. In some cases, the names of these units do not constitute limitations on the units themselves.

[0140] It should be noted that although several modules or units of the device for action execution are mentioned in the detailed description above, this division is not mandatory. In fact, according to the embodiments of the present disclosure, the features and functions of two or more modules or units described above can be concretized in one module or unit. Conversely, the features and functions of one module or unit described above can be further divided into multiple modules or units to be concretized.

[0141] Furthermore, although the steps of the method of the present disclosure are described in a particular order in the accompanying drawings, this does not require or imply that the steps must be performed in this particular order, or that all steps shown must be performed to achieve the desired results. Additionally or alternatively, some steps may be omitted, multiple steps may be combined into one step, and / or one step may be decomposed into multiple steps.

[0142] Through the description of the above embodiments, it is easy for those skilled in the art to understand that the example embodiments described herein can be implemented by software or by combining software with necessary hardware. Therefore, the technical solution according to the embodiments of the present disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (which can be a CD-ROM, a USB flash drive, a mobile hard disk, etc.) or on a network, and includes several instructions to enable a computing device (which can be a personal computer, a server, a mobile terminal, or a network device, etc.) to execute the method according to the embodiments of the present disclosure.

[0143] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the appended claims.

Claims

1. A circuit simulation verification method, characterized in that: include: Acquire simulation stimulus information of the chip circuit to be verified, wherein the simulation stimulus information includes input stimulus of the chip to be verified, output signal to be measured, and expected simulation result; Performing a timing simulation on the chip circuit to be verified based on the input stimulus to obtain a timing simulation result of the chip to be verified; Sampling the timing simulation results based on multiple sets of sampling time sequences to obtain multiple sets of simulation sampling results of the output signal to be measured, wherein each set of the sampling time sequences includes multiple sampling time sequences; Comparing the simulation expected result with the multiple groups of simulation sampling results respectively to generate multiple verification result record files; The circuit of the chip to be verified is optimized and adjusted based on the multiple verification result record files.

2. The circuit simulation verification method according to claim 1, wherein: The simulation stimulus information also includes a reference clock signal, Before sampling the timing simulation results based on multiple groups of sampling time sequences, the method further includes: Determining the plurality of sampling time sequences based on the reference clock signal, wherein the plurality of sampling time sequences have the same sampling period, and the sampling period is related to a period of the reference clock signal; The sampling of the timing simulation results based on multiple groups of sampling time sequences includes: Sampling the timing simulation result based on a sampling moment in each group of the sampling moment sequences in each sampling window of the reference clock signal; The sampling intervals between the multiple sampling moments are equal, and the duration of the sampling window is equal to the duration of the sampling period.

3. The circuit simulation verification method according to claim 2, wherein: The comparing the simulation expected result with the multiple groups of simulation sampling results to generate multiple verification result record files includes: Obtaining simulation parameters of the chip to be verified; Determine a high-level and low-level boundary value of the timing simulation result based on the simulation parameters; Determining a plurality of groups of simulation sampling value sequences corresponding to the plurality of groups of simulation sampling results based on the high and low level dividing values, and obtaining a simulation expected value sequence corresponding to the simulation expected result; Comparing the simulation expected value sequence with the multiple groups of simulation sample value sequences respectively to generate the multiple verification result record files; Wherein, in the verification result record file, the comparison result between the simulation expected result and the multiple groups of simulation sampling results is set correspondingly to the simulation parameters.

4. The circuit simulation verification method according to claim 3, wherein: The multiple groups of sampling time sequences include a first sampling time sequence, a second sampling time sequence, and a third sampling time sequence, wherein the sampling time in the first sampling time sequence is recorded as a first sampling time, and the first sampling time is aligned with the center of the sampling window; the sampling time in the second sampling time sequence is recorded as a second sampling time, and the second sampling time is offset to the left relative to the center of the sampling window; the sampling time in the third sampling time sequence is recorded as a third sampling time, and the third sampling time is offset to the right relative to the center of the sampling window; The relative left or right offset is determined based on adjustment results of multiple rounds of tests, or is determined based on the simulation parameters.

5. The circuit simulation verification method according to claim 4, wherein: The step of comparing the simulation expected value sequence with the multiple groups of simulation sample value sequences to generate the multiple verification result record files includes: Comparing the first simulation expected value and the corresponding first simulation sampling value at each of the first sampling moments, the second simulation expected value and the corresponding second simulation sampling value at each of the second sampling moments, and the third simulation expected value and the corresponding third simulation sampling value at each of the third sampling moments, respectively, to obtain the multiple verification result record files; If the comparison results are consistent, verification success is recorded in the corresponding verification result record file; if the comparison results are inconsistent, verification failure is recorded in the corresponding verification result record file.

6. The circuit simulation verification method according to claim 5, characterized in that: The optimizing and adjusting the circuit of the chip to be verified based on the multiple verification result record files includes: Determine a target verification result record file from the multiple verification result record files, the target verification result record file being the verification result record file having the least verification failure record; The circuit is optimized and adjusted based on the target verification result record file.

7. The circuit simulation verification method according to any one of claims 3 to 6, characterized in that: Also includes: The simulation parameters include process angle data, PVT parameters, operating frequency and operating mode; Determining the sampling interval based on a sampling period and the number of groups of the sampling time sequence, or determining the sampling interval based on the number of groups of the sampling time sequence and an error range in a standard specification file, or determining the sampling interval based on at least one of the process angle data, the PVT parameter, and the operating frequency; as well as An output pin of the output signal to be tested is determined based on the operating mode.

8. A circuit simulation verification device, characterized in that: include: An acquisition module is used to obtain simulation stimulus information of the chip circuit to be verified, wherein the simulation stimulus information includes the input stimulus of the chip to be verified, the output signal to be measured, and the expected simulation result; A simulation module, configured to perform a timing simulation on the circuit of the chip to be verified based on the input stimulus to obtain a timing simulation result of the chip to be verified; A sampling module, configured to sample the timing simulation results based on multiple sets of sampling time sequences to obtain multiple sets of simulation sampling results of the output signal to be measured, wherein each set of the sampling time sequences includes multiple sampling time sequences; A comparison module, configured to compare the simulation expected result with the plurality of sets of simulation sampling results respectively, and generate a plurality of verification result record files; An optimization module is used to optimize and adjust the chip circuit to be verified based on the multiple verification result record files.

9. An electronic device, characterized in that: include: processor; as well as a memory for storing executable instructions of the processor; The processor is configured to execute the circuit simulation verification method according to any one of claims 1 to 7 by executing the executable instructions.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the circuit simulation verification method according to any one of claims 1 to 7 is implemented.

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