Display device

Abstract

A display device according to an exemplary embodiment of the present disclosure can include a stretchable lower substrate, a pattern layer disposed on the lower substrate and including a plurality of plate patterns and a plurality of line patterns, a plurality of pixels disposed on each of the plurality of plate patterns, and a plurality of connection lines disposed on each of the plurality of line patterns to connect the plurality of pixels, wherein each pixel circuit formed in the plurality of pixels includes at least one light emitting element, a driving transistor, a storage capacitor, and a first to fifth transistors, and a constant power voltage can be applied to the storage capacitor.

Description

Technical Field

[0001] This disclosure relates to display devices, and more specifically, to stretchable display devices. Background Technology

[0002] Display devices used in computer monitors, TVs, mobile phones, etc. include organic light-emitting displays (OLEDs) that emit their own light and liquid crystal displays (LCDs) that require a separate light source.

[0003] Such display devices are being used in an increasing number of fields, including not only computer monitors and TVs, but also personal mobile devices. Therefore, there is research on display devices that have a wide display area while having a reduced size and weight.

[0004] Recently, display devices that can be stretched in a specific direction and changed into various shapes by forming display units, lines, etc. on a flexible substrate such as plastic, a flexible material, have attracted considerable attention as the next generation of display devices. Summary of the Invention

[0005] One aspect of this disclosure is to provide a display device that minimizes the number of connecting lines.

[0006] Another aspect of this disclosure is to provide a display device including redundant LEDs.

[0007] Another aspect of the present invention is to provide a display device that allows for a design with a small-sized storage capacitor.

[0008] The purpose of this disclosure is not limited to the above-mentioned purposes, and other purposes not mentioned above will be clearly understood by those skilled in the art from the following description.

[0009] A display device according to an exemplary embodiment of the present disclosure may include: a stretchable lower substrate; a pattern layer disposed on the lower substrate and including a plurality of plate patterns and a plurality of line patterns; a plurality of pixels disposed on each of the plurality of plate patterns; and a plurality of connecting lines disposed on each of the plurality of line patterns to connect the plurality of pixels, wherein each pixel circuit in the pixel circuits formed in the plurality of pixels includes at least one light-emitting element, a driving transistor, a storage capacitor, and a first transistor to a fifth transistor, and a constant power supply voltage can be applied to the storage capacitor.

[0010] A display device according to another exemplary embodiment of the present disclosure may include a plurality of pixels spaced apart from each other and a plurality of connecting lines connecting the plurality of pixels and capable of being stretched. Each pixel circuit formed in the plurality of pixels may include at least one light-emitting element, a driving transistor, a storage capacitor, and a first transistor to a fifth transistor, and one of a scan signal and a light-emitting signal may be applied to the gate electrode of each of the first transistors to the fifth transistor.

[0011] Other aspects of the exemplary embodiments are included in the detailed description and accompanying drawings.

[0012] According to this disclosure, the yield of a display device can be improved by including redundant LEDs.

[0013] According to this disclosure, the pixel circuit can be driven normally even when the size of the storage capacitor Cst is designed to be small.

[0014] According to this disclosure, the stretching rate and stretching reliability can be improved by reducing the number of stretching lines.

[0015] The effects of this disclosure are not limited to the examples above, and many more effects are included in this specification. Attached Figure Description

[0016] Figure 1 This is a plan view of a display device according to an exemplary embodiment of the present disclosure.

[0017] Figure 2 This is an enlarged plan view of the display area of ​​a display device according to an exemplary embodiment of the present disclosure.

[0018] Figure 3 It is along Figure 2 The cross-sectional view taken by cutting line III-III' is shown.

[0019] Figure 4 It is along Figure 2 The cross-sectional view taken by the cutting line IV-IV' is shown.

[0020] Figure 5 It is along Figure 2 The cross-sectional view shown is taken by the cutting line V-V'.

[0021] Figure 6A and Figure 6B This is a circuit diagram of a sub-pixel of a display device according to an exemplary embodiment of the present disclosure.

[0022] Figure 7 This is a waveform diagram illustrating the light emission signal and scanning signal of a display device according to an exemplary embodiment of the present disclosure.

[0023] Figure 8A This is a circuit diagram of the pixels of a display device according to an exemplary embodiment of the present disclosure during the initial time period.

[0024] Figure 8B This is a circuit diagram of the pixels of a display device according to an exemplary embodiment of the present disclosure during the sampling period.

[0025] Figure 8C This is a circuit diagram of the pixels of a display device according to an exemplary embodiment of the present disclosure during the light-emitting period.

[0026] Figure 9A and Figure 9B This is a circuit diagram of a sub-pixel of a display device according to another exemplary embodiment of the present disclosure.

[0027] Figure 10 This is a waveform diagram illustrating the light emission signal and scanning signal of a display device according to another exemplary embodiment of the present disclosure.

[0028] Figure 11A This is a circuit diagram of the pixels of a display device according to another exemplary embodiment of the present disclosure during the initial time period.

[0029] Figure 11B This is a circuit diagram of the pixels of a display device according to another exemplary embodiment of the present disclosure during the sampling period.

[0030] Figure 11C This is a circuit diagram of the pixels of a display device according to another exemplary embodiment of the present disclosure during the light-emitting period.

[0031] Figure 12 This is a diagram used to explain the arrangement of the connection lines of a display device according to an exemplary embodiment of the present disclosure.

[0032] Figure 13 This is a diagram used to explain the arrangement of the connection lines of a display device according to another exemplary embodiment of the present disclosure.

[0033] Figure 14A and Figure 14B This is a circuit diagram of a sub-pixel of a display device according to yet another exemplary embodiment of the present disclosure.

[0034] Figure 15 This is a waveform diagram illustrating the light emission signal and scanning signal of a display device according to yet another exemplary embodiment of the present disclosure.

[0035] Figure 16A This is a circuit diagram of the pixels of a display device according to yet another exemplary embodiment of the present disclosure during the initial time period.

[0036] Figure 16BThis is a circuit diagram of the pixels of a display device according to yet another exemplary embodiment of the present disclosure during the sampling period.

[0037] Figure 16C This is a circuit diagram of the pixels of a display device according to another exemplary embodiment of the present disclosure during the light-emitting period. Detailed Implementation

[0038] The advantages and features of this disclosure, as well as methods for achieving these advantages and features, will become clear from the following detailed description of exemplary embodiments and accompanying drawings. However, this disclosure is not limited to the exemplary embodiments disclosed herein, but will be implemented in various forms. Exemplary embodiments are provided by way of example only so that those skilled in the art can fully understand the disclosure and scope of this disclosure. Therefore, this disclosure will be limited only by the scope of the appended claims.

[0039] The shapes, dimensions, ratios, angles, quantities, etc., illustrated in the accompanying drawings to describe exemplary embodiments of this disclosure are merely examples, and this disclosure is not limited thereto. The same reference numerals generally denote the same elements throughout the specification. Furthermore, in the following description of this disclosure, detailed descriptions of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter. Terms such as “comprising,” “having,” and “consisting of” as used herein are generally intended to allow for the addition of other components, unless these terms are used in conjunction with the term “only.” Unless expressly stated otherwise, any singular reference may include the plural.

[0040] Even if not explicitly stated, components are interpreted as including a normal error range.

[0041] When using terms such as “above,” “over,” “below,” and “near” to describe the positional relationship and usage between two components, one or more components may be positioned between the two components unless these terms are used in conjunction with terms used for “immediately following” or “directly.”

[0042] When an element or layer is placed "on" another element or layer, another layer or element can be placed directly on the other element or layer or inserted between them.

[0043] Although terms such as "first" and "second" are used to describe various components, these components are not bound by these terms. These terms are only used to distinguish one component from others. Therefore, the first component mentioned below can be the second component in the technical concept of this disclosure.

[0044] Similar reference numerals generally denote similar elements throughout the specification.

[0045] For ease of description, the dimensions and thickness of each component shown in the accompanying drawings are illustrated, and this disclosure is not limited to the dimensions and thickness of the illustrated components.

[0046] Features of the various embodiments of this disclosure may be attached or combined with each other in part or in whole, and may be interlocked and operated in various technical ways, and these embodiments may be performed independently or in conjunction with each other.

[0047] The display device according to the exemplary embodiments of this disclosure is a display device capable of displaying images even when it is bent or stretched, and may also be referred to as a stretchable display device or a flexible display device. The display device can have greater flexibility and stretchability than conventional typical display devices. Therefore, a user can bend or stretch the display device, and the shape of the display device can be freely changed according to the user's manipulation. For example, when a user grasps and pulls the end of the display device, the display device can be stretched in the direction of the user's pull. If the user places the display device on an uneven outer surface, the display device can be configured to bend according to the shape of the outer surface. When the force applied by the user is removed, the display device can return to its original shape.

[0048] <Stretchable substrate and patterned layer>

[0049] Figure 1 This is a plan view of a display device according to an exemplary embodiment of the present disclosure.

[0050] Figure 2 This is an enlarged plan view of the display area of ​​a display device according to an exemplary embodiment of the present disclosure.

[0051] Figure 3 It is along Figure 2 The cross-sectional view taken by cutting line III-III' is shown.

[0052] Specifically, Figure 2 yes Figure 1 An enlarged plan view of region A shown.

[0053] Reference Figure 1 The display device 100 according to an exemplary embodiment of the present disclosure may include a lower substrate 111, a pattern layer 120, a plurality of pixels PX, a gating driver GD, a data driver DD, and a power supply PS. Furthermore, referring to... Figure 1 The display device 100 according to an exemplary embodiment of the present disclosure may further include a filler layer 190 and an upper substrate 112.

[0054] The lower substrate 111 is a substrate used to support and protect various components of the display device 100. The upper substrate 112 is a substrate used to cover and protect the various components of the display device 100. Specifically, the lower substrate 111 is a substrate that supports the pattern layer 120 on which pixels PX, gating drivers GD, and power supplies PS are formed. The upper substrate 112 is a substrate that covers the pixels PX, gating drivers GD, and power supplies PS.

[0055] Each of the lower substrate 111 and the upper substrate 112 is a ductile substrate and may be formed of an insulating material capable of bending or stretching. For example, each of the lower substrate 111 and the upper substrate 112 may be formed of silicone rubber such as polydimethylsiloxane (PDMS) or elastomers such as polyurethane (PU) and polytetrafluoroethylene (PTFE), and thus have flexible properties. Furthermore, the materials of the lower substrate 111 and the upper substrate 112 may be the same, but are not limited to this, and various modifications may be made.

[0056] Each of the lower substrate 111 and the upper substrate 112 is a ductile substrate and can reversibly expand and contract. Therefore, the lower substrate 111 can be referred to as a lower stretchable substrate, a lower flexible substrate, a lower extendable substrate, a lower ductile substrate, a first stretchable substrate, a first flexible substrate, a first extendable substrate, or a first ductile substrate, and the upper substrate 112 can be referred to as an upper stretchable substrate, an upper flexible substrate, an upper extendable substrate, an upper ductile substrate, a second stretchable substrate, a second flexible substrate, a second extendable substrate, or a second ductile substrate. Furthermore, the elastic modulus of the lower substrate 111 and the upper substrate 112 can be from a few MPa to several hundred MPa. Furthermore, the ductile breaking rate of the lower substrate 111 and the upper substrate 112 can be 100% or higher. Here, the ductile breaking rate is the elongation at which the object to be stretched breaks or fractures. The thickness of the lower substrate can be from 10 μm to 1 mm, but is not limited to this.

[0057] The lower substrate 111 may have a display area AA and a non-display area NA surrounding the display area AA. However, the display area AA and the non-display area NA are not limited to the lower substrate 111 and can be referenced throughout the display device.

[0058] The display area AA is the area on the display device 100 where an image is displayed. A plurality of pixels PX are disposed within the display area AA. Furthermore, each pixel in the pixel PX may include a display element and various driving elements for driving the display element. These various driving elements may refer to at least one thin-film transistor (TFT) and a capacitor, but are not limited thereto. Additionally, each pixel in the plurality of pixels PX may be connected to various lines. For example, each pixel in the plurality of pixels PX may be connected to various lines such as gating lines, data lines, high-potential voltage lines, low-potential voltage lines, reference voltage lines, and initialization voltage lines.

[0059] The non-display area NA is the area where no image is displayed. The non-display area NA can be located adjacent to the display area AA. For example, the non-display area NA can be the area surrounding the display area AA. However, this disclosure is not limited to this, and the non-display area NA corresponds to the area of ​​the lower substrate 111 other than the display area AA, and can be changed and separated into various shapes. Components for driving the plurality of pixels PX disposed in the display area AA are disposed in the non-display area NA. A gating driver GD and a power supply PS can be disposed in the non-display area NA. Additionally, a plurality of pads connected to the gating driver GD and the data driver DD can be disposed in the non-display area NA, and each pad can be connected to a corresponding pixel among the plurality of pixels PX in the display area AA.

[0060] A pattern layer 120 is provided on the lower substrate 111. The pattern layer 120 includes a plurality of first plate patterns 121 and a plurality of first line patterns 122 provided in the display area AA, and a plurality of second plate patterns 123 and a plurality of second line patterns 124 provided in the non-display area NA.

[0061] Multiple first board patterns 121 can be disposed in the display area AA of the lower substrate 111. Multiple pixels PX can be formed on the multiple first board patterns 121. In addition, multiple second board patterns 123 can be disposed in the non-display area NA of the lower substrate 111. Furthermore, a gating driver GD and a power supply PS can be formed on the multiple second board patterns 123.

[0062] The plurality of first plate patterns 121 and the plurality of second plate patterns 123 described above can be arranged in the form of islands spaced apart from each other. Each of the plurality of first plate patterns 121 and the plurality of second plate patterns 123 can be separated individually. Therefore, the plurality of first plate patterns 121 and the plurality of second plate patterns 123 can be referred to as a first island pattern and a second island pattern, or a first individual pattern and a second individual pattern.

[0063] Specifically, the gate driver GD can be mounted on multiple second board patterns 123. When manufacturing various components on the first board pattern 121, the gate driver GD can be formed on the second board patterns 123 using a gate-in-panel (GIP) method. Therefore, various circuit components constituting the gate driver GD (such as various transistors, capacitors, and lines) can be disposed on the multiple second board patterns 123. However, this disclosure is not limited thereto; the gate driver GD can also be mounted using a chip-on-film (COF) method.

[0064] Furthermore, the power supply PS can be mounted on multiple second board patterns 123. Utilizing multiple power blocks patterned during the fabrication of various components on the first board pattern 121, the power supply PS can be formed on the second board pattern 123. Therefore, power blocks disposed on different layers can be disposed on the second board pattern 123. That is, lower power blocks and upper power blocks can be sequentially disposed on the second board pattern 123. Additionally, a low-potential voltage can be applied to the lower power block, and a high-potential voltage can be applied to the upper power block. Therefore, a low-potential voltage can be provided to multiple pixels PX through the lower power block. Conversely, a high-potential voltage can be provided to multiple pixels PX through the upper power block. However, the implementation is not limited to this. For example, a low-potential voltage can be applied to the upper power block, and a high-potential voltage can be applied to the lower power block.

[0065] Reference Figure 1 The size of the plurality of second board patterns 123 can be larger than the size of the plurality of first board patterns 121. Specifically, the size of each second board pattern in the plurality of second board patterns 123 can be larger than the size of each first board pattern in the plurality of first board patterns 121. As described above, a gating driver GD can be disposed on each of the plurality of second board patterns 123, and a first stage of the gating driver GD can be disposed on each of the plurality of second board patterns 123. Therefore, since the area occupied by the various circuit components constituting the first stage of the gating driver GD is relatively larger than the area occupied by the pixel PX, the size of each second board pattern in the plurality of second board patterns 123 can be larger than the size of each first board pattern in the first board pattern 121. However, the implementation is not limited to this. For example, the size of the plurality of second board patterns 123 can be equal to or even smaller than the size of the plurality of first board patterns 121.

[0066] exist Figure 1In this illustration, a plurality of second plate patterns 123 are exemplified as being disposed on both sides along a first direction X in a non-display area NA; however, this disclosure is not limited thereto, and the plurality of second plate patterns 123 may be disposed in any area of ​​the non-display area NA. Furthermore, although the plurality of first plate patterns 121 and the plurality of second plate patterns 123 are shown in a quadrilateral shape, this disclosure is not limited thereto, and the plurality of first plate patterns 121 and the plurality of second plate patterns 123 may be varied in various forms. For example, the plurality of first plate patterns 121 and the plurality of second plate patterns 123 may have the same or different shapes.

[0067] Reference Figure 1 and Figure 3 The pattern layer 120 may also include a plurality of first line patterns 122 disposed in the display area AA and a plurality of second line patterns 124 disposed in the non-display area NA.

[0068] The plurality of first line patterns 122 are patterns disposed in the display area AA and connecting adjacent first plate patterns 121, and may be referred to as first connecting patterns. That is, the plurality of first line patterns 122 are disposed between the plurality of first plate patterns 121.

[0069] The plurality of second line patterns 124 may be patterns disposed in the non-display area NA and connecting adjacent first board patterns 121 and second board patterns 123, or a plurality of adjacent second board patterns 123. Therefore, the plurality of second line patterns 124 may be referred to as second connecting patterns. That is, the plurality of second line patterns 124 may be disposed between adjacent first board patterns 121 and second board patterns 123. Additionally, the plurality of second line patterns 124 may be disposed between adjacent plurality of second board patterns 123. (See reference...) Figure 1 The plurality of first line patterns 122 and the plurality of second line patterns 124 have a wavy shape. For example, the plurality of first line patterns 122 and the plurality of second line patterns 124 may have a sine wave shape. However, the shape of the plurality of first line patterns 122 and the plurality of second line patterns 124 is not limited thereto. For example, the plurality of first line patterns 122 and the plurality of second line patterns 124 may extend in a zigzag manner. Alternatively, the plurality of first line patterns 122 and the plurality of second line patterns 124 may have various shapes, such as a shape in which a plurality of rhomboid-shaped substrates extend by connecting at their vertices. Figure 1 The number and shape of the plurality of first line patterns 122 and second line patterns 124 shown are exemplary, and the number and shape of the plurality of first line patterns 122 and second line patterns 124 can be varied according to the design.

[0070] Furthermore, the plurality of first plate patterns 121, the plurality of first line patterns 122, the plurality of second plate patterns 123, and the plurality of second line patterns 124 are rigid patterns. That is, the plurality of first plate patterns 121, the plurality of first line patterns 122, the plurality of second plate patterns 123, and the plurality of second line patterns 124 can be rigid compared to the lower substrate 111 and the upper substrate 112. Therefore, the elastic modulus of the plurality of first plate patterns 121, the plurality of first line patterns 122, the plurality of second plate patterns 123, and the plurality of second line patterns 124 can be higher than the elastic modulus of the lower substrate 111. The elastic modulus is a parameter that represents the rate of deformation relative to the stress applied to the substrate. When the elastic modulus is relatively high, the hardness can be relatively high. Therefore, the plurality of first plate patterns 121, the plurality of first line patterns 122, the plurality of second plate patterns 123, and the plurality of second line patterns 124 can be referred to as a plurality of first rigid patterns, a plurality of second rigid patterns, a plurality of third rigid patterns, and a plurality of fourth rigid patterns, respectively. The elastic modulus of the plurality of first plate patterns 121, the plurality of first line patterns 122, the plurality of second plate patterns 123 and the plurality of second line patterns 124 may be 1,000 times higher than the elastic modulus of the lower substrate 111 and the upper substrate 112, but this disclosure is not limited thereto.

[0071] The plurality of first plate patterns 121, first line patterns 122, second plate patterns 123, and second line patterns 124, which are multiple rigid substrates, can be formed of a material (e.g., a plastic material) with lower flexibility than the lower substrate 111 and the upper substrate 112. For example, the plurality of first plate patterns 121, first line patterns 122, second plate patterns 123, and second line patterns 124 can be formed of at least one material selected from polyimide (PI), polyacrylate, and polyacetate. In this case, the plurality of first plate patterns 121, first line patterns 122, second plate patterns 123, and second line patterns 124 can be formed of the same material, but they are not limited to this and can be formed of different materials. When the plurality of first plate patterns 121, first line patterns 122, second plate patterns 123, and second line patterns 124 are formed of the same material, they can be integrally formed.

[0072] In some embodiments, the lower substrate 111 may be defined to include a plurality of first lower patterns and a plurality of second lower patterns. The plurality of first lower patterns may be regions of the lower substrate 111 that overlap with the plurality of first plate patterns 121 and the plurality of second plate patterns 123. The second lower patterns may be regions that do not overlap with the plurality of first plate patterns 121 and the plurality of second plate patterns 123.

[0073] Furthermore, the upper substrate 112 may be defined to include a plurality of first upper patterns and a plurality of second upper patterns. The plurality of first upper patterns may be regions of the upper substrate 112 that overlap with the plurality of first plate patterns 121 and the plurality of second plate patterns 123. The second upper pattern may be a region that does not overlap with the plurality of first plate patterns 121 and the plurality of second plate patterns 123.

[0074] In this case, the elastic modulus of the plurality of first lower patterns and first upper patterns can be greater than that of the second lower patterns and second upper patterns. For example, the plurality of first lower patterns and first upper patterns can be formed of the same material as the plurality of first plate patterns 121 and the plurality of second plate patterns 123, and the second lower patterns and second upper patterns can be formed of a material with an elastic modulus lower than that of the plurality of first plate patterns 121 and the plurality of second plate patterns 123.

[0075] In other words, the first lower pattern and the first upper pattern can be formed from polyimide (PI), polyacrylate, polyacetate, etc., and the second lower pattern and the second upper pattern can be formed from silicone rubber such as polydimethylsiloxane (PDMS) or elastomers such as polyurethane (PU) or polytetrafluoroethylene (PTFE).

[0076] <Non-display area driving element>

[0077] A gating driver GD is a component that provides gating voltages to multiple pixels PX disposed in a display area AA. The gating driver GD includes multiple stages formed on multiple second board patterns 123, and the stages of the gating driver GD can be electrically connected to each other via multiple gating connection lines. Therefore, a gating voltage output from one stage can be transferred to another stage. Furthermore, each stage can sequentially provide gating voltages to the multiple pixels PX connected to that stage.

[0078] A power supply PS can be connected to a gating driver GD and provide a gating drive voltage and a gating clock voltage. Furthermore, the power supply PS can be connected to multiple pixels PX and provide a pixel drive voltage to each of the multiple pixels PX. The power supply PS can also be formed on multiple second board patterns 123. That is, the power supply PS can be formed on multiple second board patterns 123 adjacent to the gating driver GD. Furthermore, each power supply PS formed on the multiple second board patterns 123 can be electrically connected to the gating driver GD and the multiple pixels PX. That is, the multiple power supplies PS formed on the multiple second board patterns 123 can be connected via gating power connection lines and pixel power connection lines. Therefore, each power supply PS can provide a gating drive voltage, a gating clock voltage, and a pixel drive voltage.

[0079] A printed circuit board (PCB) is an assembly that transmits signals and voltages used to drive display elements from a control unit to the display elements. Therefore, a PCB can also be called a drive substrate. Control units such as IC chips or circuits can be mounted on the PCB. Furthermore, memory, processors, and the like can be mounted on the PCB. Additionally, the PCB provided in the display device 100 can include stretchable and non-stretchable areas to ensure stretchability. Moreover, IC chips, circuits, memory, processors, etc., can be mounted on the non-stretchable areas, and lines electrically connected to the IC chips, circuits, memory, and processor can be provided in the stretchable areas.

[0080] A data driver (DD) is a component that provides data voltage to multiple pixels (PX) located in the display area (AA). The data driver (DD) can be configured as an IC chip, and therefore can also be called a data integrated circuit (D-IC). Furthermore, the data driver (DD) can be mounted on a non-stretchable area of ​​a printed circuit board (PCB). That is, the data driver (DD) can be mounted on the PCB as a chip-on-board (COB). Although in Figure 1 The illustration shows a data driver DD mounted on a chip-on-board (COB) basis, but this disclosure is not limited thereto, and the data driver DD can also be mounted on a chip-on-film (COF), chip-on-glass (COG), tape-on-carrier (TCP) basis, etc.

[0081] Furthermore, despite Figure 1 The illustration shows a data driver DD configured to correspond to a row of first panel patterns 121 in the display area AA, but the present disclosure is not limited thereto. That is, a data driver DD can be configured to correspond to multiple rows of first panel patterns 121.

[0082] See below for reference. Figure 4 and Figure 5 The display area AA of the display device 100 according to an exemplary embodiment of the present disclosure will be described in more detail.

[0083] <Planar and cross-sectional structure of the display area>

[0084] Figure 4 It is along Figure 2 The cross-sectional view taken by the cutting line IV-IV' is shown.

[0085] Figure 5 It is along Figure 2 The cross-sectional view shown is taken by the cutting line V-V'.

[0086] For ease of description, please refer to the following: Figures 1 to 3 .

[0087] Reference Figure 1 and Figure 2 Multiple first plate patterns 121 are disposed on a lower substrate 111 in a display area AA. The multiple first plate patterns 121 are arranged to be spaced apart from each other on the lower substrate 111. For example, as... Figure 1 As shown, multiple first plate patterns 121 can be arranged in a matrix on the lower substrate 111, but are not limited thereto.

[0088] Reference Figure 2 and Figure 3 The subpixels, including multiple subpixels SPX, are disposed on the first plate pattern 121. Furthermore, each subpixel in the SPX may include an LED 170 as a display element and a driving transistor 160 and a switching transistor 150 for driving the LED 170. However, the display element in the SPX is not limited to LEDs and may be an organic light-emitting diode. Additionally, the multiple subpixels SPX may include red subpixels, green subpixels, and blue subpixels, but are not limited to these. The colors of the multiple subpixels SPX can be varied as needed.

[0089] Multiple sub-pixels SPX can be connected to multiple connection lines 181 and 182. That is, multiple sub-pixels SPX can be electrically connected to a first connection line 181 extending along a first direction X. In addition, multiple sub-pixels SPX can be electrically connected to a second connection line 182 extending along a second direction Y.

[0090] In the following text, reference will be made to Figure 3 Describe the cross-sectional structure of display area AA in detail.

[0091] Reference Figure 3 Multiple inorganic insulating layers are disposed on multiple first board patterns 121. For example, the multiple inorganic insulating layers may include a buffer layer 141, a gate insulating layer 142, a first interlayer insulating layer 143, a second interlayer insulating layer 144, and a passivation layer 145. However, this disclosure is not limited thereto. Various inorganic insulating layers may be further disposed on the multiple first board patterns 121. One or more of the buffer layer 141, gate insulating layer 142, first interlayer insulating layer 143, second interlayer insulating layer 144, and passivation layer 145, which are inorganic insulating layers, may be omitted.

[0092] Specifically, a buffer layer 141 is disposed on a plurality of first plate patterns 121. The buffer layer 141 is formed on the plurality of first plate patterns 121 to protect various components of the display device 100 from moisture (H2O), oxygen (O2), etc., penetrating from the lower substrate 111 and the plurality of first plate patterns 121. The buffer layer 141 may be formed of an insulating material. For example, the buffer layer 141 may be formed as a single layer or multiple layers of silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), etc. However, depending on the structure or characteristics of the display device 100, the buffer layer 141 may be omitted.

[0093] In this case, the buffer layer 141 may be formed only in the region where the buffer layer 141 overlaps with the plurality of first plate patterns 121 and the plurality of second plate patterns 123. As described above, the buffer layer 141 may be formed of an inorganic material. Therefore, the buffer layer 141 may be easily damaged, for example, easily broken, when the display device 100 is stretched. Therefore, the buffer layer 141 may not be formed in the region between the plurality of first plate patterns 121 and the plurality of second plate patterns 123. The buffer layer 141 may be patterned into the shape of the plurality of first plate patterns 121 and the plurality of second plate patterns 123, and formed only on the upper part of the plurality of first plate patterns 121 and the plurality of second plate patterns 123. Therefore, in the display device 100 according to the exemplary embodiment of the present disclosure, the buffer layer 141 is formed only in the region where the buffer layer 141 overlaps with the plurality of first plate patterns 121 and the plurality of second plate patterns 123, which are rigid substrates, thereby preventing damage to various components of the display device 100 even when the display device 100 is deformed (e.g., bent or stretched).

[0094] Reference Figure 3 A switching transistor 150, including a gate electrode 151, an active layer 152, a source electrode 153, and a drain electrode 154, and a driving transistor 160, including a gate electrode 161, an active layer 162, a source electrode, and a drain electrode 164, are formed on a buffer layer 141.

[0095] First, refer to Figure 3 The active layer 152 of the switching transistor 150 and the active layer 162 of the driving transistor 160 are disposed on the buffer layer 141. For example, each of the active layer 152 of the switching transistor 150 and the active layer 162 of the driving transistor 160 may be formed of an oxide semiconductor. Alternatively, the active layer 152 of the switching transistor 150 and the active layer 162 of the driving transistor 160 may be formed of amorphous silicon (a-Si), polycrystalline silicon (poly-Si), organic semiconductors, etc.

[0096] A gate insulating layer 142 is disposed on the active layer 152 of the switching transistor 150 and the active layer 162 of the driving transistor 160. The gate insulating layer 142 is configured to electrically insulate the gate electrode 151 of the switching transistor 150 from the active layer 152 of the switching transistor 150 and to electrically insulate the gate electrode 161 of the driving transistor 160 from the active layer 162 of the driving transistor 160. Furthermore, the gate insulating layer 142 may be formed of an insulating material. For example, the gate insulating layer 142 may be formed as a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or a multilayer of silicon nitride (SiNx) or silicon oxide (SiOx), but is not limited thereto.

[0097] The gate electrode 151 of the switching transistor 150 and the gate electrode 161 of the driving transistor 160 are disposed on the gate insulating layer 142. The gate electrode 151 of the switching transistor 150 and the gate electrode 161 of the driving transistor 160 are disposed apart from each other on the gate insulating layer 142. Furthermore, the gate electrode 151 of the switching transistor 150 overlaps with the active layer 152 of the switching transistor 150, and the gate electrode 161 of the driving transistor 160 overlaps with the active layer 162 of the driving transistor 160.

[0098] Each of the gate electrode 151 of the switching transistor 150 and the gate electrode 161 of the driving transistor 160 may be formed of a variety of metallic materials, such as any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). Alternatively, each of the gate electrode 151 of the switching transistor 150 and the gate electrode 161 of the driving transistor 160 may be formed of an alloy of two or more of them, or by a multilayer thereof, but is not limited thereto.

[0099] A first interlayer insulating layer 143 is disposed on the gate electrode 151 of the switching transistor 150 and the gate electrode 161 of the driving transistor 160. The first interlayer insulating layer 143 insulates the gate electrode 161 of the driving transistor 160 from the intermediate metal layer IM. The first interlayer insulating layer 143 may also be formed of an inorganic material, like the buffer layer 141. For example, the first interlayer insulating layer 143 may be formed as a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or a multilayer of silicon nitride (SiNx) or silicon oxide (SiOx), but is not limited thereto.

[0100] An intermediate metal layer IM is disposed on the first interlayer insulating layer 143. Furthermore, the intermediate metal layer IM overlaps with the gate electrode 161 of the driving transistor 160. Therefore, a storage capacitor is formed in the region where the intermediate metal layer IM overlaps with the gate electrode 161 of the driving transistor 160. Specifically, the gate electrode 161 of the driving transistor 160, the first interlayer insulating layer 143, and the intermediate metal layer IM form a storage capacitor. However, the location of the intermediate metal layer IM is not limited to this. The intermediate metal layer IM can overlap with another electrode in various ways to form a storage capacitor.

[0101] The intermediate metal layer IM can be formed from one of various metallic materials, such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). Alternatively, the intermediate metal layer IM can be formed from an alloy of two or more of these, or from multiple layers of them, but is not limited thereto.

[0102] The second interlayer insulating layer 144 is disposed on the intermediate metal layer IM. The second interlayer insulating layer 144 insulates the gate electrode 151 of the switching transistor 150 from the source electrode 153 and drain electrode 154 of the switching transistor 150. Furthermore, the second interlayer insulating layer 144 insulates the intermediate metal layer IM from the source electrode and drain electrode 164 of the driving transistor 160. The second interlayer insulating layer 144 may also be formed of an inorganic material, like the buffer layer 141. For example, the first interlayer insulating layer 143 may be formed as a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or a multilayer of silicon nitride (SiNx) or silicon oxide (SiOx), but is not limited thereto.

[0103] The source electrode 153 and drain electrode 154 of the switching transistor 150 are disposed on the second interlayer insulating layer 144. Furthermore, the source electrode and drain electrode 164 of the driving transistor 160 are disposed on the second interlayer insulating layer 144. The source electrode 153 and drain electrode 154 of the switching transistor 150 are disposed on the same layer and spaced apart from each other. Furthermore, although... Figure 3 The source of the driving transistor 160 is not shown, but the source electrode of the driving transistor 160 is also configured to be spaced apart from the drain electrode 164 of the driving transistor 160 on the same layer. In the switching transistor 150, the source electrode 153 and the drain electrode 154 can be electrically connected to the active layer 152 to contact the active layer 152. Furthermore, in the driving transistor 160, the source electrode and the drain electrode 164 can be electrically connected to the active layer 162 to contact the active layer 162. Additionally, the drain electrode 154 of the switching transistor 150 can be electrically connected to the gate electrode 161 of the driving transistor 160 to contact the gate electrode 161 of the driving transistor 160 through a contact hole.

[0104] The source electrode 153 and drain electrodes 154 and 164 can be formed from a variety of metallic materials, such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). Alternatively, the source electrode 153 and drain electrodes 154 and 164 can be formed from an alloy of two or more of them, or from multiple layers of them, but are not limited thereto.

[0105] Furthermore, while the driving transistor 160 has been described in this disclosure as having a coplanar structure, various types of transistors with interleaved structures, etc., may also be used. Additionally, in this specification, the transistor may be formed not only as a top-gate structure but also as a bottom-gate structure.

[0106] The gating pad GP and data pad DP can be set on the second interlayer insulating layer 144.

[0107] Specifically, refer to Figure 4 The gating pad GP is used to transmit the gating voltage to multiple sub-pixels SPX. The gating pad GP is connected to the first connection line 181 via a contact hole. In addition, the gating voltage provided from the first connection line 181 can be transmitted from the gating pad GP to the gate electrode 151 of the switching transistor 150 via a line formed on the first board pattern 121.

[0108] Additionally, refer to Figure 3 The data pad DP is used to transmit data voltage to multiple sub-pixels SPX. The data pad DP is connected to the second connection line 182 via a contact hole. In addition, the data voltage provided from the second connection line 182 can be transmitted from the data pad DP to the source electrode 153 of the switching transistor 150 via a line formed on the first board pattern 121.

[0109] In addition, refer to Figure 3 The voltage pad VP is a pad used to transfer a low-potential voltage to multiple sub-pixels (SPX). The voltage pad VP is connected to the first connection line 181 via a contact hole. Additionally, the low-potential voltage provided from the first connection line 181 can be transferred from the voltage pad VP to the n-electrode 174 of the LED 170 via a line formed on the first board pattern 121.

[0110] The gating pad GP and data pad DP can be formed from the same material as the source electrode 153 and the drain electrodes 154 and 164, but are not limited thereto.

[0111] Reference Figure 3A passivation layer 145 is formed on the switching transistor 150 and the driving transistor 160. The passivation layer 145 covers the switching transistor 150 and the driving transistor 160 to protect them from the penetration of moisture, oxygen, etc. The passivation layer 145 can be formed from an inorganic material and can be formed as a single layer or multiple layers, but is not limited thereto.

[0112] Furthermore, the gate insulating layer 142, the first interlayer insulating layer 143, the second interlayer insulating layer 144, and the passivation layer 145 can be patterned and formed only in the regions where they overlap with the plurality of first plate patterns 121. The gate insulating layer 142, the first interlayer insulating layer 143, the second interlayer insulating layer 144, and the passivation layer 145 can also be formed from inorganic materials, like the buffer layer 141. Therefore, when the display device 100 is stretched, the gate insulating layer 142, the first interlayer insulating layer 143, the second interlayer insulating layer 144, and the passivation layer 145 may be easily damaged, for example, easily cracked. Therefore, the gate insulating layer 142, the first interlayer insulating layer 143, the second interlayer insulating layer 144, and the passivation layer 145 may not be formed in the regions between the plurality of first plate patterns 121, and can be patterned into the shape of the plurality of first plate patterns 121 and formed only on the upper part of the plurality of first plate patterns 121.

[0113] A planarization layer 146 is formed on the passivation layer 145. The planarization layer 146 is used to planarize the upper portions of the switching transistor 150 and the driving transistor 160. The planarization layer 146 can be formed as a single layer or multiple layers, and can be formed of an organic material. Therefore, the planarization layer 146 can also be referred to as an organic insulating layer. For example, the planarization layer 146 can be formed of an acrylic-based organic material, but is not limited thereto.

[0114] Reference Figure 3A planarization layer 146 may be disposed on a plurality of first board patterns 121 to cover the upper and side surfaces of the buffer layer 141, the gate insulating layer 142, the first interlayer insulating layer 143, the second interlayer insulating layer 144, and the passivation layer 145. Furthermore, the planarization layer 146, together with the plurality of first board patterns 121, surrounds the buffer layer 141, the gate insulating layer 142, the first interlayer insulating layer 143, the second interlayer insulating layer 144, and the passivation layer 145. Specifically, the planarization layer 146 may be configured to cover the upper and side surfaces of the passivation layer 145, the side surfaces of the first interlayer insulating layer 143, the second interlayer insulating layer 144, the side surfaces of the gate insulating layer 142, the side surfaces of the buffer layer 141, and a portion of the upper surfaces of the plurality of first board patterns 121. Therefore, the planarization layer 146 can compensate for the steps between the side surfaces of the buffer layer 141, the gate insulating layer 142, the first interlayer insulating layer 143, the second interlayer insulating layer 144, and the passivation layer 145. In addition, the planarization layer 146 can enhance the adhesion strength between the planarization layer 146 and the connection lines 181 and 182 disposed on the side surface of the planarization layer 146.

[0115] Reference Figure 3 The tilt angle of the side surface of the planarization layer 146 can be smaller than that of the side surfaces of the buffer layer 141, gate insulating layer 142, first interlayer insulating layer 143, second interlayer insulating layer 144, and passivation layer 145. For example, the side surface of the planarization layer 146 can have a gentler slope than the side surfaces of the passivation layer 145, the first interlayer insulating layer 143, the second interlayer insulating layer 144, the gate insulating layer 142, and the buffer layer 141. Therefore, the connecting lines 181 and 182 that contact the side surface of the planarization layer 146 are configured to have a gentler slope. Therefore, when the display device 100 is stretched, the stress generated in the connecting lines 181 and 182 can be reduced. In addition, cracks in the connecting lines 181 and 182 or peeling of the connecting lines 181 and 182 from the side surface of the planarization layer 146 can be suppressed.

[0116] Reference Figures 2 to 4 Connecting lines 181 and 182 refer to lines that electrically connect pads disposed on a plurality of first board patterns 121. Connecting lines 181 and 182 are disposed on a plurality of first board patterns 122. Additionally, connecting lines 181 and 182 may extend on the plurality of first board patterns 121 to electrically connect to gating pads GP and data pads DP on the plurality of first board patterns 121. Furthermore, refer to... Figure 5 The first line pattern 122 is not set in the area between multiple first plate patterns 121 where no connecting lines 181 and 182 are set.

[0117] Connecting lines 181 and 182 include a first connecting line 181 and a second connecting line 182. The first connecting line 181 and the second connecting line 182 are disposed between a plurality of first plate patterns 121. Specifically, the first connecting line 181 refers to the line of connecting lines 181 and 182 that extends along the X-axis direction between the plurality of first plate patterns 121. The second connecting line 182 refers to the line of connecting lines 181 and 182 that extends along the Y-axis direction between the plurality of first plate patterns 121.

[0118] The connecting lines 181 and 182 may be formed of metallic materials such as copper (Cu), aluminum (Al), titanium (Ti) or molybdenum (Mo), or the connecting lines 181 and 182 may have a laminated structure of metallic materials such as copper / molybdenum-titanium (Cu / MoTi) or titanium / aluminum / titanium (Ti / Al / Ti), but are not limited thereto.

[0119] In the display panel of a general-purpose display device, various lines, such as multiple gate lines and multiple data lines, extend in straight lines and are arranged between multiple sub-pixels, and multiple sub-pixels are connected to a single signal line. Therefore, in the display panel of a general-purpose display device, various lines, such as gate lines, data lines, high-potential voltage lines, and reference voltage lines, extend continuously from one side of the display panel of the organic light-emitting display device to the other side on the substrate.

[0120] In contrast, in the display device 100 according to an exemplary embodiment of the present disclosure, various lines such as gate lines, data lines, high-potential voltage lines, reference voltage lines, and initialization voltage lines, which are formed in straight lines and are considered to be used in a general organic light-emitting display device, are only provided on a plurality of first board patterns 121 and a plurality of second board patterns 123. In the display device 100 according to an exemplary embodiment of the present disclosure, lines formed in straight lines are only provided on a plurality of first board patterns 121 and a plurality of second board patterns 123.

[0121] In a display device 100 according to an exemplary embodiment of the present disclosure, pads on two adjacent first board patterns 121 can be connected by connecting lines 181 and 182. Therefore, connecting lines 181 and 182 electrically connect gating pads GP or data pads DP on two adjacent first board patterns 121. Thus, the display device 100 according to an exemplary embodiment of the present disclosure may include multiple connecting lines 181 and 182 to electrically connect various lines between multiple first board patterns 121, such as gating lines, data lines, high-potential voltage lines, and reference voltage lines. For example, gating lines may be provided on multiple first board patterns 121 arranged adjacent to each other along a first direction X. Furthermore, gating pads GP may be provided at both ends of the gating line. In this case, multiple gating pads GP on multiple first board patterns 121 arranged adjacent to each other along the first direction X can be connected to each other by a first connecting line 181 serving as a gating line. Therefore, the gating lines provided on multiple first board patterns 121 and the first connecting line 181 provided on a first line pattern 122 can be used as a single gating line. The aforementioned gate line can be referred to as a scan signal line. Furthermore, lines extending along the first direction X (such as light-emitting signal lines, low-potential voltage lines, and high-potential voltage lines) that can be included in all the various lines in the display device 100 can also be electrically connected via the first connection line 181 as described above.

[0122] Reference Figure 2 and Figure 4 The first connecting line 181 can connect two gating pads GP on side-by-side of a plurality of first board patterns 121 arranged adjacent to each other along the first direction X. The first connecting line 181 can be used as a gating line, a light-emitting signal line, a high-potential voltage line, or a low-potential voltage line, but is not limited thereto. The gating pads GP on the plurality of first board patterns 121 arranged along the first direction X can be connected by the first connecting line 181, which serves as a gating line. A single gating voltage can be transmitted to the gating pad GP.

[0123] In addition, refer to Figure 2 and Figure 3 The second connecting line 182 can connect two data pads DP on side-by-side of a plurality of first board patterns 121 arranged adjacent to each other along the second direction Y. The second connecting line 182 can be used as a data line, a high-potential voltage line, a low-potential voltage line, or a reference voltage line, but is not limited thereto. Internal lines on the plurality of first board patterns 121 arranged along the second direction Y can be connected by multiple second connecting lines 182 used as data lines. A single data voltage can be transmitted to them.

[0124] like Figure 4As shown, the first connecting line 181 can contact the upper and side surfaces of the planarization layer 146 disposed on the first plate pattern 121. Additionally, the first connecting line 181 can extend to the upper surface of the first line pattern 122. The second connecting line 182 can be configured to contact the upper and side surfaces of the planarization layer 146 disposed on the first plate pattern 121. Additionally, the second connecting line 182 can extend to the upper surface of the first line pattern 122.

[0125] However, as Figure 5 As shown, it is not necessary to set a rigid pattern in the area where the first connecting line 181 and the second connecting line 182 are not set. Therefore, in the absence of the first connecting line 181 and the second connecting line 182, the first line pattern 122, which is a rigid pattern, is not set.

[0126] In addition, refer to Figure 3 A dam 147 is formed on the connecting pads CNT, connecting lines 181 and 182, and planarization layer 146. The dam 147 is a component used to distinguish adjacent sub-pixels SPX. The dam 147 is configured to cover at least a portion of the connecting pads CNT, connecting lines 181 and 182, and planarization layer 146. The dam 147 can be formed of an insulating material. Furthermore, the dam 147 can contain a black material. Because the dam 147 contains a black material, it is used to hide lines visible through the display area AA. The dam 147 can be formed of, for example, a transparent carbon-based mixture. Specifically, the dam 147 can contain carbon black, but is not limited to this. The dam 147 can also be formed of a transparent insulating material. Furthermore, although in Figure 5 The height of the embankment 147 is shown to be lower than the height of the LED 70, but the height of the embankment 147 is not limited to this, and the height of the embankment 147 may be the same as or even higher than the height of the LED 170.

[0127] Reference Figure 3 LED 170 is disposed on the connection pad CNT and the first connection line 181. LED 170 includes an n-type layer 171, an active layer 172, a p-type layer 173, an n-electrode 174, and a p-electrode 175. The LED 170 of the display device 100 according to an exemplary embodiment of the present disclosure has a flip-chip structure, wherein the n-electrode 174 and the p-electrode 175 are formed on one of its surfaces.

[0128] An n-type layer 171 can be formed by implanting an n-type impurity into gallium nitride (GaN), which has excellent crystallinity. The n-type layer 171 can be disposed on a separate substrate formed of a light-emitting material.

[0129] An active layer 172 is disposed on the n-type layer 171. The active layer 172 is the light-emitting layer in the LED 170 and can be formed of a nitride semiconductor, such as indium gallium nitride (InGaN). A p-type layer 173 is disposed on the active layer 172. The p-type layer 173 can be formed by implanting p-type impurities into gallium nitride (GaN).

[0130] As described above, an LED 170 according to an exemplary embodiment of the present disclosure is manufactured by sequentially stacking an n-type layer 171, an active layer 172, and a p-type layer 173, and then etching predetermined regions of these layers, thereby forming an n-electrode 174 and a p-electrode 175. In this case, the predetermined region is the space that separates the n-electrode 174 and the p-electrode 175 from each other, and is etched to expose a portion of the n-type layer 171. In other words, the surface of the LED 170 where the n-electrode 174 and the p-electrode 175 are disposed may not be flat and may have different height levels.

[0131] In this manner, the n-electrode 174 is disposed in the etched region, and the n-electrode 174 can be formed of a conductive material. Additionally, the p-electrode 175 is disposed in the non-etched region, and the p-electrode 175 can also be formed of a conductive material. For example, the n-electrode 174 is disposed on the n-type layer 171 exposed by the etching process, and the p-electrode 175 is disposed on the p-type layer 173. The p-electrode 175 can be formed of the same material as the n-electrode 174.

[0132] An adhesive layer AD is disposed on the upper surface of the connection pad CNT and the first connection line 181, and between the connection pad CNT and the first connection line 181. Therefore, the LED 170 can be bonded to the connection pad CNT and the first connection line 181. In this case, the n-electrode 174 can be disposed on the first connection line 181, and the p-electrode 175 can be disposed on the connection pad CNT.

[0133] The adhesive layer AD can be a conductive adhesive layer formed by dispersing conductive balls in an insulating substrate member. Therefore, when heat or pressure is applied to the adhesive layer AD, the conductive balls become electrically connected to become conductive in the portion of the adhesive layer AD to which heat or pressure is applied. Furthermore, the unpressurized areas of the adhesive layer AD can have insulating properties. For example, the n-electrode 174 is electrically connected to the first connection line 181 via the adhesive layer AD, and the p-electrode 175 is electrically connected to the connection pad CNT via the adhesive layer AD. After the adhesive layer AD is applied to the upper surfaces of the first connection line 181 and the connection pad CNT by an inkjet method or the like, the LED 170 can be transferred onto the adhesive layer AD. The LED 170 can then be pressed and heated, thereby electrically connecting the connection pad CNT to the p-electrode 175 and the first connection line 181 to the n-electrode 174. However, except for the portions of the adhesive layer AD disposed between the n-electrode 174 and the first connection line 181, and the portions of the adhesive layer AD disposed between the p-electrode 175 and the connection pad CNT, the other portions of the adhesive layer AD have insulating properties. In addition, the adhesive layer AD can be individually applied to each of the connecting pads CNT and the first connecting line 181.

[0134] Furthermore, the connection pad CNT is electrically connected to the drain electrode 164 of the drive transistor 160 and receives the drive voltage for driving the LED 170 from the drive transistor 160. Although Figure 3 The example illustrates that the connection pad CNT and drain electrode 164 of the driving transistor 160 are indirectly connected to each other without direct contact, but this disclosure is not limited thereto, and the connection pad CNT and drain electrode 164 of the driving transistor 160 can be in direct contact. Additionally, a low-potential driving voltage for driving the LED 170 is applied to the first connection line 181. Therefore, when the display device 100 is turned on, different voltage levels applied to the connection pad CNT and the first connection line 181 are transmitted to the n electrode 174 and p electrode 175, respectively, causing the LED 170 to emit light.

[0135] The upper substrate 112 is used to support various components disposed below the upper substrate 112. Specifically, the upper substrate 112 can be formed by coating and hardening a material used to form the upper substrate 112 onto the lower substrate 111 and the first plate pattern 121. Therefore, the upper substrate 112 can be configured to overlap with the lower substrate 111, the first plate pattern 121, the first line pattern 122, and the connecting lines 181 and 182.

[0136] The upper substrate 112 can be formed of the same material as the lower substrate 111. For example, the upper substrate 112 can be formed of silicone rubber such as polydimethylsiloxane (PDMS) or elastomers such as polyurethane (PU) and polytetrafluoroethylene (PTFE). Therefore, the upper substrate 112 can be flexible. However, the material of the upper substrate 112 is not limited to this.

[0137] Furthermore, despite Figure 3 As not shown, a polarizing layer may also be disposed on the upper substrate 112. The polarizing layer polarizes light incident from the outside of the display device 100 and reduces the reflection of external light. In addition, other optical films may be disposed on the upper substrate 112 instead of the polarizing layer.

[0138] Additionally, a filler layer 190 may be provided, which is disposed on the entire surface of the lower substrate 111 and fills the gap between the upper substrate 112 and the components disposed on the lower substrate 111. The filler layer 190 may be formed of a curable adhesive. Specifically, the material for forming the filler layer 190 is coated on the entire surface of the lower substrate 111 and then cured, such that the filler layer 190 can be disposed between the upper substrate 112 and the components disposed on the lower substrate 111. For example, the filler layer 190 may be an optically clear adhesive (OCA) and may include acrylic adhesives, silicone adhesives, and polyurethane adhesives.

[0139] <Circuit structure and driving method of the display area>

[0140] Figure 6A and Figure 6B This is a circuit diagram of a sub-pixel of a display device according to an exemplary embodiment of the present disclosure.

[0141] Specifically, Figure 6A An example is illustrated where a sub-pixel of a display device according to an exemplary embodiment of the present disclosure includes a light-emitting element (LED). Furthermore, Figure 6B An example is illustrated where a subpixel of a display device according to an exemplary embodiment of the present disclosure comprises two light-emitting elements, LED1 and LED2.

[0142] For reference only. Figure 3 The switching transistor 150 shown can correspond to Figure 6A and Figure 6B The first transistor T1, Figure 3 The driving transistor 160 shown can correspond to Figure 6A and Figure 6B The driving transistor DT, and Figure 3 The LED 170 shown can correspond to Figure 6A and Figure 6B The light-emitting elements are LEDs or LED1 and LED2.

[0143] like Figure 6B As shown, according to an exemplary embodiment of this disclosure, two light-emitting elements LED1 and LED2 can be connected in parallel in a sub-pixel of the display device. That is, the corresponding anodes of the two light-emitting elements LED1 and LED2 can be connected to each other, and the corresponding cathodes of the two light-emitting elements LED1 and LED2 can all be connected to the low-potential voltage VSS line.

[0144] Therefore, when one of the two light-emitting elements, LED1 and LED2, fails to emit light due to a defect (e.g., a transmission defect), the other LED2 can still emit light normally. In other words, the other of the two light-emitting elements, LED1 and LED2, can perform the function of a redundant LED. As a result, the display device according to the exemplary embodiments of this disclosure includes redundant LEDs, thereby improving the yield of the display device.

[0145] In the following text, reference will be made to Figure 6A Describe in detail the configuration and driving methods of subpixels.

[0146] The switching element constituting each of the plurality of sub-pixels can be implemented as a transistor having an n-type or p-type MOSFET structure. Although a p-type transistor is illustrated in the following embodiments, this disclosure is not limited thereto.

[0147] Furthermore, a transistor is a three-electrode device comprising a gate electrode, a source electrode, and a drain electrode. The source electrode is the electrode that supplies charge carriers to the transistor. In a transistor, charge carriers begin to flow from the source electrode. The drain electrode is the electrode from which charge carriers leave the transistor. That is, charge carriers flow from the source electrode to the drain electrode in a MOSFET. In the case of an n-type MOSFET (NMOS), since the charge carriers are electrons, the voltage at the source electrode is lower than the voltage at the drain electrode, allowing electrons to flow from the source electrode to the drain electrode. In an n-type MOSFET, because electrons flow from the source electrode to the drain electrode, the current flows from the drain electrode to the source electrode. In the case of a p-type MOSFET (PMOS), since the charge carriers are holes, the voltage at the source electrode is higher than the voltage at the drain electrode, allowing holes to flow from the source electrode to the drain electrode. In a p-type MOSFET, because holes flow from the source electrode to the drain electrode, the current flows from the source electrode to the drain electrode. It should be noted that the source and drain electrodes of a MOSFET are not fixed. For example, the source and drain electrodes of a MOSFET can change depending on the applied voltage. This invention should not be limited to the source and drain electrodes of the transistor in the following embodiments.

[0148] Each sub-pixel includes a light-emitting element (LED), a driving transistor (DT), first transistors T1 through sixth transistors T6, and a storage capacitor Cst. However, the implementation is not limited to this. For example, each sub-pixel may include more or fewer transistors.

[0149] The LED emits light through a drive current supplied from the driving transistor DT. The anode of the LED is connected to the fourth transistor T4 and the fifth transistor T5, and the cathode of the LED is connected to the input terminal of the low potential voltage VSS.

[0150] The driving transistor DT controls the driving current applied to the light-emitting element LED according to its gate-source voltage Vgs. In addition, the source electrode of the driving transistor DT is connected to the first node N1, the gate electrode of the driving transistor DT is connected to the second node N2, and the drain electrode of the driving transistor DT is connected to the second transistor T2 and the fourth transistor T4.

[0151] The first transistor T1 applies the data voltage Vdata supplied from the data line to the first node N1, which serves as the source electrode of the driving transistor DT. The first transistor T1 includes a source electrode connected to the data line, a drain electrode connected to the first node N1, and a gate electrode connected to the second scan signal line that transmits the second scan signal SCAN2. Therefore, the first transistor T1 applies the data voltage Vdata supplied from the data line to the first node N1, which serves as the source electrode of the driving transistor DT, in response to the low-level second scan signal SCAN2, which is an on-state level.

[0152] The second transistor T2 connects the gate and drain diodes of the driving transistor DT. The second transistor T2 includes a source electrode connected to the drain electrode of the driving transistor DT, a drain electrode connected to a second node N2 which serves as the gate electrode of the driving transistor DT, and a gate electrode connected to the second scan signal line that transmits the second scan signal SCAN2. Therefore, the second transistor T2 connects the gate and drain diodes of the driving transistor DT in response to the low-level second scan signal SCAN2, which is an on-state.

[0153] The third transistor T3 applies a high-potential voltage VDD to the first node N1, which serves as the source electrode of the driving transistor DT. The third transistor T3 includes a source electrode connected to the third node N3, a drain electrode connected to the first node N1, and a gate electrode connected to a light-emitting signal line that transmits the light-emitting signal EM. The third node N3 is connected to a high-potential voltage line that transmits the high-potential voltage VDD. Therefore, the third transistor T3 applies the high-potential voltage VDD to the first node N1, which serves as the source electrode of the driving transistor DT, in response to the low-level light-emitting signal EM, which is the on-state.

[0154] The fourth transistor T4 forms a current path between the driving transistor DT and the light-emitting element LED. The fourth transistor T4 includes a source electrode connected to the drain electrode of the driving transistor DT, a drain electrode connected to the light-emitting element LED, and a gate electrode connected to the light-emitting signal line that transmits the light-emitting signal EM. Therefore, the fourth transistor T4 forms a current path between the light-emitting element LED and the drain electrode of the driving transistor DT in response to the light-emitting signal EM.

[0155] The fifth transistor T5 applies an initialization voltage Vini to the anode electrode of the LED. The fifth transistor T5 includes a source electrode connected to an initialization voltage line transmitting the initialization voltage Vini, a drain electrode connected to the anode electrode of the LED, and a gate electrode connected to a second scan signal line transmitting the second scan signal SCAN2. Therefore, the fifth transistor T5 applies the initialization voltage Vini to the anode electrode of the LED in response to the low level of the second scan signal SCAN2, which is an on-state level.

[0156] The sixth transistor T6 applies an initialization voltage Vini to the second node N2, which serves as the gate electrode of the driving transistor DT. The sixth transistor T6 includes a source electrode connected to an initialization voltage line that transmits the initialization voltage Vini, a drain electrode connected to the second node N2, which serves as the gate electrode of the driving transistor DT, and a gate electrode connected to a first scan signal line that transmits the first scan signal SCAN1. Therefore, the sixth transistor T6 applies the initialization voltage Vini to the second node N2, which serves as the gate electrode of the driving transistor DT, in response to the low-level first scan signal SCAN1, which is an on-state level.

[0157] The storage capacitor Cst includes a first electrode connected to the second node N2 and a second electrode connected to the third node N3. That is, one electrode of the storage capacitor Cst is connected to the gate electrode of the driving transistor DT, while the other electrode of the storage capacitor Cst is connected to the high-potential voltage line that transmits the high-potential voltage VDD.

[0158] Figure 7 This is a waveform diagram illustrating the light emission signal and scanning signal of a display device according to an exemplary embodiment of the present disclosure.

[0159] Figure 8A This is a circuit diagram of the pixels of a display device according to an exemplary embodiment of the present disclosure during the initial time period.

[0160] Figure 8B This is a circuit diagram of the pixels of a display device according to an exemplary embodiment of the present disclosure during the sampling period.

[0161] Figure 8CThis is a circuit diagram of the pixels of a display device according to an exemplary embodiment of the present disclosure during the light-emitting period.

[0162] Reference Figures 7 to 8C The driving mechanism of a display device according to an exemplary embodiment of the present disclosure will be described below.

[0163] In addition, refer to Figure 7 and Figure 8A During the initial period (Initial), the first scan signal SCAN1 is at a low level as the on-state, the second scan signal SCAN2 is at a high level as the off-state, and the light-emitting signal EM is at a high level as the off-state. Therefore, the sixth transistor T6 is turned on to apply the initialization voltage Vini to the second node N2. As a result, the gate electrode of the driving transistor DT is initialized to the initialization voltage Vini. The initialization voltage Vini can be selected within a voltage range sufficiently lower than the operating voltage of the light-emitting element LED, and can be set to be equal to or lower than the low potential voltage VSS. Furthermore, during the initial period (Initial), the high potential voltage VDD is maintained at the third node N3.

[0164] In addition, refer to Figure 7 and Figure 8B During the sampling period, the first scan signal SCAN1 is a high level acting as a cutoff level, the second scan signal SCAN2 is a low level acting as a turn-on level, and the emission signal EM is a high level acting as a cutoff level. Furthermore, during the sampling period, the first transistor T1 is turned on, causing the data voltage Vdata to be applied to the first node N1. Additionally, since the second transistor T2 is also turned on, the driving transistor DT is connected to a diode, and the gate and drain electrodes of the driving transistor DT are short-circuited, causing the driving transistor DT to operate like a diode.

[0165] During the sampling period, current flows between the source and drain of the driving transistor DT. Since the gate and drain of the driving transistor DT are in a diode-connected state, the voltage at the second node N2 increases due to the current flowing from the source to the drain until the gate-source voltage Vgs of the driving transistor DT becomes Vth. During the sampling period, the voltage at the second node N2 is charged with a voltage Vdata+Vth corresponding to the sum of the threshold voltage Vth and the data voltage Vdata of the driving transistor DT.

[0166] Furthermore, during the sampling period, the fifth transistor T5 is turned on to apply the initialization voltage Vini to the anode electrode of the LED. Additionally, even during the sampling period, the high potential voltage VDD remains at the third node N3.

[0167] In addition, refer to Figure 7 and Figure 8C During the emission period, the first scan signal SCAN1 is a high level as a cutoff level, the second scan signal SCAN2 is a high level as a cutoff level, and the emission signal EM is a low level as a conduction level. Therefore, the third transistor T3 is turned on to apply a high potential voltage VDD to the first node N1. Additionally, the fourth transistor T4 is also turned on to form a current path between the driving transistor DT and the light-emitting element LED. As a result, a drive current passing through the source and drain electrodes of the driving transistor DT is applied to the light-emitting element LED.

[0168] In other words, the voltage at the second node N2, which serves as the gate electrode of the driving transistor DT, is Vdata+Vth, corresponding to the sum of the threshold voltage Vth and the data voltage Vdata of the driving transistor DT, and the voltage at the first node N1, which serves as the source electrode of the driving transistor DT, is a high-potential voltage VDD. Therefore, the gate-source voltage Vgs of the driving transistor DT can be Vdata+Vth-VDD.

[0169] During the emission period, the relationship between the driving current Iled flowing through the LED is shown in Equation 1 below.

[0170] [Formula 1]

[0171] Iled=k*(Vgs-Vth)^2=k*(Vdata+Vth-VDD-Vth)^2=k*(Vdata-VDD)^2

[0172] In Equation 1, k represents a proportionality constant determined by the electron mobility, parasitic capacitance, and channel capacitance of the driving transistor DT.

[0173] As shown in [Equation 1], the threshold voltage Vth component of the driving transistor DT is erased from the expression for the driving current Iled. This means that in the display device according to this disclosure, the driving current Iled does not change even if the threshold voltage Vth changes. In other words, the display device according to an exemplary embodiment of this disclosure can program the data voltage regardless of the amount of change in the threshold voltage Vth.

[0174] Furthermore, in the display device according to an exemplary embodiment of this disclosure, a high potential voltage VDD, which is a constant power supply voltage, is applied to the storage capacitor Cst. This stabilizes the storage capacitor Cst, allowing the pixel circuit to drive normally even if the size of the storage capacitor Cst is designed to be small. Therefore, the area occupied by the storage capacitor Cst in a sub-pixel is reduced, enabling the pixel circuit to drive normally as... Figure 6B Redundant LEDs are provided in the sub-pixels as shown. As a result, due to the above circuit structure, the yield of the display device according to the exemplary embodiment of this disclosure can be improved.

[0175] Hereinafter, a display device according to another exemplary embodiment of the present disclosure will be described. The exemplary embodiments of the present disclosure and the other exemplary embodiment of the present disclosure differ in terms of the circuit configuration and driving method of the sub-pixels. Therefore, the description of overlapping portions of the exemplary embodiments of the present disclosure and the other exemplary embodiment of the present disclosure will be omitted, and the differences between the exemplary embodiments of the present disclosure and the other exemplary embodiment of the present disclosure will be primarily described.

[0176] <Another exemplary embodiment of this disclosure>

[0177] Figure 9A and Figure 9B This is a circuit diagram of a sub-pixel of a display device according to another exemplary embodiment of the present disclosure.

[0178] Specifically, Figure 9A This illustrates a case where a sub-pixel of a display device according to another exemplary embodiment of the present disclosure includes a light-emitting element (LED). Furthermore, Figure 9B An example is given of a display device according to another exemplary embodiment of the present disclosure, in which a sub-pixel includes two light-emitting elements, LED1 and LED2.

[0179] For reference only. Figure 3 The switching transistor 150 shown can correspond to Figure 9A and Figure 9B The first transistor T1, Figure 3 The driving transistor 160 shown can correspond to Figure 9A and Figure 9B The driving transistor DT, and Figure 3 The LED 170 shown can correspond to Figure 9A and Figure 9B The light-emitting elements are LEDs or LED1 and LED2.

[0180] like Figure 9BAs shown, according to another exemplary embodiment of this disclosure, two light-emitting elements LED1 and LED2 can be connected in parallel in a sub-pixel of the display device. That is, the corresponding anodes of the two light-emitting elements LED1 and LED2 can be connected to each other, and the corresponding cathodes of the two light-emitting elements LED1 and LED2 can all be connected to the low-potential voltage VSS line.

[0181] Therefore, when one of the two light-emitting elements, LED1 and LED2, fails to emit light due to a transmission defect, the other LED2 can still emit light normally. In other words, the other of the two light-emitting elements, LED1 and LED2, can perform the function of a redundant LED. As a result, the display device according to the exemplary embodiments of this disclosure includes redundant LEDs, thereby improving the yield of the display device.

[0182] In the following text, reference will be made to Figure 9A Describe in detail the configuration and driving methods of subpixels.

[0183] In a display device according to another exemplary embodiment of the present disclosure, each sub-pixel includes a light-emitting element LED, a driving transistor DT, a first transistor T1 to a fifth transistor T5, and a storage capacitor Cst.

[0184] The LED emits light through a drive current supplied from the driving transistor DT. The anode of the LED is connected to the fourth transistor T4 and the fifth transistor T5, and the cathode of the LED is connected to the input terminal of the low potential voltage VSS.

[0185] The driving transistor DT controls the driving current applied to the light-emitting element LED according to its gate-source voltage Vgs. In addition, the source electrode of the driving transistor DT is connected to the first node N1, the gate electrode of the driving transistor DT is connected to the second node N2, and the drain electrode of the driving transistor DT is connected to the second transistor T2 and the fourth transistor T4.

[0186] The first transistor T1 applies the data voltage Vdata provided from the data line to the first node N1, which serves as the source electrode of the driving transistor DT. The first transistor T1 includes a source electrode connected to the data line, a drain electrode connected to the first node N1, and a gate electrode connected to the scan signal line that transmits the scan signal SCAN. Therefore, the first transistor T1 applies the data voltage Vdata provided from the data line to the first node N1, which serves as the source electrode of the driving transistor DT, in response to the low-level scan signal SCAN, which is an on-state.

[0187] The second transistor T2 connects the gate and drain diodes of the driving transistor DT. The second transistor T2 includes a source electrode connected to the drain electrode of the driving transistor DT, a drain electrode connected to a second node N2 which serves as the gate electrode of the driving transistor DT, and a gate electrode connected to the scan signal line that transmits the scan signal SCAN. Therefore, the second transistor T2 connects the gate and drain diodes of the driving transistor DT in response to the low-level scan signal SCAN, which is an on-state.

[0188] The third transistor T3 applies a high-potential voltage VDD to the first node N1, which serves as the source electrode of the driving transistor DT. The third transistor T3 includes a source electrode connected to the third node N3, a drain electrode connected to the first node N1, and a gate electrode connected to a light-emitting signal line that transmits the light-emitting signal EM. The third node N3 is connected to a high-potential voltage line that transmits the high-potential voltage VDD. Therefore, the third transistor T3 applies the high-potential voltage VDD to the first node N1, which serves as the source electrode of the driving transistor DT, in response to the low-level light-emitting signal EM, which is the on-state.

[0189] The fourth transistor T4 forms a current path between the driving transistor DT and the light-emitting element LED. The fourth transistor T4 includes a source electrode connected to the drain electrode of the driving transistor DT, a drain electrode connected to the light-emitting element LED, and a gate electrode connected to the light-emitting signal line that transmits the light-emitting signal EM. Therefore, the fourth transistor T4 forms a current path between the light-emitting element LED and the drain electrode of the driving transistor DT in response to the light-emitting signal EM.

[0190] The fifth transistor T5 applies an initialization voltage Vini to the anode electrode of the LED. The fifth transistor T5 includes a source electrode connected to an initialization voltage line transmitting the initialization voltage Vini, a drain electrode connected to the anode electrode of the LED, and a gate electrode connected to a scan signal line transmitting the scan signal SCAN. Therefore, the fifth transistor T5 applies the initialization voltage Vini to the anode electrode of the LED in response to a low-level scan signal SCAN, which is an on-state level.

[0191] The storage capacitor Cst includes a first electrode connected to the second node N2 and a second electrode connected to the third node N3. That is, one electrode of the storage capacitor Cst is connected to the gate electrode of the driving transistor DT, and the other electrode of the storage capacitor Cst is connected to the high-potential voltage line that transmits the high-potential voltage VDD.

[0192] Figure 10 This is a waveform diagram illustrating the light emission signal and scanning signal of a display device according to another exemplary embodiment of the present disclosure.

[0193] Figure 11AThis is a circuit diagram of the pixels of a display device according to another exemplary embodiment of the present disclosure during the initial time period.

[0194] Figure 11B This is a circuit diagram of the pixels of a display device according to another exemplary embodiment of the present disclosure during the sampling period.

[0195] Figure 11C This is a circuit diagram of the pixels of a display device according to another exemplary embodiment of the present disclosure during the light-emitting period.

[0196] Reference Figures 10 to 11C Describes the driving of a display device according to another exemplary embodiment of the present disclosure.

[0197] In addition, refer to Figure 10 and Figure 11A During the initial period, the scan signal SCAN is at a low level as the on-state, and the light emission signal EM is also at a low level as the on-state. Therefore, the second transistor T2, the fourth transistor T4, and the fifth transistor T5 are turned on to apply the initialization voltage Vini to the second node N2. As a result, the gate electrode of the driving transistor DT is initialized to the initialization voltage Vini. The initialization voltage Vini can be selected within a voltage range sufficiently lower than the operating voltage of the light-emitting element LED, and can be set to be equal to or lower than the low potential voltage VSS.

[0198] Additionally, during the initial period (Initial), the first transistor T1 is turned on, and the data voltage Vdata can be equal to the initialization voltage Vini. Therefore, the initialization voltage Vini is applied to the first node N1. Furthermore, during the initial period (Initial), the high potential voltage VDD is maintained at the third node N3.

[0199] In addition, refer to Figure 10 and Figure 11B During the sampling period, the scan signal SCAN is at a low level (on) and the emission signal EM is at a high level (off). Furthermore, during the sampling period, the first transistor T1 is turned on, causing the data voltage Vdata to be applied to the first node N1. Additionally, since the second transistor T2 is also turned on, the driving transistor DT is connected to a diode, and the gate and drain electrodes of the driving transistor DT are short-circuited, causing the driving transistor DT to operate like a diode.

[0200] During the sampling period, current flows between the source and drain of the driving transistor DT. Since the gate and drain of the driving transistor DT are in a diode-connected state, the voltage at the second node N2 increases due to the current flowing from the source to the drain until the gate-source voltage Vgs of the driving transistor DT becomes Vth. During the sampling period, the voltage at the second node N2 is charged with a voltage Vdata+Vth corresponding to the sum of the threshold voltage Vth and the data voltage Vdata of the driving transistor DT.

[0201] Furthermore, during the sampling period, the fifth transistor T5 is turned on to apply the initialization voltage Vini to the anode electrode of the LED. Additionally, even during the sampling period, the high potential voltage VDD remains at the third node N3.

[0202] In addition, refer to Figure 10 and Figure 11C During the emission period, the scan signal SCAN is at a high level (cutoff level), and the emission signal EM is at a low level (on level). Therefore, the third transistor T3 is turned on to apply a high potential voltage VDD to the first node N1. Additionally, the fourth transistor T4 is also turned on to form a current path between the driving transistor DT and the light-emitting element LED. As a result, a drive current passing through the source and drain electrodes of the driving transistor DT is applied to the light-emitting element LED.

[0203] In other words, the voltage at the second node N2, which serves as the gate electrode of the driving transistor DT, is Vdata+Vth, corresponding to the sum of the threshold voltage Vth and the data voltage Vdata of the driving transistor DT, and the voltage at the first node N1, which serves as the source electrode of the driving transistor DT, is a high-potential voltage VDD. Therefore, the gate-source voltage Vgs of the driving transistor DT can be Vdata+Vth-VDD.

[0204] During the emission period, the relationship between the driving current flowing through the LED is shown in Equation 1 below.

[0205] [Formula 1]

[0206] Iled=k*(Vgs-Vth)^2=k*(Vdata+Vth-VDD-Vth)^2=k*(Vdata-VDD)^2

[0207] In Equation 1, k represents a proportionality constant determined by the electron mobility, parasitic capacitance, and channel capacitance of the driving transistor DT.

[0208] As shown in [Equation 1], the threshold voltage Vth component of the driving transistor DT is erased from the expression for the driving current Iled. This means that in the display device according to this disclosure, the driving current Iled does not change even if the threshold voltage Vth changes. In other words, the display device according to another exemplary embodiment of this disclosure can program the data voltage regardless of the amount of change in the threshold voltage Vth.

[0209] Furthermore, in a display device according to another exemplary embodiment of this disclosure, a high potential voltage VDD, which is a constant power supply voltage, is applied to the storage capacitor Cst. Therefore, the storage capacitor Cst can be stabilized, allowing the pixel circuit to be driven normally even if the size of the storage capacitor Cst is designed to be small. Thus, the area occupied by the storage capacitor Cst in a sub-pixel is reduced, enabling the... Figure 9B The diagram shows redundant LEDs arranged in sub-pixels. As a result, due to the above circuit structure, the yield of the display device according to another exemplary embodiment of this disclosure can be improved.

[0210] Furthermore, compared to the display device according to the exemplary embodiment of this disclosure, the display device according to another exemplary embodiment of this disclosure allows for a reduction in the number of scan lines. Therefore, the number of stretch lines in the display device according to another exemplary embodiment of this disclosure can be reduced. Consequently, due to the reduction in the number of stretch lines, the stretch ratio and stretch reliability can be improved. (Refer to...) Figure 12 and Figure 13 Describe it in detail.

[0211] Figure 12 This is a diagram used to explain the arrangement of the connection lines of a display device according to an exemplary embodiment of the present disclosure.

[0212] Figure 13 This is a diagram used to explain the arrangement of the connection lines of a display device according to another exemplary embodiment of the present disclosure.

[0213] like Figure 12 As shown, in a display device according to an exemplary embodiment of the present disclosure, five first connection lines 181 need to be connected to a pixel PX, and four second connection lines 182 need to be connected to a pixel PX.

[0214] Specifically, each of the five first connection lines 181 includes a first scan signal line for transmitting the first scan signal SCAN1, a second scan signal line for transmitting the second scan signal SCAN2, a light emission signal line for transmitting the light emission signal EM, a low-potential voltage line for transmitting the low-potential voltage VSS, and a high-potential voltage line for transmitting the high-potential voltage VDD. Additionally, each of the four second connection lines 182 includes a red data line for transmitting the red data voltage Data_R, a green data line for transmitting the green data voltage Data_G, a blue data line for transmitting the blue data voltage Data_B, and an initialization voltage line for transmitting the initialization voltage Vini.

[0215] In a display device according to an exemplary embodiment of the present disclosure, the stretching ratio (or stretch length ratio) of the first connecting line 181 extending along the first direction X is as follows. Based on 100 ppi (pixels per inch), the length of the first connecting line 181 in the first direction X before stretching is 127 μm, and the length of the fully stretched first connecting line 181 in the first direction X is 183 μm. Therefore, in a display device according to an exemplary embodiment of the present disclosure, the stretching ratio (or stretch length ratio) of the first connecting line 181 extending along the first direction X is 1.4 (=183 μm / 127 μm).

[0216] Unlike this, such as Figure 13 As shown, in a display device according to another exemplary embodiment of the present disclosure, four first connection lines 181 need to be connected to a pixel PX, and four second connection lines 182 need to be connected to a pixel PX.

[0217] Specifically, each of the four first connection lines 181 includes a scan signal line for transmitting the scan signal SCAN, a light emission signal line for transmitting the light emission signal EM, a low-potential voltage line for transmitting the low-potential voltage VSS, and a high-potential voltage line for transmitting the high-potential voltage VDD. Additionally, each of the four second connection lines 182 includes a red data line for transmitting the red data voltage Data_R, a green data line for transmitting the green data voltage Data_G, a blue data line for transmitting the blue data voltage Data_B, and an initialization voltage line for transmitting the initialization voltage Vini.

[0218] In a display device according to another exemplary embodiment of the present disclosure, the stretch ratio (or stretch length ratio) of the first connecting line 181 extending along the first direction X is as follows. Based on 100 ppi (pixels per inch), the length of the first connecting line 181 in the first direction X before stretching is 127 μm, and the length of the fully stretched first connecting line 181 in the first direction X is 240 μm. Therefore, in the display device according to another exemplary embodiment of the present disclosure, the stretch ratio (or stretch length ratio) of the first connecting line 181 extending along the first direction X is 1.9 (=240 μm / 127 μm).

[0219] As a result, in a display device according to another exemplary embodiment of the present disclosure, it can be seen that by configuring the pixel circuits to integrate the scan signal lines, the stretching ratio of the display device is increased by 35% or more.

[0220] Hereinafter, a display device according to yet another exemplary embodiment of the present disclosure will be described. The exemplary embodiments of the present disclosure and yet another exemplary embodiment of the present disclosure differ only in the connection relationship of the storage capacitors. Therefore, the description of the overlapping parts of the exemplary embodiments of the present disclosure and yet another exemplary embodiment of the present disclosure will be omitted, and the differences between the exemplary embodiments of the present disclosure and yet another exemplary embodiment of the present disclosure will be mainly described.

[0221] <Another exemplary embodiment of this disclosure>

[0222] Figure 14A and Figure 14B This is a circuit diagram of a sub-pixel of a display device according to yet another exemplary embodiment of the present disclosure.

[0223] Specifically, Figure 14A An example is illustrated where a sub-pixel of a display device according to yet another exemplary embodiment of the present disclosure includes a light-emitting element (LED). Furthermore, Figure 14B An example is given of a display device according to yet another exemplary embodiment of the present disclosure, in which the sub-pixels include two light-emitting elements, LED1 and LED2.

[0224] For reference only. Figure 3 The switching transistor 150 shown can correspond to Figure 14A and Figure 14B The first transistor T1, Figure 3 The driving transistor 160 shown can correspond to Figure 14A and Figure 14B The driving transistor DT, and Figure 3 The LED170 shown can correspond to Figure 14A and Figure 14B The light-emitting elements are LEDs or LED1 and LED2.

[0225] like Figure 14B As shown, according to another exemplary embodiment of this disclosure, two light-emitting elements LED1 and LED2 can be connected in parallel in a sub-pixel of the display device. That is, the corresponding anodes of the two light-emitting elements LED1 and LED2 can be connected to each other, and the corresponding cathodes of the two light-emitting elements LED1 and LED2 can be connected to a low-potential voltage VSS line.

[0226] Therefore, when one of the two light-emitting elements, LED1 and LED2, fails to emit light due to a transmission defect, the other LED2 can still emit light normally. In other words, the other of the two light-emitting elements, LED1 and LED2, can perform the function of a redundant LED. As a result, the display device according to yet another exemplary embodiment of this disclosure includes redundant LEDs, thereby improving the yield of the display device.

[0227] In the following text, reference will be made to Figure 14A Describe in detail the configuration and driving methods of subpixels.

[0228] In a display device according to yet another exemplary embodiment of the present disclosure, each sub-pixel includes a light-emitting element LED, a driving transistor DT, a first transistor T1 to a fifth transistor T5, and a storage capacitor Cst.

[0229] The LED emits light through a drive current supplied from the driving transistor DT. The anode of the LED is connected to the fourth transistor T4 and the fifth transistor T5, and the cathode of the LED is connected to the input terminal of the low potential voltage VSS.

[0230] The driving transistor DT controls the driving current applied to the light-emitting element LED according to its gate-source voltage Vgs. In addition, the source electrode of the driving transistor DT is connected to the first node N1, the gate electrode of the driving transistor DT is connected to the second node N2, and the drain electrode of the driving transistor DT is connected to the second transistor T2 and the fourth transistor T4.

[0231] The first transistor T1 applies the data voltage Vdata provided from the data line to the first node N1, which serves as the source electrode of the driving transistor DT. The first transistor T1 includes a source electrode connected to the data line, a drain electrode connected to the first node N1, and a gate electrode connected to the scan signal line that transmits the scan signal SCAN. Therefore, the first transistor T1 applies the data voltage Vdata provided from the data line to the first node N1, which serves as the source electrode of the driving transistor DT, in response to the low-level scan signal SCAN, which is an on-state.

[0232] The second transistor T2 connects the gate and drain diodes of the driving transistor DT. The second transistor T2 includes a source electrode connected to the drain electrode of the driving transistor DT, a drain electrode connected to a second node N2 which serves as the gate electrode of the driving transistor DT, and a gate electrode connected to the scan signal line that transmits the scan signal SCAN. Therefore, the second transistor T2 connects the gate and drain diodes of the driving transistor DT in response to the low-level scan signal SCAN, which is an on-state.

[0233] The third transistor T3 applies a high-potential voltage VDD to the first node N1, which serves as the source electrode of the driving transistor DT. The third transistor T3 includes a source electrode connected to a high-potential voltage line transmitting the high-potential voltage VDD, a drain electrode connected to the first node N1, and a gate electrode connected to a light-emitting signal line transmitting the light-emitting signal EM. Therefore, the third transistor T3 applies the high-potential voltage VDD to the first node N1, which serves as the source electrode of the driving transistor DT, in response to the low-level light-emitting signal EM, which is a conduction level.

[0234] The fourth transistor T4 forms a current path between the driving transistor DT and the light-emitting element LED. The fourth transistor T4 includes a source electrode connected to the drain electrode of the driving transistor DT, a drain electrode connected to the light-emitting element LED, and a gate electrode connected to the light-emitting signal line that transmits the light-emitting signal EM. Therefore, the fourth transistor T4 forms a current path between the light-emitting element LED and the drain electrode of the driving transistor DT in response to the light-emitting signal EM.

[0235] The fifth transistor T5 applies an initialization voltage Vini to the anode electrode of the LED. The fifth transistor T5 includes a source electrode connected to a third node N3 connected to the initialization voltage line transmitting the initialization voltage Vini, a drain electrode connected to the anode electrode of the LED, and a gate electrode connected to the scan signal line transmitting the scan signal SCAN. Therefore, the fifth transistor T5 applies the initialization voltage Vini to the anode electrode of the LED in response to a low-level scan signal SCAN, which is the on-state level.

[0236] The storage capacitor Cst includes a first electrode connected to the second node N2 and a second electrode connected to the third node N3. That is, one electrode of the storage capacitor Cst is connected to the gate electrode of the driving transistor DT, and the other electrode of the storage capacitor Cst is connected to the initialization voltage line that transmits the initialization voltage Vini.

[0237] Figure 15 This is a waveform diagram illustrating the light emission signal and scanning signal of a display device according to yet another exemplary embodiment of the present disclosure.

[0238] Figure 16AThis is a circuit diagram of the pixels of a display device according to yet another exemplary embodiment of the present disclosure during the initial time period.

[0239] Figure 16B This is a circuit diagram of the pixels of a display device according to yet another exemplary embodiment of the present disclosure during the sampling period.

[0240] Figure 16C This is a circuit diagram of the pixels of a display device according to another exemplary embodiment of the present disclosure during the light-emitting period.

[0241] Reference Figures 15 to 16C Describes the driving of a display device according to yet another exemplary embodiment of the present disclosure.

[0242] In addition, refer to Figure 15 and Figure 16A During the initial period, the scan signal SCAN is at a low level as the on-state, and the light emission signal EM is also at a low level as the on-state. Therefore, the second transistor T2, the fourth transistor T4, and the fifth transistor T5 are turned on to apply the initialization voltage Vini to the second node N2. As a result, the gate electrode of the driving transistor DT is initialized to the initialization voltage Vini. The initialization voltage Vini can be selected within a voltage range sufficiently lower than the operating voltage of the light-emitting element LED, and can be set to be equal to or lower than the low potential voltage VSS.

[0243] Additionally, during the initial period (Initial), the first transistor T1 is turned on, and the data voltage Vdata can be equal to the initialization voltage Vini. Therefore, the initialization voltage Vini is applied to the first node N1. Furthermore, during the initial period (Initial), the initialization voltage Vini is maintained at the third node N3.

[0244] In addition, refer to Figure 15 and Figure 16B During the sampling period, the scan signal SCAN is at a low level (on) and the emission signal EM is at a high level (off). Furthermore, during the sampling period, the first transistor T1 is turned on, causing the data voltage Vdata to be applied to the first node N1. Additionally, since the second transistor T2 is also turned on, the driving transistor DT is connected by a diode, and the gate and drain electrodes of the driving transistor DT are short-circuited, causing the driving transistor DT to operate like a diode.

[0245] During the sampling period, current flows between the source and drain of the driving transistor DT. Since the gate and drain of the driving transistor DT are in a diode-connected state, the voltage at the second node N2 increases due to the current flowing from the source to the drain until the gate-source voltage Vgs of the driving transistor DT becomes Vth. During the sampling period, the voltage at the second node N2 is charged with a voltage Vdata+Vth corresponding to the sum of the threshold voltage Vth and the data voltage Vdata of the driving transistor DT.

[0246] Furthermore, during the sampling period, the fifth transistor T5 is turned on to apply the initialization voltage Vini to the anode electrode of the LED. Additionally, during the sampling period, the initialization voltage Vini is maintained at the third node N3.

[0247] In addition, refer to Figure 15 and Figure 16C During the light-emitting period, the scan signal SCAN is at a high level, which is the cutoff level, and the light-emitting signal EM is at a low level, which is the on level. Therefore, the third transistor T3 is turned on to apply a high potential voltage VDD to the first node N1. In addition, the fourth transistor T4 is also turned on to form a current path between the driving transistor DT and the light-emitting element LED. As a result, a drive current through the source and drain electrodes of the driving transistor DT is applied to the light-emitting element LED.

[0248] In other words, the voltage at the second node N2, which serves as the gate electrode of the driving transistor DT, is Vdata+Vth, corresponding to the sum of the threshold voltage Vth and the data voltage Vdata of the driving transistor DT, and the voltage at the first node N1, which serves as the source electrode of the driving transistor DT, is a high-potential voltage VDD. Therefore, the gate-source voltage Vgs of the driving transistor DT can be Vdata+Vth-VDD.

[0249] During the emission period, the relationship between the driving current flowing through the LED is shown in Equation 1 below.

[0250] [Formula 1]

[0251] Iled=k*(Vgs-Vth)^2=k*(Vdata+Vth-VDD-Vth)^2=k*(Vdata-VDD)^2

[0252] In Equation 1, k represents a proportionality constant determined by the electron mobility, parasitic capacitance, and channel capacitance of the driving transistor DT.

[0253] As shown in [Equation 1], the threshold voltage Vth component of the driving transistor DT is erased from the expression for the driving current Iled. This means that in the display device according to this disclosure, the driving current Iled does not change even if the threshold voltage Vth changes. In other words, the display device according to another exemplary embodiment of this disclosure can program the data voltage regardless of the amount of change in the threshold voltage Vth.

[0254] Furthermore, in another exemplary embodiment of the display device according to this disclosure, an initialization voltage Vini, which is a constant power supply voltage, is applied to the storage capacitor Cst. Therefore, the storage capacitor Cst can be stabilized, allowing the pixel circuit to be driven normally even if the size of the storage capacitor Cst is designed to be small. Thus, the area occupied by the storage capacitor Cst in a sub-pixel is reduced, enabling the pixel circuit to be driven normally. Figure 14B Redundant LEDs are provided in the sub-pixels as shown. As a result, due to the above circuit structure, the yield of the display device according to the exemplary embodiment of this disclosure can be improved.

[0255] Furthermore, compared to the display device according to the exemplary embodiments of the present disclosure, the display device according to yet another exemplary embodiment of the present disclosure allows for a reduction in the number of scan lines. Therefore, the number of stretch lines in the display device according to yet another exemplary embodiment of the present disclosure can be reduced. Consequently, due to the reduction in the number of stretch lines, the stretch ratio and stretch reliability can be improved.

[0256] Exemplary embodiments of this disclosure can also be described as follows:

[0257] A display device according to an exemplary embodiment of the present disclosure may include: a stretchable lower substrate; a pattern layer disposed on the lower substrate and including a plurality of plate patterns and a plurality of line patterns; a plurality of pixels disposed on each of the plurality of plate patterns; and a plurality of connecting lines disposed on each of the plurality of line patterns to connect the plurality of pixels, wherein each pixel circuit formed in the plurality of pixels includes at least one light-emitting element, a driving transistor, a storage capacitor, and a first to a fifth transistor, and a constant power supply voltage can be applied to the storage capacitor.

[0258] At least one light-emitting element may include a first light-emitting element and a second light-emitting element connected in parallel.

[0259] The driving transistor may include a source electrode connected to a first node, a drain electrode connected to a second transistor and a fourth transistor, and a gate electrode connected to a second node. The first transistor may include a source electrode connected to one of a plurality of data lines, a drain electrode connected to the first node, and a gate electrode connected to a scan signal line. The second transistor may include a source electrode connected to the drain electrode of the driving transistor, a drain electrode connected to the second node, and a gate electrode connected to the scan signal line. The third transistor may include a source electrode connected to a high-potential voltage line, a drain electrode connected to the first node, and a gate electrode connected to a light-emitting signal line. The fourth transistor may include a source electrode connected to the drain electrode of the driving transistor, a drain electrode connected to at least one light-emitting element, and a gate electrode connected to the light-emitting signal line. The fifth transistor may include a source electrode connected to an initialization voltage line, a drain electrode connected to at least one light-emitting element, and a gate electrode connected to the scan signal line.

[0260] One electrode of the storage capacitor can be connected to the second node, and the other electrode of the storage capacitor can be connected to the initialization voltage line.

[0261] One electrode of the storage capacitor can be connected to the second node, and the other electrode of the storage capacitor can be connected to the high-potential voltage line.

[0262] The multiple connecting lines may include multiple first connecting lines extending along a first direction and multiple second connecting lines extending along a second direction.

[0263] The multiple first connection lines may include high-potential voltage lines, low-potential voltage lines, light emission signal lines, and scan signal lines, and the multiple second connection lines may include multiple data lines and initialization voltage lines.

[0264] The number of multiple first connection lines can be the same as the number of multiple second connection lines.

[0265] Each pixel circuit in the plurality of pixel circuits may include: an initial period in which an initialization voltage may be applied to a first node and a second node; a sampling period in which the voltage of the second node may be charged to a voltage corresponding to the sum of the threshold voltage of the driving transistor and the data voltage; and an emission period in which at least one light-emitting element emits light.

[0266] A display device according to another exemplary embodiment of the present disclosure may include a plurality of pixels spaced apart from each other and a plurality of connecting lines connecting the plurality of pixels and capable of being stretched. Each pixel circuit formed in the plurality of pixels may include at least one light-emitting element, a driving transistor, a storage capacitor, and a first transistor to a fifth transistor, and one of a scan signal and a light-emitting signal may be applied to the gate electrode of each of the first transistors to the fifth transistor.

[0267] At least one light-emitting element may include a first light-emitting element and a second light-emitting element connected in parallel.

[0268] The driving transistor may include a source electrode connected to the first node, a drain electrode connected to the second and fourth transistors, and a gate electrode connected to the second node.

[0269] The first transistor may include a source electrode connected to one of the multiple data lines, a drain electrode connected to a first node, and a gate electrode connected to a scan signal line. The second transistor may include a source electrode connected to the drain electrode of a driving transistor, a drain electrode connected to a second node, and a gate electrode connected to a scan signal line. The third transistor may include a source electrode connected to a high-potential voltage line, a drain electrode connected to the first node, and a gate electrode connected to a light-emitting signal line. The fourth transistor may include a source electrode connected to the drain electrode of a driving transistor, a drain electrode connected to at least one light-emitting element, and a gate electrode connected to a light-emitting signal line. The fifth transistor may include a source electrode connected to an initialization voltage line, a drain electrode connected to at least one light-emitting element, and a gate electrode connected to a scan signal line.

[0270] The storage capacitor can be connected to the initialization voltage line, through which a fixed initialization voltage can be applied.

[0271] The storage capacitor can be connected to a high-potential voltage line through which a fixed high-potential voltage can be applied.

[0272] The multiple connecting lines may include multiple first connecting lines extending along a first direction and multiple second connecting lines extending along a second direction.

[0273] The multiple first connection lines may include high-potential voltage lines, low-potential voltage lines, light emission signal lines, and scan signal lines, and the multiple second connection lines may include multiple data lines and initialization voltage lines.

[0274] The number of multiple first connection lines can be the same as the number of multiple second connection lines.

[0275] Each pixel circuit in a plurality of pixel circuits can be driven during the following time periods: an initial time period in which the scan signal can be at an on level and the light emission signal can be at an on level; a sampling time period in which the scan signal can be at an on level and the light emission signal can be at an off level; and a light emission time period in which the scan signal can be at an off level and the light emission signal can be at an on level. During the sampling time period, the voltage of the second node can be charged to a voltage Vdata+Vth corresponding to the sum of the threshold voltage and the data voltage of the driving transistor.

[0276] Although exemplary embodiments of the present disclosure have been described in detail with reference to the accompanying drawings, the present disclosure is not limited thereto and may be implemented in many different forms without departing from the technical concept of the present disclosure. Therefore, the exemplary embodiments of the present disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above exemplary embodiments are illustrative in all respects and do not limit the present disclosure. The scope of protection of the present disclosure should be interpreted based on the appended claims, and all technical concepts within their equivalent scope should be interpreted as falling within the scope of the present disclosure.

[0277] Cross-references to related applications

[0278] This application claims the benefit and priority of Korean Patent Application No. 10-2021-0190926, filed in Korea on December 29, 2021, the entire contents of which are hereby expressly incorporated by reference.

Claims

1. A display device, the display device comprising: Stretchable lower substrate; A pattern layer is disposed on the lower substrate and includes multiple board patterns and multiple line patterns; Multiple pixels, wherein the multiple pixels are disposed on each of the multiple plate patterns; as well as Multiple connecting lines are disposed on each of the multiple line patterns to connect the multiple pixels disposed on different plate patterns. Each pixel circuit formed in the plurality of pixels includes at least one light-emitting element, a driving transistor, a storage capacitor, and a first to a fifth transistor. A constant power supply voltage is applied to the storage capacitor. The plurality of connecting lines include: Multiple first connecting lines extending along a first direction; and Multiple second connecting lines extending along the second direction, and The plurality of first connection lines include a first scan signal line for transmitting a first scan signal, a second scan signal line for transmitting a second scan signal, a light emission signal line for transmitting a light emission signal, a low-potential voltage line for transmitting a low-potential voltage, and a high-potential voltage line for transmitting a high-potential voltage. The driving transistor includes a source electrode connected to the first node, a drain electrode connected to the second and fourth transistors, and a gate electrode connected to the second node. The first transistor includes a source electrode connected to one of the multiple data lines, a drain electrode connected to the first node, and a gate electrode connected to the scan signal line. The second transistor includes a source electrode connected to the drain electrode of the driving transistor, a drain electrode connected to the second node, and a gate electrode connected to the scan signal line. The third transistor includes a source electrode connected to a high-potential voltage line, a drain electrode connected to the first node, and a gate electrode connected to a light-emitting signal line. The fourth transistor includes a source electrode connected to the drain electrode of the driving transistor, a drain electrode connected to the at least one light-emitting element, and a gate electrode connected to the light-emitting signal line. The fifth transistor includes a source electrode connected to the initialization voltage line, a drain electrode connected to the at least one light-emitting element, and a gate electrode connected to the scan signal line. In this configuration, one electrode of the storage capacitor is directly connected to the second node, and the other electrode of the storage capacitor is directly connected to the high-potential voltage line. The initialization voltage line is directly connected to only the fifth transistor and is not directly connected to any other transistors. During the initial period, the second transistor, the fourth transistor, and the fifth transistor are turned on to apply an initialization voltage to the second node, and the gate electrode of the driving transistor is initialized to the initialization voltage.

2. The display device according to claim 1, in, The at least one light-emitting element includes a first light-emitting element and a second light-emitting element connected in parallel.

3. The display device according to claim 2, in, When one of the first light-emitting element and the second light-emitting element fails to emit light due to a defect, the other of the first light-emitting element and the second light-emitting element emits light normally.

4. The display device according to claim 1, in, The plurality of second connection lines include the plurality of data lines and the initialization voltage line.

5. The display device according to claim 1, in, Each pixel circuit in the multiple pixel circuits is driven during the following time periods: During the initial period, the initialization voltage is applied to the first node and the second node; During the sampling period, the voltage of the second node is charged to a voltage corresponding to the sum of the threshold voltage and the data voltage of the driving transistor; as well as During the light-emitting period, at least one light-emitting element emits light.

6. The display device according to claim 1, in, The multiple plate patterns are arranged in the form of islands spaced apart from each other.

7. The display device according to claim 1, in, The pattern layer also includes a plurality of second plate patterns and a plurality of second line patterns disposed in the non-display area, and Among them, a gating driver for providing scanning signals and light emission signals, and a power supply for providing high-potential voltage and low-potential voltage are formed on the plurality of second plate patterns.

8. The display device according to claim 1, in, The plurality of plate patterns and the plurality of line patterns are rigid compared to the lower substrate.

9. The display device according to claim 1, in, The multiple connecting lines have a sine wave shape or a Z-shape and are connected to lines formed as straight lines and only disposed on the multiple plate patterns.

10. The display device according to claim 1, wherein, Each of the plurality of pixels includes: The driving transistor on each of the plurality of plate patterns, the driving transistor including a gate electrode serving as a first electrode of the storage capacitor; An intermediate metal layer, which overlaps with the gate electrode and serves as the second electrode of the storage capacitor; and An interlayer insulating layer is located between the intermediate metal layer and the gate electrode of the driving transistor, and the interlayer insulating layer serves as a dielectric for the storage capacitor.

11. A display device, the display device comprising: Multiple pixels spaced apart from each other and multiple connecting lines connecting the multiple pixels that can be stretched. Each pixel circuit formed in the plurality of pixels includes at least one light-emitting element, a driving transistor, a storage capacitor, and a first to a fifth transistor. In this process, one of the scanning signal and the light emission signal is applied to the gate electrode of each of the first to fifth transistors. The plurality of connecting lines include: Multiple first connecting lines extending along a first direction; and Multiple second connecting lines extending along the second direction, and The plurality of first connection lines include a first scan signal line for transmitting a first scan signal, a second scan signal line for transmitting a second scan signal, a light emission signal line for transmitting a light emission signal, a low-potential voltage line for transmitting a low-potential voltage, and a high-potential voltage line for transmitting a high-potential voltage. The driving transistor includes a source electrode connected to the first node, a drain electrode connected to the second and fourth transistors, and a gate electrode connected to the second node. The first transistor includes a source electrode connected to one of the multiple data lines, a drain electrode connected to the first node, and a gate electrode connected to the scan signal line. The second transistor includes a source electrode connected to the drain electrode of the driving transistor, a drain electrode connected to the second node, and a gate electrode connected to the scan signal line. The third transistor includes a source electrode connected to a high-potential voltage line, a drain electrode connected to the first node, and a gate electrode connected to a light-emitting signal line. The fourth transistor includes a source electrode connected to the drain electrode of the driving transistor, a drain electrode connected to the at least one light-emitting element, and a gate electrode connected to the light-emitting signal line. The fifth transistor includes a source electrode connected to the initialization voltage line, a drain electrode connected to the at least one light-emitting element, and a gate electrode connected to the scan signal line. In this configuration, one electrode of the storage capacitor is directly connected to the second node, and the other electrode of the storage capacitor is directly connected to the high-potential voltage line. The initialization voltage line is directly connected to only the fifth transistor and is not directly connected to any other transistors. During the initial period, the second transistor, the fourth transistor, and the fifth transistor are turned on to apply an initialization voltage to the second node, and the gate electrode of the driving transistor is initialized to the initialization voltage.

12. The display device according to claim 11, in, The at least one light-emitting element includes a first light-emitting element and a second light-emitting element connected in parallel.

13. The display device according to claim 11, in, The plurality of second connection lines include the plurality of data lines and the initialization voltage line.

14. The display device according to claim 11, in, Drive each pixel circuit in a multi-pixel circuit during the following time periods: During the initial time period, the scanning signal is at the on level and the light emission signal is at the on level. During the sampling period, the scanning signal is at the on level and the light emission signal is at the off level; as well as During the light-emitting period, the scanning signal is at a cutoff level, and the light-emitting signal is at a conduction level. During the sampling period, the voltage of the second node is charged to a voltage Vdata+Vth corresponding to the sum of the threshold voltage and the data voltage of the driving transistor.

15. The display device according to claim 11, wherein, Each of the plurality of pixels includes: The driving transistor includes a gate electrode that serves as a first electrode of the storage capacitor; An intermediate metal layer, which overlaps with the gate electrode and serves as the second electrode of the storage capacitor; and An interlayer insulating layer is located between the intermediate metal layer and the gate electrode of the driving transistor, and the interlayer insulating layer serves as a dielectric for the storage capacitor.

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