A duty ratio adjustment circuit, its driving method, a display panel, and an electronic device

Abstract

The present disclosure provides a duty cycle adjustment circuit, a driving method thereof, a display panel, and an electronic device. The circuit at least includes a reset circuit, an adjustment circuit, a control circuit, and a storage circuit. The adjustment signal is used to switch the pixel driving signal output by the control circuit between a first operating voltage and a second operating voltage, thereby adjusting the duty cycle of the pixel driving signal, and a PWM driving of full gray levels is achieved by using pixel driving signals with different duty cycles, so as to simplify the circuit complexity, reduce the overall power consumption and heat generation of the circuit.

Description

Technical Field

[0001] The present disclosure relates to the field of display technologies, and particularly to a duty ratio adjustment circuit, a driving method thereof, a display panel, and an electronic device. Background Art

[0002] Pulse Amplitude Modulation (PAM) is the main grayscale driving method for existing display products. With the continuous development of a series of display technologies such as Liquid Crystal Display (LCD), Organic Light-Emitting Diode (OLED), and Quantum Dot Display (QD), the disadvantages of high PAM driving power consumption, large heat generation, and inability to achieve low grayscale display have become increasingly prominent. Therefore, Pulse Width Modulation (PWM) grayscale driving method is introduced on the basis of PAM to improve such problems.

[0003] Currently, the PWM driving method is for full-screen driving, or a fixed duty ratio timing signal is introduced into the pixel driving circuit and combined with PAM driving to achieve low grayscale display. Both of the above two circuit design methods greatly increase the complexity of the driving circuit, which is not conducive to the development of high-tech such as high PPI and narrow borders. At the same time, the problems of high power consumption and large heat generation existing in the PAM driving method itself are not improved, and the complex process will lead to a decrease in yield and further increase in cost. Summary of the Invention

[0004] The purpose of the embodiments of the present disclosure is to provide a duty ratio adjustment circuit, a driving method thereof, a display panel, and an electronic device, so as to solve the problems of high power consumption, large heat generation, complex circuit, and low yield rate caused by the combined use of PAM and PWM driving methods in the prior art.

[0005] Embodiments of the present disclosure adopt the following technical solutions: A duty cycle adjustment circuit for a driving signal, the duty cycle adjustment circuit is connected to a pixel driving circuit, and the duty cycle adjustment circuit at least includes: a reset circuit, an adjustment circuit, a control circuit, and a storage circuit; wherein, a first end of the reset circuit is configured to receive a reset signal, a second end of the reset circuit is configured to output the reset signal to a second end of the storage circuit and a first end of the control circuit, and the reset circuit is configured to reset a voltage applied to the first end of the control circuit based on the reset signal; a first end of the adjustment circuit is configured to receive a first operating voltage, a second end of the adjustment circuit is configured to receive an adjustment signal, a third end of the adjustment circuit is connected to the first end of the control circuit, and the adjustment circuit is configured to adjust a voltage applied to the first end of the control circuit based on the adjustment signal; a second end of the control circuit is configured to receive a second operating voltage, a third end of the control circuit is configured to receive the first operating voltage, a fourth end of the control circuit is configured to receive a control signal, an output end of the control circuit is connected to a third end of the storage circuit and the pixel driving circuit, and the control circuit is configured to receive the first operating voltage according to the control signal, and output the first operating voltage or the second operating voltage as a driving signal from the output end according to the voltage applied to the first end of the control circuit; a first end of the storage circuit is connected to a rated voltage, and the storage circuit is configured to store the reset signal and the first operating voltage or the second operating voltage output from the output end.

[0006] In some embodiments, the reset circuit includes a second transistor. A first pole of the second transistor receives the reset signal. A second pole of the second transistor is connected to a second end of the storage circuit and a first end of the control circuit. A gate of the second transistor is connected to the first pole of the second transistor; The adjustment circuit includes at least a fifth transistor. A first pole of the fifth transistor receives the first operating voltage. A second pole of the fifth transistor is connected to the first end of the control circuit. A gate of the fifth transistor receives the adjustment signal; The control circuit includes at least a first transistor and a third transistor. A gate of the third transistor is connected to the second pole of the fifth transistor and the second pole of the second transistor. A first pole of the third transistor receives the second operating voltage. A second pole of the third transistor and a second pole of the first transistor are both connected to the output terminal. A gate of the first transistor receives the control signal. A first pole of the first transistor receives the first operating voltage; The storage circuit includes at least a first capacitor and a second capacitor. A first pole of the first capacitor is connected to the output terminal. A first pole of the second capacitor is connected to the gate of the third transistor and the second pole of the fifth transistor. A second pole of the first capacitor and a second pole of the second capacitor are both connected to the rated voltage.

[0007] In some embodiments, the adjustment circuit further includes: a fourth transistor. A gate of the fourth transistor is connected to the output terminal. A first pole of the fourth transistor is connected to the second pole of the fifth transistor. A second pole of the fourth transistor is connected to the gate of the third transistor and the second pole of the second transistor.

[0008] In some embodiments, the first transistor, the third transistor, and the fourth transistor are P-type transistors. The second transistor and the fifth transistor are N-type transistors. The first operating voltage is a negative voltage. The second operating voltage is a positive voltage.

[0009] In some embodiments, the first transistor, the third transistor, and the fourth transistor are N-type transistors. The second transistor and the fifth transistor are P-type transistors. The first operating voltage is a positive voltage. The second operating voltage is a negative voltage.

[0010] In some embodiments, both the control signal and the reset signal are pulse width modulation signals, and the control signal and the reset signal have the same period.

[0011] In some embodiments, the voltage value of the adjustment signal is within a first preset range, and the first preset range is determined according to the turn-on threshold of the fifth transistor, the period of the reset signal, the voltage value of the effective level of the reset signal, the turn-on threshold of the third transistor, and the first operating voltage.

[0012] Embodiments of the present disclosure also disclose a driving method for a duty ratio adjustment circuit as described above, including: the reset circuit resets the voltage applied to the first end of the control circuit according to the reset signal; the control circuit outputs the first operating voltage from the output end under the drive of the control signal, and stores the first operating voltage through the storage circuit; the adjustment circuit adjusts the voltage applied to the first end of the control circuit under the drive of the adjustment signal until the second operating voltage is output from the output end, and stores the second operating voltage through the storage circuit.

[0013] Embodiments of the present disclosure also disclose a display panel, which at least includes a pixel driving circuit and a duty ratio adjustment circuit as described above. Among them, the pixel driving circuit at least includes a driving transistor and a light-emitting device; the duty ratio adjustment circuit is connected to the driving transistor so that the driving transistor drives the light-emitting device to emit light based on the driving signal output by the duty ratio adjustment circuit.

[0014] Embodiments of the present disclosure also disclose an electronic device, which at least includes a display panel as described above.

[0015] The beneficial effects of the embodiments of the present disclosure are as follows: The adjustment signal is used to switch the pixel driving signal output by the control circuit between the first operating voltage and the second operating voltage, thereby adjusting the duty ratio of the pixel driving signal, and using pixel driving signals with different duty ratios to achieve PWM driving of full gray levels, so as to simplify the circuit complexity and reduce the overall power consumption and heat generation of the circuit. Description of the Drawings

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments recorded in the present disclosure. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0017] Figure 1 It is a schematic diagram of the duty ratio adjustment circuit in the first embodiment of the present disclosure;

[0018] Figure 2 It is a specific implementation manner of the duty ratio adjustment circuit in the first embodiment of the present disclosure;

[0019] Figure 3 This is another specific implementation of the duty cycle adjustment circuit in the first embodiment of the present disclosure;

[0020] Figure 4 is Figure 2 and Figure 3 the schematic diagram of the simulation result of the duty cycle adjustment circuit shown;

[0021] Figure 5 This is another specific implementation of the duty cycle adjustment circuit in the first embodiment of the present disclosure;

[0022] Figure 6 This is another specific implementation of the duty cycle adjustment circuit in the first embodiment of the present disclosure;

[0023] Figure 7 is Figure 5 and Figure 6 the schematic diagram of the simulation result of the duty cycle adjustment circuit shown;

[0024] Figure 8 This is the flowchart of the driving method of the duty cycle adjustment circuit in the second embodiment of the present disclosure. Specific implementation

[0025] Reference is made herein to the various aspects and features of the present disclosure with reference to the accompanying drawings.

[0026] It should be understood that various modifications can be made to the embodiments claimed herein. Accordingly, the above description should not be regarded as limiting, but merely as exemplifications of the embodiments. Those skilled in the art will envision other modifications within the scope and spirit of the present disclosure.

[0027] The accompanying drawings, which are included in and form a part of this specification, illustrate embodiments of the present disclosure and, together with the general description of the present disclosure given above and the detailed description of the embodiments given below, serve to explain the principles of the present disclosure.

[0028] These and other features of the present disclosure will become apparent from the following description of the preferred forms of the embodiments given as non - limiting examples with reference to the accompanying drawings.

[0029] It should also be understood that, although the present disclosure has been described with reference to some specific examples, those skilled in the art can surely implement many other equivalent forms of the present disclosure, which have the features as claimed and thus are all within the scope of protection defined hereby.

[0030] When combined with the accompanying drawings, the above and other aspects, features, and advantages of the present disclosure will become more apparent in view of the following detailed description.

[0031] Specific embodiments of the present disclosure will be described hereinafter with reference to the accompanying drawings; however, it should be understood that the embodiments claimed are merely examples of the present disclosure and can be implemented in various ways. Well-known and / or repetitive functions and structures are not described in detail to avoid obscuring the present disclosure with unnecessary or redundant details. Therefore, the specific structural and functional details claimed herein are not intended to be limiting, but rather are merely a basis and representative basis for the claims to teach those skilled in the art to use the present disclosure in substantially any suitable detailed structure in a variety of ways.

[0032] This specification may use the phrase "in one embodiment", "in another embodiment", "in yet another embodiment", or "in other embodiments", each of which may refer to one or more of the same or different embodiments according to the present disclosure.

[0033] PAM is the main grayscale driving method for existing display products. With the continuous development of a series of display technologies such as LCD, OLED, and QD, the disadvantages of PAM driving, such as high driving power consumption, large heat generation, and inability to achieve low grayscale display, have become increasingly prominent. Therefore, the PWM grayscale driving method is introduced on the basis of PAM to improve such problems.

[0034] Currently, the PWM driving method is for full-screen driving, or a fixed duty cycle timing signal is introduced into the pixel driving circuit to cooperate with PAM driving to achieve low grayscale display. Both of the above two circuit design methods greatly increase the complexity of the driving circuit, which is not conducive to the development of high-tech such as high PPI and narrow borders. At the same time, the problems of high power consumption and large heat generation existing in the PAM driving method itself are not improved, and the complex process will lead to a decrease in yield and further increase in cost.

[0035] To solve the above problems, the first embodiment of the present disclosure provides a duty cycle adjustment circuit for driving signals. The duty cycle adjustment circuit is connected to the pixel driving circuit to modulate the driving signals generated by the pixel driving circuit to form a PWM signal with an adjustable duty cycle, so that the light-emitting device is lit according to the modulated driving signals to achieve pixel-level full grayscale PWM driving.

[0036] Figure 1 The schematic diagram of the duty cycle adjustment circuit of this embodiment is shown. As Figure 1 shown, the duty cycle adjustment circuit mainly includes a reset circuit 10, an adjustment circuit 20, a control circuit 30, and a storage circuit 40. The control circuit 30 has an output terminal connected to the pixel driving circuit 50. The pixel driving circuit 50 in this embodiment can directly use the same or similar driving circuit as in the prior art and will not be described in detail herein.

[0037] The first end of the reset circuit 10 receives a reset signal HF_Reset, and the second end is connected to the first end of the control circuit 30 and the second end of the storage circuit 40 to output the reset signal. The reset circuit 10 is configured to reset the voltage applied to the first end of the control circuit 30 based on the reset signal.

[0038] The first end of the adjustment circuit 20 receives a first operating voltage V1, the second end receives an adjustment signal Datastep, and the third end is connected to the first end of the control circuit 30. The adjustment circuit 20 mainly adjusts the voltage applied to the first end of the control circuit 30 based on the magnitude of the adjustment signal Datastep. In this embodiment, the voltage value of the adjustment signal Datastep varies continuously within a first preset range. According to the gray scale situation presented by the light emitting device actually required, the voltage applied to the first end of the control circuit 30 can be adjusted by different magnitudes of the adjustment signal Datastep in each lighting cycle.

[0039] The first end of the control circuit 30 is simultaneously connected to the second end of the reset circuit 10, the third section of the adjustment circuit 20, and the second end of the storage circuit 40. The second end receives a second operating voltage V2, the third end receives the first operating voltage V1, the fourth end receives a control signal HF_Input, and its output end HF_Output is connected to the third end of the storage circuit 40 and is connected to the pixel driving circuit 50. The control circuit 30 receives the first operating voltage V1 based on the control signal HF_Input, and outputs the first operating voltage V1 or the second operating voltage V2 as a driving signal according to the voltage condition applied to its first end.

[0040] The first end of the storage circuit 40 is connected to a rated voltage V3, and it is mainly configured to store the reset signal HF_Reset and the first operating voltage V1 or the second operating voltage V2 output by the output end HF_Output to ensure the stability of the driving signal output by the duty cycle adjustment circuit.

[0041] Specifically, the first operating voltage V1 and the second operating voltage V2 in this embodiment are two voltages with different voltage values, and their specific values can be adjusted according to parameters such as the type and turn-on threshold of the driving transistors in the pixel driving circuit 50. Generally, a positive voltage and a negative voltage can be set so that the driving transistors exhibit two states of on and off under the driving of different voltages. When using the duty cycle adjustment circuit provided in this embodiment, the value of the adjustment signal Datastep can be specifically adjusted according to the gray scale situation to be presented by the light-emitting device, so that within one lighting cycle, the voltage applied to the first end of the control circuit 30 gradually changes starting from the reset signal HF_Reset, and after changing to a certain extent, the voltage output from the output end HF_Output is switched from the first operating voltage V1 to the second operating voltage V2, realizing the output of two signals within one lighting cycle, and then forming a PWM signal to control the on and off of the driving transistors. When presenting different gray scales, the value of the adjustment signal Datastep is also different, so that the change amplitude of the voltage applied to the first end of the control circuit 30 is also different, and thus the time for switching from the first operating voltage V1 to the second operating voltage V2 within one lighting cycle is also different, that is, the duty cycle of the driving signal changes, corresponding to the change in the lighting time of the light-emitting device, so that the display device finally presents different gray scales.

[0042] This embodiment uses the adjustment signal to switch the pixel driving signal output by the control circuit between the first operating voltage and the second operating voltage, thereby adjusting the duty cycle of the pixel driving signal, and using the pixel driving signals with different duty cycles to achieve PWM driving of the full gray scale, so as to simplify the circuit complexity, reduce the overall power consumption and heat generation of the circuit.

[0043] Figure 2 Shows a specific implementation manner of the duty cycle adjustment circuit in this embodiment. As Figure 2As shown, the reset circuit 10 mainly includes a second transistor M2. The first pole of the second transistor M2 is used to receive a reset signal HF_Reset, and its second pole is connected to the first end of the control circuit 30 and the second end of the storage circuit 40 to output the reset signal. The gate of the second transistor M2 is connected to its first pole and also inputs the reset signal HF_Reset. The adjustment circuit 20 at least includes a fifth transistor M5. The first pole of the fifth transistor M5 receives a first operating voltage V1, the second pole is connected to the first end of the control circuit 30, and its gate receives an adjustment signal Datastep. The control circuit 30 at least includes a first transistor M1 and a third transistor M3. The gate of the third transistor M3 is connected to the second pole of the fifth transistor M5 and the second pole of the second transistor M2. The first pole of the third transistor M3 receives a second operating voltage V2. The second pole connection of the third transistor M3 and the second pole of the first transistor M1 are both connected to the output terminal HF_Output. The gate of the first transistor M1 receives a control signal HF_Input, and the first pole of the first transistor M1 receives the first operating voltage V1. The storage circuit 40 at least includes a first capacitor C1 and a second capacitor C2. The first pole of the first capacitor C1 is connected to the output terminal HF_Output. The first pole of the second capacitor C2 is connected to the gate of the third transistor M3 and the second pole of the fifth transistor M5. The second poles of the first capacitor C1 and the second capacitor C2 are both connected to a rated voltage V3.

[0044] Specifically, both the reset signal HF_Reset and the control signal HF_Input are PWM signals, and they have the same period. In this embodiment, both the first transistor M1 and the second transistor M2 are digitally triggered transistors, and they form a first-order digital flip-flop to mark the start or end of a lighting cycle. To avoid the damage to the human eye caused by the stroboscopic effect generated by the lighting of the low-frequency PWM signal, in this embodiment, the reset signal HF_Reset and the control signal HF_Input can be defined as high-frequency PWM signals. For example, it can be defined that they are between 5000 Hz and 10000 Hz, and the duration of each lighting cycle is between 200 microseconds (us) and 100 microseconds, so that the light-emitting device is finally lit and extinguished at a higher frequency, avoiding harmful effects on the human eye. Taking the period H of the reset signal HF_Reset and the control signal HF_Input as 100 us as an example, generally speaking, the effective level of the control signal HF_Input represents the start of a lighting cycle, and the effective level of the reset signal HF_Reset can be used to represent the upcoming start of a lighting cycle or mark the end of the previous lighting cycle. Combining the digital triggering characteristics of M1 and M2, the duration of the effective levels of the control signal HF_Input and the reset signal HF_Reset can be set to a short signal. For example, it can be defined that the effective levels in both the control signal HF_Input and the reset signal HF_Reset are levels with a duration of 0.1 us.

[0045] The implementation principle of the duty cycle adjustment circuit will be described below in conjunction with Figure 2 the circuit shown. The value of the signal involved in the adjustment process is only for illustration and can be adjusted according to actual needs during actual use.

[0046] Corresponding to Figure 2 the circuit shown, both the first transistor M1 and the third transistor M3 included in the circuit are P-type transistors, and both the second transistor M2 and the fifth transistor M5 are N-type transistors. At this time, the first operating voltage V1 is a negative voltage, which is represented by VSS in Figure 2 and its value is -8V, while the second operating voltage V2 is a positive voltage, in Figure 2It is represented by VDD, and its value is 8V. The turn-on threshold Vth of the P-type transistor in this embodiment is generally around -1V. That is, when the voltage difference Vgs between the gate voltage and the source voltage of the transistor is less than -1V, the P-type transistor conducts; while the turn-on threshold Vth of the N-type transistor can be set at around 0.6V. That is, when the voltage difference Vgs between the gate voltage and the source voltage of the transistor is greater than 0.6V, the N-type transistor conducts. However, when actually applying voltage to the N-type transistor, the N-type transistor can also conduct when Vgs is slightly less than Vth. But at this time, the N-type transistor is in an incompletely conducting state, and the allowable current is small.

[0047] The high level of the control signal HF_Input is 12V, the low level is -12V, the period H = 100us, and the duty cycle: low level / high level = 0.1us / 99.9us; the high level of the reset signal HF_Reset is 20V, the low level is -12V, the period H = 100us, and the duty cycle: low level / high level = 99.9us / 0.1us; the value range of the adjustment signal Datastep is between -7.45V and -6.7V. Here, Datastep = [-7.45V, -7.4V, -7.3V, -7.2V, -7.1V, -7V, -6.9V, -6.8V, -6.7V], the capacitance value of the first capacitor C1 is 50F, and the capacitance value of the second capacitor C2 is 2pF.

[0048] Before the start of a lighting cycle (during the periodic lighting process, it can also be considered as the last 0.1us of the previous lighting cycle), the HF_Reset signal turns on M2 at high voltage, and the Q point (used to represent the gate voltage of M3 and the second pole voltage of C2) is reset to the high voltage of 20V. At this time, the Vgs of M3 is 20 - 8 = 12V, which is much higher than its Vth, and M3 is in the off state; after the start of this lighting cycle, the HF_Reset signal turns off M2 at low voltage, the HF_Input signal turns on M1 at low voltage, VSS is written into C1, the HF_Output outputs a low voltage signal of -8V, the Datastep voltage is written into the gate of M5, and after M5 is turned on, the Q point starts to discharge. By controlling the magnitude of the saturation current Id of M5, the discharge speed of the Q point is controlled; after a time t, the voltage of the Q point discharges to a certain extent so that the voltage difference between the Q point voltage and VDD (i.e., the Vgs of M3) is less than the Vth of M3, and then M3 is turned on. At this time, VDD is written into C1, and the HF_Output outputs a high voltage signal of 8V; before the end of the current lighting cycle, the HF_Reset signal turns on M2 at high voltage, the voltage of the Q point is reset to 20V, C1 maintains the high voltage, the HF_Output continuously outputs the high voltage signal, and then the next lighting cycle starts. The HF_Input signal turns on M1 at low voltage, VSS is written into C1, and the HF_Output signal outputs the low voltage, repeating the above process.

[0049] In this embodiment, the Datastep voltage is written to the gate of M5. By controlling the magnitude of the saturation current Id of M5, the discharge speed of the Q point is controlled. The time t required for the Q point to discharge to (Q point - VDD), that is, the time when the Vgs voltage is less than the Vth voltage of M3, is the low-voltage duration of the output timing signal HF_Output. By adjusting the magnitude of the Datastep voltage, output timing signals HF_Output with different duty cycles can be obtained.

[0050] Figure 3 Another specific implementation manner of the duty cycle adjustment circuit in this embodiment is shown. The difference between it and Figure 2 the circuit shown is that the adjustment circuit 20 further includes a fourth transistor M4. Its gate is connected to the output terminal HF_Output, its first pole is connected to the second pole of the fifth transistor M5, and its second pole is connected to the gate of the third transistor M3 and the second pole of the second transistor M2. Corresponding to Figure 3 the circuit shown in, the fourth transistor M4 is also a P-type transistor. After the start of the lighting period, VSS is applied to the gate of M4 via M1, M4 is turned on, the Q point starts to discharge towards VSS. After a duration t, M3 is turned on. After VDD is applied to the gate of M4, it is turned off and the Q point stops discharging. Compared with Figure 2 the circuit shown, the setting of M4 prevents the voltage of the Q point from further decreasing to VSS. And the lower the voltage of the Q point, the longer the time required for its reset. The design of M4 can be used to shorten the reset time of the Q point.

[0051] Figure 4 For Figure 2 and Figure 3 the schematic diagram of the simulation results of the duty cycle adjustment circuit shown. As Figure 4 shown, each lighting period is started by the HF_Input signal, the duty cycle is controlled by the magnitude of the Datastep voltage, and the Q point is reset by the HF_Reset signal at the end of the cycle. When Datastep = [-7.45V, -7.4V, -7.3V, -7.2V, -7.1V, -7V, -6.9V, -6.8V, -6.7V], the corresponding duty cycle of HF_Output (high voltage / cycle H) = [36%, 43%, 54%, 62.5%, 69%, 74%, 78.5%, 82%, 84%]. It should be noted that Figure 4The duty cycle shown is determined with the high voltage as the active level. In actual implementation, the low voltage can also be used as the active level, and the corresponding duty cycles are [64%, 57%, 46%, 37.5%, 31%, 26%, 21.5%, 18%, 16%], which specifically depends on the type of driving transistor of the pixel driving circuit connected to HF_Output. Additionally, the values of the above Datastep are only for illustration, and it can actually be any voltage value within the first preset range.

[0052] In some embodiments, the first preset range is determined based on the turn-on threshold of M5, the period of the HF_Reset signal, the voltage value of the active level of the HF_Reset signal (i.e., the voltage value when Q point is reset), the turn-on threshold of M3, and the first operating voltage. Taking the period of the HF_Reset signal as 100 us as an example, when the duty cycle adjustment circuit uses the output high voltage as the active level, the lowest duty cycle can be 0, that is, the Q point does not discharge to meet the condition for M3 to turn on within one lighting period, and at this time HF_Output continuously outputs low voltage; conversely, the highest duty cycle of the high voltage can be 99.99%, that is, the Q point discharges to the first operating voltage instantaneously after M5 turns on, then M3 directly turns on, and HF_Output starts to output high voltage only after 0.1 us. Therefore, when actually determining the upper and lower limits of the first preset range, as long as the above parameters are combined to determine the voltage values of Datastep when the duty cycle of the allowable active level is 0 and 99.99% is sufficient. Although too high or too low voltages can also achieve the same effect, they will cause unnecessary energy consumption.

[0053] In actual implementation, N-type transistors can also be used as the first transistor M1, the third transistor M3, and the fourth transistor M4, and the corresponding second transistor M2 and fifth transistor M5 are implemented using P-type transistors. At this time, the first operating voltage is the positive voltage VDD, and the second operating voltage is the negative voltage VSS. The corresponding circuit diagram is as Figure 5 and Figure 6 shown. The difference between its circuit and the circuits of Figure 2 and Figure 3 is that the connection positions of VDD and VSS are different, and the active levels of the applied PWM signals change from high level to low level, or from low level to high level, but the connection methods of each transistor and capacitor remain unchanged, and the principle of realizing duty cycle adjustment is also the same.

[0054] For example, Figure 5In the shown circuit, the first operating voltage is a positive voltage VDD = 8V, and the second operating voltage is a negative voltage VSS = -8V; HF_Input: high voltage 12V, low voltage -12V, period H = 100us, duty cycle: high voltage / low voltage = 0.1us / 99.9us; HF_Reset: high voltage 8V, low voltage -20V, period H = 100us, duty cycle: high voltage / low voltage = 99.9us / 0.1us; Datastep = [7.1V, 7.15V, 7.2V, 7.25V, 7.3V, 7.35V, 7.4V]; the capacitance value of the first capacitor C1 is 50F, and the capacitance value of the second capacitor C2 is 2pF.

[0055] Before the start of a lighting cycle (during the periodic lighting process, it can also be considered as the last 0.1us of the previous lighting cycle), the low voltage of the HF_Reset signal turns on M2, the Q point is reset to -20V, and M3 is turned off; after the start of this lighting cycle, the high voltage of the HF_Reset signal turns off M2, the high voltage of the HF_Input signal turns on M1, VSS is written into C1, the HF_Output outputs a high voltage signal of 8V, the Datastep voltage is written into the gate of M5, and after M5 is turned on, VDD charges the Q point. By controlling the magnitude of the saturation current Id of M5, the charging speed of the Q point is controlled; after a time duration t, when the voltage difference between the Q point voltage and VSS (i.e., the Vgs of M3) is greater than the Vth of M3, M3 is turned on. At this time, VSS is written into C1, and the HF_Output outputs a low voltage signal of -8V; before the end of the current lighting cycle, the low voltage of the HF_Reset signal turns on M2, the Q point voltage is reset to -20V, C1 maintains a low voltage, the HF_Output continuously outputs a low voltage signal, and then the next lighting cycle starts. The high voltage of the HF_Input signal turns on M1, VDD is written into C1, and the HF_Output signal outputs a high voltage, repeating the above process.

[0056] Figure 6 The shown circuit compared with Figure 5 is additionally provided with M4. After the start of the lighting cycle, VDD is applied to the gate of M4 through M1, M4 is turned on, the Q point starts to charge, after a time duration t, M3 is turned on, and after applying VSS to the gate of M4, it is turned off, and the Q point stops charging. Compared with Figure 5 the shown circuit, the setting of M4 prevents the voltage of the Q point from further rising to VDD, and the higher the voltage of the Q point, the longer the time required for its reset. Using the design of M4 can shorten the reset time of the Q point.

[0057] Figure 7 shows Figure 5 and Figure 6 the schematic diagram of the simulation results of the duty cycle adjustment circuit shown. As Figure 7As shown in the simulation results, each cycle is started by the HF_Input signal, the duty cycle is controlled by the magnitude of the Datastep voltage, and the Q point is reset by the HF_Reset signal at the end of the cycle. When Datastep = [7.1V, 7.15V, 7.2V, 7.25V, 7.3V, 7.35V, 7.4V], the corresponding duty cycle (high voltage / cycle H) = [22.5%, 26.5%, 31.5%, 39%, 48%, 62%, 78%].

[0058] In actual utilization Figure 2 、 Figure 3 、 Figure 5 or Figure 6 When performing PWM driving of full gray levels at the pixel level for any one of the circuits in, M1 and M2 determine the cycle duration H of the output HF_Output signal, that is, the lighting frequency of the light-emitting device, and M3, M4, and M5 determine the duty cycle of the output HF_Output signal; during actual operation, the Gate and Data IC cooperate to write different Data voltages to each pixel, control each pixel to output HF_Output signals with different duty cycles, and pixel-level full gray level PWM driving can be achieved through the HF_Output signal. In addition, the rated voltages connected to C1 and C2 do not change with the change of the transistor type, and they mainly play a voltage stabilizing role, and are both VSS in the circuit of this embodiment.

[0059] In actual implementation, the OLED or LED light-emitting circuit usually consists of a D-TFT (driving transistor) and a light-emitting device. When the D-TFT is turned on, the current drives the light-emitting device to emit light, and when the D-TFT is turned off, the light emission stops. The HF_Output signal is written to the DTFT Gate terminal of the light-emitting circuit, and the on-time of the DTFT can be adjusted by adjusting the duty cycle to achieve gray level display; when the duty cycle is low, the on-time of the DTFT is short, the light-emitting time is short, and a low gray level is displayed; when the duty cycle is high, the on-time of the DTFT is long, the light-emitting time is long, and a high gray level is displayed. It should be noted that the division between the low gray level and the high gray level needs to be determined in combination with the model, parameters, driving transistor parameters of the light-emitting device and actual requirements, etc. Any value between 30 nit and 80 nit can be used as the standard for distinguishing the high and low gray levels, and this embodiment does not limit it here.

[0060] Based on the same inventive concept, the second embodiment of the present disclosure provides a driving method for a duty cycle adjustment circuit provided in the first embodiment, and its flowchart is as Figure 8 shown, mainly including:

[0061] S1, the reset circuit resets the voltage applied to the first end of the control circuit according to the reset signal;

[0062] S2. The control circuit outputs the first operating voltage from the output terminal under the drive of the control signal, and stores the first operating voltage through the storage circuit.

[0063] S3. The adjustment circuit adjusts the voltage applied to the first terminal of the control circuit under the drive of the adjustment signal until the second operating voltage is output from the output terminal, and stores the second operating voltage through the storage circuit.

[0064] In this embodiment, the adjustment signal is used to switch the pixel driving signal output by the control circuit between the first operating voltage and the second operating voltage, thereby adjusting the duty cycle of the pixel driving signal. The PWM driving of the full gray scale is realized by using the pixel driving signals with different duty cycles, so as to simplify the circuit complexity, reduce the overall power consumption and heat generation of the circuit. The specific driving process of the duty cycle adjustment circuit has been described in detail in the first embodiment and will not be repeated in this embodiment.

[0065] The third embodiment of the present disclosure provides a display panel, which at least includes a pixel driving circuit and the duty cycle adjustment circuit provided in the first embodiment of the present disclosure. The pixel driving circuit at least includes a driving transistor and a light emitting device. The output terminal of the duty cycle adjustment circuit is connected to the driving transistor, so that the driving transistor drives the light emitting device to light up based on the driving signal output by the duty cycle adjustment circuit. The type of the driving transistor can be P-type or N-type. No matter which circuit among Figure 2 、 Figure 3 、 Figure 5 and Figure 6 is used for the duty cycle adjustment circuit, it can meet the driving of P-type transistors and N-type transistors, and can be selected according to power consumption requirements and the like during actual implementation.

[0066] The fourth embodiment of the present disclosure provides an electronic device, which should at least include the display panel disclosed in the third embodiment. The electronic device can be a smart phone, a tablet computer and other devices, especially for devices that users will use for a long time. Using high-frequency PWM signals for driving can avoid the damage to the human eye caused by low-frequency PWM signals.

[0067] The above has described multiple embodiments of the present disclosure in detail, but the present disclosure is not limited to these specific embodiments. Those skilled in the art can make various variations and modifications to the embodiments based on the concept of the present disclosure, and these variations and modifications should fall within the scope of protection required by the present disclosure.

Claims

1. A duty cycle adjustment circuit for a driving signal, characterized in that, The duty cycle adjustment circuit is connected to the pixel driving circuit, and the duty cycle adjustment circuit at least includes: a reset circuit, an adjustment circuit, a control circuit, and a storage circuit; wherein, a first end of the reset circuit is configured to receive a reset signal, a second end of the reset circuit is configured to output the reset signal to a second end of the storage circuit and a first end of the control circuit, and the reset circuit is configured to reset a voltage applied to the first end of the control circuit based on the reset signal; a first end of the adjustment circuit is configured to receive a first operating voltage, a second end of the adjustment circuit is configured to receive an adjustment signal, a third end of the adjustment circuit is connected to the first end of the control circuit, and the adjustment circuit is configured to adjust a voltage applied to the first end of the control circuit based on the adjustment signal; a second end of the control circuit is configured to receive a second operating voltage, a third end of the control circuit is configured to receive the first operating voltage, a fourth end of the control circuit is configured to receive a control signal, an output end of the control circuit is connected to a third end of the storage circuit and the pixel driving circuit, and the control circuit is configured to receive the first operating voltage according to the control signal, and output the first operating voltage or the second operating voltage as a driving signal from the output end according to the voltage applied to the first end of the control circuit; a first end of the storage circuit is connected to a rated voltage, and the storage circuit is configured to store the reset signal and the first operating voltage or the second operating voltage output from the output end; the reset circuit includes a second transistor, a first pole of the second transistor receives the reset signal, a second pole of the second transistor is connected to the second end of the storage circuit and the first end of the control circuit, and a gate of the second transistor is connected to the first pole of the second transistor; the adjustment circuit at least includes a fifth transistor, a first pole of the fifth transistor receives the first operating voltage, a second pole of the fifth transistor is connected to the first end of the control circuit, and a gate of the fifth transistor receives the adjustment signal; the control circuit at least includes a first transistor and a third transistor, a gate of the third transistor is connected to a second pole of the fifth transistor and a second pole of the second transistor, a first pole of the third transistor receives the second operating voltage, a second pole of the third transistor and a second pole of the first transistor are both connected to the output end, a gate of the first transistor receives the control signal, and a first pole of the first transistor receives the first operating voltage; the storage circuit at least includes a first capacitor and a second capacitor, a first pole of the first capacitor is connected to the output end, a first pole of the second capacitor is connected to a gate of the third transistor and a second pole of the fifth transistor, and a second pole of the first capacitor and a second pole of the second capacitor are both connected to the rated voltage.

2. The duty cycle adjustment circuit according to claim 1, characterized in that, The adjustment circuit further includes: a fourth transistor, the gate of the fourth transistor is connected to the output terminal, the first pole of the fourth transistor is connected to the second pole of the fifth transistor, and the second pole of the fourth transistor is connected to the gate of the third transistor and the second pole of the second transistor.

3. The duty cycle adjustment circuit according to claim 2, wherein The first transistor, the third transistor, and the fourth transistor are P-type transistors, the second transistor and the fifth transistor are N-type transistors, the first operating voltage is a negative voltage, and the second operating voltage is a positive voltage.

4. The duty cycle adjustment circuit according to claim 2, wherein The first transistor, the third transistor, and the fourth transistor are N-type transistors, the second transistor and the fifth transistor are P-type transistors, the first operating voltage is a positive voltage, and the second operating voltage is a negative voltage.

5. The duty cycle adjustment circuit according to claim 3 or 4, wherein Both the control signal and the reset signal are pulse width modulation signals, and the control signal and the reset signal have the same period.

6. The duty cycle adjustment circuit according to claim 5, wherein The voltage value of the adjustment signal is within a first preset range, and the first preset range is determined according to the turn-on threshold of the fifth transistor, the period of the reset signal, the voltage value of the effective level of the reset signal, the turn-on threshold of the third transistor, and the first operating voltage.

7. A driving method for a duty cycle adjustment circuit according to any one of claims 1 to 6, characterized in that Comprising: The reset circuit resets the voltage applied to the first end of the control circuit according to the reset signal; The control circuit outputs the first operating voltage from the output terminal under the drive of the control signal, and stores the first operating voltage through the storage circuit; The adjustment circuit adjusts the voltage applied to the first end of the control circuit under the drive of the adjustment signal until the second operating voltage is output from the output terminal, and stores the second operating voltage through the storage circuit.

8. A display panel, characterized in that, The display panel at least includes a pixel driving circuit and a duty ratio adjustment circuit according to any one of claims 1 to 6, wherein, The pixel driving circuit at least includes a driving transistor and a light emitting device; The duty ratio adjustment circuit is connected to the driving transistor so that the driving transistor drives the light emitting device to emit light based on the driving signal output by the duty ratio adjustment circuit.

9. An electronic device, characterized in that, At least includes the display panel according to claim 8.

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