Techniques for enhancing system performance after hold loss

Abstract

The present application relates to techniques for enhancing system performance after a loss of retention. A memory system may program a page of memory cells in response to receiving a power outage notification. As part of the programming, the memory system may record an indication of a voltage threshold for the page and be powered off for a period of time during which the memory system may experience a loss of retention. Upon powering on, the memory device may compare the voltage threshold for the page with the indication stored before the power outage and determine a voltage offset for one or more blocks of the memory system. In some cases, the memory system may use the voltage offset to determine a starting block group and may initiate a block group scan to determine a final block group for the one or more blocks.

Description

[0001] Cross-references

[0002] This patent application claims priority to U.S. patent application No. 17 / 646,253, filed by Yeung et al. on December 28, 2021, entitled “TECHNIQUES FOR ENHANCED SYSTEM PERFORMANCE AFTERRETENTION LOSS,” which is assigned to the present assignee and is expressly incorporated herein by reference in its entirety. Technical Field

[0003] The following relates generally to one or more systems for memory and, more particularly, to techniques for enhancing system performance after a retention loss. Background Art

[0004] Memory devices are widely used to store information in various electronic devices, such as computers, user devices, wireless communication devices, cameras, and digital displays. Information is stored by programming memory cells within the memory device to various states. For example, a binary memory cell can be programmed to one of two supported states, often corresponding to a logical 1 or a logical 0. In some instances, a single memory cell can support more than two possible states, and the memory cell can store any of these more than two possible states. To access information stored by a memory device, a component can read or sense the state of one or more memory cells within the memory device. To store information, a component can write or program one or more memory cells within the memory device to a corresponding state.

[0005] There are various types of memory devices, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), 3-dimensional cross-point memory (3D cross-point), NOR and NAND memory devices, etc. Memory devices can be volatile or non-volatile. Unless periodically refreshed by an external power source, volatile memory cells (e.g., DRAM cells) may lose their programmed state over time. Non-volatile memory cells (e.g., NAND memory cells) can maintain their programmed state for extended periods of time even in the absence of an external power source. Summary of the Invention

[0006] A device is described. The device may include: a memory system; and a controller coupled to the memory system and configured to cause the device to: receive a power-off notification from a host system; write a first page of the memory system based at least in part on receiving the power-off notification; power off the memory system based at least in part on writing the first page of the memory system; read the first page of the memory system as part of a power-on operation; and select a first group of memory blocks associated with a first read voltage offset for one or more memory cells of the memory system using voltage shifts of the one or more memory cells based at least in part on reading the first page.

[0007] A non-transitory computer-readable medium storing code is described. The code may include instructions that, when executed by a processor of an electronic device, cause the electronic device to: receive a power-off notification from a host system; write a first page of a memory system based at least in part on receiving the power-off notification; power off the memory system based at least in part on writing the first page of the memory system; read the first page of the memory system as part of a power-on operation; and select a first group of memory blocks associated with a first read voltage offset for one or more memory cells of the memory system using voltage shifts of the one or more memory cells based at least in part on reading the first page.

[0008] A method is described. The method, executable by a memory system, includes receiving a power-off notification from a host system; writing a first page of the memory system based at least in part on receiving the power-off notification; powering off the memory system based at least in part on writing the first page of the memory system; reading the first page of the memory system as part of a power-on operation; and selecting a first group of memory blocks associated with a first read voltage offset for one or more memory cells of the memory system using voltage shifts of the one or more memory cells based at least in part on reading the first page. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 An example of a system supporting techniques for enhancing system performance after a hold loss according to examples disclosed herein is shown.

[0010] Figure 2 An example of a system supporting techniques for enhancing system performance after a hold loss according to examples disclosed herein is shown.

[0011] Figure 3 An example of a graph illustrating an example read distribution according to example support techniques for enhancing system performance after retention loss as disclosed herein.

[0012] Figure 4 An example of a graph illustrating an example read distribution according to example support techniques for enhancing system performance after retention loss as disclosed herein.

[0013] Figure 5 An example of a process flow supporting techniques for enhancing system performance after a hold loss according to examples disclosed herein is shown.

[0014] Figure 6 A block diagram illustrating a memory device supporting techniques for enhancing system performance after retention loss according to examples disclosed herein.

[0015] Figure 7 A flow chart illustrating one or more methods supporting techniques for enhancing system performance after a hold loss according to examples disclosed herein is shown. DETAILED DESCRIPTION

[0016] In some memory systems, retention loss may affect the read performance of the memory system over time. For example, the voltage level stored in one or more memory cells may change over time due to retention loss (for example, charge may leak from the memory cell). Such retention loss may cause system performance to degrade, such as inaccurate reading of memory cells (for example, the voltage may drop below the read threshold voltage, and the memory cell may be incorrectly read as a different logical state), unnecessary triggering of error handling, increased read latency, or any combination thereof. The retention loss amount of one or more memory cells (for example, a memory cell block) may be indicated by a block group. For example, a memory system may have a certain number of block groups (for example, eight block groups) into which memory cell blocks can be classified. Block groups may be numbered, sorted, or otherwise marked so that memory cell blocks in a "small" block group (for example, block group 0, the first block group in a sequence) experience less retention loss than memory cell blocks in a "large" block group (for example, subsequent block groups in a sequence, such as block group 1, block group 2, etc.). In some cases, a memory system may issue a block group scan. For example, a block group scan can be a process of determining the amount of retention loss a block of memory cells has experienced and selecting a block group number for the block of memory cells, the block group number indicating the size or amount of retention loss experienced by the block. In some cases, the block group scan can be a background scan that runs according to a schedule, such as issuing a block group scan every 24 hours, but any schedule or period for block group scans can be used. Thus, the memory system can identify and record the block group numbers for corresponding portions of the memory system. The block group number can indicate retention loss for a portion of the memory system (e.g., the block group number can indicate how much charge has been lost from the memory cell block, a voltage offset used to adjust a read threshold for the memory cell block that can account for retention loss, etc.), and using a voltage offset as part of an access command can improve read performance and accuracy. For example, the memory system can shift the read threshold by a specified voltage offset associated with the block group number during an access operation, which can produce more accurate results for read operations, reduce errors, etc. However, issuing such a block group scan according to a schedule can still result in reduced read performance. For example, if the memory system spends a relatively long time in a powered-off state, the memory system may experience a significant retention loss, but may not perform a block group scan for a relatively long time (e.g., until the next block group scan indicated by the schedule). Thus, the memory system may experience reduced read performance between powering up and issuing a block group scan.

[0017] According to the techniques described herein, a memory system may implement techniques for retention loss recovery that enable the memory system to determine whether a relatively high retention loss has occurred (e.g., due to a relatively long power outage or exposure to high temperatures). For example, as part of a power-on operation, the memory system may determine a voltage offset associated with a reference set of memory cells (e.g., a block, page, etc.). In some examples, the memory system may use the voltage offset to determine (e.g., select) a block group of one or more blocks of memory cells. For example, after receiving a power outage notification, the memory system may program a reference set of memory cells (e.g., a page), such as memory cells associated with a firmware log or a flash translation layer (FTL) table. The memory system may record a voltage indication of the page (e.g., a measure of the voltage distribution), and the memory system may subsequently power down. Upon power-up, the memory system may determine a second voltage of the page (e.g., after the page has experienced retention loss) and compare the second voltage to a voltage indication stored before the power cycle. In some examples, the voltage offset can be the difference between a stored voltage (e.g., a voltage before the memory system is powered off) and a second voltage (e.g., a voltage after the memory system is powered on). In some cases, the memory system can use the voltage offset to select a block group for one or more blocks (e.g., the memory system can select a block group for a read operation without issuing a block group scan). Additionally or alternatively, the memory system can use the voltage offset to determine a starting block group for a block group scan (e.g., dynamically issuing a block group scan in addition to or in lieu of a scheduled block group scan). These techniques can improve system performance by reducing read errors due to, for example, retention losses during the period between powering on the memory system and the next scheduled block group scan, among other advantages.

[0018] First, in reference Figures 1 to 2 Features of the present disclosure are described in the context of systems, devices, and circuits. Figure 3-5 Features of the present disclosure are described in the context of a read profile graph and process flow. Figure 6-7 These and other features of the present disclosure are further illustrated and described in the context of device diagrams and flow charts related to techniques for enhancing system performance after a retention loss.

[0019] Figure 1 An example of a system 100 is shown that supports techniques for enhancing system performance after a retention loss according to examples disclosed herein. The system 100 includes a host system 105 coupled to a memory system 110.

[0020] The memory system 110 may be or include any device or collection of devices, wherein the device or collection of devices includes at least one memory array. For example, the memory system 110 may be or include a universal flash storage (UFS) device, an embedded multimedia controller (eMMC) device, a flash device, a universal serial bus (USB) flash device, a secure digital (SD) card, a solid-state drive (SSD), a hard disk drive (HDD), a dual in-line memory module (DIMM), a small outline DIMM (SO-DIMM), or a non-volatile DIMM (NVDIMM), among other possibilities.

[0021] System 100 may be included in a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, drone, train, car, or other transportation vehicle), an Internet of Things (IoT)-enabled device, an embedded computer (e.g., an embedded computer included in a vehicle, industrial equipment, or a networked business device), or any other computing device that includes memory and processing devices.

[0022] The system 100 may include a host system 105 that may be coupled to a memory system 110. In some instances, this coupling may include an interface with a host system controller 106, which may be an instance of a controller or control component configured to cause the host system 105 to perform various operations according to the examples described herein. The host system 105 may include one or more devices, and in some cases may include a processor chipset and a software stack executed by the processor chipset. For example, the host system 105 may include an application configured to communicate with the memory system 110 or a device therein. The processor chipset may include one or more cores, one or more caches (e.g., memory local to or included in the host system 105), a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a Peripheral Component Interconnect Express (PCIe) controller, a Serial Advanced Technology Attachment (SATA) controller). The host system 105 may use the memory system 110, for example, to write data to the memory system 110 and to read data from the memory system 110. Although Figure 1 One memory system 110 is shown in FIG. 1 , but the host system 105 may be coupled to any number of memory systems 110 .

[0023] The host system 105 can be coupled to the memory system 110 via at least one physical host interface. In some cases, the host system 105 and the memory system 110 can be configured to communicate via the physical host interface using an associated protocol (e.g., to exchange or otherwise convey control, address, data, and other signals between the memory system 110 and the host system 105). Examples of physical host interfaces can include, but are not limited to, a SATA interface, a UFS interface, an eMMC interface, a PCIe interface, a USB interface, a Fibre Channel interface, a Small Computer System Interface (SCSI), a Serial Attached SCSI (SAS), a Double Data Rate (DDR) interface, a DIMM interface (e.g., a DDR-capable DIMM socket interface), an Open NAND Flash Interface (ONFI), and a Low Power Double Data Rate (LPDDR) interface. In some examples, one or more such interfaces can be included in or otherwise supported between the host system controller 106 of the host system 105 and the memory system controller 115 of the memory system 110. In some examples, host system 105 may be coupled to memory system 110 via a respective physical host interface for each memory device 130 included in memory system 110, or via a respective physical host interface for each type of memory device 130 included in memory system 110 (e.g., host system controller 106 may be coupled to memory system controller 115).

[0024] The memory system 110 may include a memory system controller 115 and one or more memory devices 130. The memory devices 130 may include one or more memory arrays of any type of memory cells (e.g., non-volatile memory cells, volatile memory cells, or any combination thereof). Figure 1 , two memory devices 130-a and 130-b are shown in the example of , but the memory system 110 may include any number of memory devices 130. Furthermore, if the memory system 110 includes more than one memory device 130, different memory devices 130 within the memory system 110 may include the same or different types of memory cells.

[0025] The memory system controller 115 can be coupled to and communicate with the host system 105 (e.g., via a physical host interface) and can be an example of a controller or control component configured to cause the memory system 110 to perform various operations according to the examples described herein. The memory system controller 115 can also be coupled to and communicate with the memory devices 130 to perform operations, which can generally be referred to as access operations, at the memory devices 130, such as reading data, writing data, erasing data, or updating data, as well as other such operations. In some cases, the memory system controller 115 can receive commands from the host system 105 and communicate with one or more memory devices 130 to execute such commands (e.g., at a memory array within the one or more memory devices 130). For example, the memory system controller 115 can receive commands or operations from the host system 105 and can convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory devices 130. In some cases, the memory system controller 115 may exchange data with the host system 105 and one or more memory devices 130 (e.g., in response to or otherwise in conjunction with commands from the host system 105). For example, the memory system controller 115 may convert responses associated with the memory devices 130 (e.g., data packets or other signals) into corresponding signals for the host system 105.

[0026] The memory system controller 115 may be configured for other operations associated with the memory device 130. For example, the memory system controller 115 may perform or manage operations such as wear leveling operations, garbage collection operations, error control operations such as error detection operations or error correction operations, encryption operations, cache operations, media management operations, background refresh, health monitoring, and address translation between logical addresses (e.g., logical block addresses (LBAs)) associated with commands from the host system 105 and physical addresses (e.g., physical block addresses) associated with memory cells within the memory device 130.

[0027] The memory system controller 115 may include hardware, such as one or more integrated circuits or discrete components, buffer memory, or a combination thereof. The hardware may include circuitry having dedicated (e.g., hard-coded) logic to perform the operations attributed herein to the memory system controller 115. The memory system controller 115 may be or include a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a digital signal processor (DSP)), or any other suitable processor or processing circuitry.

[0028] The memory system controller 115 may also include local memory 120. In some cases, the local memory 120 may include read-only memory (ROM) or other memory that may store operating code (e.g., executable instructions) that can be executed by the memory system controller 115 to perform the functions attributed herein to the memory system controller 115. In some cases, the local memory 120 may additionally or alternatively include static random access memory (SRAM) or other memory that may be used by the memory system controller 115, for example, for internal storage or computations related to the functions attributed herein to the memory system controller 115. Additionally or alternatively, the local memory 120 may act as a cache for the memory system controller 115. For example, if a memory device 130 is read from or written to, the data may be stored in the local memory 120 and may be available in the local memory 120 for subsequent retrieval or operation (e.g., update) by the host system 105 according to a cache policy (e.g., with reduced latency relative to the memory device 130).

[0029] although Figure 1 The example of the memory system 110 in FIG. 1 has been shown as including a memory system controller 115, but in some cases the memory system 110 may not include a memory system controller 115. For example, the memory system 110 may additionally or alternatively rely on an external controller (e.g., implemented by the host system 105) or one or more local controllers 135, which may each be internal to the memory device 130, to perform the functions attributed herein to the memory system controller 115. In general, one or more functions attributed herein to the memory system controller 115 may in some cases instead be performed by the host system 105, the local controller 135, or any combination thereof. In some cases, a memory device 130 that is at least partially managed by the memory system controller 115 may be referred to as a managed memory device. An example of a managed memory device is a managed NAND (MNAND) device.

[0030] Memory device 130 may include one or more arrays of non-volatile memory cells. For example, memory device 130 may include NAND (e.g., NAND flash) memory, ROM, phase change memory (PCM), select memory, other chalcogenide-based memory, ferroelectric random access memory (RAM) (FeRAM), magnetic RAM (MRAM), NOR (e.g., NOR flash) memory, spin transfer torque (STT)-MRAM, conductive bridging RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), electrically erasable programmable ROM (EEPROM), or any combination thereof. Additionally or alternatively, memory device 130 may include one or more arrays of volatile memory cells. For example, memory device 130 may include RAM memory cells, such as dynamic RAM (DRAM) memory cells and synchronous DRAM (SDRAM) memory cells.

[0031] In some examples, the memory devices 130 may include (e.g., on the same die or within the same package) a local controller 135 that may perform operations on one or more memory cells of the respective memory devices 130. The local controller 135 may operate in conjunction with the memory system controller 115, or may perform one or more functions attributed herein to the memory system controller 115. For example, Figure 1 As shown, memory device 130 - a may include a local controller 135 - a , and memory device 130 - b may include a local controller 135 - b .

[0032] In some cases, memory device 130 may be or include a NAND device (e.g., a NAND flash device). Memory device 130 may be or include a memory die 160. For example, in some cases, memory device 130 may be a package that includes one or more die 160. In some examples, die 160 may be a block of electronic-grade semiconductor cut from a wafer (e.g., a silicon die cut from a silicon wafer). Each die 160 may include one or more planes 165, and each plane 165 may include a corresponding set of blocks 170, wherein each block 170 may include a corresponding set of pages 175, and each page 175 may include a set of memory cells.

[0033] In some cases, the NAND memory device 130 may include memory cells configured to each store one bit of information, which may be referred to as a single-level cell (SLC). Additionally or alternatively, the NAND memory device 130 may include memory cells configured to each store multiple bits of information, which may be referred to as a multi-level cell (MLC) if each is configured to store two bits of information, a triple-level cell (TLC) if each is configured to store three bits of information, a quad-level cell (QLC) if each is configured to store four bits of information, or more generally, a multi-level memory cell. A multi-level memory cell may provide greater storage density relative to an SLC memory cell, but in some cases may involve narrower read or write margins or greater complexity for supporting circuitry.

[0034] In some cases, a plane 165 may refer to a group of blocks 170, and in some cases, parallel operations may occur within different planes 165. For example, parallel operations may be performed on memory cells within different blocks 170, as long as the different blocks 170 are in different planes 165. In some cases, an individual block 170 may be referred to as a physical block, and a virtual block 180 may refer to a group of blocks 170 within which parallel operations may occur. For example, parallel operations may be performed on blocks 170-a, 170-b, 170-c, and 170-d within planes 165-a, 165-b, 165-c, and 165-d, respectively, and blocks 170-a, 170-b, 170-c, and 170-d may be collectively referred to as a virtual block 180. In some cases, a virtual block may include blocks 170 from different memory devices 130 (e.g., blocks in one or more planes including memory device 130-a and memory device 130-b). In some cases, blocks 170 within a virtual block may have the same block address within their respective planes 165 (e.g., block 170-a may be "block 0" of plane 165-a, block 170-b may be "block 0" of plane 165-b, etc.). In some cases, parallel operations in different planes 165 may be subject to one or more restrictions, such as parallel operations on memory cells in different pages 175 that have the same page address within their respective planes 165 (e.g., related to command decode, page address decode circuitry, or other circuitry shared across planes 165).

[0035] In some cases, block 170 can include memory cells organized into rows (pages 175) and columns (e.g., strings, not shown). For example, memory cells in the same page 175 can share (e.g., be coupled to) a common word line, and memory cells in the same string can share (e.g., be coupled to) a common digit line (which can alternatively be referred to as a bit line).

[0036] For some NAND architectures, memory cells can be read and programmed (e.g., written) at a first level of granularity (e.g., at a page granularity level), but can be erased at a second level of granularity (e.g., at a block granularity level). That is, a page 175 can be the smallest unit of memory (e.g., a collection of memory cells) that can be independently programmed or read (e.g., programmed or read simultaneously as part of a single program or read operation), and a block 170 can be the smallest unit of memory (e.g., a collection of memory cells) that can be independently erased (e.g., erased simultaneously as part of a single erase operation). Additionally, in some cases, a NAND memory cell can be erased before it can be rewritten with new data. Thus, for example, in some cases, a used page 175 may not be updated until the entire block 170 containing the page 175 has been erased.

[0037] The system 100 may include any number of non-transitory computer-readable media that support techniques for enhancing system performance after a retention loss. For example, the host system 105, the memory system controller 115, or the memory device 130 may include or otherwise have access to one or more non-transitory computer-readable media that store instructions (e.g., firmware) to perform the functions attributed herein to the host system 105, the memory system controller 115, or the memory device 130. For example, if executed by the host system 105 (e.g., by the host system controller 106), by the memory system controller 115, or by the memory device 130 (e.g., by the local controller 135), such instructions may cause the host system 105, the memory system controller 115, or the memory device 130 to perform one or more associated functions as described herein.

[0038] In some cases, memory system 110 may utilize memory system controller 115 to provide a managed memory system, which may include, for example, one or more memory arrays and related circuitry in combination with a local (e.g., on-die or in-package) controller, such as local controller 135. An example of a managed memory system is a managed NAND (MNAND) system.

[0039] In some cases, the memory system 110 can determine the block group for one or more memory cell blocks 170 at power-up by determining a voltage offset of a reference block 170. For example, after receiving a power-off notification, the memory system can program one or more memory cells of page 175, such as by programming a firmware log or FTL table. As part of programming page 175, the memory system can record an indication of a voltage metric of the one or more memory cells, such as an intermediate voltage or a low voltage, and the memory system 110 can subsequently power down. At power-up, the memory system can determine a voltage metric of page 175 (e.g., after page 175 has experienced a retention loss) and compare the voltage metric to a read threshold indication stored before the power cycle. Using the difference between these two metrics, the memory system 110 can determine a voltage offset. In some cases, the memory system 110 can use the voltage offset to determine the final block group for the block 170 containing the memory cell page 175. Additionally or alternatively, the memory system 110 can use the voltage offset to determine a starting block group for a block group scan. Determining the block groups of memory cell blocks 170 may improve system performance by reducing read errors due to hold losses prior to block group scans issued as part of a block group scan schedule.

[0040] Figure 2 An example of a system 200 that supports techniques for enhancing system performance after a hold loss according to examples disclosed herein is shown. The system 200 may be as described in reference Figure 1 or an example of the system 100 described in its aspects. The system 200 may include a memory system 210 configured to store data received from a host system 205 and to send the data to the host system 205 if requested by the host system 205 using an access command (e.g., a read command or a write command). The system 200 may implement reference Figure 1 Aspects of the described system 100. For example, memory system 210 and host system 205 can be instances of memory system 110 and host system 105, respectively.

[0041] The memory system 210 may include a memory device 240 to store data transferred between the memory system 210 and the host system 205, such as in response to receiving an access command from the host system 205, as described herein. The memory device 240 may include a memory device 240 as described in reference to FIG. Figure 1 For example, memory device 240 may include NAND memory, PCM, self-select memory, 3D cross-point, other chalcogenide-based memory, FERAM, MRAM, NOR (e.g., NOR flash) memory, STT-MRAM, CBRAM, RRAM, or OxRAM.

[0042] The memory system 210 may include a memory controller 230 for controlling the transfer of data directly into and out of the memory devices 240, such as for storing data, retrieving data, and determining memory locations in which data is to be stored and from which data is to be retrieved. The memory controller 230 may communicate with the memory devices 240 directly or via a bus (not shown) using a protocol specific to each type of memory device 240. In some cases, a single memory controller 230 may be used to control multiple memory devices 240 of the same or different types. In some cases, the memory system 210 may include multiple memory controllers 230, such as a different memory controller 230 for each type of memory device 240. In some cases, the memory controller 230 may be implemented as described with reference to FIG. Figure 1 Aspects of the local controller 135 are described.

[0043] The memory system 210 may further include an interface 220 for communicating with the host system 205, and a buffer 225 for temporarily storing data transferred between the host system 205 and the memory device 240. The interface 220, buffer 225, and memory controller 230 may be used to translate data between the host system 205 and the memory device 240, such as shown by data path 250, and may be collectively referred to as data path components.

[0044] Using buffer 225 to temporarily store data during transfers allows data to be buffered while commands are being processed, thereby reducing latency between commands and allowing arbitrary data sizes to be associated with commands. This can also allow bursts of commands to be handled, and once the bursts have ceased, the buffered data can be stored or transmitted (or both). Buffer 225 can include relatively fast memory (e.g., some type of volatile memory, such as SRAM or DRAM), or a hardware accelerator, or both, to allow for rapid storage and retrieval of data to and from buffer 225. Buffer 225 can include a data path switch component for bidirectional data transfer between buffer 225 and other components.

[0045] Temporary storage of data within buffer 225 may refer to storage of data in buffer 225 during the execution of an access command. That is, after the access command is completed, the associated data may no longer be maintained in buffer 225 (e.g., it may be overwritten with data from another access command). Furthermore, buffer 225 may be a non-cacheable buffer. That is, the host system 205 may not read data directly from buffer 225. For example, a read command may be added to a queue without requiring an address to be matched against an address already in buffer 225 (e.g., without requiring a cache address match or lookup operation).

[0046] The memory system 210 may further include a memory system controller 215 for executing commands received from the host system 205 and controlling the data path components when moving data. The memory system controller 215 may be a memory system controller 215 such as that described in reference Figure 1 An example of a memory system controller 115 is depicted. Bus 235 may be used for communication between system components.

[0047] In some cases, one or more queues (e.g., command queue 260, buffer queue 265, and store queue 270) may be used to control the processing of access commands and the movement of corresponding data. This may be beneficial, for example, if the memory system 210 processes more than one access command from the host system 205 in parallel. As an example of a possible implementation, the command queue 260, buffer queue 265, and store queue 270 are depicted at the interface 220, the memory system controller 215, and the storage controller 230, respectively. However, the queues, if used, may be located anywhere within the memory system 210.

[0048] Data transferred between the host system 205 and the memory device 240 may take a different path within the memory system 210 than non-data information (e.g., commands, status information). For example, system components in the memory system 210 may communicate with each other using the bus 235, while data may use the data path 250 via data path components instead of the bus 235. The memory system controller 215 may control how and whether data is transferred between the host system 205 and the memory device 240 by communicating with the data path components via the bus 235 (e.g., using a protocol specific to the memory system 210).

[0049] If the host system 205 transmits an access command to the memory system 210, the command may be received by the interface 220, for example, according to a protocol (e.g., the UFS protocol or the eMMC protocol). Therefore, the interface 220 may be considered the front end of the memory system 210. After receiving each access command, the interface 220 may communicate the command to the memory system controller 215, for example, via the bus 235. In some cases, each command may be added to the command queue 260 by the interface 220 for communication to the memory system controller 215.

[0050] The memory system controller 215 may determine that an access command has been received based on (e.g., using) a communication from the interface 220. In some cases, the memory system controller 215 may determine that an access command has been received by retrieving a command from the command queue 260. After the command has been retrieved from the command queue 260, for example, by the memory system controller 215, the command may be removed from the command queue. In some cases, the memory system controller 215 may cause the interface 220 to remove the command from the command queue 260, for example, via the bus 235.

[0051] After determining that an access command has been received, the memory system controller 215 may execute the access command. For a read command, this may mean obtaining data from the memory device 240 and transferring the data to the host system 205. For a write command, this may mean receiving data from the host system 205 and moving the data to the memory device 240.

[0052] In either case, the memory system controller 215 may use the buffer 225, among other things, for temporary storage of data received from or sent to the host system 205. The buffer 225 may be considered an intermediary for the memory system 210. In some cases, buffer address management (e.g., pointers to address locations in the buffer 225) may be performed by hardware (e.g., dedicated circuitry) in the interface 220, the buffer 225, or the memory controller 230.

[0053] To process a write command received from the host system 205, the memory system controller 215 may first determine whether the buffer 225 has sufficient available space to store the data associated with the command. For example, the memory system controller 215 may determine, for example, via firmware (e.g., controller firmware), the amount of space available within the buffer 225 to store the data associated with the write command.

[0054] In some cases, the buffer queue 265 can be used to control the flow of commands associated with data stored in the buffer 225, including write commands. The buffer queue 265 can include access commands associated with the data currently stored in the buffer 225. In some cases, commands in the command queue 260 can be moved to the buffer queue 265 by the memory system controller 215 and can remain in the buffer queue 265 while the associated data is stored in the buffer 225. In some cases, each command in the buffer queue 265 can be associated with an address at the buffer 225. That is, a pointer can be maintained indicating the location in the buffer 225 where the data associated with each command is stored. Using the buffer queue 265, multiple access commands can be received sequentially from the host system 205, and at least some of the access commands can be processed in parallel.

[0055] If the buffer 225 has sufficient space to store the write data, the memory system controller 215 can cause the interface 220 to transmit an indication of availability (e.g., a "ready to transfer" indication) to the host system 205, for example, according to a protocol (e.g., a UFS protocol or an eMMC protocol). When the interface 220 subsequently receives data associated with a write command from the host system 205, the interface 220 can use the data path 250 to transfer the data to the buffer 225 for temporary storage. In some cases, the interface 220 can obtain the location of the stored data within the buffer 225 from the buffer 225 or the buffer queue 265. The interface 220 can indicate to the memory system controller 215, for example, via the bus 235, whether the data transfer to the buffer 225 has been completed.

[0056] Once the write data has been stored in buffer 225 via interface 220, the data can be transferred from buffer 225 and stored in memory device 240. This can be accomplished using memory controller 230. For example, memory system controller 215 can cause memory controller 230 to retrieve the data from buffer 225 and transfer the data to memory device 240 using data path 250. Memory controller 230 can be considered the back end of memory system 210. Memory controller 230 can indicate to memory system controller 215, for example, via bus 235, that the data transfer to a memory device in memory device 240 has been completed.

[0057] In some cases, storage queue 270 may be used to facilitate the transfer of write data. For example, memory system controller 215 may push a write command from buffer queue 265 (e.g., via bus 235) to storage queue 270 for processing. Storage queue 270 may include an entry for each access command. In some examples, storage queue 270 may additionally include a buffer pointer (e.g., an address) that may indicate where in buffer 225 the data associated with the command is stored, and a storage pointer (e.g., an address) that may indicate the location associated with the data in memory device 240. In some cases, storage controller 230 may obtain the location within buffer 225 from which the data is obtained from buffer 225, buffer queue 265, or storage queue 270. Storage controller 230 may manage the location of stored data within memory device 240 (e.g., for wear leveling, garbage collection, etc.). Entries may be added to storage queue 270, for example, by memory system controller 215. After the transfer of the data is complete, the entry may be removed from the store queue 270 , for example, by the memory controller 230 or the memory system controller 215 .

[0058] To process a read command received from the host system 205, the memory system controller 215 may again first determine whether the buffer 225 has sufficient available space to store the data associated with the command. For example, the memory system controller 215 may determine, for example, via firmware (e.g., controller firmware), the amount of space available within the buffer 225 to store the data associated with the read command.

[0059] In some cases, the buffer queue 265 can be used to assist in buffer storage of data associated with a read command in a similar manner as discussed above with respect to a write command. For example, if the buffer 225 has sufficient space to store the read data, the memory system controller 215 can cause the memory controller 230 to retrieve the data associated with the read command from the memory device 240 and store the data in the buffer 225 for temporary storage using the data path 250. The memory controller 230 can indicate to the memory system controller 215, for example, via the bus 235, whether the data transfer to the buffer 225 has been completed.

[0060] In some cases, storage queue 270 can be used to assist in the transfer of read data. For example, memory system controller 215 can push read commands to storage queue 270 for processing. In some cases, storage controller 230 can obtain the location within memory device 240 from which to retrieve data from buffer 225 or storage queue 270. In some cases, storage controller 230 can obtain the location within buffer 225 to store data from buffer queue 265. In some cases, storage controller 230 can obtain the location within buffer 225 to store data from storage queue 270. In some cases, memory system controller 215 can move commands processed by storage queue 270 back to command queue 260.

[0061] Once the data has been stored in the buffer 225 by the memory controller 230, the data can be transferred from the buffer 225 and sent to the host system 205. For example, the memory system controller 215 can cause the interface 220 to retrieve the data from the buffer 225 using the data path 250 and transfer the data to the host system 205, for example, according to a protocol (e.g., the UFS protocol or the eMMC protocol). For example, the interface 220 can process commands from the command queue 260 and can indicate to the memory system controller 215, for example, via the bus 235, that the data transfer to the host system 205 is complete.

[0062] The memory system controller 215 may execute the received commands in order (e.g., in a first-in, first-out order according to the order of the command queue 260). For each command, the memory system controller 215 may move data corresponding to the command into and out of the buffer 225, as discussed above. The command may remain in the buffer queue 265 while the data is moved into and stored in the buffer 225. If processing of the command is complete (e.g., if data corresponding to an access command has been transferred from the buffer 225), the command may be removed from the buffer queue 265, for example, by the memory system controller 215. If a command is removed from the buffer queue 265, the address where the data associated with the command was previously stored may be used to store data associated with a new command.

[0063] The memory system controller 215 may be further configured for operations associated with the memory device 240. For example, the memory system controller 215 may perform or manage operations such as wear leveling operations, garbage collection operations, error control operations such as error detection operations or error correction operations, encryption operations, cache operations, media management operations, background refresh, health monitoring, and address translation between logical addresses (e.g., LBAs) associated with commands from the host system 205 and physical addresses (e.g., physical block addresses) associated with memory cells within the memory device 240. That is, the host system 205 may issue a command indicating one or more LBAs, and the memory system controller 215 may identify the one or more physical block addresses indicated by the LBAs. In some cases, one or more contiguous LBAs may correspond to non-contiguous physical block addresses. In some cases, the storage controller 230 may be configured to perform one or more of the above operations in conjunction with or in place of the memory system controller 215. In some cases, the memory system controller 215 may perform the functions of the storage controller 230 and the storage controller 230 may be omitted.

[0064] In some cases, the memory system 210 may determine a block group for one or more memory cell blocks of the memory device 240 at power-up, for example, by determining a voltage offset of a reference block using the memory system controller 215. For example, after receiving a power-off notification, the memory system 210 may program one or more memory cells of a page of the memory device 240, such as by programming a firmware log or FTL table. As part of programming the page, the memory system may record an indication of a voltage metric for the page, and the memory system 210 may subsequently power down. At power-up, the memory system 210 may determine a voltage metric for the page (e.g., after the page has experienced a retention loss) and compare the voltage metric to an indication of a voltage metric stored before the power cycle. Using the difference between these two voltage metrics, the memory system 210 may determine a voltage offset. In some cases, the memory system 210 may use the voltage offset to determine a final block group for the block containing the memory cell page. Additionally or alternatively, the memory system 210 may use the voltage offset to determine a starting block group for a block group scan. Determining block groups of memory cell blocks may improve system performance by reducing read errors due to hold losses prior to block group scans issued as part of a block group scan schedule.

[0065] Figure 3 An example of a graph 300 illustrating an example read distribution according to an example disclosed herein supporting techniques for enhancing system performance after a retention loss. The graph 300 may illustrate the distribution of reads by a user as shown in FIG. Figure 1 100 or another system as described herein. For clarity of illustration, graph 300 may include a voltage axis 305 and a magnitude axis 310, although any other metric may be used (e.g., a current axis or a charge axis instead of a voltage axis). In general, graph 300 may illustrate an example distribution 315 of voltages of memory cells in a memory array before and after a certain duration of time in a powered-off state.

[0066] Graph 300 may include distributions 315-a and 315-b. Distribution 315 may illustrate voltage distributions for one or more memory cells (e.g., a page of memory cells) programmed with the same logic state (e.g., a logic 1, 0, or other logic state) before and after a certain duration in a power-off state. For example, distribution 315-a may be an example of a voltage distribution corresponding to a first logic state (e.g., a logic 1 for an SLC memory cell) programmed to the memory cell after receiving a power-off notification but before powering off a memory system containing the memory cell, while distribution 315-b may be an example of a voltage distribution corresponding to the same logic state stored in the memory cell after being in the power-off state for a certain duration.

[0067] Graph 300 may include voltage metrics 320-a and voltage metrics 320-b, which may be examples of a lower threshold, an upper threshold, an average, or a median value of distribution 315, as well as other metric examples. That is, voltage metrics 320 may be metrics associated with corresponding voltage distribution 315 (e.g., voltage metrics 320-a may correspond to distribution 315-a, and voltage metrics 320-b may correspond to distribution 315-b). In some cases, a memory system (e.g., a memory device) may use a read threshold for a read operation. For example, if a sensing component of a memory system detects a voltage below the read threshold, the memory system may read the corresponding memory cell as storing a first logic value (e.g., 0 or 1). Alternatively, if the sensing component detects a voltage above the read threshold, the memory system may read the corresponding memory cell as storing a second logic value (e.g., 1 or 0).

[0068] In some instances, distribution 315-b may shift relative to distribution 315-a due to retention loss (e.g., due to exposure to relatively high temperatures, being in a power-off state for a relatively long period of time, or both). For example, after a certain duration in the power-off state, distribution 315-b may have shifted downward (e.g., the voltage stored in the memory cell may have decreased). That is, a portion of the charge stored in the memory cell may have leaked out of the cell, thereby reducing the stored voltage. In such instances, reading data stored in the memory cell using a read threshold after the certain duration in the power-off state may result in a read error (e.g., due to the shift in distribution 315-b). Therefore, the memory system may determine a voltage offset 325 to apply to read operations performed on the memory cell, thereby improving the accuracy and speed of read commands. For example, the memory system may identify a voltage offset 325 indicating a voltage shift downward from distribution 315-a to distribution 315-b (e.g., the voltage offset may be estimated using a difference between metric 320-a and metric 320-b, such as the average voltage offset of the distribution).

[0069] In some cases, the memory system can use voltage offset 325 to determine a block group from one or more block groups for a memory cell. In some instances, the block group can indicate the size or amount of retention loss experienced by the block. That is, blocks assigned to a "small" block group may have experienced less retention loss and, therefore, be associated with a smaller voltage offset than blocks assigned to a "large" block group. For example, if the memory system identifies a relatively large voltage offset 325, the memory system can assign a block group number associated with a larger retention loss. Therefore, if reading from a memory cell associated with the assigned block group number, the memory system can use a read threshold adjusted by an amount associated with the block group number (e.g., the memory system can shift the read threshold to the left by a value associated with the block group number), which can enable the use of a more accurate read threshold. In other words, the adjusted read threshold can account for the voltage shift and correct any errors that may occur due to erroneously reading the logic states in distribution 315 as different logic states (e.g., some states in the distribution may have voltages that shift below the unadjusted read threshold and, therefore, be erroneously read).

[0070] In some cases, the memory system can identify a voltage shift 325 of the distribution 315 after a certain duration in the power-off state by, for example, comparing the distribution 315-a of a reference memory cell set (e.g., an SLC page) programmed before power-off with the distribution 315-b of the reference memory cell set after power-on. For example, before powering off, the memory system may receive a power-off notification from the host system (e.g., a normal power-off). In response to receiving the power-off notification, the memory system may write to the memory cell page as part of the power-off operation, such as writing or updating a firmware log or FTL table, among other examples. In some examples, the memory cell page may be an example of an SLC page, but may also be another page type (e.g., a multi-level cell (MLC) page, a triple-level cell (TLC) page, a quad-level cell (QLC) page, etc.) or part of a memory system.

[0071] In some cases, as part of writing a page of memory cells, the memory system may also store an indication of voltage metric 320-a. In this case, the memory system may obtain voltage metric 320-b during power-up and compare it to the stored voltage metric 320-a to determine voltage offset 325. Additionally or alternatively, voltage metric 320-a may be determined (e.g., estimated) using characterization data after power-up. For example, the memory system may use data associated with the characterization of the page (or any other reference portion of memory cells used to identify voltage offset 325) to estimate voltage metric 320-a before power-down and use voltage metric 320-a to identify voltage offset 325.

[0072] After power is applied, the memory system may determine a voltage metric 320-b for the page of memory cells, for example, by using a binary search and an erased page check to determine whether the voltage metric 320-b for the page of memory cells is above a threshold. Thus, a voltage offset 325 may be determined by comparing voltage metric 320-a (e.g., the middle voltage of the programmed memory cells before power is applied) with voltage metric 320-b (e.g., the middle voltage of the page after experiencing retention loss).

[0073] The memory system can use the voltage offset 325 (e.g., the voltage offset corresponding to the reference SLC before and after a certain duration in a power-off state) to determine a read threshold for performing a read on the TLC block. That is, the voltage offset 325 of the SLC page can allow for a quick estimation of the voltage offset 325 of the TLC page, for example, using a known relationship between the retention loss of the SLC and the TLC block or characterization data, among other examples.

[0074] In some cases, different voltage metrics 330-a and 330-b (e.g., different from voltage metrics 320-a and 320-b) can be used to determine voltage offset 325. For example, the voltage offset can be determined using the difference between the middle voltage of distribution 315-a and the middle voltage of distribution 315-b. Additionally or alternatively, the voltage offset can be determined using the difference between the low voltage of distribution 315-a and the low voltage of distribution 315-b. In this case, the different voltage metrics 330-a and 330-b (e.g., the low voltage threshold or the middle voltage threshold) can be determined using characterization data or recorded as part of writing to a firmware log or FTL table. In some instances, some combination of metrics can be used to identify voltage offset 325.

[0075] In some cases, the memory system may determine whether the voltage offset 325 meets a threshold. That is, the memory system may determine whether the voltage offset 325 is relatively small (e.g., small enough so as not to significantly cause a read error). If the memory system determines that the voltage offset 325 does not meet the threshold (e.g., the voltage offset 325 is greater than the threshold offset, which may indicate that the voltage offset 325 is relatively large), the memory system may initiate a block group scan on each block in the memory system to retarget the read offset of each block in the memory system. The block group scan may be a process performed by the memory system (e.g., by firmware) to assign block groups to memory cell blocks. In some cases, before performing the block group scan, the memory system may select a block group (e.g., using the voltage offset 325) as the starting block group in the block group scan.

[0076] Using the block group selected using the determined voltage offset 325 can improve the speed and efficiency of the block group scan, for example, by using the block group to jump directly to a larger block group approximation. That is, by using a starting block group (e.g., a small block group, i.e., a block group corresponding to a small retention loss) and iteratively increasing the block group size, the block group scan can begin searching for the final block group for determining the read threshold until the final block group has been determined. Using the block group selected using the determined voltage offset 325 as the starting block group can reduce the iterations performed in the block group scan, thereby reducing system latency and power consumption.

[0077] Additionally or alternatively, the memory system can use the voltage offset 325 to determine the final block group (e.g., without performing a block group scan). For example, the memory system can use characterization data, perform calculations, or a combination thereof. Determining the final block group can reduce system latency and power consumption, for example, by avoiding performing a full block group scan (e.g., until a scheduled block group scan occurs).

[0078] If the memory system determines that the voltage offset 325 meets the threshold, the memory system may delay initiating a block group scan. For example, the memory system may issue a block group scan as part of a block group scan schedule, where the block group scan is issued periodically (e.g., every 24 hours). Issuing a block group scan as part of a block group scan schedule may reduce system latency or processing overhead during the power-up process because, if the voltage offset 325 is small (e.g., meets the threshold), the memory system may accurately read the data stored in the block without having to update the read threshold.

[0079] In some cases, a memory system may perform an access operation (e.g., a read operation) on a block of memory cells using a selected block group in a block to adjust a read threshold. For example, if the voltage of a memory cell is measured and compared to a read voltage, the memory system may adjust (e.g., shift, increase, decrease) the read threshold by an amount indicated by the corresponding block group associated with the block (e.g., the block group selected using voltage offset 325). Adjusting the read voltage may allow the memory system to more accurately sense the logic state stored in the memory cell by allowing the memory system to compensate for any retention loss associated with the block containing the memory cell.

[0080] Figure 4 An example of a graph 400 illustrating an example read distribution according to an example disclosed herein supporting techniques for enhancing system performance after a retention loss. The graph 400 may illustrate the distribution of reads by a user as shown in FIG. Figure 1100 or another system as described herein. Graph 400 may include aspects of graph 300. For example, for clarity of illustration, graph 400 may include voltage axes 405-a and 405-b and magnitude axes 410-a and 410-b, although other metrics may be used (e.g., a current axis or a charge axis instead of a voltage axis), and may also include a distribution 415, which may be as described in reference to FIG. Figure 3 An example of distribution 315 is described.

[0081] In general, graph 400 may illustrate example distributions 415-a and 420-a, respectively, corresponding to a first logic state (e.g., a logic 0 or 1) and a second logic state (e.g., a logic 1 or 0) of a reference set of memory cells (e.g., an SLC memory cell page) before a certain duration in a powered-off state, while distributions 415-b and 420-b may correspond to the first logic state and the second logic state of the SLC memory cell page after a certain duration in a powered-off state and a loss of retention. Furthermore, graph 400 may illustrate distribution 425-a, which may correspond to a logic state (e.g., a logic 0, 1, 2, 3, 4, 5, 6, or 7) of a TLC memory cell page before a certain duration in a powered-off state, while distribution 425-b may correspond to a logic state of the TLC memory cell page after a certain duration in a powered-off state and a loss of retention.

[0082] In some cases, the voltage metric 430 of the SLC memory cell page can be correlated with the voltage metric 430 of the TLC memory cell page. That is, if the SLC block and the TLC block experience similar retention loss, a relationship (e.g., a formula, calculation, equation, etc.) can exist between the voltage metric 430 of the SLC block and the voltage metric 430 of the TLC block. Therefore, by determining the voltage offset 435 of the SLC block before and after a certain duration of time in a powered-off state, the voltage offset 435 of the TLC block can be estimated.

[0083] In some cases, measuring the voltage offset 435 of an SLC cell page can be more efficient (e.g., executes faster, uses fewer computations, consumes less power, etc.) than determining the voltage offset 435 of a TLC cell page. Furthermore, measuring the voltage offset 435 of an SLC cell page can be more accurate than measuring the voltage offset 435 of a TLC cell page, for example, because there are relatively large voltage gaps between states in an SLC block (e.g., larger read margins, larger write margins). Therefore, a memory system can improve system performance by determining the voltage offset 435 of an SLC memory cell page and using the voltage offset 435 of the SLC memory cell page to estimate the voltage offsets 435 of other TLC memory cell blocks in the memory system.

[0084] For example, as referenced Figure 3 As described, a memory system may program a page of SLC memory cells in response to receiving a power outage notification, for example, as part of updating an FTL table or firmware log. As part of programming the page, the memory system may program an indication of a voltage measurement or other characterizing data for the SLC cell page (e.g., an indication of the voltage measurement before the power outage). The memory system may then be powered off and remain in the powered-off state for a certain duration.

[0085] During the power-off state, the memory cells of the memory system may experience a loss of retention (e.g., distributions 415-a and 420-a of the SLC memory cell page may shift down to distributions 415-b and 420-b, and distribution 425-a of the TLC memory cell page may shift down to distribution 425-b). If the memory system is subsequently powered on, the memory system may determine, for example, a voltage shift 435 of distributions 420-a and 420-b.

[0086] The voltage offset 435 can be determined, for example, by using an indication of a voltage metric or other characterization data of the SLC cell page recorded before power is lost. For example, the memory system can measure an indication of a voltage metric of the SLC memory cell page after a retention loss occurs to compare with the indication recorded before power is lost, or otherwise use characterization data of the SLC memory cell page before and after a certain duration in a powered-off state to determine the voltage offset 435 of the SLC memory cell page. In some cases, the voltage offset 435 of the SLC memory cell page can be used to estimate the voltage offset 435 of the TLC memory cell page.

[0087] The memory system may use voltage offsets to select a block group for performing an access operation on a memory system block. In one example, the memory system may use the block group as a starting block group for a block group scan. The memory system may initiate a block group scan to determine the final read level of a block (e.g., SLC, MLC, TLC, QLC block) of the memory system. Figure 3 As discussed, using the starting block group determined using voltage offset 435 can improve system performance. Additionally or alternatively, the memory system can avoid performing a block group scan and instead use the selected block group to determine a final block group for performing access operations on memory system blocks using characterization data or performing calculations.

[0088] In some cases, the voltage offset 435 may be small (eg, less than a threshold). In this case, the memory system performs an access operation on the memory system block using the selected block group without determining the final block group, as shown in FIG. Figure 3In such cases, the memory system may issue block group scans as part of a schedule (e.g., once every hour, every 24 hours, etc.). Issuing block group scans as part of a schedule can improve system performance by, for example, freeing up system resources that would otherwise be used to perform block group scans during power-up.

[0089] Figure 5 An example of a process flow 500 is shown that supports techniques for enhancing system performance after a hold loss according to examples disclosed herein. The process flow 500 may be performed by a memory system (e.g., a reference Figure 1 and 2 For example, process flow 500 may be performed by a memory system or a memory device (or both) (e.g., as described in reference to FIG. Figure 1 The process flow 500 may be performed by a controller (e.g., the memory system controller 115 or the local controller 135) described herein. The process flow 500 may be implemented to reduce latency and power consumption and improve system performance, among other benefits. Aspects of the process flow 500 may be implemented by a controller as well as other components. Additionally or alternatively, aspects of the process flow 500 may be implemented as instructions stored in a memory (e.g., firmware stored in a memory coupled to the memory system controller 115 or the local controller 135). For example, the instructions, if executed by a controller (e.g., the memory system controller 115 or the local controller 135), may cause the controller to perform the operations of the process flow 500. In the following description of the process flow 500, the operations may be performed in an order different from that shown. For example, certain operations may be omitted from the process flow 500, or other operations may be added to the process flow 500.

[0090] At 505, a power outage notification may be received. For example, the host system may transmit the power outage notification to the memory system. In response to receiving the power outage notification, at 510, the first page may be written. For example, the memory system may write the page of memory cells to one or more blocks, such as a firmware log block or an FTL table. In some cases, the one or more blocks may be instances of SLC blocks.

[0091] In some cases, as part of writing the page of memory cells, a first voltage can be measured. For example, in response to the power outage notification received at 505, the memory system can identify (e.g., measure) a first voltage associated with the page of memory cells. The first voltage can be an example of a low voltage or an intermediate voltage. In some examples, the first voltage can be referred to as a voltage metric as described herein. For example, an indication of the first voltage can be written to one or more blocks, such as by the memory system.

[0092] At 515, the memory system can be powered off (e.g., it enters a powered-off state), for example, in response to receiving the power-off notification at 505. In some cases, the memory system can remain in the powered-off state for a duration 520. In some cases, one or more blocks can experience retention loss during the duration 520. In some cases, such as if the memory system undergoes a high-temperature bake, the retention loss can be accelerated or exacerbated.

[0093] At 525, the memory system can be powered on (e.g., out of a power-off state). In some cases, as part of performing the power-on process, at 530, a first page can be read. For example, the memory system can read the first page (e.g., the firmware log or FTL table programmed at 510). As part of reading the first page, the memory system can identify a second voltage associated with the first page. For example, the second voltage can indicate a low voltage or an intermediate voltage.

[0094] In some cases, the memory system may further read one or more memory blocks storing an indication of the first voltage (e.g., the first voltage may be identified after a duration of time in a powered-off state). Additionally or alternatively, the memory system may estimate the first voltage using characterization data associated with the first page. In some cases, the memory system may use a difference between the first voltage and the second voltage to identify a voltage shift.

[0095] At 535, it can be determined (eg, identified) whether the voltage shift satisfies a threshold. For example, the memory system can determine whether the voltage shift identified at 525 is small enough (eg, less than a threshold) so that using the default read voltage does not significantly cause a read error.

[0096] At 540, in response to determining that the voltage offset satisfies the threshold (e.g., the voltage offset is less than the threshold), the one or more memory cells can be read. For example, the memory system can use the first read voltage offset to read the one or more memory cells. That is, the memory system can use the determined first read voltage offset as part of reading the first page at 530 without performing a block group scan or selecting a final block group for performing an access operation (e.g., an access operation to one or more memory blocks (e.g., TLC blocks) different from the memory block containing the first page).

[0097] Additionally or alternatively, at 545, in response to determining that the voltage offset does not satisfy the threshold (e.g., the voltage is greater than the threshold), the first block group can be selected. For example, the memory system can use the voltage shift of one or more memory cells of the memory system to select a first block group associated with a first read voltage offset for the one or more memory cells. In some cases,

[0098] At 550, a block group scan can be initiated. For example, the memory system can initiate a block group scan using the first block group selected at 545 as the starting block group. In some cases, the block group scan can determine a final (e.g., second) block group for one or more blocks of memory cells of the memory system. The final block group can indicate a second read voltage offset for performing an access operation on the one or more blocks of the memory system. Thus, at 555, as part of the access operation, the one or more memory cells can be read using the second read voltage offset, for example, by the memory system.

[0099] Aspects of process flow 500 may be implemented by a controller and other components. Additionally or alternatively, aspects of process flow 500 may be implemented as instructions stored in a memory (e.g., firmware stored in a memory coupled to a memory system). For example, the instructions, when executed by a controller, may cause the controller to perform the operations of process flow 500.

[0100] Figure 6 A block diagram 600 illustrates a memory system 620 that supports techniques for enhancing system performance after a retention loss according to examples disclosed herein. The memory system 620 may be as described in reference Figures 1 to 5 Memory system 620 or its various components may be examples of devices for performing various aspects of the techniques for enhancing system performance after a retention loss as described herein. For example, memory system 620 may include a power manager 625, a write component 630, a read component 635, a block group manager 640, a voltage manager 645, or any combination thereof. Each of these components may communicate with each other directly or indirectly (e.g., via one or more buses).

[0101] The power manager 625 may be configured as or otherwise support means for receiving a power outage notification from a host system. The write component 630 may be configured as or otherwise support means for writing a first page of the memory system based at least in part on receiving the power outage notification. In some examples, the power manager 625 may be configured as or otherwise support means for powering off the memory system based at least in part on writing the first page of the memory system. The read component 635 may be configured as or otherwise support means for reading the first page of the memory system as part of a power-on operation. The block group manager 640 may be configured as or otherwise support means for selecting a first block group associated with a first read voltage offset for one or more memory cells of the memory system based at least in part on reading the first page.

[0102] In some examples, to support powering off the memory system, the power manager 625 may be configured or otherwise support means for powering off the memory system for a duration, wherein selecting the first block group is based at least in part on powering off the memory system for the duration.

[0103] In some examples, the block group manager 640 can be configured to or otherwise support means for initiating a block group scan of the one or more memory cells using the selected first block group. In some examples, the block group manager 640 can be configured to or otherwise support means for identifying a second block group associated with a second read voltage offset for the one or more memory cells based at least in part on initiating the block group scan. In some examples, the read component 635 can be configured to or otherwise support means for reading the one or more memory cells using a read voltage threshold corresponding to the second read voltage offset based at least in part on identifying the second block group.

[0104] In some examples, the read component 635 can be configured as or otherwise support means for reading one or more memory cells using a read voltage threshold corresponding to a first read voltage offset based at least in part on selecting the first block group.

[0105] In some examples, the voltage manager 645 may be configured to or otherwise support means for identifying a first voltage associated with the first page during a first duration associated with writing the first page. In some examples, the voltage manager 645 may be configured to or otherwise support means for identifying a second voltage associated with the first page during a second duration associated with reading the first page. In some examples, the voltage manager 645 may be configured to or otherwise support means for identifying a voltage shift based at least in part on reading the first page, wherein the voltage shift comprises a difference between the first voltage and the second voltage.

[0106] In some examples, to support identifying the first voltage, the voltage manager 645 may be configured as or otherwise support means for measuring the first voltage in response to the power-off notification and writing the first page. In some examples, to support identifying the first voltage, the write component 630 may be configured as or otherwise support means for writing an indication of the first voltage in one or more memory blocks before powering off the memory system. In some examples, to support identifying the first voltage, the read component 635 may be configured as or otherwise support means for reading the one or more memory blocks based at least in part on a power-on operation.

[0107] In some examples, the one or more memory blocks include one or more log blocks or flash translation layer tables.

[0108] In some examples, to support identifying the first voltage, voltage manager 645 may be configured or otherwise support means for estimating the first voltage as part of a power-on operation based at least in part on characterization data associated with the first page.

[0109] In some examples, to support identifying the second voltage, the voltage manager 645 may be configured as or otherwise support means for determining whether the voltage distribution of the first page satisfies a threshold. In some examples, to support identifying the second voltage, the voltage manager 645 may be configured as or otherwise support means for identifying a low voltage of the voltage distribution or an intermediate voltage of the voltage distribution based at least in part on determining whether the voltage distribution satisfies the threshold, where the second voltage comprises the low voltage or the intermediate voltage.

[0110] In some examples, voltage manager 645 may be configured as or otherwise support means for determining whether the voltage shift satisfies a threshold, wherein selecting the first block group is based at least in part on the voltage shift satisfying the threshold.

[0111] Figure 7 A flowchart illustrating a method 700 for supporting techniques for enhancing system performance after a retention loss according to examples disclosed herein is shown. The operations of the method 700 may be implemented by a memory system or components thereof as described herein. For example, the operations of the method 700 may be implemented by a memory system or components thereof as described herein. Figures 1 to 6 The memory system described herein performs. In some examples, the memory system may execute an instruction set to control functional elements of the device to perform the described functions. Additionally or alternatively, the memory system may use dedicated hardware to perform various aspects of the described functions.

[0112] At 705, the method may include receiving a power outage notification from the host system. The operations of 705 may be performed according to examples disclosed herein. In some examples, aspects of the operations of 705 may be performed as described in reference to Figure 6 The power manager 625 described here performs.

[0113] At 710, the method may include writing a first page of a memory system based at least in part on receiving a power outage notification. The operations of 710 may be performed according to examples disclosed herein. In some examples, aspects of the operations of 710 may be implemented as described in reference to Figure 6 The write component 630 described here performs.

[0114] At 715, the method may include powering off the memory system based at least in part on writing the first page of the memory system. The operations of 715 may be performed according to examples disclosed herein. In some examples, aspects of the operations of 715 may be described in detail with reference to Figure 6 The power manager 625 described here performs.

[0115] At 720, the method may include reading a first page of the memory system as part of a power-on operation. The operations of 720 may be performed according to examples as disclosed herein. In some examples, aspects of the operations of 720 may be described by reference to Figure 6 The read component 635 of the description executes.

[0116] At 725, the method may include selecting a first block group associated with a first read voltage offset for one or more memory cells using a voltage shift of one or more memory cells of the memory system based at least in part on reading the first page. The operations of 725 may be performed according to examples as disclosed herein. In some examples, aspects of the operations of 725 may be described by reference to Figure 6 The block group manager 640 described here performs.

[0117] In some examples, an apparatus as described herein may perform one or more methods, such as method 700. The apparatus may include features, circuitry, logic, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for receiving a power outage notification from a host system, writing a first page of a memory system based at least in part on receiving the power outage notification, powering down the memory system based at least in part on writing the first page of the memory system, reading the first page of the memory system as part of a power-on operation, and selecting a first block group associated with a first read voltage offset for the one or more memory cells of the memory system using voltage shifts of the one or more memory cells of the memory system based at least in part on reading the first page.

[0118] In some examples of method 700 and apparatus described herein, powering off the memory system may include operations, features, circuitry, logic, means, or instructions for powering off the memory system for a duration, wherein selecting the first group of blocks may be based at least in part on powering off the memory system for the duration.

[0119] Some examples of method 700 and apparatus described herein may further include operations, features, circuitry, logic, means, or instructions for initiating a block group scan of the one or more memory cells using the selected first block group, identifying a second block group associated with a second read voltage offset for the one or more memory cells based at least in part on initiating the block group scan, and reading the one or more memory cells using a read voltage threshold corresponding to the second read voltage offset based at least in part on identifying the second block group.

[0120] Some examples of method 700 and apparatus described herein may further include operations, features, circuitry, logic, means, or instructions for reading one or more memory cells using a read voltage threshold corresponding to the first read voltage offset based at least in part on selecting the first block group.

[0121] Some examples of method 700 and apparatus described herein may further include operations, features, circuitry, logic, means, or instructions for identifying a first voltage associated with the first page during a first duration associated with writing the first page, identifying a second voltage associated with the first page during a second duration associated with reading the first page, and identifying a voltage shift based at least in part on reading the first page, wherein the voltage shift comprises a difference between the first voltage and the second voltage.

[0122] In some examples of method 700 and apparatus described herein, identifying the first voltage may include operations, features, circuitry, logic, means, or instructions for measuring the first voltage in response to the power off notification and writing the first page, writing an indication of the first voltage in the one or more memory blocks before powering off the memory system, and reading the one or more memory blocks based at least in part on the power on operation.

[0123] In some examples of the method 700 and apparatus described herein, the one or more memory blocks include one or more log blocks or a flash translation layer table.

[0124] In some examples of method 700 and apparatus described herein, identifying the first voltage may include operations, features, circuitry, logic, means, or instructions for estimating the first voltage as part of a power-on operation based at least in part on characterization data associated with the first page.

[0125] In some instances of method 700 and the devices described herein, identifying the second voltage may include operations, features, circuit systems, logic, devices, or instructions for: determining whether the voltage distribution of the first page satisfies a threshold; and identifying a low voltage of the voltage distribution or an intermediate voltage of the voltage distribution based at least in part on determining whether the voltage distribution satisfies the threshold, wherein the second voltage includes the low voltage or the intermediate voltage.

[0126] Some examples of method 700 and apparatus described herein may further include operations, features, circuitry, logic, means, or instructions for determining whether the voltage shift satisfies a threshold, wherein selecting the first block group may be based at least in part on the voltage shift satisfying the threshold.

[0127] It should be noted that the methods described above describe possible embodiments, and that the operations and steps may be rearranged or otherwise modified, and that other embodiments are possible. Additionally, portions from two or more of the methods described may be combined.

[0128] The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some figures may illustrate a signal as a single signal; however, a signal may represent a bus of signals, where the bus may have various bit widths.

[0129] The terms "electronic communication," "conductive contact," "connected," and "coupled" may refer to a relationship between components that supports the flow of electrons between the components. Components are considered to be in electronic communication with each other (or in conductive contact with each other, or connected to each other, or coupled to each other) if there is any conductive path between the components that can support the flow of signals between the components at any time. At any given time, the conductive path between components that are in electronic communication with each other (or in conductive contact or connected or coupled) may be an open circuit or a closed circuit based on the operation of the device that includes the connected components. The conductive path between the connected components may be a direct conductive path between the components, or the conductive path between the connected components may be an indirect conductive path that may include an intermediate component such as a switch, transistor, or other component. In some instances, the flow of signals between the connected components may be interrupted for a period of time, for example, using one or more intermediate components such as a switch or transistor.

[0130] The term "coupling" refers to the condition of moving from an open-circuit relationship between components, in which signals are currently unable to communicate between the components via the conductive paths, to a closed-circuit relationship between the components, in which signals are able to communicate between the components via the conductive paths. If a component, such as a controller, couples other components together, the component initiates a change that allows signals to flow between the other components via the conductive paths that previously did not permit signal flow.

[0131] The term "isolation" refers to a relationship between components where signals are currently unable to flow between them. Components are isolated from one another if an open circuit exists between them. For example, components separated by a switch positioned between them are isolated from one another when the switch is open. If a controller isolates two components, it implements a change that prevents signals from flowing between the components using the conductive path that previously allowed signal flow.

[0132] The terms "if," "when," "based on," or "based at least in part on" are used interchangeably. In some instances, the terms "if," "when," "based on," or "based at least in part on" are interchangeable if they are used to describe a conditional action, a conditional process, or a connection between parts of a process.

[0133] The term "in response to" may refer to a condition or action that occurs at least in part (if not entirely) as a result of a prior condition or action. For example, a first condition or action may occur, and a second condition or action may occur at least in part as a result of the prior condition or action occurring (whether directly after the first condition or action or after one or more other intermediate conditions or actions occur after the first condition or action).

[0134] In addition, the term "directly in response to" or "directly in response to" may refer to a condition or action occurring as a direct result of a previous condition or action. In some instances, a first condition or action may be performed, and a second condition or action may occur directly as a result of a previous condition or action occurring, regardless of whether other conditions or actions occur. In some instances, a first condition or action may be performed, and a second condition or action may occur directly as a result of a previous condition or action occurring, such that no other intermediate conditions or actions occur between the earlier condition or action and the second condition or action, or a limited number of one or more intermediate steps or actions occur between the earlier condition or action and the second condition or action. Unless otherwise specified, any condition or action described herein as being "based on," "at least partially based on," or "in response to" some other step, action, event, or condition may be performed additionally or alternatively (e.g., in alternative instances) "directly in response to" or "directly in response to" such other condition or action.

[0135] The devices discussed herein, including memory arrays, can be formed on a semiconductor substrate such as silicon, germanium, a silicon-germanium alloy, gallium arsenide, gallium nitride, or the like. In some examples, the substrate is a semiconductor wafer. In some other examples, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or a subregion of the substrate can be controlled by doping using various chemical species including, but not limited to, phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate by ion implantation or by any other doping method.

[0136] The switch components or transistors discussed herein may represent field effect transistors (FETs) and include a three-terminal device comprising a source, a drain, and a gate. The terminals may be connected to other electronic components via a conductive material (e.g., a metal). The source and drain may be conductive and may include a heavily doped semiconductor region, such as a degenerate semiconductor region. The source and drain may be separated by a lightly doped semiconductor region or channel. If the channel is n-type (i.e., the majority carriers are electrons), the FET may be referred to as an n-type FET. If the channel is p-type (i.e., the majority carriers are holes), the FET may be referred to as a p-type FET. The channel may be terminated by an insulating gate oxide. Channel conductivity may be controlled by applying a voltage to the gate. For example, applying a positive voltage or a negative voltage to an n-type FET or a p-type FET, respectively, may cause the channel to become conductive. If a voltage greater than or equal to the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "switched on" or "activated." If a voltage less than the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "off" or "deactivated."

[0137] The description set forth herein in conjunction with the accompanying drawings describes example configurations and does not represent all examples that may be implemented or within the scope of the claims. The term "exemplary" as used herein means "serving as an example, instance, or illustration," rather than "preferred" or "superior to other examples." The detailed description includes specific details to provide an understanding of the described technology. However, these technologies can be practiced without these specific details. In some cases, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0138] In the drawings, similar components or features may have the same reference label. Furthermore, various components of the same type may be distinguished by following the reference label with a dash and a second label that distinguishes between the similar components. If only the first reference label is used in the specification, the description applies to any of the similar components having the same first reference label, regardless of the second reference label.

[0139] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored on or transmitted via a computer-readable medium as one or more instructions or codes. Other examples and implementations are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the functions described above may be implemented using software executed by a processor, hardware, firmware, hardwiring, or a combination of any of these. Features implementing the functions may also be physically located at various locations, including being distributed so that portions of the functions are implemented at different physical locations.

[0140] For example, the various illustrative blocks and components described in connection with the disclosure herein may be implemented or performed using a general purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any processor, controller, microcontroller, or state machine. A processor may be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0141] As used herein, "or," as used in a list of items (e.g., a list of items followed by a phrase such as "at least one of" or "one or more of"), included in the claims, indicates an inclusive list, such that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Additionally, as used herein, the phrase "based on" should not be construed as referring to a closed set of conditions. For example, an exemplary step described as "based on condition A" could be based on both condition A and condition B without departing from the scope of this disclosure. In other words, as used herein, the phrase "based on" should be interpreted similarly to the phrase "based at least in part on."

[0142] Computer-readable media include non-transitory computer storage media and communication media including any media that facilitates transferring a computer program from one place to another. Non-transitory storage media can be any available media that can be accessed by a general-purpose or special-purpose computer. By way of example and not limitation, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compact disc (CD) ROM or other optical disc storage devices, magnetic disk storage devices or other magnetic storage devices, or any other non-transitory media that can be used to carry or store the required program code in the form of instructions or data structures and can be accessed by a general-purpose or special-purpose computer, or a general-purpose or special-purpose processor. Also, any connection is appropriately referred to as a computer-readable medium. For example, if a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL) or wireless technologies such as infrared, radio and microwaves are used to transmit software from a website, server or other remote source, the coaxial cable, fiber optic cable, twisted pair, DSL or wireless technologies such as infrared, radio and microwaves are included in the definition of media. Disk and disc, as used herein, include CDs, laser discs, optical discs, digital versatile discs (DVDs), floppy disks, and Blu-ray discs. Disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above are also included within the scope of computer-readable media.

[0143] The description herein is provided to enable one skilled in the art to make or use the present disclosure. Various modifications to the present disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of the present disclosure. Therefore, the present disclosure is not limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A device comprising: Memory system; as well as A controller coupled to the memory system and configured to cause the device to: Receive power outage notification from the host system; writing data and a voltage metric to a first page of the memory system based at least in part on receiving the power outage notification; powering off the memory system based at least in part on writing the first page of the memory system; as part of a power-on operation, reading the first page of the memory system; as well as A first block group associated with a first read voltage offset for one or more memory cells of the memory system is selected using voltage shifts of the one or more memory cells based at least in part on reading the first page of the memory system.

2. The apparatus of claim 1 , wherein the controller is further configured to cause the apparatus to: The memory system is powered off for a duration, wherein selecting the first group of blocks is based at least in part on powering off the memory system for the duration.

3. The apparatus of claim 1 , wherein the controller is further configured to cause the apparatus to: initiating a block group scan of the one or more memory cells using the selected first block group; identifying a second block group associated with a second read voltage offset for the one or more memory cells based at least in part on initiating the block group scan; and Based at least in part on identifying the second block group, the one or more memory cells are read using a read voltage threshold corresponding to the second read voltage offset.

4. The apparatus of claim 1 , wherein the controller is further configured to cause the apparatus to: Based at least in part on selecting the first block group, the one or more memory cells are read using a read voltage threshold corresponding to the first read voltage offset.

5. The apparatus of claim 1 , wherein the controller is further configured to cause the apparatus to: identifying a first voltage associated with the first page of the memory system during a first duration associated with writing to the first page of the memory system; identifying a second voltage associated with the first page of the memory system during a second duration associated with reading the first page of the memory system; as well as The voltage shift is identified based at least in part on reading the first page of the memory system, wherein the voltage shift comprises a difference between the first voltage and the second voltage.

6. The device of claim 5, wherein the controller is further configured to cause the device to: measuring the first voltage in response to the power outage notification and writing the first page of the memory system; Before powering off the memory system, writing an indication of the first voltage in one or more memory blocks; and The one or more memory blocks are read based at least in part on the power-on operation.

7. The apparatus of claim 6, wherein the one or more memory blocks comprise one or more log blocks or a flash translation layer table.

8. The apparatus of claim 5, wherein the controller is further configured to cause the apparatus to: The first voltage is estimated as part of the power-on operation based at least in part on characterization data associated with the first page of the memory system.

9. The apparatus of claim 5, wherein the controller is further configured to cause the apparatus to: determining whether a voltage distribution of the first page of the memory system satisfies a threshold; and A low voltage of the voltage distribution or an intermediate voltage of the voltage distribution is identified based at least in part on determining whether the voltage distribution satisfies the threshold, wherein the second voltage comprises the low voltage or the intermediate voltage.

10. The device of claim 1, wherein the controller is further configured to cause the device to: A determination is made as to whether a voltage shift satisfies a threshold, wherein selecting the first block group is based at least in part on the voltage shift satisfying the threshold.

11. A non-transitory computer-readable medium storing code comprising instructions that, when executed by a processor of a memory system, cause the memory system to: Receive power outage notification from the host system; writing data and a voltage metric to a first page of the memory system based at least in part on receiving the power outage notification; powering off the memory system based at least in part on writing the first page of the memory system; as part of a power-on operation, reading the first page of the memory system; as well as A first block group associated with a first read voltage offset for one or more memory cells of the memory system is selected using voltage shifts of the one or more memory cells based at least in part on reading the first page of the memory system.

12. The non-transitory computer-readable medium of claim 11 , wherein the instructions, when executed by the processor of the memory system, further cause the memory system to: The memory system is powered off for a duration, wherein selecting the first group of blocks is based at least in part on powering off the memory system for the duration.

13. The non-transitory computer-readable medium of claim 11 , wherein the instructions, when executed by the processor of the memory system, further cause the memory system to: initiating a block group scan of the one or more memory cells using the selected first block group; identifying a second block group associated with a second read voltage offset for the one or more memory cells based at least in part on initiating the block group scan; as well as Based at least in part on identifying the second block group, the one or more memory cells are read using a read voltage threshold corresponding to the second read voltage offset.

14. The non-transitory computer-readable medium of claim 11 , wherein the instructions, when executed by the processor of the memory system, further cause the memory system to: Based at least in part on selecting the first block group, the one or more memory cells are read using a read voltage threshold corresponding to the first read voltage offset.

15. The non-transitory computer-readable medium of claim 11, wherein the instructions, when executed by the processor of the memory system, further cause the memory system to: identifying a first voltage associated with the first page of the memory system during a first duration associated with writing to the first page of the memory system; identifying a second voltage associated with the first page of the memory system during a second duration associated with reading the first page of the memory system; as well as The voltage shift is identified based at least in part on reading the first page of the memory system, wherein the voltage shift comprises a difference between the first voltage and the second voltage.

16. The non-transitory computer-readable medium of claim 15, wherein the instructions, when executed by the processor of the memory system, further cause the memory system to: measuring the first voltage in response to the power outage notification and writing the first page of the memory system; Before powering off the memory system, writing an indication of the first voltage in one or more memory blocks; and The one or more memory blocks are read based at least in part on the power-on operation.

17. The non-transitory computer-readable medium of claim 16, wherein the one or more memory blocks comprise one or more log blocks or a flash translation layer table.

18. The non-transitory computer-readable medium of claim 15, wherein the instructions, when executed by the processor of the memory system, further cause the memory system to: The first voltage is estimated as part of the power-on operation based at least in part on characterization data associated with the first page of the memory system.

19. The non-transitory computer-readable medium of claim 15, wherein the instructions, when executed by the processor of the memory system, further cause the memory system to: determining whether a voltage distribution of the first page of the memory system satisfies a threshold; and A low voltage of the voltage distribution or an intermediate voltage of the voltage distribution is identified based at least in part on determining whether the voltage distribution satisfies the threshold, wherein the second voltage comprises the low voltage or the intermediate voltage.

20. The non-transitory computer-readable medium of claim 11, wherein the instructions, when executed by the processor of the memory system, further cause the memory system to: A determination is made as to whether a voltage shift satisfies a threshold, wherein selecting the first block group is based at least in part on the voltage shift satisfying the threshold.

21. A method performed by a memory system, comprising: Receive power outage notification from the host system; writing data and a voltage metric to a first page of the memory system based at least in part on receiving the power outage notification; powering off the memory system based at least in part on writing the first page of the memory system; as part of a power-on operation, reading the first page of the memory system; as well as A first block group associated with a first read voltage offset for one or more memory cells of the memory system is selected using voltage shifts of the one or more memory cells based at least in part on reading the first page of the memory system.

22. The method of claim 21 , wherein powering off the memory system comprises: The memory system is powered off for a duration, wherein selecting the first group of blocks is based at least in part on powering off the memory system for the duration.

23. The method of claim 21, further comprising: initiating a block group scan of the one or more memory cells using the selected first block group; identifying a second block group associated with a second read voltage offset for the one or more memory cells based at least in part on initiating the block group scan; as well as Based at least in part on identifying the second block group, the one or more memory cells are read using a read voltage threshold corresponding to the second read voltage offset.

24. The method of claim 21, further comprising: Based at least in part on selecting the first block group, the one or more memory cells are read using a read voltage threshold corresponding to the first read voltage offset.

25. The method of claim 21, further comprising: identifying a first voltage associated with the first page of the memory system during a first duration associated with writing to the first page of the memory system; identifying a second voltage associated with the first page of the memory system during a second duration associated with reading the first page of the memory system; as well as The voltage shift is identified based at least in part on reading the first page of the memory system, wherein the voltage shift comprises a difference between the first voltage and the second voltage.

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