A fast offline verification method for wireless communication codec

Abstract

The application provides a wireless communication codec offline verification method, comprising the following steps: S1, converting frame data of a tag response into binary code data stream to be transmitted by the tag; S2, performing Miller2 coding on the binary code s_bit of the tag frame data obtained in S1; S3, coding s_miller2_code_final generated in S2 according to an ADC sampling rate and a bit width; and S4, writing the s_adc_idata array generated in S3 into a text through a file writing function fprintf. The application saves tag response data generated according to a certain rule into a text by using Matlab, and simulates the interaction between the generated text data and the tag information, which greatly accelerates the code debug time and the board debug time, and the coding mode and the link rate data can also be quickly generated, and the code coverage and the function coverage are obviously improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of wireless communication codec verification, and particularly relates to a fast offline verification method of wireless communication codec. BACKGROUND

[0002] When using FPGA devices as codec devices in a wireless communication system, in order to verify the correctness of the logic code development as soon as possible, a system simulation platform is generally built in Modelsim to do front-end simulation and quickly verify the accuracy of the code development. However, there is a key problem in building a simulation platform, that is, where does the downlink data come from, which has been puzzling developers. The commonly used method is to use a signal generator to generate a modulated signal according to the coding rules required by the wireless communication protocol (such as ISO18000-63), input the signal from the circulator, and save the data after the signal is sampled by the phase-locked loop and ADC into a text file, and finally load the saved data into the Modelsim simulation platform for logic code verification. However, this method has the problem that the use of a signal generator to generate a modulated signal is complicated to configure, is not convenient for changes in coding rules and link rates, the coverage of the logic project can only reach a small part, and it is difficult to find a development board with the same specifications and models as the project design requirements (with the same specifications and models of ADC and clock) before the board is launched. SUMMARY

[0003] For the convenience of the description of the present method, first we need to clarify two concepts:

[0004] First, all tag encoding methods are based on counting the state changes of the tag within a certain time interval, or based on the frequency of the state changes of the tag, so that we do not need to care about the actual received superimposed signal which is stronger or weaker compared to the original antenna signal, but focus on the number or frequency of the actual intensity changes. Therefore, all tag encoding schemes are variations of frequency shift keying (FSK), where the frequency refers to the baseband frequency of the tag rather than the carrier frequency. Therefore, Miller2, Miller4 and Miller8 are further modulated to 2, 4 or 8 subcarriers based on the Miller encoded data, which can be further understood as for a symbol period, the Miller encoding period is 1 Tc carrier, Miller2 is 2 (1 / 2*Tc) carriers, and so on.

[0005] Second, the information (frame data) transmitted by the sender and receiver in wireless communication generally includes three components: frame flag area, user data area and check bit area. The frame flag is used to generate a sampling pulse sequence strictly synchronized with the received code elements, so as to determine the integration interval of each code element and the sampling decision time, and also to determine the start of a frame of data. The check bit usually uses the CRC algorithm with stronger error detection capability to facilitate the receiver to verify the integrity of the user data. In different communication protocols, the user data area is further split into various field structures to represent specific meanings. For example, in the ISO18000-63 standard, the user data area is divided into a 1-bit data header, a variable number of storage area data, and a 16-bit random number. The 1-bit data header indicates the success or failure of this transaction, and the 16-bit random number is used to verify the legitimacy of the sender's identity in this transaction.

[0006] Therefore, the present application aims to provide a fast offline verification wireless communication encoding and decoding method.

[0007] To solve the above technical problems, the technical scheme adopted by the present application is as follows: a fast offline verification wireless communication encoding and decoding method, comprising the following steps:

[0008] S1: According to the wireless communication protocol (such as ISO18000-63), use Matlab tool to convert the frame data of the tag response into the binary code data stream to be sent by the tag. The purpose of step S1 is to convert the frame data of the tag response into the binary code data stream to be sent by the tag, which specifically includes the following steps:

[0009] S11: Define an array s_tag_code_header to store 23-bit frame flags, and the receiver uses the frame flags to obtain the sampling pulse sequence of the received code elements, and uses the frame flags as the start of a frame of data.

[0010] S12: Define an array s_tag_code_data to store the data header, storage area data and random number of the user data area. The 1-bit data header indicates whether the transaction data is successful. The 16-bit random number is used to verify the legitimacy of the sender's identity. Finally, the data header, storage area data and random number are calculated using the CRC16 calculation module according to the flow and state transition table of the CRC16 calculation module, and a CRC16 value is calculated using verilog to develop a CRC16 module, and the CRC16 value is appended to the end of the s_m2_code_data array.

[0011] S13: Merge s_tag_code_header and s_tag_code_data into an array, and convert into binary numbers using the hex2bin function and store into the s_array array. Since the elements of the s_array array are of type char, each char type element in the s_array array needs to be converted into a double type and stored in the s_bit array.

[0012] S2: Miller encode the tag frame data binary code s_bit obtained in S1. The steps of Miller2 encoding are as follows:

[0013] S21: Miller encode the data in the s_bit array, set four sample value arrays, s1=[1,1], s2=[1,0], s3=[0,1], s4=[0,0], and the initial state is defined as state=1, then perform encoding according to the state transition table, and the encoded data is s_miller_code.

[0014] S22: Modulate each element in the s_miller_code array to 2 carriers. To avoid the multiplication of the subcarrier and the symbol 0 being 0, and to achieve the effect of phase inversion, -1 is used instead of the occurrence of symbol 0. Therefore, the length of the Miller code is first calculated, which can be achieved by setting a loop function and appending the array elements:

[0015] s_miller2_carrier=[s_miller2_carrier,1,-1].

[0016] For the s_miller_code array, the same method is used to achieve the appending of the array elements by setting a loop function: when the element is 1, s_miller2_code=[s_miller2_code,1,1]; when the element is 0, s_miller2_code=[s_miller2_code,-1,-1].

[0017] S23: The final result of Miller2 encoding s_miller2_code_final is equal to the dot product of s_miller2_code and s_miller2_carrier.

[0018] S3: Encode s_miller2_code_final obtained in S2 according to the ADC sampling rate and bit width. The purpose of this process is to encode s_miller2_code_final generated in S2 according to the sampling rate and bit width of the ADC device. The specific steps are as follows:

[0019] S31: Sampling rate coding, for example, the label reverse rate 320K required in the protocol standard, the time of 1 symbol Tb=1 / 320 / 2 us; the sampling clock of the ADC is 26Mhz, Ts=38.46ns, therefore, the data of s_miller2_code_final is first expanded according to the sampling time, the number of expansion is N=round(Tb*1000 / Ts), for the element 1 in the s_miller2_code_final array, the expansion is replaced according to ones(1, N), and the element -1 is replaced according to zeros(1, N). The data after sampling rate coding is stored in the digit_fill_data array.

[0020] S32: Bit width coding, each element in the array digit_fill_data after sampling expansion is coded according to the bit width (n bit) of the ADC. The coding is according to the complement rule as follows: the element is 1, the coding is 2^(n-1)-1; the element is 0, the coding is 2^(n-1), and is stored in the array s_adc_idata.

[0021] S4: The data in the s_adc_idata array is stored as a text by using the built-in functions fopen, fprintf and fclose in Matlab, as a stimulus source of Modelsim.

[0022] After step S4, there is S5, mainly loading the stimulus source file to verify the coding and decoding module in the logic project, solving the bug existing in the code. Moreover, it can be quickly adjusted to any one of FM0 coding, Miller2 coding, Miller4 coding and Miller8 coding, verifying the code coverage and functional coverage.

[0023] S5: In the Modelsim system simulation, the text is loaded into the simulation platform through the data_read_into module, not only the logic coding and decoding module can be debugged, the bug existing in the code can be solved, but also the coding mode (FM0, Miller2, Miller4, Miller8) and the link rate (40K, 80K, 160K, 320K, 640K) can be conveniently adjusted, and the code coverage and functional coverage of the logic project are improved.

[0024] In the application, preferably, the coding of the label is FM0 and Miller coding, and the Miller coding is divided into Miller2 coding, Miller4 coding and Miller8 coding according to the number of subcarriers in a symbol period.

[0025] The application has the advantages and positive effects that: the example of the application stores the frame data of the label to be sent according to the frame mark, user data and CRC16 check into an array according to the ISO 18000-63 protocol by using the Matlab tool, and converts the data in the array into Miller2 data s_miller2_code_final, further encodes the s_miller2_code_final array according to the characteristics of the ADC device, and finally saves the result as a text. The FPGA simulation platform of the ISO18000-63 protocol is built in Modelsim, the text data is loaded into the simulation platform through the text reading module (data_read_into), the information interaction between the reader and the label is simulated, not only the correctness of the logic engineering decoding module is verified, but also the encoding mode (FM0, Miller2, Miller4, Miller8) and the link rate (40K, 80K, 160K, 320K, 640K) can be conveniently adjusted, and the code coverage and the function coverage of the logic engineering are improved. Thus, the logic code development and simulation verification of each module can be carried out at the beginning of the project, the code debug time and the backboard debugging time are greatly shortened, and the product market time is improved. BRIEF DESCRIPTION OF DRAWINGS

[0026] The accompanying drawings are included to provide a further understanding of the application, and constitute a part of the specification, illustrate the application, and are used to explain the application together with the embodiments of the application, and do not constitute a limitation on the application. In the drawings:

[0027] Figure 1 is a wireless communication system block diagram of the prior art;

[0028] Figure 2 is a flowchart of a fast offline verification wireless communication encoding and decoding method of the application;

[0029] Figure 3 is a structure diagram of the tag response data (frame data) of the fast offline verification wireless communication encoding and decoding method of the application;

[0030] Figure 4 is Figure 3 the data structure diagram of the user data area in

[0031] Figure 5 is a CRC16 calculation flowchart of the fast offline verification wireless communication encoding and decoding method of the application;

[0032] Figure 6 is a CRC16 calculation state transition diagram of the fast offline verification wireless communication encoding and decoding method of the application;

[0033] Figure 7 is a state transition table of Miller encoding of a fast offline verification wireless communication encoding and decoding method of the present application;

[0034] Figure 8 is a state transition diagram of Miller encoding of a fast offline verification wireless communication encoding and decoding method of the present application;

[0035] Figure 9 is a CRC calculation result simulation diagram of a fast offline verification wireless communication encoding and decoding method of the present application;

[0036] Figure 10 is a Miller2 encoding result diagram of a fast offline verification wireless communication encoding and decoding method of the present application;

[0037] Figure 11 is a tag response data loading simulation platform diagram of a fast offline verification wireless communication encoding and decoding method of the present application;

[0038] Figure 12 is Figure 11 an amplification schematic diagram. DETAILED DESCRIPTION

[0039] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments of the present application. Based on the embodiments in the present application, all the other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application.

[0040] It should be noted that when a component is referred to as being “fixed” to another component, it can be directly on the other component or there can be intervening components. When a component is referred to as being “connected” to another component, it can be directly connected to the other component or there can be intervening components. When a component is referred to as being “disposed on” another component, it can be directly on the other component or there can be intervening components. The terms “vertical”, “horizontal”, “left”, “right”, and similar terms as used herein are for purposes of description only.

[0041] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description herein is for describing particular embodiments only and is not intended to be limiting of the application. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0042] In wireless communication systems, when using FPGA devices as codecs, a system simulation platform is typically built on Modelsim for front-end simulation to quickly verify the correctness of the logic code. However, a key issue arises when building this simulation platform: the downlink... Figure 1 The origin of the signal link data (represented by the thick line) has long been a challenge for developers. A common method is to use a signal generator to generate a modulated signal according to the encoding rules required by wireless communication protocols (such as ISO 18000-63). This signal is then input from a circulator, passes through a phase-locked loop, and the data sampled by an ADC is saved as text. Finally, the saved data is loaded into the Modelsim simulation platform for logic code verification. However, this approach has drawbacks: using a signal generator to generate the modulated signal is cumbersome to configure, makes it difficult to change encoding rules and link rates, and limits the coverage of logic engineering. Furthermore, it is difficult to find a development board (with the same specifications and model of ADC and clock) that meets the project design requirements before deployment.

[0043] This invention provides a fast offline verification method for wireless communication codecs (alternative) Figure 1 The portion shown in the dashed box aims to enable the development and simulation verification of the logic code for each module at the beginning of the project, including the following steps (such as...). Figure 2 and Figure 3 (as shown)

[0044] S1: Convert the tag's response frame data into a binary code data stream that the tag will send. The frame data consists of three parts: a frame flag area, a user data area, and a check bit area. The frame flag is used to facilitate the receiver in generating a sampling pulse sequence that is strictly synchronized with the received symbols. It determines the integration interval and sampling decision time for each symbol and can also be used to determine the start of a frame. The check bit usually uses the CRC algorithm, which has stronger error detection capabilities, to facilitate the receiver in verifying the integrity of the user data (e.g., ...). Figure 3 (As shown)

[0045] S2: Perform Miller2 encoding on the binary code s_bit of the tag frame data obtained in S1.

[0046] S3: Encode the Miller2 encoded data generated in S2 according to the ADC sampling rate and bit width.

[0047] S4: Store the data in the s_adc_idata array generated in S3 as text and use it as the stimulus source for Modelsim.

[0048] This embodiment uses the ISO 18000-63 wireless communication protocol as an example, assuming the tag's response data must meet FM0 encoding or Miller encoding. Taking the data header 1'b0 and the storage area data...

[0049] ["3578","6297","3410","2819","8671","369c"], the random number is 16'h1BC0, and the data process required by the user data description generation protocol rule is shown in the table. Figure 4 As shown in the table, in the embodiment, CRC16 calculation is performed on the data header, the storage area data, and the random number, and the calculation result is appended after the tag user area data to obtain the tag frame data to be converted. Figure 5 As shown in the table, in the embodiment, CRC16 calculation is performed on the data header, the storage area data, and the random number, and the calculation result is appended after the tag user area data to obtain the tag frame data to be converted.

[0050] In the embodiment of CRC16 calculation, the data is read from the text and stored in the DPRAM by the text reading module. After all the data is written into the DPRAM, the CRC16 calculation state machine is triggered to work. First, when start=1, pre=1, load=1, and data=1'b0 in S0 state, pre=0, load=0 in S1 state, and when bit_cnt=1, the state machine jumps to S2, data=16'h3578, load=1. bit_cnt is set to the corresponding length according to the length of the loaded data. When the state is S3, the last data 16'h369C in the user area is read, and the state jumps to S4. In S4 state, the CRC16 result 16'h8E2E is calculated. Figure 9 As shown in the table.

[0051] In the embodiment, further, the step S1 specifically includes the following steps:

[0052] S11: define an array s_tag_code_header to store 23-bit frame marks, and the receiver uses the frame marks to obtain the sampling pulse sequence of the received code elements, and uses the frame marks as the start of a frame of data. The frame marks are fixed 16 0s and 7'b010111, that is, s_tag_code_header=[zeros(1,16),0,1,0,1,1,1].

[0053] S12: calculate the length s_len of the data s_tag_code_data=["3578","6297","3410","2819","8671","369c", "8E2E"], and then dec2bin(hex2dec(s_tag_code_data(i)),16)

[0054] The cycle converts the hexadecimal data into binary characters, writes the binary characters into an array s_array, concatenates the preamble s_tag_code_header and a 1-bit header, and finally stores the complete baseband encoding data into s_whole_array. The 1-bit header indicates whether the transaction data is successful. The 16-bit random number is used to verify the legitimacy of the sender's identity by the receiver. Finally, the data header, the storage area data, and the random number are calculated according to the CRC16 calculation module flow and state transition table (as shown in Figure 5 and Figure 6 The CRC16 module is developed using verilog, and the corresponding CRC16 value (as shown in Figure 9 is appended to the end of the s_m2_code_data array. Since the data stored now is of the char type and cannot be used for subsequent calculations, the char type needs to be converted to the double type, and the str2num function is used to convert all characters of s_whole_array to the double type and write them into s_bit;

[0055] In the embodiment, further, step S2 is to perform Miller2 encoding on the binary code s_bit generated in S1, and specifically includes the following steps.

[0056] S21: Miller encoding is performed on each element of the s_bit array, and four sample value arrays are set according to the state transition table (as shown in Figure 7 a coordinate axis diagram) of Miller encoding, s1=[1,1]; s2=[1,0]; s3=[0,1]; s4=[0,0], and the initial state state=1 is set according to the state transition table shown in Figure 8 . s_bit(i) is judged. If it is 0, the state jumps to state=4, i=i+1, and s4 is appended to s_miller_code. If it is 1, the state jumps to state=2, i=i+1, and s2 is appended to s_miller_code. When state=2, s_bit(i) is judged. If it is 0, the state machine jumps to state=4, i=i+1, and s4 is appended to s_miller_code. If it is 1, the state machine jumps to state=3, i=i+1, and s3 is appended to s_miller_code. Similarly, the encoded data of state=3 and state=4 is written into s_miller_code.

[0057] S22: modulate each element in s_miller_code array to 2 carriers, to avoid the multiplication of subcarrier and symbol 0 to be 0, and to achieve the effect of phase inversion, so use -1 instead of the occurrence of symbol 0. Therefore, the length of Miller code is calculated first, which can be realized by setting a loop function and appending array elements:

[0058] s_miller2_carrier = [s_miller2_carrier, 1, -1].

[0059] For s_miller_code array, it is also realized by setting a loop function and appending array elements: element 1, s_miller2_code = [s_miller2_code, 1, 1]; element 0, s_miller2_code = [s_miller2_code, -1, -1];

[0060] S23: s_miller2_code_final is the dot product of s_miller2_code and s_miller2_carrier (s_miller2_code_final = s_miller2_code.*s_miller2_carrier). Figure 10 The Miller2 encoding result is shown in the figure).

[0061] In this embodiment, further, step S3 is to encode the Miller2 code s_miller2_code_final generated in S2 according to the sampling rate and bit width of ADC, which specifically includes the following steps:

[0062] S31: sampling rate encoding: since the system clock Fs of FPGA is 26Mhz (Ts = 1 / Fs = 38.46ns), LF = 320K. The code rate of the tag data is 1 / LF / 2 = 1.5625us. Therefore, the number of symbols that can be sampled N = round(Tb*1000 / Ts); then each element of s_miller2_code_final is expanded.

[0063] When s_miller2_code_final(i) = 1, sig = ones(1, N);

[0064] When s_miller2_code_final(i) = 0, sig = zeros(1, N). The sampled encoded data is stored in the digit_fill_data array.

[0065] S32: Bit-width encoding. Each element in the sampled and expanded array digit_fill_data is encoded according to the ADC bit width (n bits). In this embodiment, since the ADC designed for the project is 10-bit data, the encoding follows the two's complement rule. The two's complement data range represented by a 10-bit bit width is -512 to 511; when sig(i)=1, s_adc_idata=511; when sig(i)=0, s_adc_idata=512.

[0066] In this embodiment, step S4 further involves writing the s_adc_idata array generated in S3 into a text file using the file writing function fprintf.

[0067] fid=fopen('idata_miller2.txt','wt');

[0068] fprintf(fid,'%5d\n',s_adc_idata);

[0069] fclose(fid).

[0070] In this embodiment, step S4 is further followed by step S5: loading the stimulus text generated in step S4 into the Modelsim simulation platform to verify the encoding / decoding module in the logic engineering and resolve bugs in the code. Furthermore, it can quickly switch to any one of FM0 encoding, Miller2 encoding, Miller4 encoding, or Miller8 encoding to verify the code coverage and functional coverage.

[0071] In this invention, preferably, the tag is encoded with FM0 and Miller encoding. Miller encoding is further divided into Miller2 encoding, Miller4 encoding, and Miller8 encoding according to the number of subcarriers in one symbol period.

[0072] Finally, to verify the correctness of the algorithm, the generated label response data idata_miller2 was loaded into the simulation platform through the data_read_into module, and the simulation results were displayed (e.g., Figure 11 The preamble was correctly matched, and the data was decoded according to Miller2 encoding. The decoded data is ["3578","6297","3410","2819","8671","369c"]( Figure 12 right Figure 11 (Signal amplification). This method can also be extended to other encodings in the ISO 18000-63 protocol, such as FM0, Miller4, and Miller8.

[0073] The application designs a fast offline verification wireless communication coding and decoding method, generates label response data of certain rules according to ISO18000-63 protocol by Matlab, and saves the text. Then, the FPGA simulation platform of ISO18000-63 protocol is built in Modelsim, the generated text data is loaded into the simulation platform by the text reading module (data_read_into), and the information interaction simulation of the reader and the label is simulated. In this way, the logical code development and simulation verification of each module can be carried out at the beginning of the project, which greatly speeds up the code debug time, the backboard debugging time, and improves the product market time.

[0074] The application is suitable for generating the coding data of the protocol in the communication protocol code development process, then further converting the baseband data after coding into ADC data according to the ADC sampling rate and bit width required in the project, finally storing the data into text, and verifying the accuracy of the code development by the Modelsim simulation platform. Since other coding and link rate can be conveniently generated, the code coverage and functional coverage can also be verified.

[0075] The above embodiments of the application are described in detail, but the content described is only the preferred embodiments of the application, and cannot be considered as limiting the scope of the implementation of the application. Any equivalent changes and improvements within the scope of the application should still belong to the scope covered by the patent.

Claims

1. A fast offline verification wireless communication codec method, characterized by, The method comprises the following steps: S1: converting frame data of a tag response into binary code data to be transmitted by the tag; S2: Miller 2 coding of the binary code s_bit of the frame data obtained in S1 to obtain s_miller2_code_final; S3: coding s_miller2_code_final generated in S2 according to an ADC sampling rate and bit width to obtain an s_adc_idata array; S4: writing the s_adc_idata array generated in S3 into a text through a file writing function fprintf; The step S2 specifically comprises the following steps: S21: Miller coding is performed on each element of the s_bit array, four sample value arrays are set according to a state transition table of the Miller coding, s1=[1,1], s2=[1,0], s3=[0,1], s4=[0,0], an initial state state=1 is set according to the state transition table, s_bit(i) is judged, if 0, the state jumps to state=4, i=i+1, s4 is appended to s_miller_code, and s_bit jumps to the next element value judgment; if 1, the state jumps to state=2, i=i+1, s2 is appended to s_miller_code; when state=2, s_bit(i) is judged, if 0, the state machine jumps to state=4, i=i+1, s4 is appended to s_miller_code; if 1, the state machine jumps to state=3, i=i+1, s3 is appended to s_miller_code, and the coded data of state=3 and state=4 is written into s_miller_code; S22: each element in the s_miller_code array is modulated onto two carriers, in order to avoid that a subcarrier multiplied by symbol 0 is 0, and in order to achieve the effect of phase inversion, -1 is used to replace the occurrence of symbol 0, the length of the Miller code is first calculated, and the array element is appended through a loop function: s_miller2_carrier=[s_miller2_carrier,1,-1]; for the s_miller_code array, the array element is also appended through a loop function: when the element is 1, s_miller2_code=[s_miller2_code,1,1]; when the element is 0, s_miller2_code=[s_miller2_code,-1,-1]; S23: s_miller2_code_final is obtained by point multiplication operation of s_miller2_code and s_miller2_carrier.

2. The method of claim 1, wherein, The tag response data in step S1 is subjected to CRC16 calculation, and the calculation result is appended after the tag user area data to obtain conversion data.

3. The method of claim 1, wherein, The step S1 specifically comprises the following steps: S11: define an array s_tag_code_header to store 23bit frame flag, the frame flag is fixed as 16 zeros and 7'b010111, i.e. s_tag_code_header = [zeros(1, 16), 0, 1, 0, 1, 1, 1]; S12: calculate the length s_len of user data, then convert the hexadecimal data into binary characters by the loop of dec2bin(hex2dec(s_tag_code_data(i)), 16) and write them into the array s_array, concatenate the characters of the frame flag s_tag_code_header and 1bit header, and finally store the complete baseband encoding data into s_whole_array.

4. The method of claim 1, wherein, Step S3 specifically includes the following steps: S31: sampling rate encoding, since the system clock Fs of FPGA is 26Mhz (Ts = 1 / Fs = 38.46ns), LF = 320K, the code rate of tag data is 1 / LF / 2 = 1.5625us, the number of code elements that can be sampled N = round(Tb*1000 / Ts), then expand each element of s_miller2_code_final; When s_miller2_code_final(i) = 1, sig = ones(1, N); When s_miller2_code_final(i) = 0, sig = zeros(1, N), the sampled encoding data is stored in the array digit_fill_data; S32: bit width encoding, encode each element in the array digit_fill_data according to the ADC bit width (nbit) after sampling and expansion, the encoding is according to the complement rule, the complement data range represented by 10bit bit width is -512 to 511; when sig(i) = 1, s_adc_idata = 511; when sig(i) = 0, s_adc_idata = 512.

5. The method of claim 1, wherein, Step S4 writes the contents of s_adc_idata array into the text by fprintf function.

6. The method of claim 1, wherein, After step S4, it further includes S5: verify the accuracy of the encoding and decoding module code through the modelsim simulation platform, test the code coverage and functional coverage.

7. The method of claim 1, wherein, The tag response data satisfies FM0 and Miller encoding, and the Miller encoding is divided into Miller2 encoding, Miller4 encoding and Miller8 encoding according to the number of subcarriers in a code element period.

8. The method of claim 3, wherein, Convert all characters of s_whole_array into int type by str2num function and write them into s_bit array.

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