Semiconductor device and polytranscoder

Abstract

An environmental power generating device (100) outputs generated electric charges to a power line (6) to which a capacitor (4) is connected. A voltage comparison circuit (20) outputs a voltage detection signal (VCMP) when a generated voltage (VPWR) equivalent to a charging voltage of the capacitor (4) is equal to or higher than a start determination voltage. Internal circuits (13, 16) of a semiconductor device (10x) are started in response to the voltage detection signal (VCMP). A setting change circuit (11) switches the start determination voltage in accordance with a setting input (11v).

Description

Technical Field

[0001] This disclosure relates to semiconductor devices and multi-rotor encoders. Background Technology

[0002] A semiconductor device has been developed that uses electricity generated by an environmental power generation device as its power source. This device converts energy from the surrounding environment into electricity. Environmental power generation is also known as energy harvesting or energy collection. Examples of environmental power generation include vibration power generation, photovoltaic power generation, and thermoelectric power generation, as well as energy extraction from the rotation or vibration of motors. By using such an environmental power generation device as a power source, battery-free devices that do not require batteries can be developed.

[0003] As an example, Japanese Patent No. 5769879 (Patent Document 1) discloses a battery-free multi-rotation encoder that uses electricity generated by the rotational energy of a motor shaft to count and maintain the rotational direction and speed of more than one revolution of the shaft.

[0004] Existing technical documents

[0005] Patent documents

[0006] Patent Document 1: Japanese Patent No. 5769879 Summary of the Invention

[0007] The problem the invention aims to solve

[0008] In semiconductor devices that use the electricity generated by intermittently generating ambient power plants as a power source, the power is typically supplied via a capacitor used to store the generated charge. On the other hand, the input voltage from the capacitor to the semiconductor device varies depending on the balance between the electricity generated by the ambient power plant and the capacitance of the capacitor.

[0009] When the capacitance of a capacitor is too small, problems may arise such as the maximum input voltage supplied to the semiconductor device exceeding the rated (maximum operating voltage) or the rise time of the input voltage becoming too short to ensure the startup time of the semiconductor device's internal circuitry. Conversely, when the capacitance of a capacitor is too large, the input voltage to the semiconductor device may take a long time to rise to the voltage level at which the semiconductor device can operate. Therefore, the capacitance of the capacitor supplying the input voltage to the semiconductor device needs to be adjusted in a way that balances with the power generated by the ambient power generation device.

[0010] On the other hand, when the capacitance of a capacitor changes, the relationship between the input voltage to the semiconductor device and the amount of charge (i.e., energy) in the capacitor also changes. As a result, the amount of charge required for the input voltage to rise to the voltage at which the semiconductor device can operate also varies depending on the capacitance. Therefore, it is difficult to properly start the semiconductor device for power generation devices operating in environments with varying power outputs.

[0011] This disclosure was made to solve such problems. The purpose of this disclosure is to enable a semiconductor device that is powered by an ambient power generation device to start properly in response to the difference in the power generation capacity of the ambient power generation device, and to provide a multi-rotor encoder using the semiconductor device.

[0012] means for solving problems

[0013] In one aspect of this disclosure, a semiconductor device is connected to a power line, to which the generated charge from an ambient power generation device is input. The semiconductor device includes a voltage comparison circuit, internal circuitry, and a setting change circuit. The voltage comparison circuit outputs a voltage detection signal when the generated voltage is above a start-up determination voltage; this generated voltage is equivalent to the charging voltage of a capacitor connected to the power line. The internal circuitry is activated in response to the voltage detection signal from the voltage comparison circuit. The setting change circuit switches the start-up determination voltage according to a first setting input.

[0014] According to another aspect of this disclosure, a multi-rotation encoder is provided for detecting the rotational speed of a rotating shaft. It incorporates the semiconductor device of this disclosure, and the ambient power generation device comprises a power generation element using magnetic wire exhibiting the large Backhausen effect, the magnetic wire being mounted on a magnet that rotates in conjunction with the rotating shaft. The internal circuitry is activated each time a voltage pulse with a power generation voltage exceeding the start-up determination voltage is output from the power generation element, and counts the multi-rotation values ​​of the rotating shaft.

[0015] The effects of the invention

[0016] According to this disclosure, when the capacitance value of the capacitor is adjusted according to the power generation capacity (charge amount) of the ambient power generation device, the start-up determination voltage of the semiconductor device can be switched according to the setting input from the outside, thus enabling appropriate start-up according to the difference in the power generation capacity of the ambient power generation device. Therefore, a battery-free multi-rotation encoder using this semiconductor device can be provided. Attached Figure Description

[0017] Figure 1 This is a block diagram illustrating the structure of the semiconductor device according to Embodiment 1.

[0018] Figure 2This is a conceptual waveform diagram illustrating the first action example when a semiconductor device is started.

[0019] Figure 3 This is a conceptual waveform diagram illustrating the second action example when a semiconductor device is started.

[0020] Figure 4 This is a conceptual waveform diagram illustrating the third operation example when a semiconductor device is started.

[0021] Figure 5 This is a conceptual waveform diagram illustrating the fourth action example when a semiconductor device is started.

[0022] Figure 6 This is a conceptual waveform diagram illustrating the fifth operation example during the startup of a semiconductor device.

[0023] Figure 7 Yes Figure 1 The block diagram shown illustrates the first structural example of the setting change circuit and voltage comparison circuit.

[0024] Figure 8 This is a block diagram illustrating the second structural example of the setting change circuit and the voltage comparison circuit.

[0025] Figure 9 This is a block diagram illustrating the third structural example of the setting change circuit and the voltage comparison circuit.

[0026] Figure 10 This is a conceptual bar chart used to illustrate the setting of the starting determination voltage in a modified example of Embodiment 1.

[0027] Figure 11 This is a block diagram illustrating the structure of the semiconductor device in Embodiment 2.

[0028] Figure 12 This is a block diagram illustrating a modified example of the structure of the semiconductor device in Embodiment 2.

[0029] Figure 13 This is a block diagram illustrating a structural example of a multi-rotor encoder according to Embodiment 3.

[0030] Figure 14 It is a conceptual waveform diagram used to illustrate the generation pulse loss.

[0031] Figure 15 This is a block diagram illustrating a structural example of the semiconductor device and multi-rotor encoder according to Embodiment 4.

[0032] Figure 16 This is a conceptual waveform diagram used to illustrate the setting of the start-up determination voltage in the semiconductor device of Embodiment 4.

[0033] Figure 17 This is a block diagram illustrating a first structural example of the voltage comparison circuit and setting change circuit in the semiconductor device of Embodiment 4.

[0034] Figure 18 This is a block diagram illustrating a second structural example of the voltage comparison circuit and setting change circuit in the semiconductor device of Embodiment 4.

[0035] Figure 19 This is a block diagram illustrating a structural example of a semiconductor device and a multi-rotor encoder, a modified example of Embodiment 4. Detailed Implementation

[0036] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. Furthermore, the same or equivalent parts in the drawings will be labeled with the same reference numerals, and their descriptions will generally not be repeated.

[0037] Implementation method 1.

[0038] Figure 1 This is a block diagram illustrating the structure of the semiconductor device according to Embodiment 1.

[0039] like Figure 1 As shown, the semiconductor device 10a in Embodiment 1 operates using the electricity generated by the ambient power generation device 100 as its power source. The signal processing device 200a equipped with the semiconductor device 10a includes a rectifier circuit 2, a clamping circuit 3, and a capacitor 4 between the ambient power generation device 100 and the semiconductor device 10a.

[0040] In this embodiment, the ambient power generation device 100 assumes intermittent power generation elements. For example, it can be composed of a power generation element combining a magnetic wire with a large Backhausen effect and a pickup coil, a power generation module combining a magnetostrictive element and a pickup coil, or a piezoelectric element that generates electricity through the displacement of a piezoelectric element. The positive voltage power generation pulses and negative voltage power generation pulses output from the ambient power generation device 100 are rectified by the rectifier circuit 2, thereby supplying the generated charge from the ambient power generation device 100 to the power line 6.

[0041] A capacitor 4 and a clamping circuit 3 are connected to the power line 6. The capacitor 4 is charged by the generated charge from the ambient power generation device 100. Therefore, the voltage VPWR of the power line 6 (hereinafter also referred to as "generated voltage VPWR") is equivalent to the charging voltage of the capacitor 4. Thus, the generated voltage VPWR can be expressed as generated voltage VPWR = Qch / Cch using the charging charge Qch and capacitance value Cch of the capacitor 4.

[0042] The generated voltage VPWR is input to the semiconductor device 10a. A clamping circuit 3 is connected to the power line 6 for overvoltage protection. The clamping circuit 3 typically consists of a diode that conducts when the generated voltage VPWR exceeds a predetermined upper limit voltage Vmax, and operates as a protection circuit to ensure that VPWR ≤ Vmax.

[0043] Semiconductor device 10a includes a constant voltage circuit 13, a POR (Power On Reset) circuit 15, a digital circuit 16 with functions corresponding to the application, and a non-volatile memory 17. The non-volatile memory 17 stores the program and data used by the digital circuit 16, as well as data generated by the digital circuit 16. The constant voltage circuit 13, the digital circuit 16, and the non-volatile memory 17 are shown as an example of the "internal circuitry" of semiconductor device 10a.

[0044] The constant voltage circuit 13 generates the power supply voltage VCORE for the digital circuit 16 and the non-volatile memory 17 based on the generated voltage VPWR of the power supply line 6. When the POR circuit 15 detects that the power supply voltage VCORE has stably reached a state above the specified reset release voltage during startup from the constant voltage circuit 13, it generates a POR signal to release the reset state of the digital circuit 16.

[0045] In addition, Figure 1 The example shows a structure in which the digital circuit 16 and the non-volatile memory 17 operate via a power supply voltage VCORE from a common constant voltage circuit 13. However, different power supply voltages can also be supplied to the digital circuit 16 and the non-volatile memory 17 from different constant voltage circuits. Alternatively, the power supply voltage for one of the digital circuit 16 and the non-volatile memory 17 can be generated by a constant voltage circuit, and the power supply voltage for the other can be generated by boosting or bucking that power supply voltage.

[0046] In addition, Figure 1 In this example, the rectifier circuit 2 and the clamping circuit 3 are disposed outside the semiconductor device 10a, but they can also be disposed inside the semiconductor device 10a. Conversely, the non-volatile memory 17 can also be disposed outside the semiconductor device 10a.

[0047] The semiconductor device 10a also includes a voltage comparison circuit 20 that compares the generated voltage VPWR on the power supply line 6 with the start-up determination voltage Vdet, and a setting change circuit 11 that switches the start-up determination voltage Vdet based on a setting input 11V from an external source, the semiconductor device 10a. When the generated voltage VPWR on the power supply line 6 becomes higher than the start-up determination voltage Vdet, the voltage comparison circuit 20 generates a voltage detection signal VCMP. The constant voltage circuit 13 is started based on this voltage detection signal VCMP.

[0048] The operation of the semiconductor device 10a will be described. The power generation pulse from the ambient power generation device 100 is rectified by the rectifier circuit 2 and charged into the capacitor 4, thereby increasing the power generation voltage VPWR. When the voltage comparator circuit 20 detects that the power generation voltage VPWR exceeds the start-up determination voltage Vdet, the constant voltage circuit 13 is activated, wherein the start-up determination voltage Vdet is set in a variable manner by the setting change circuit 11. Hereinafter, the activation of the constant voltage circuit 13 will also be referred to as the activation of the semiconductor device 10a.

[0049] Digital circuit 16 is de-reset in response to the POR signal (POR circuit 15) accompanying the rise of the power supply voltage VCORE, thereby initiating operation. Thus, digital circuit 16 begins the pre-installation process. During operation of digital circuit 16, data input / output (read and write) is performed between digital circuit 16 and non-volatile memory 17.

[0050] Here, the semiconductor device 10a needs to be started after the amount of charge (energy consumed by the semiconductor device 10a) required from the start to the completion of the process is charged to the capacitor 4. This is because the following failure mode is taken into consideration: if the semiconductor device 10a is started expecting to supply the required amount of charge for power generation without charging the required amount, then the ambient power generation device 100 will not be able to generate the required amount of charge before the semiconductor device 10a completes the process. In particular, if a destructive read-out type memory such as FeRAM (Ferroelectric Random Access Memory) is applied to the non-volatile memory 17, if the power supply voltage VCORE drops due to insufficient charge, causing the semiconductor device 10a to be interrupted before completion, it may result in a failure mode such as data loss of the non-volatile memory 17.

[0051] Next, use Figures 2-6 The operation example of the semiconductor device 10a during startup is explained by using waveform examples of the generator voltage VPWR and the power supply voltage VCORE.

[0052] exist Figure 2In this process, the generated charge from the ambient power generation device 100 is used to charge the capacitor 4, causing the generated voltage VPWR to rise. At time t1, when the generated voltage VPWR becomes higher than the start-up determination voltage Vdet(V1), the constant voltage circuit 13 starts in response to the voltage detection signal VCMP. Thus, the generation of the power supply voltage VCORE begins.

[0053] After the semiconductor device 10a is started, the power supply voltage VCORE is maintained at a constant value by the constant voltage circuit 13. On the other hand, as the energy in the digital circuit 16 and the non-volatile memory 17 is consumed, the charging charge of the capacitor 4 is released, and therefore, the generated voltage VPWR gradually decreases. When the processing of the digital circuit 16 and the non-volatile memory 17 is completed, at time t2, the constant voltage circuit 13 stops generating the power supply voltage VCORE.

[0054] exist Figure 2 In the example, for the power generation capacity (charge amount) of the environmental power generation device 100, the capacitance value of capacitor 4 is adjusted so that the maximum value of the power generation voltage VPWR does not exceed the maximum operating voltage Vopmax of the semiconductor device 10a.

[0055] exist Figure 2 In the above, when the capacitance value of capacitor 4 is Cchg1, the amount of charge Qopr1 charged into capacitor 4 at time t1 is represented by the following equation (1).

[0056] Qopr1=V1·Cchg1…(1)

[0057] exist Figure 3 The diagram shows the power generation capacity (charge) of the environmental power generation device 100 compared to... Figure 2 Example of a large-scale action waveform.

[0058] exist Figure 3 In the process, the energy (charge) consumed by the digital circuit 16 and the non-volatile memory 17, as well as the capacitance value of the capacitor 4, are related to... Figure 2 The same. On the other hand, the amount of charge output from the environmental power generation device 100 to the power line 6 is the same. Figure 2 Compared to the increase.

[0059] As a result, the maximum value of the generated voltage VPWR exceeds the maximum operating voltage Vopmax of the semiconductor device 10a. Conversely, the capacitance value of capacitor 4 needs to be adjusted according to the power generation capacity (charge amount) of the ambient power generation device 100 so that the maximum value of the generated voltage VPWR is lower than the maximum operating voltage Vopmax.

[0060] exist Figure 4 In, it is shown in Figure 3The waveform of the action when the capacitance value of capacitor 4 is adjusted so that the maximum value of the generating voltage VPWR does not exceed the maximum operating voltage Vopmax.

[0061] exist Figure 4 In this process, by making the capacitance value of capacitor 4 Cchg2 (Cchg2>Cchg1), the maximum value of the generating voltage VPWR is lower than the maximum operating voltage Vopmax.

[0062] On the other hand, Figure 4 In China, it is also used with Figure 2 and Figure 3 The same start-up determination voltage Vdet = V1 is used to determine the start-up timing of semiconductor device 10a. Therefore, at the moment t1a when VPWR ≧ Vdet(V1), the amount of charge Qopr2 charged to capacitor 4 is expressed by the following equation (2) using the capacitance value Cchg2 of capacitor 4.

[0063] Qopr2=V1·Cchg2…(2)

[0064] Here, Cchg2 > Cchg1, therefore Qopr2 > Qopr1. That is, if the capacitance of capacitor 4 is increased, the amount of charge required to raise the generation voltage VPWR to the same starting determination voltage Vdet also increases.

[0065] On the other hand, since the capacitance value of capacitor 4 is increased from Cchg1 to Cchg2, therefore, Figure 4 In this case, it can be understood that when the generation voltage VPWR is lower than V1 (Vdet = V1), the amount of charge required before the processing of the semiconductor device 10a is completed is charged. That is, in Figure 4 In the case where the starting determination voltage Vdet is set to the same as... Figure 2 The same V1 is equivalent to uselessly increasing the amount of charge required to start up the semiconductor device 10a.

[0066] Therefore, in this embodiment, the starting determination voltage Vdet can be variably set according to the setting input 11v for the setting change circuit 11. Thus, the starting determination voltage Vdet can be changed in response to adjustments in the capacitance value of the capacitor 4 that stores the charge generated from the ambient power generation device 100.

[0067] exist Figure 5 In, it is shown that relative to Figure 4 The waveform diagram shows the operation when the starting determination voltage Vdet is reduced due to the situation.

[0068] exist Figure 5 In China, the use of Figure 4The capacitance value of capacitor 4 (Cchg2) is the same, therefore, the maximum value of the generation voltage VPWR is lower than the maximum operating voltage Vopmax. Furthermore, by setting the starting determination voltage Vdet = V2 (V2 < V1), at time t1b, it is possible to achieve a higher voltage output than at... Figure 4 At time t1a, a small amount of charge is charged into capacitor 4, which triggers semiconductor device 10a by generating voltage detection signal VCMP.

[0069] The capacitance value Cchg2 of capacitor 4 is expressed by the following equation (3). Figure 5 The amount of charge Qopr3 that is charged into capacitor 4 at time t1b.

[0070] Qopr3=V2·Cchg2…(3)

[0071] It is understandable that, in order to make the charge Qopr3 in equation (3) equal to the charge Qopr1 in equation (1), it is set according to the following equation (4). Figure 5 The starting determination voltage Vdet (Vdet = V2) can be used. Therefore, when Cchg2 > Cchg1, V2 < V1, and the larger the capacitance value of capacitor 4, the lower the starting determination voltage Vdet can be variably set.

[0072] V2=V1·(Cchg1 / Cchg2)…(4)

[0073] Furthermore, as will be discussed later, it is difficult to set the start-up determination voltage Vdet to an arbitrary value; therefore... Figure 5 The starting determination voltage Vdet (Vdet = V2) is preferably set to the minimum voltage among a plurality of voltage values ​​that can be set in stages according to the set input 11v within the range of the following equation (5).

[0074] V2≧V1·(Cchg1 / Cchg2)…(5)

[0075] exist Figures 2-5 The example illustrates adjusting the capacitance value of capacitor 4 based on the relationship between the generation voltage VPWR and the maximum operating voltage Vopmax. On the other hand, with... Figure 3 Conversely, the power generation capacity (charge) of the environmental power generation device 100 is higher than that of the environmental power generation device 100. Figure 2 In cases where the voltage is low, the generated voltage VPWR may not reach the start-up determination voltage Vdet, potentially preventing the semiconductor device 10a from starting its processing. Therefore, in such situations, contrary to the above, it is necessary to adjust the capacitance value of capacitor 4 to be reduced.

[0076] However, if the capacitance of capacitor 4 is reduced, the amount of charge that can be applied to capacitor 4 at the same start-up determination voltage Vdet becomes smaller. Therefore, in order to ensure the required amount of charge before the processing of semiconductor device 10a is completed, the start-up determination voltage Vdet needs to be set higher than the required amount. Figure 2 high.

[0077] In addition, we also consider the case where the capacitance value of capacitor 4 needs to be adjusted from the perspective of the rise time of the generated voltage VPWR.

[0078] like Figure 6 As shown, when the capacitance value of capacitor 4 is changed for the same environment in the power generation device 100, the rise time of the generation voltage VPWR also changes. When this rise time is shorter than the allowable rise time of the semiconductor device 10a, a poor start-up of the semiconductor device 10a may occur. For example, in the semiconductor device 10a, a certain preparation time is required before the voltage comparison circuit 20, which compares the generation voltage VPWR and the start-up determination voltage Vdet, begins to operate. The aforementioned allowable rise time is set as a specified value to ensure this preparation time.

[0079] For example, suppose the following situation is assumed: when the capacitance value of capacitor 4 is Cchg1, the rise time Ton1 is shorter than the rise time that semiconductor device 10a can tolerate; on the other hand, when the capacitance value of capacitor 4 is Cchg2 (Cchg2 > Cchg1), the rise time Ton2 is longer than the tolerated rise time.

[0080] In this situation, the capacitance value of capacitor 4 needs to be set to Cchg2 to correspond to the power generation capacity (charge amount) of the environmental power generation device 100. In this case, it is also related to... Figure 4 Similarly, if the capacitance value of capacitor 4 is Cchg1, it is preferable to reduce the starting determination voltage Vdet.

[0081] Therefore, the capacitance value of the capacitor that charges the generated charge needs to be adjusted according to the power generation capacity (charge amount) of the ambient power generation device 100. Thus, by adjusting the capacitance value of the capacitor 4, the semiconductor device 10a of this embodiment can be configured to switch the start-up determination voltage Vdet that is compared with the generated voltage VPWR, thereby enabling it to handle ambient power generation devices 100 with different characteristics without unnecessarily increasing the amount of charge required to start the semiconductor device 10a.

[0082] Next, an example of the structure of the setting change circuit 11 and the voltage comparison circuit 20 used to switch the setting of the start-up determination voltage Vdet will be described.

[0083] exist Figure 7The first structural example of setting change circuit 11 and voltage comparison circuit 20 is shown.

[0084] The setting change circuit 11 generates a control signal Ssg for switching the setting of the start-up determination voltage Vdet. This control signal Ssg needs to be set before the digital circuit 16 is started. Therefore, the setting change circuit 11 cannot be constructed using the non-volatile memory 17 that reads data from the digital circuit 16.

[0085] The setting change circuit 11 is equipped with fine-tuning elements 12, such as metal fuses, polysilicon fuses, and Zener breakdown elements, which do not require readout. For example, n (n: an integer greater than 2) fine-tuning elements 121 to 12n are built into the setting change circuit 11.

[0086] Each fine-tuning element 12 is configured to produce an irreversible transition between a non-destructive state and a destructive state via fine-tuning inputs such as laser irradiation or voltage / current input, i.e., it is capable of fine-tuning. When the generated voltage VPWR is applied, each fine-tuning element 12 can generate a 1-bit digital signal that sets the ground voltage GND to a logic low level (hereinafter, "L level") and the generated voltage VPWR to a logic high level (hereinafter, "H level"), depending on whether it is a non-destructive state or a destructive state. Therefore, the setting change circuit 11 can generate an n-bit control signal Ssg by taking the fine-tuning inputs for the n fine-tuning elements 121 to 12n as setting input 11v.

[0087] Furthermore, regarding the setting input 11v for the setting change circuit 11, if it is a fine-tuning based on laser irradiation, it is usually set during the manufacturing process of the semiconductor device 10a. Alternatively, if it is a fine-tuning based on voltage / current input, the setting input 11v for the setting change circuit 11 may be set during the manufacturing process of the semiconductor device 10a; or the setting input 11v for the setting change circuit 11 may be set via a control circuit (not shown) such as a microcomputer after the semiconductor device 10a is mounted on the substrate. Thus, at least once before (during) or after the semiconductor device 10a is completed, the setting input 11v is input to the setting change circuit 11 from an external element different from the structural elements of the semiconductor device 10a, i.e., from outside the semiconductor device 10a.

[0088] like Figure 7 As shown, the voltage comparison circuit 20 has a voltage divider circuit 22X and a comparator 24. The voltage divider circuit 22X has a resistor element 21 (resistance value R1) connected between the power supply line 6 and the node Nx, and a resistor element 22 (resistance value R2) connected between the node Nx and the ground line 7.

[0089] The voltage divider circuit 22X outputs the generated voltage VPWR to node Nx as a divided voltage VDIV after being divided by resistors 21 and 22. If the voltage division ratio Kr of the voltage divider circuit 22X is used (Kr=R2 / (R1+R2)), then VDIV is expressed as VDIV=Kr·VPWR (Kr<1.0).

[0090] Comparator 24 compares the divided voltage VDIV with a fixed reference voltage VREF. When VDIV ≥ VREF is detected, the output voltage of comparator 24 changes from level L to level H. Consequently, a voltage detection signal VCMP is output from comparator 24.

[0091] Therefore, in order to generate a voltage detection signal VCMP when the generator voltage VPWR becomes above the start-up determination voltage Vdet (VPWR≧Vdet), the following relationship (6) holds between the reference voltage VREF, the start-up determination voltage Vdet, and the voltage division ratio Kr.

[0092] Vdet=VREF / Kr…(6)

[0093] In the voltage divider circuit 22X, at least one of the resistive elements 21 and 22 is a variable resistor whose resistance value changes according to the control signal Ssg. Figure 7 In the example, resistors 21 and 22 are each composed of variable resistors. As a result, by changing the resistance value of resistors 21 and / or 22 according to the control signal Ssg, the voltage division ratio Kr of the voltage divider circuit 22X can be changed.

[0094] Therefore, in equation (6), the reference voltage VREF is fixed, and in contrast, the voltage division ratio Kr is changed by the control signal Ssg, thereby enabling the start-up determination voltage Vdet to be set to be variable.

[0095] exist Figure 8 The second structural example of setting change circuit 11 and voltage comparison circuit 20 is shown in the figure.

[0096] exist Figure 8 In the illustrated structural example, the voltage comparison circuit 20 includes a voltage divider circuit 22Y, a comparator 24, and a digital-to-analog (D / A) converter 25.

[0097] The voltage divider circuit 22Y outputs the divided voltage VDIV (VDIV = Kr·VPWR) from resistors 21 and 22 to node Nx. The resistance values ​​of resistors 21 and 22 are fixed, and the voltage division ratio Kr (Kr = R2 / (R1+R2)) of the voltage divider circuit 22Y is a fixed value.

[0098] From and Figure 7The control signal Ssg of the same configuration setting change circuit 11 is input to the D / A converter 25 that generates the reference voltage VREF. The D / A converter 25 generates an analog voltage obtained by analog-converting the multi-bit control signal Ssg as the reference voltage VREF. That is, the D / A converter 25 corresponds to an embodiment of a "voltage generator".

[0099] exist Figure 8 In the structural example, in equation (6), the voltage division ratio Kr is fixed, and in contrast, the reference voltage VREF is changed by the control signal Ssg, thereby enabling the start-up determination voltage Vdet to be set to be variable.

[0100] Or, such as Figure 9 As shown, a reference voltage VREF can also be input using a terminal 11x that is configured to receive an analog voltage from an external source of the semiconductor device 10a. In this case, the start-up determination voltage Vdet is variably set from an external source of the semiconductor device 10a by means of the analog voltage at terminal 11x, thereby forming a setting change circuit 11.

[0101] Thus, in the semiconductor device 10a, the start-up determination voltage Vdet, which is compared with the generated voltage VPWR by the voltage comparison circuit 20, can be switched by the setting input 11v to the setting change circuit 11. Therefore, by appropriately adjusting the capacitance value of the capacitor charging the generated charge for different environmental power generation devices 100, the semiconductor device 10a can be started appropriately based on ensuring the amount of charge required for processing in the semiconductor device 10a. Thus, the semiconductor device can be used for various environmental power generation devices, and conversely, an appropriate environmental power generation device can be selected based on the product equipped with the semiconductor device.

[0102] For example, when the semiconductor device 10a of this embodiment is applied to a product mounted on a small substrate, an ambient power generation device 100 is used, which has a small power generation capacity but is also small in size and expensive. Therefore, in the semiconductor device 10a, the start-up determination voltage Vdet can be set relatively high by the setting input 11v to the setting change circuit 11, so that it is suitable for the capacitance value of the capacitor 4, which is adjusted according to the power generation capacity (charge amount) of the ambient power generation device 100.

[0103] On the other hand, when the semiconductor device 10a of this embodiment is applied to a product mounted on a large substrate, it is possible to use an ambient power generation device 100 that has a large power generation capacity, large size, and low cost. Therefore, in the semiconductor device 10a, the start-up determination voltage Vdet can be set relatively low by means of the setting input 11v to the setting change circuit 11, so that it is suitable for the capacitance value of the capacitor 4, which is adjusted according to the power generation capacity (charge amount) of the ambient power generation device 100. In this way, the versatility of the semiconductor device 10a of Embodiment 1 is improved for the ambient power generation device 100.

[0104] A variation of implementation method 1.

[0105] In a variation of Embodiment 1, a more detailed setting of the start-up determination voltage Vdet in the semiconductor device 10a of Embodiment 1 will be described.

[0106] exist Figure 10 The diagram shows a conceptual bar chart illustrating the setting of the start-up determination voltage in Embodiment 1. Figure 10 The width of the horizontal axis represents the capacitance value of capacitor 4, and the length of the vertical axis represents the start-up determination voltage Vdet. Therefore, the area of ​​each column becomes the product of the capacitance value and the voltage value, showing the amount of charge charged into capacitor 4 at the time when the generation voltage VPWR reaches the start-up determination voltage Vdet (i.e., when the semiconductor device 10a starts).

[0107] Figure 10 The vertical axis represents the minimum operating voltage Vopmin of the semiconductor device 10a. The minimum operating voltage Vopmin is defined as a specified value representing the lower limit of the input power supply voltage at which the semiconductor device 10a can operate. Figure 1 In the example, when the power supply voltage VCORE from the constant voltage circuit 13 is 1.8 [V], the generated voltage VPWR, which becomes the input voltage of the constant voltage circuit 13, needs to be 0.2 to 0.3 [V] higher than 1.8 [V]. Therefore, for example, the minimum operating voltage Vopmin becomes around 2.0 [V].

[0108] When the semiconductor device 10a is started, the sum of a charge Qmin and a charge Qact needs to be stored in the capacitor 4. The charge Qmin is the amount of charge required to bring the generated voltage VPWR to the minimum operating voltage Vopmin, and the charge Qact is the amount of charge consumed by the semiconductor device 10a from the start of the pre-installation process to the completion of the process. The charge Qmin is understood to vary depending on the capacitance value of the capacitor 4.

[0109] On the other hand, the charge Qact is equivalent to the energy (charge) consumed by the operation of the constant voltage circuit 13, POR circuit 15, digital circuit 16, and non-volatile memory 17 when the semiconductor device 10a performs the pre-installed processing. Therefore, the charge Qact is determined by the circuit structure and processing content of the semiconductor device 10a, and thus does not depend on the capacitance value of the capacitor 4.

[0110] Therefore, the amount of charge Qstr (Qstr = Qact + Qmin) required to start up the semiconductor device 10a varies depending on the capacitance value of the capacitor 4. It is understood that the smaller the capacitance value, the smaller the amount of charge Qstr.

[0111] exist Figure 10 On the right end, it shows the target Figure 2 The capacitance value Cchg1 of capacitor 4 described herein is set as the charge Qmin1 and Qact when the start-up determination voltage Vdet = V1. Qmin1 is represented by the product of the capacitance value Cchg1 and the minimum operating voltage Vopmin. Here, V1 = 2·Vopmin. In the case on the right, the charge Qstr1 charged into capacitor 4 when semiconductor device 10a is started is represented by Qstr1 = V1·Cchg1 = 2·Vopmin·Cchg1.

[0112] Here, in order to correspond to different specifications of the environmental power generation device 100, we consider setting the starting determination voltage Vdet (Cchg3=(2 / 3)·Cchg1) when the capacitance value of capacitor 4 is set to (2 / 3) times Cchg1.

[0113] exist Figure 10 In the center, the case where the starting determination voltage Vdet = V3 (i.e., V3 = (3 / 2)·V1 = 3·Vopmin) is set according to the ratio of the capacitance values ​​of capacitor 4 using the above equation (4). In this case, it is understood that the amount of charge Qstr2 = V3·Cchg3 = (3 / 2)·V1·(2 / 3)·Cchg1 = V1·Cchg1 = Qstr1 is charged into capacitor 4 at the start of processing.

[0114] On the other hand, in the central case, as the capacitance of capacitor 4 decreases, the amount of charge Qmin3 used to ensure the minimum operating voltage Vopmin is smaller than the amount of charge Qmin1 in the right-hand case. Therefore, it can be understood that the amount of charge (Qstr2-Qmin3) is greater than the amount of charge Qact consumed by semiconductor device 10a, and the amount of charge Qstr2 is excessive relative to the minimum required amount of charge Qmin3+Qact.

[0115] exist Figure 10On the left end, a setting example of the start-up determination voltage Vdet of a variation of Embodiment 1 is shown. In the case of the left end, the start-up determination voltage Vdet is set to V4, such that the amount of charge Qstr3 charged in capacitor 4 at the start of processing is the sum of the amount of charge Qmin3 used to ensure the minimum operating voltage Vopmin and the amount of charge Qact consumed in the processing of semiconductor device 10a.

[0116] As mentioned above, the charge Qmin3 depends on the capacitance Cchg3 of capacitor 4 and is represented by Qmin3 = Cchg3·Vopmin. On the other hand, the charge Qact does not depend on the capacitance of capacitor 4 and is the same value as in the case on the right (Qstr1).

[0117] In the case of the right end, according to V1 = 2·Vopmin, Qact = Cchg1·(V1-Vopmin) = Cchg1·(2·Vopmin-Vopmin) = Cchg1·Vopmin can be expressed as Qact = (3 / 2)·Cchg3·Vopmin. Similarly, as in the case of the center, it can be expressed as Qmin3 = Cchg3·Vopmin. As a result, Qstr3 = Qmin3 + Qact = (5 / 2)·Cchg3·Vopmin, and therefore, Vdet = V4 = 2.5·Vopmin can be set.

[0118] As a result, in the case of the left end of the variation of embodiment 1, the start-up determination voltage Vdet can be set lower than in the case of the middle according to formula (5). Therefore, the semiconductor device 10a can be started appropriately with less charge than in embodiment 1.

[0119] Based on the above, in a variation of Embodiment 1, the start-up determination voltage Vdet can be set according to the following formula (7) using the minimum operating voltage Vopmin (as specified value), the charge consumption Qact for performing pre-installation processing on the semiconductor device 10a, and the capacitance value Cchg of the capacitor used to charge the generated charge of the ambient power generation device 100. The charge consumption Qact can be predetermined based on the measured value of the power consumption and the simulated design value.

[0120] Vdet=Vopmin+(Qact / Cchg)…(7)

[0121] According to the setting of the start-up determination voltage Vdet in the modified embodiment 1, the versatility of the semiconductor device 10a is improved, enabling it to be used in environments with low generated charge, such as the power generation device 100.

[0122] Implementation method 2.

[0123] Figure 11 This is a block diagram illustrating the structure of the semiconductor device in Embodiment 2.

[0124] like Figure 11 As shown, in Embodiment 2, the semiconductor device 10b is mounted on the signal processing device 200b. The signal processing device 200b differs from the other device in that it includes the semiconductor device 10b instead of the semiconductor device 10a. Figure 1 The signal processing device 200a shown is shown.

[0125] The semiconductor device 10b of Embodiment 2 differs from the semiconductor device 10a of Embodiment 1 in that it also includes a capacitance adjustment circuit 18 connected to the power supply line 6. The other structures of the semiconductor device 10b are the same as those of the semiconductor device 10a, so detailed descriptions will not be repeated.

[0126] The capacitance adjustment circuit 18 has k (k: a natural number) sub-capacitors Cs and switches SW connected in series between the power supply line 6 and the ground line 7. When k ≥ 2, multiple groups of sub-capacitors Cs and switches SW connected in series are connected in parallel between the power supply line 6 and the ground line 7.

[0127] exist Figure 11 The example shown is k≧3. The group of sub-capacitor Cs1 and switch SW1, the group of sub-capacitor Cs2 and switch SW2, ..., and the group of sub-capacitor Csk and switch SWk are connected in parallel between the power line 6 and the ground line 7.

[0128] The opening and closing of the k switches are controlled by control signals S1 to Sk from the setting change circuit 11. The control signals S1 to Sk can be generated in the same way as the control signal Ssg described above by increasing the number of fine-tuning elements 12 in the setting change circuit 11. That is, the control signals S1 to Sk can also be generated according to the setting input 11c for the setting change circuit 11, which corresponds to the fine-tuning input. The setting input 11c is also input to the setting change circuit 11 in the same manner as the setting input 11v described above.

[0129] As a result, in the capacitance adjustment circuit 18, some or all of the sub-capacitors Cs1 to Csk can be connected to the power supply line 6 for charging the generated charge from the ambient power generation device 100. That is, the sub-capacitor Cs that is additionally connected to the power supply line 6 according to the control signals S1 to Sk corresponds to the "auxiliary capacitor".

[0130] Capacitor 4, serving as the main capacitor, is connected to the power supply line 6 in the same manner as in Embodiment 1. Thus, the generated charge from the ambient power generation device 100 is charged by both capacitor 4 and the sub-capacitor Cs, which is additionally connected via the capacitance adjustment circuit 18. Furthermore, the additional capacitance value added through the connection of the sub-capacitor to the capacitance adjustment circuit 18 can be set to a variable via control signals S1 to Sk, i.e., the setting input 11c for the setting change circuit 11.

[0131] Therefore, in the semiconductor device 10b of Embodiment 2, by configuring the capacitance value adjustment circuit 18, the total capacitance value of the capacitor that charges the generated charge from the ambient power generation device 100 can be adjusted by using the setting input 11c for the setting change circuit 11.

[0132] For environmental power generation devices 100, even products of the same model can have varying power generation capacities due to manufacturing deviations, depending on the production batch (differences in materials, manufacturing date and time, manufacturing equipment, etc.). Therefore, even for environmental power generation devices of the same model, although the differences are not to the extent of model number differences, there are still individuals with lower power generation and individuals with higher power generation.

[0133] In the semiconductor device 10b of Embodiment 2, in accordance with the product deviation of the power generation capacity (charge amount) of the ambient power generation device 100, the total capacitance value of the capacitor that charges the generated charge is finely adjusted by setting input 11c, thereby ensuring proper startup.

[0134] For example, in the manufacturing process of a product equipped with an ambient power generation device 100 and a semiconductor device 10b, the actual amount of charge generated by the ambient power generation device 100 can be measured, and the additional capacitor value based on the capacitor value adjustment circuit 18 can be adjusted according to the amount of charge generated. Furthermore, the start-up determination voltage Vdet is switched by setting the input 11V in relation to the total capacitor value including the adjusted additional capacitor value. Thus, a semiconductor device that can operate appropriately even if there is a large manufacturing deviation in the power generated by the ambient power generation device 100 can be provided.

[0135] Furthermore, the structure of embodiment 2 can also be as follows: Figure 12 The deformation is as shown. Figure 12 In the semiconductor device 10c and signal processing device 200c of the modified embodiment 2 shown, with Figure 11 The difference between the semiconductor device 10b and the signal processing device 200b is that the capacitor 4 (main capacitor) is disposed inside the semiconductor device 10c, which has a capacitance adjustment circuit 18. Even for Figure 12 The structure can also enjoy the same effects produced by the structure of Implementation Method 2.

[0136] Implementation method 3.

[0137] In Embodiment 3, a battery-free multi-rotation encoder using the semiconductor device of Embodiment 1 will be described.

[0138] Figure 13 This is a block diagram illustrating a structural example of a battery-free multi-rotor encoder according to Embodiment 3.

[0139] like Figure 13 As shown, the multi-rotor encoder of Embodiment 3 does not accept power from an external source, detects the rotation direction and speed of the rotating shaft 105, which is the object of detection, and maintains data representing the detection results. The multi-rotor encoder includes a rotation detection mechanism 110 for detecting the rotation of the rotating shaft 105, and a signal processing device 200x electrically connected to the rotation detection mechanism 110.

[0140] The rotation detection mechanism 110 includes a magnet 111 and power generation elements 100a and 100b mounted on the rotation shaft 105. The rotation shaft 105 may be, for example, the output shaft (rotation shaft) of a motor, but can be configured as a rotating body that can rotate in any direction about the shaft.

[0141] Magnet 111 has a circular plate shape and is mounted concentrically relative to the rotation axis 105. Therefore, magnet 111 can rotate clockwise and counterclockwise in conjunction with the rotation axis 105. Furthermore, as long as magnet 111 rotates in conjunction with the rotation of the rotation axis 105, magnet 111 can be mounted on the rotation axis using any configuration. In this embodiment, a structure is shown where magnet 111 has two magnetic poles per half-circumference, but the number of magnetic poles can be arbitrary. Additionally, the shape of magnet 111 is not limited to a circular plate shape.

[0142] The power generation elements 100a and 100b can be composed of a combination of magnetic wires exhibiting the large Backhausen effect disposed above the magnet 111 and on the circumference of the magnet 111's rotation, and a wave-collecting coil. The power generation elements 100a and 100b correspond to the environmental power generation device 100 in embodiments 1 and 2, generating power pulses based on the rotation of the magnet 111 accompanying the rotation of the rotation axis 105. In this embodiment, a structure with two power generation elements 100a and 100b is shown, but the number of power generation elements can be arbitrary.

[0143] The signal processing device 200x includes rectifier circuits 2a and 2b, clamping circuits 3a and 3b, capacitors 4a and 4b, power lines 6a and 6b, and a semiconductor device 10x according to Embodiment 3.

[0144] A power generation pulse is output from power generation element 100a to power line 6a via rectifier circuit 2a. Clamping circuit 3a and capacitor 4a are connected to power line 6a. Similarly, a power generation pulse is output from power generation element 100b to power line 6b via rectifier circuit 2b. Clamping circuit 3b and capacitor 4b are connected to power line 6b.

[0145] In the signal processing apparatus 200x, a rectifier circuit 2, a power line 6, a clamping circuit 3, and a capacitor 4, as described in Embodiment 1, are configured in two separate systems relative to the two power generation elements 100a and 100b. As the generated charge from the power generation element 100a is charged into the capacitor 4a, the generated voltage VPWRa of the power line 6a increases. Similarly, as the generated charge from the power generation element 100b is charged into the capacitor 4b, the generated voltage VPWRb of the power line 6b increases.

[0146] Semiconductor device 10x and Figure 1 Compared to the semiconductor device 10a, the difference lies in that it is equipped with voltage comparison circuits 20 corresponding to the power supply lines 6a and 6b, respectively. Figure 1 The same voltage comparison circuits 20a and 20b are used, and a logic gate 19 is also provided to generate a voltage detection signal VCMP. Furthermore, the constant voltage circuit 13 is activated based on the voltage detection signal VCMP from the logic gate 19. The constant voltage circuit 13, the POR circuit 15, the digital circuit 16, and the non-volatile memory 17 operate with the same functions as described in Embodiment 1.

[0147] Voltage comparator circuit 20a compares the generated voltage VPWRa of power line 6a with the start-up determination voltage Vdet. When VPWRa ≥ Vdet, it outputs signal VCMPa. Similarly, voltage comparator circuit 20b compares the generated voltage VPWRb of power line 6b with the start-up determination voltage Vdet. When VPWRb ≥ Vdet, it outputs signal VCMPb.

[0148] The start-up determination voltage Vdet is set together for voltage comparison circuits 20a and 20b. Similar to Embodiment 1, the start-up determination voltage Vdet can be switched by the setting input 11v for the setting change circuit 11.

[0149] Logic gate 19 outputs the result of the logical AND (OR) operation of signals VCMPa or VCMPb as the voltage detection signal VCMP to the constant voltage circuit 13. Therefore, the constant voltage circuit 13 is started when either the generator voltage VPWRa or VPWRb becomes above the start-up determination voltage Vdet. Then, when the POR circuit 15 detects that the power supply voltage VCORE output from the constant voltage circuit 13 is stable, the reset of the digital circuit 16 is released, and the pre-installed processing begins.

[0150] Furthermore, in embodiment 3, the output signal VCMPa of voltage comparator circuit 20a and the output signal VCMPb of voltage comparator circuit 20b are input to digital circuit 16. Digital circuit 16 can identify, based on these signals VCMPa and VCMPb, which power generation pulse originates from power generation element 100a or 100b to initiate operation.

[0151] The semiconductor device 10x for the multi-rotor encoder is activated each time a power generation pulse with a voltage of at least the start-up determination voltage Vdet is output from the power generation element 100a or 100b, and performs a pre-installed process. In this process, for example, information (count value data) representing the rotational direction and speed of the rotating shaft 105 is read from the non-volatile memory 17. Furthermore, when the information (count value data) representing the multi-rotor value is updated according to a predetermined conversion table and based on the detection of the power generation pulse, the updated information (count value data) representing the multi-rotor value is written to the non-volatile memory 17. Thus, the information (count value data) representing the rotational direction and speed of the rotating shaft 105 is retained in the non-volatile memory 17. Additionally, in the process of reflecting the detected power generation pulse in the count value data, any known technology, such as the technology described in Japanese Patent No. 5511748, can be applied.

[0152] Thus, the battery-free multi-rotor encoder of Embodiment 3 can measure the rotational speed of the rotating shaft 105 in accordance with the detection of the power generation pulses output from the power generation elements 100a and 100b according to the rotation of the rotating shaft 105.

[0153] Furthermore, in the battery-free multi-revolution encoder of Embodiment 3, it is sometimes necessary to change the magnet 111 and / or the power generation elements 100a and 100b in correspondence with the rotation shaft 105 (motor) of the object being detected. In such cases, the amount of charge generated by the ambient power generation device 100 will also change as the magnet 111 or the power generation elements 100a and 100b changes. However, as described in Embodiment 1, by providing a mechanism that adjusts the capacitance value of the capacitor 4 in accordance with the amount of charge generated and sets the start-up determination voltage Vdet in a variable manner in accordance with the capacitance value of the capacitor 4, the semiconductor device 10x can be started appropriately, so that the multi-revolution encoder can operate appropriately.

[0154] Furthermore, in Embodiment 3, an example is shown where the power generation elements 100a and 100b are composed of a combination of magnetic wire and a pickup coil, but the power generation elements are not limited to such a structure. For example, when the rotational speed of the rotating shaft 105 is high, the power generation element can be constructed solely of a coil, and power can be generated through electromagnetic induction.

[0155] Implementation method 4.

[0156] In the multi-rotor encoder of embodiment 3, the digital circuit 16 operates in accordance with the generator pulse making the generator voltage VPWR (VPWRa, VPWRb) above the start determination voltage Vdet, thereby measuring the rotational speed of the rotating shaft 105, wherein the generator pulse is generated based on the rotation of the rotating shaft 105.

[0157] Therefore, even if a power generation pulse is generated, if the power generation voltage VPWR (VPWRa, VPWRb) does not rise to the start-up determination voltage Vdet, the multi-rotor encoder cannot recognize the generation of the power generation pulse. Therefore, even if the rotating shaft 105 rotates, the rotational speed of the rotating shaft 105 may not be accurately measured due to the omission of detection of the power generation pulse, which is called pulse loss.

[0158] exist Figure 14 The diagram shows a conceptual waveform of the power generation pulse used to illustrate pulse loss.

[0159] like Figure 14 As shown, the generated voltage VPWR changes in response to the generation of generated pulses PLS1 to PLS4. Furthermore, the waveforms of generated pulses PLS1 to PLS4 are shown after passing through rectifier circuits 2 (2a, 2b). However, when generated pulse PLS2 is generated, the generated voltage VPWR does not rise to the start-up determination voltage Vdet. Therefore, in the semiconductor device 10x, the generation of generated pulses PLS1, PLS3, and PLS4 can be detected based on the comparison between the generated voltage VPWR and the start-up determination voltage Vdet; on the other hand, the generation of generated pulse PLS2 cannot be detected. Thus, low-voltage generated pulses are generated with a certain probability corresponding to the rotation of the rotating shaft 105, which may lead to pulse loss.

[0160] Furthermore, if the technology described in Japanese Patent No. 5511748 is applied, even in the event of pulse loss, it can sometimes be restored via subsequent power generation pulses. Figure 14 The rotational speed of the rotating shaft 105 is accurately and continuously measured by correcting the detection of the generated pulses (PLS3, PLS4). However, when pulse loss occurs repeatedly, the above correction may become difficult. In this case, the operation of the multi-rotor encoder is stopped as needed, and a warning is sent to the upper-level system. Although the frequency of such uncorrectable pulse loss is low, it is not entirely nonexistent. Therefore, by reducing the frequency of pulse loss, the probability of the multi-rotor encoder stopping can be reduced.

[0161] Figure 15 This is a block diagram illustrating the structure of the battery-free multi-rotor encoder of Embodiment 4.

[0162] like Figure 15As shown, the multi-rotor encoder of Embodiment 4 includes the same rotation detection mechanism 110 as that of Embodiment 3, and a signal processing device 200y electrically connected to the rotation detection mechanism 110. That is, the multi-rotor encoder of Embodiment 4 differs from the multi-rotor encoder of Embodiment 3 in that it includes a signal processing device 200y instead of a signal processing device 200x. Figure 13 ).

[0163] The signal processing device 200y includes a power terminal 201 for inputting an external power supply voltage VDD, a power supply circuit 8, and a semiconductor device 10y according to Embodiment 4. The semiconductor device 10y differs from the semiconductor device 10x of Embodiment 3 in that it also includes a power line 6c, a power switching circuit 23, and an external power supply detection circuit 28. The power line 6c is equivalent to a "power node".

[0164] The power supply circuit 8 converts the external power supply voltage VDD input to the power supply terminal 201 into a DC voltage equivalent to the input voltage of the constant voltage circuit 13. The DC voltage from the power supply circuit 8 is output to the power supply line 6c. The external power supply detection circuit 28 detects whether an external power supply voltage has been input. Hereinafter, the state with an external power supply voltage input and the state without an external power supply input will be referred to as "external power supply on" and "external power supply off," respectively.

[0165] For example, the external power supply detection circuit 28 detects whether the external power supply is on or off by comparing a judgment voltage determined according to the input voltage level input to the constant voltage circuit 13 with the power supply line 6c. The detection result of the external power supply detection circuit 28 is transmitted to the power switching circuit 23, the constant voltage circuit 13, and the digital circuit 16.

[0166] When the external power supply is turned on, the power switching circuit 23 connects the power line 6c to the input side of the constant voltage circuit 13. On the other hand, when the external power supply is turned off, the power switching circuit 23 connects the power lines 6a and 6b to the input side of the constant voltage circuit 13.

[0167] Therefore, in semiconductor device 10y, the operation when the external power supply is disconnected is the same as that of semiconductor device 10x. That is, the power supply voltage VCORE of semiconductor device 10y is generated by the generated voltages VPWRa and VPWRb from power lines 6a and 6b. On the other hand, when the external power supply is turned on, the power supply voltage VCORE is generated by the external power supply voltage input to power terminal 201. When the external power supply is turned on, the power of the generated pulses is only used as the power supply for the setting change circuit 11 and the voltage comparison circuits 20a and 20b, as well as the comparator 24 ( Figures 7-9 The input voltage is such that there is no need to ensure connection with the generator pulse. Figure 10The charge Qstr described herein corresponds to energy. As a result, the power (or charge) required for the generation pulse is reduced compared to when the external power supply is disconnected. Therefore, even if the start-up determination voltage Vdet is lowered compared to when the external power supply is disconnected, the semiconductor device 10y can still be started.

[0168] Therefore, the semiconductor device of Embodiment 4 is characterized in that the start-up determination voltage Vdet is switched between when the external power supply is turned on and when the external power supply is turned off.

[0169] exist Figure 16 The diagram shows a conceptual waveform for illustrating the setting of the start-up determination voltage Vdet in the semiconductor device of Embodiment 4.

[0170] like Figure 16 As shown, in the semiconductor device of Embodiment 4, the start-up determination voltage Vdet when the external power supply is turned on during times ta to tb is set lower than the start-up determination voltage Vdet when the external power supply is turned off (before time ta and after time tb). Therefore, Figure 14 The PLS2 can detect power generation pulses that were previously undetectable, thereby reducing the probability of pulse loss. That is, the state of external power supply being on corresponds to "state 1", and the state of external power supply being off corresponds to "state 2".

[0171] use Figure 17 and Figure 18 To explain the use of Figure 16 The example shown illustrates the structure of a voltage comparison circuit and a setting change circuit that enable the switching of the start-up determination voltage Vdet.

[0172] exist Figure 17 In the middle, it is shown that it is used for... Figure 7 The voltage comparison circuit 20 and setting change circuit 11 shown are mechanisms for switching the start-up determination voltage Vdet between external power supply being turned on and external power supply being turned off.

[0173] Figure 17 The voltage comparator circuit 20 shown is... Figure 7 Compared to the voltage comparator circuit 20, the difference lies in the inclusion of a selector 26 and a pull-down resistor 27. The selector 26 selects one of the control signal Ssg from the setting change circuit 11 and the control signal Ssg from the digital circuit 16 based on the voltage level of node Nz, and transmits it to the appropriate circuit. Figure 7 The same voltage divider circuit 22X. Digital circuit 16 can output a control signal Ssg set according to a pre-configured control. Alternatively, as shown by the dashed line in the figure, the control signal Ssg can also be set or changed by writing data that generates the control signal Ssg to digital circuit 16.

[0174] When the external power supply is disconnected, digital circuit 16 cannot operate until the generated voltage VPWR rises. Therefore, node Nx is set to ground voltage GND (L level) through pull-down resistor 27. At this time, selector 26 transmits the control signal Ssg from setting change circuit 11, which is input to the "0" side, to voltage divider circuit 22X.

[0175] In contrast, when the external power supply is turned on, the digital circuit 16 can output a voltage of H level (VCORE) to node Nx through the power supply voltage VCORE generated by the external power supply voltage, and output a preset control signal Ssg. Correspondingly, the selector 26 transmits the control signal Ssg input to the "1" side from the digital circuit 16 to the voltage divider circuit 22X.

[0176] Therefore, when the external power supply is disconnected, similar to Embodiment 1, the voltage division ratio of the voltage divider circuit 22X is changed according to the control signal Ssg for the setting input 11v of the setting change circuit 11, thereby allowing the start-up determination voltage Vdet to be set variably. Furthermore, when the external power supply is connected, the voltage division ratio of the voltage divider circuit 22X is changed according to the control signal Ssg for the setting input 11d pre-input to the digital circuit 16, thereby allowing the start-up determination voltage Vdet to be set variably.

[0177] exist Figure 18 In the middle, it is shown that it is used for... Figure 8 The voltage comparison circuit 20 and setting change circuit 11 shown are mechanisms for switching the start-up determination voltage Vdet between when the external power supply is turned on and when the external power supply is turned off.

[0178] Figure 18 The voltage comparator circuit 20 shown is... Figure 8 Compared to the voltage comparator circuit 20, the difference is that it also includes... Figure 17 The same selector 26 and pull-down resistor 27. Figure 18 In this structure, when the external power supply is off, selector 26 also transmits the control signal Ssg from the setting change circuit 11, which is input to the "0" side, to the D / A converter 25. Conversely, when the external power supply is on, selector 26 transmits the control signal Ssg from the digital circuit 16, which is input to the "1" side, to the D / A converter 25.

[0179] Therefore, when the external power supply is disconnected, similar to Embodiment 1, the reference voltage VREF is changed according to the control signal Ssg for the setting input 11v of the setting change circuit 11, thereby allowing the start-up determination voltage Vdet to be set variably. Furthermore, when the external power supply is connected, the reference voltage VREF is changed according to the control signal Ssg preset according to the setting input 11d of the digital circuit 16, thereby allowing the start-up determination voltage Vdet to be set variably.

[0180] As a result, according to Figure 17 and Figure 18 Each of its structures allows for the variable setting of the start-up determination voltage Vdet when the external power supply is connected and the start-up determination voltage Vdet when the external power supply is disconnected. Furthermore, in Figure 17 and Figure 18 In the structure, by setting the setting inputs 11v and 11d, the start-up determination voltage Vdet set by the control signal Ssg from the digital circuit 16 is lower than the start-up determination voltage Vdet set by the control signal Ssg from the setting change circuit 11, thereby enabling... Figure 16 The switching of the start-up determination voltage Vdet is shown. That is, the start-up determination voltage Vdet when the external power supply is turned on can be set to be lower than the start-up determination voltage Vdet when the external power supply is turned off.

[0181] Or, in settings Figure 9 With such a terminal 11x, it is possible to switch the analog voltage input from the outside as the reference voltage VREF in conjunction with the supply of the external power supply voltage VDD.

[0182] A variation of implementation method 4.

[0183] exist Figure 19 The diagram shows a block diagram illustrating a modified example of the semiconductor device and the multi-rotor encoder of Embodiment 4.

[0184] like Figure 19 As shown, the semiconductor device 10z in the modified example of Embodiment 4 differs from the semiconductor device 10y in that it also includes capacitor value adjustment circuits 18a and 18b, which are the same as those in Embodiment 2. The capacitor value adjustment circuits 18a and 18b are connected to power lines 6a and 6b, respectively. Similar to Embodiment 2, the additional capacitor value connected via capacitor value adjustment circuits 18a and 18b can be adjusted jointly using control signals from the setting change circuit 11. Figure 19 The signal processing device 200z shown is configured with a semiconductor device 10z equipped with capacitor value adjustment circuits 18a and 18b.

[0185] Like semiconductor device 10y, semiconductor device 10z can also operate via an external power supply voltage VDD input to power terminal 201. However, as described above, the power (or charge) required for the power generation pulse is smaller when the external power supply is on compared to when it is off. Therefore, in semiconductor device 10z, the voltage of the power generation pulse may exceed the maximum operating voltage when the external power supply is on.

[0186] Therefore, in the semiconductor device 10z, when the external power supply is turned on, in order to reduce the voltage of the power generation pulse, it is preferable to incorporate control that makes the capacitance value (additional capacitance value) of the sub-capacitor additionally connected through the capacitance value adjustment circuit 18 (18a, 18b) larger than when the external power supply is turned off.

[0187] For example, by using Figure 17 and Figure 18 With the same circuit structure, when the external power supply is disconnected, the control signal for the capacitor value adjustment circuit 18 (18a, 18b) can be generated using the control signal from the setting change circuit 11. On the other hand, when the external power supply is turned on, the control signal for the capacitor value adjustment circuit 18 can be generated using the control signal from the digital circuit 16. Therefore, the additional capacitor value based on the capacitor value adjustment circuit 18 (18a, 18b) can be variably set between when the external power supply is turned on and when it is disconnected. Furthermore, the setting input 11c for the setting change circuit 11 and the setting input 11d for the digital circuit 16 can be set such that the additional capacitor value set using the control signal from the digital circuit 16 is greater than the additional capacitor value set using the control signal from the setting change circuit 11. This reduces the voltage of the power generation pulse when the external power supply is turned on.

[0188] In addition, Figure 14 In the semiconductor device 10y shown, it is also possible to connect with... Figure 19 The same capacitor adjustment circuits 18a and 18b are connected to power lines 6a and 6b, which are omitted from the diagram.

[0189] Furthermore, in this embodiment, an environmental power generation device 100 is assumed to intermittently output positive or negative voltage power generation pulses. However, for an environmental power generation device 100 that only intermittently outputs positive voltage power generation pulses, the semiconductor device and multi-rotor encoder of this embodiment can also be applied. In this case, the device that omits... Figure 1 The configuration of the rectifier circuits 2 (2a, 2b) described in the specification is as follows. Furthermore, regarding the various embodiments described above, including combinations not mentioned in the specification, the structures described in each embodiment can be appropriately combined without causing mismatches or contradictions. This was intended from the very beginning of this application, and is hereby confirmed.

[0190] The embodiments disclosed herein are illustrative in all respects and should not be considered limiting. The scope of this disclosure is shown in the claims rather than the foregoing description, and includes all modifications within the same meaning and scope as the claims.

[0191] Explanation of reference numerals in the attached figures

[0192] 2. Rectifier circuits (2a, 2b); 3. Clamping circuits (3a, 3b); 4. Capacitors (4a, 4b); 6. Power lines (6a, 6b, 6c); 7. Grounding wire; 8. Power supply circuit; 10a-10c, 10x-10z semiconductor devices; 11. Setting change circuit; 11c, 11V setting input; 11x terminal; 12. Fine-tuning elements (121-12n); 13. Constant voltage circuit; 15. POR circuit; 16. Digital circuit; 17. Non-volatile memory; 18. Capacitor value adjustment circuits (18a, 18b); 19. Logic gate; 20. Voltage comparator circuits (20a, 20b); 21. Resistor elements (22X, 22Y); 23. Power switching circuit; 24. Comparator; 25. Digital-to-analog converter; 26. Selector; 27. Pull-down resistor; 28. External power supply detection circuit; 100. Ambient light. Power generation device, 100a, 100b power generation elements, 105 rotating shaft, 110 rotating detection mechanism, 111 magnet, 200a~200c, 200x~200z signal processing device, 201 power supply terminal, Cchg, Cchg1~Cchg3 capacitance values, Cs, Cs1~Csk sub-capacitors, GND grounding voltage, PLS1~PLS4 power generation pulses, S1~Sk, Ssg control signals, SW1~SWk switches, VCMP voltage detection signal, VCORE power supply voltage, VDD external power supply voltage, VDIV voltage divider, VPWR, VPWRa, VPWRb power generation voltage, VREF reference voltage, Vdet start-up judgment voltage, Vmax upper limit voltage, Vopmax maximum operating voltage, Vopmin minimum operating voltage.

Claims

1. A semiconductor device which is connected with a power line to which a generated charge of an environmental power generation device is output, wherein the semiconductor device comprises: a voltage comparison circuit which outputs a voltage detection signal when a generated voltage which corresponds to a charging voltage of a capacitor connected with the power line is equal to or higher than a start determination voltage which is variable; an internal circuit which is started in response to the voltage detection signal from the voltage comparison circuit; and a setting change circuit which switches the start determination voltage in accordance with a first setting input, wherein the start determination voltage in a case where the capacitor has a first capacitance value is set to a voltage which is higher than the start determination voltage in a case where the capacitor has a second capacitance value which is larger than the first capacitance value.

2. The semiconductor device according to claim 1, wherein the start determination voltage is set to a sum of a value obtained by dividing a predetermined consumed charge amount for the internal circuit to perform a predetermined processing after start-up by a capacitance value of the capacitor and a predetermined minimum operating voltage of the semiconductor device.

3. A semiconductor device which is connected with a power line to which a generated charge of an environmental power generation device is output, wherein the semiconductor device comprises: a voltage comparison circuit which outputs a voltage detection signal when a generated voltage which corresponds to a charging voltage of a capacitor connected with the power line is equal to or higher than a start determination voltage which is variable; an internal circuit which is started in response to the voltage detection signal from the voltage comparison circuit; and a setting change circuit which switches the start determination voltage in accordance with a first setting input, wherein the start determination voltage is set to a sum of a value obtained by dividing a predetermined consumed charge amount for the internal circuit to perform a predetermined processing after start-up by a capacitance value of the capacitor and a predetermined minimum operating voltage of the semiconductor device.

4. The semiconductor device according to any one of claims 1 to 3, wherein the voltage comparison circuit includes: a voltage dividing circuit which divides the generated voltage; and a comparator which compares a divided voltage output from the voltage dividing circuit with a predetermined reference voltage and outputs the voltage detection signal, the setting change circuit generates a first control signal in accordance with the first setting input, and the voltage dividing circuit is configured to make a voltage dividing ratio variable in accordance with the first control signal.

5. The semiconductor device according to any one of claims 1 to 3, wherein the setting change circuit generates a first control signal in accordance with the first setting input, the voltage comparison circuit includes: a voltage dividing circuit which divides the generated voltage; a voltage generator which outputs a reference voltage in accordance with the first control signal; and a comparator which compares a divided voltage after being divided by the voltage dividing circuit with the reference voltage output from the voltage generator and outputs the voltage detection signal. ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ 6. The semiconductor device according to any one of claims 1 to 3, wherein the setting change circuit includes a first terminal for inputting an analog voltage from outside of the semiconductor device as the first setting input, the voltage comparison circuit includes: a voltage dividing circuit that divides the generated voltage; and a comparator that compares a divided voltage output from the voltage dividing circuit with an input voltage input to the first terminal, and outputs the voltage detection signal.

7. The semiconductor device according to claim 4, wherein the setting change circuit has a plurality of first trimming elements capable of being finely adjusted by the first setting input, the setting change circuit generates the first control signal as a first digital signal that sets a ground voltage and the generated voltage as a logic low level and a logic high level, respectively, each bit of the first digital signal is set to one of the logic low level and the logic high level in accordance with presence or absence of fine adjustment of each of the first trimming elements.

8. The semiconductor device according to claim 5, wherein the setting change circuit has a plurality of first trimming elements capable of being finely adjusted by the first setting input, the setting change circuit generates the first control signal as a first digital signal that sets a ground voltage and the generated voltage as a logic low level and a logic high level, respectively, each bit of the first digital signal is set to one of the logic low level and the logic high level in accordance with presence or absence of fine adjustment of each of the first trimming elements.

9. The semiconductor device according to any one of claims 1 to 3, wherein the setting change circuit further accepts a second setting input, and generates a second control signal in accordance with the second setting input, the semiconductor device further includes a capacitance value adjustment circuit that connects an auxiliary capacitor to the power supply line, the auxiliary capacitor having a variable additional capacitance value corresponding to the second control signal.

10. The semiconductor device according to claim 4, wherein the setting change circuit further accepts a second setting input, and generates a second control signal in accordance with the second setting input, the semiconductor device further includes a capacitance value adjustment circuit that connects an auxiliary capacitor to the power supply line, the auxiliary capacitor having a variable additional capacitance value corresponding to the second control signal.

11. The semiconductor device according to claim 5, wherein the setting change circuit further accepts a second setting input, and generates a second control signal in accordance with the second setting input, the semiconductor device further includes a capacitance value adjustment circuit that connects an auxiliary capacitor to the power supply line, the auxiliary capacitor having a variable additional capacitance value corresponding to the second control signal.

12. The semiconductor device according to claim 6, wherein the setting change circuit further accepts a second setting input, and generates a second control signal in accordance with the second setting input, The semiconductor device further includes a capacitance adjustment circuit that connects an auxiliary capacitor having a variable additional capacitance value corresponding to the second control signal to the power supply line.

13. The semiconductor device according to claim 9, wherein the setting change circuit further includes a plurality of second trimming elements capable of being finely adjusted by the second setting input, the setting change circuit generates the second control signal as a first digital signal that sets a ground voltage and the generated voltage as a logic low level and a logic high level, respectively, of a second digital signal, each bit of the second digital signal is set to one of the logic low level and the logic high level in accordance with the presence or absence of fine adjustment of each of the second trimming elements.

14. The semiconductor device according to any one of claims 10 to 12, wherein the setting change circuit further includes a plurality of second trimming elements capable of being finely adjusted by the second setting input, the setting change circuit generates the second control signal as a first digital signal that sets a ground voltage and the generated voltage as a logic low level and a logic high level, respectively, of a second digital signal, each bit of the second digital signal is set to one of the logic low level and the logic high level in accordance with the presence or absence of fine adjustment of each of the second trimming elements.

15. The semiconductor device according to claim 9, wherein the semiconductor device further includes: a power supply node that receives an input of an external power supply voltage from an outside of the semiconductor device; an external power supply detection circuit that detects the input of the external power supply voltage based on a voltage of the power supply node; and a power supply switching circuit that switches between a first state in which the power supply voltage of the internal circuit is generated from the generated voltage of the power supply line and a second state in which the power supply voltage is generated from the external power supply voltage of the power supply node based on a detection result of the external power supply detection circuit, the voltage comparison circuit controls the additional capacitance value to a first value in accordance with the second control signal in the first state and controls the additional capacitance value to a second value larger than the first value in the second state based on the detection result of the external power supply detection circuit.

16. The semiconductor device according to any one of claims 10 to 13, wherein the semiconductor device further includes: a power supply node that receives an input of an external power supply voltage from an outside of the semiconductor device; an external power supply detection circuit that detects the input of the external power supply voltage based on a voltage of the power supply node; and a power supply switching circuit that switches between a first state in which the power supply voltage of the internal circuit is generated from the generated voltage of the power supply line and a second state in which the power supply voltage is generated from the external power supply voltage of the power supply node based on a detection result of the external power supply detection circuit, the voltage comparison circuit controls the additional capacitance value to a first value in accordance with the second control signal in the first state and controls the additional capacitance value to a second value larger than the first value in the second state based on the detection result of the external power supply detection circuit. ​ The voltage comparison circuit controls the additional capacitance value to a first value in the first state and controls the additional capacitance value to a second value larger than the first value in the second state based on the detection result of the external power supply detection circuit in accordance with the second control signal.

17. The semiconductor device according to claim 14, wherein the semiconductor device further comprises: a power supply node configured to accept an input of an external power supply voltage from outside of the semiconductor device; an external power supply detection circuit configured to detect the input of the external power supply voltage based on a voltage of the power supply node; and a power supply switching circuit configured to switch between a first state in which the power supply voltage of the internal circuit is generated from the generated voltage of the power supply line and a second state in which the power supply voltage is generated from the external power supply voltage of the power supply node based on a detection result of the external power supply detection circuit, the voltage comparison circuit controls the additional capacitance value to a first value in the first state and controls the additional capacitance value to a second value larger than the first value in the second state based on the detection result of the external power supply detection circuit in accordance with the second control signal.

18. The semiconductor device according to any one of claims 1 to 3, 7 to 8, 10 to 13, wherein the semiconductor device further comprises: a power supply node configured to accept an input of an external power supply voltage from outside of the semiconductor device; an external power supply detection circuit configured to detect the input of the external power supply voltage based on a voltage of the power supply node; and a power supply switching circuit configured to switch between a first state in which the power supply voltage of the internal circuit is generated from the external power supply voltage of the power supply node and a second state in which the power supply voltage is generated from the generated voltage of the power supply line based on a detection result of the external power supply detection circuit, the voltage comparison circuit switches the start determination voltage between the first state and the second state such that the start determination voltage is set lower in the first state than in the second state based on the detection result of the external power supply detection circuit.

19. The semiconductor device according to any one of claims 1 to 3, 7 to 8, 10 to 13, wherein the internal circuit includes: a constant voltage circuit configured to generate a power supply voltage as an input from the generated voltage of the power supply line in response to the voltage detection signal; a digital circuit configured to operate using the power supply voltage from the constant voltage circuit; and a nonvolatile memory configured to input and output data between the digital circuit while the digital circuit is operating.

20. The semiconductor device according to any one of claims 1 to 3, 7 to 8, 10 to 13, wherein the internal circuit includes: a constant voltage circuit configured to generate a power supply voltage as an input from the generated voltage of the power supply line in response to the voltage detection signal; and a digital circuit which operates using the power supply voltage from the constant voltage circuit, the digital circuit performs reading and writing of data between a nonvolatile memory which is arranged outside the semiconductor device when the digital circuit operates.

21. The semiconductor device according to claim 19, wherein the semiconductor device further comprises: a power supply node for inputting an external power supply voltage from outside the semiconductor device; an external power supply detection circuit which detects input of the external power supply voltage based on a voltage of the power supply node; and a power supply switching circuit which connects the power supply node to the constant voltage circuit when the external power supply voltage is input, and connects the power supply line to the constant voltage circuit when the external power supply voltage is not input, based on a detection result of the external power supply detection circuit, the voltage comparison circuit is configured to set the start determination voltage lower when the external power supply voltage is input than when the external power supply voltage is not input, based on the detection result of the external power supply detection circuit.

22. The semiconductor device according to claim 20, wherein the semiconductor device further comprises: a power supply node for inputting an external power supply voltage from outside the semiconductor device; an external power supply detection circuit which detects input of the external power supply voltage based on a voltage of the power supply node; and a power supply switching circuit which connects the power supply node to the constant voltage circuit when the external power supply voltage is input, and connects the power supply line to the constant voltage circuit when the external power supply voltage is not input, based on a detection result of the external power supply detection circuit, the voltage comparison circuit is configured to set the start determination voltage lower when the external power supply voltage is input than when the external power supply voltage is not input, based on the detection result of the external power supply detection circuit.

23. The semiconductor device according to claim 21 or 22, wherein the digital circuit performs a series of processes of detecting the generated power voltage as an input pulse when the generated power voltage having a voltage of the start determination voltage or more is detected, reading count value data from the nonvolatile memory when the input pulse is detected, updating the count value data in accordance with the detection, and writing the updated count value data into the nonvolatile memory.

24. A semiconductor device which is connected to a power supply line to which a generated charge of an environmental power generation device is output, wherein the semiconductor device comprises: a voltage comparison circuit which outputs a voltage detection signal when a generated power voltage which corresponds to a charging voltage of a capacitor connected to the power supply line is the start determination voltage or more, the start determination voltage being variable; an internal circuit which is started in response to the voltage detection signal from the voltage comparison circuit; and a setting change circuit which switches the start determination voltage in accordance with a first setting input, the setting change circuit further accepts a second setting input, and generates a second control signal in accordance with the second setting input. ​ The semiconductor device further includes a capacitance adjustment circuit for connecting an auxiliary capacitor having a variable additional capacitance corresponding to the second control signal to the power line.

25. A semiconductor device connected to a power line to which a power generation charge from an environmental power generation device is output, wherein The semiconductor device includes: a voltage comparison circuit for outputting a voltage detection signal when a power generation voltage corresponding to a charging voltage of a capacitor connected to the power line is equal to or higher than a start determination voltage which is variable; an internal circuit which is started in response to the voltage detection signal from the voltage comparison circuit; a setting change circuit which switches the start determination voltage in accordance with a first setting input; a power supply node for accepting an input of an external power supply voltage from outside the semiconductor device; an external power supply detection circuit which detects the input of the external power supply voltage based on a voltage of the power supply node; and a power supply switching circuit which switches between a first state in which the power supply voltage of the internal circuit is generated from the external power supply voltage of the power supply node and a second state in which the power supply voltage is generated from the power generation voltage of the power line based on a detection result of the external power supply detection circuit, the voltage comparison circuit switches the start determination voltage between the first state and the second state based on the detection result of the external power supply detection circuit so that the start determination voltage is set lower in the first state than in the second state.

26. A multi-turn encoder for detecting a rotational speed of a rotational shaft, wherein The multi-turn encoder includes the semiconductor device according to any one of claims 1 to 25, the environmental power generation device is configured from a power generation element using a magnetic wire having a large Barkhausen effect which is installed on a magnet which rotates in conjunction with the rotational shaft, the internal circuit is started each time a voltage pulse having the power generation voltage equal to or higher than the start determination voltage is output from the power generation element, and counts a multi-turn value of the rotational shaft. ​

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