Temperature sensing circuit

Abstract

The application discloses a temperature sensing circuit, which comprises a temperature detecting unit and a data processing unit, wherein the temperature detecting unit is coupled with the data processing unit, is adapted to generate a temperature detecting signal with a frequency corresponding to the temperature of the current environment and is adapted to output; the temperature detecting unit comprises a temperature sensing module, the temperature sensing module is composed of N PMOS tubes, and the gate and the drain of the N PMOS tubes are connected with each other; N is greater than or equal to 2; the data processing unit is adapted to receive the temperature detecting signal, and is adapted to determine the temperature value of the current environment according to the frequency of the output signal. By using the above scheme, the circuit structure of the temperature sensor circuit can be simplified, and the process complexity can be reduced.

Description

Technical Field

[0001] This invention relates to the field of temperature detection technology, and more particularly to a temperature sensing circuit. Background Technology

[0002] Temperature is one of the most common measurement variables in daily life. Temperature sensing circuits are widely used in electronic devices to detect the current operating environment temperature and then adjust certain parameters in the electronic devices (such as the oscillation frequency of the oscillator).

[0003] In existing technologies, temperature sensors typically use thermistors to sense temperature and analog-to-digital converters to convert the temperature data from analog to digital, resulting in complex circuit structures and manufacturing processes. Summary of the Invention

[0004] The embodiments of the present invention address the technical problems of complex circuit structure and manufacturing process of temperature sensing circuits.

[0005] To address the aforementioned technical problems, this invention provides a temperature sensing circuit, comprising: a temperature detection unit and a data processing unit, wherein: the temperature detection unit is coupled to the data processing unit and is adapted to generate and output a temperature detection signal with a frequency corresponding to the current ambient temperature; the temperature detection unit includes a temperature sensing module composed of N PMOS transistors, wherein the gates and drains of the N PMOS transistors are interconnected; N≥2; the data processing unit is adapted to receive the temperature detection signal and determine the current ambient temperature value based on the frequency of the output signal.

[0006] Optionally, the temperature detection unit further includes a first inverting module, a second inverting module, and a capacitor, wherein: the input terminal of the first inverting module is coupled to the second terminal of the capacitor, and its output terminal is coupled to the input terminal of the second inverting module; the output terminal of the second inverting module is coupled to the first terminal of the capacitor and the output terminal of the temperature detection unit; the temperature sensing module has its first terminal coupled to the output terminal of the first inverting module, and its second terminal coupled to the input terminal of the first inverting module.

[0007] Optionally, the temperature sensing module includes a first PMOS transistor and a second PMOS transistor, wherein: the source of the first PMOS transistor is coupled to the output terminal of the first inverting module, its gate is coupled to the gate and drain of the second PMOS transistor, and its drain is coupled to the drain of the second PMOS transistor; the source of the second PMOS transistor is coupled to the input terminal of the first inverting module.

[0008] Optionally, the substrate of the first PMOS transistor is coupled to the output terminal of the first inverting module, and the substrate of the second PMOS transistor is coupled to the input terminal of the first inverting module.

[0009] Optionally, the first inverting module includes a third PMOS transistor and a first NMOS transistor, wherein: the source of the third PMOS transistor is coupled to the power supply terminal of the first inverting module, its gate is coupled to the input terminal of the first inverting module, and its drain is coupled to the output terminal of the first inverting module; the gate of the first NMOS transistor is coupled to the gate of the third PMOS transistor, its drain is coupled to the drain of the third PMOS transistor, and its source is coupled to the ground terminal of the first inverting module.

[0010] Optionally, the second inverting module includes a fourth PMOS transistor and a second NMOS transistor, wherein: the source of the fourth PMOS transistor is coupled to the power supply terminal of the second inverting module, its gate is coupled to the output terminal of the first inverting module, and its drain is coupled to the output terminal of the second inverting module; the gate of the second NMOS transistor is coupled to the gate of the fourth PMOS transistor, its drain is coupled to the drain of the fourth PMOS transistor, and its source is coupled to the ground terminal of the second inverting module.

[0011] Optionally, the capacitor is a MOM capacitor.

[0012] Optionally, the data processing unit includes a first D flip-flop, a pulse counter, a rising edge data flip-flop, and a decoder, wherein: the first D flip-flop receives the temperature detection signal at its clock input terminal, its data input terminal is coupled to its inverted output terminal, its non-inverted output terminal is coupled to the enable input terminal of the pulse counter and the data input terminal of the second D flip-flop, and its inverted output terminal is coupled to the latch-on indicator terminal of the decoder and the control terminal of the rising edge data flip-flop; the second D flip-flop has its non-inverted output terminal coupled to the low-level synchronous reset terminal of the pulse counter; the pulse counter has its pulse counting output terminal coupled to the data input terminal of the rising edge data flip-flop; the rising edge data flip-flop has its output terminal coupled to the data input terminal of the decoder; and the decoder is adapted to determine the current ambient temperature value based on the output of the rising edge data flip-flop.

[0013] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:

[0014] The temperature detection unit forms an oscillation circuit, outputting a temperature detection signal with a frequency corresponding to the current ambient temperature. The data processing unit measures the frequency of the temperature detection signal to determine the current ambient temperature. The temperature sensing module in the temperature detection unit consists of N PMOS transistors, eliminating the need for dedicated thermistors. Therefore, the entire temperature sensing circuit can be composed of basic components such as MOS transistors and capacitors, simplifying the circuit structure, and the manufacturing processes for MOS transistors are relatively mature. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of the structure of a temperature sensing circuit according to an embodiment of the present invention;

[0016] Figure 2 This is an equivalent circuit diagram of a temperature sensing module in an embodiment of the present invention;

[0017] Figure 3 This is a schematic diagram showing the change in resistance of a temperature sensing module as a function of temperature in an embodiment of the present invention.

[0018] Figure 4 This is a waveform diagram of the working state of a temperature detection unit in an embodiment of the present invention;

[0019] Figure 5 This is a timing diagram of a data processing unit in an embodiment of the present invention. Detailed Implementation

[0020] As described in the background section above, in the prior art, temperature sensors typically use thermistors to sense temperature and analog-to-digital converters to convert the temperature data from analog to digital, resulting in complex circuit structures and manufacturing processes.

[0021] In this invention, the temperature detection unit forms an oscillation circuit, outputting a temperature detection signal with a frequency corresponding to the current ambient temperature. The data processing unit measures the frequency of the temperature detection signal to determine the current ambient temperature. The temperature sensing module in the temperature detection unit consists of N PMOS transistors, eliminating the need for dedicated thermistors. Therefore, the entire temperature sensing circuit can be composed of basic components such as MOS transistors and capacitors, simplifying the circuit structure. Furthermore, the manufacturing processes for MOS transistors are relatively mature, reducing the demands on manufacturing processes.

[0022] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0023] Reference Figure 1 The present invention provides a temperature sensing circuit according to an embodiment of the present invention. The following is in conjunction with… Figure 1 Please provide an explanation.

[0024] In this embodiment of the invention, the temperature sensing circuit may include a temperature detection unit and a data processing unit.

[0025] In practical implementation, the temperature detection unit can be coupled to the data processing unit. The temperature detection unit can detect the temperature of the current environment, generate a temperature detection signal with a frequency corresponding to the current environment temperature, and output the temperature detection signal to the data processing unit.

[0026] The data processing unit can receive temperature detection signals and reconstruct the current ambient temperature based on the frequency of the temperature detection signals.

[0027] In this embodiment of the invention, the temperature detection unit may include a temperature sensing module. Specifically, the temperature sensing module may consist of N PMOS transistors, and the gates and drains of the N PMOS transistors are interconnected; N≥2.

[0028] Reference Figure 2 An equivalent circuit diagram of a temperature sensing module in an embodiment of the present invention is provided. Figure 2 In this temperature sensing module, two PMOS transistors are used. The gate of the first PMOS transistor P1 is coupled to its drain, and also to the gate and drain of the second PMOS transistor P2. Thus, the two PMOS transistors form a diode structure. A parasitic body diode D1 is formed between the substrate and drain of the first PMOS transistor P1, and a parasitic body diode D2 is formed between the substrate and drain of the second PMOS transistor P2. Due to its symmetrical structure, there are two diodes connected in series (the diode structure formed by P1 and P2, and either body diode D1 or D2) from point X to point Y, or from point Y to point X. The equivalent resistance of the temperature sensing module is between 80MΩ and 60GΩ, which is extremely high.

[0029] Under a fixed voltage, the current flowing through the diode increases with increasing temperature. As a result, the equivalent resistance of the temperature sensing module decreases with increasing temperature, thus enabling the detection of temperature changes.

[0030] In a specific implementation, the temperature detection unit may further include a first inverting module, a second inverting module, and a capacitor, wherein:

[0031] The input terminal of the first inverting module is coupled to the second terminal of the capacitor, and the output terminal of the first inverting module is coupled to the input terminal of the second inverting module.

[0032] The output terminal of the second inverting module is coupled to the first terminal of the capacitor and the output terminal of the temperature detection unit.

[0033] The first terminal of the temperature sensing module is coupled to the output terminal of the first inverting module, and the second terminal of the temperature sensing module is coupled to the input terminal of the first inverting module.

[0034] The first end of the capacitor is coupled to the output of the second inverting module, and the second end of the capacitor is coupled to the input of the first inverting module.

[0035] Specifically, refer to Figure 1 The temperature sensing module may include a first PMOS transistor MP1 and a second PMOS transistor MP2, wherein:

[0036] The source of the first PMOS transistor MP1 is connected to the output terminal of the first inverting module (e.g., Figure 1 The first PMOS transistor MP1 is coupled to the gate of the second PMOS transistor MP2 and the drain of the second PMOS transistor MP2. The drain of the first PMOS transistor MP1 is coupled to the drain of the second PMOS transistor MP2. The substrate of the first PMOS transistor MP1 is coupled to the output terminal of the first inverting module.

[0037] The source of the second PMOS transistor MP2 is coupled to the input terminal of the first inverting module; the substrate of the second PMOS transistor MP2 is coupled to the input terminal of the first inverting module.

[0038] In a specific implementation, the first inverting module may include a third PMOS transistor MP3 and a first NMOS transistor MN1, wherein:

[0039] The source of the third PMOS transistor MP3 is coupled to the power supply terminal of the first inverting module, the gate of the third PMOS transistor MP3 is coupled to the input terminal of the first inverting module, and the drain of the third PMOS transistor MP3 is coupled to the output terminal of the first inverting module.

[0040] The gate of the first NMOS transistor MN1 is coupled to the gate of the third PMOS transistor MP3, the drain of the first NMOS transistor MN1 is coupled to the drain of the third PMOS transistor MP3, and the source of the first NMOS transistor MN1 is coupled to the ground terminal of the first inverting module. The gate of the first NMOS transistor MN1 is connected to the TA node.

[0041] In a specific implementation, the second inverting module may include a fourth PMOS transistor MP4 and a second NMOS transistor MN2, wherein:

[0042] The source of the fourth PMOS transistor MP4 is coupled to the power supply terminal of the second inverting module, the gate of the fourth PMOS transistor MP4 is coupled to the input terminal of the second inverting module, and the drain of the fourth PMOS transistor MP4 is coupled to the output terminal of the second inverting module.

[0043] The gate of the second NMOS transistor MN2 is coupled to the gate of the fourth PMOS transistor MP4, the drain of the second NMOS transistor MN2 is coupled to the drain of the fourth PMOS transistor MP4, and the source of the second NMOS transistor MN2 is coupled to the ground terminal of the second inverting module. The drain of the second NMOS transistor MN2 is connected to the TC node.

[0044] In practical implementation, the power supply terminal of the first inverting module can be connected to the power supply voltage VCC, and the ground terminal of the first inverting module is connected to GND. The power supply terminal of the second inverting module can also be connected to the power supply voltage VCC, and the ground terminal of the second inverting module is connected to GND.

[0045] In the specific implementation, the substrates of the third PMOS transistor MP3 and the fourth PMOS transistor MP4 are both connected to the power supply voltage VCC. The substrates of the first NMOS transistor MN1 and the second NMOS transistor MN2 are both connected to GND.

[0046] In practice, the capacitor CM can be a MOM capacitor, a MIM capacitor, or other types of capacitors.

[0047] In a specific implementation, the temperature detection unit may also include a third NMOS transistor MN3. The drain of the third NMOS transistor MN3 is coupled to the source of the first NMOS transistor MN1 and the source of the second NMOS transistor MN2. The source of the third NMOS transistor is grounded, and the gate of the third NMOS transistor is input with an enable signal EN.

[0048] In this embodiment of the invention, the temperature detection unit described above can essentially be regarded as an oscillator that changes with temperature.

[0049] In this embodiment of the invention, because the equivalent resistance of the temperature sensing module is extremely large, an ultra-small capacitor can be used, allowing the frequency of the oscillation signal output by the temperature detection unit to be set relatively low (e.g., 1Hz to 20kHz). This reduces the number of times the components in the data processing unit flip per second, effectively saving power. The operating current can be controlled below 1μA, and the minimum operating current at -45℃ can be controlled to the order of 100nA.

[0050] Reference Figure 3 The present invention provides a schematic diagram showing the resistance of a temperature sensing module as a function of temperature in an embodiment of the invention.

[0051] from Figure 3 As can be seen, the resistance of the temperature sensing module changes across four orders of magnitude with temperature. The temperature coefficient of the two inverting modules and the capacitor is less than ±20% over the temperature range of -45℃ to 125℃, which is negligible compared to the temperature sensing module's four-order-of-magnitude variation. The resistance of the temperature sensing module decreases as temperature increases, while the oscillation frequency of the temperature detection signal increases with temperature.

[0052] In this embodiment of the invention, the data processing unit may include a first D flip-flop, a pulse counter, a rising edge data flip-flop, and a decoder, wherein:

[0053] The clock input terminal of the first D flip-flop receives the temperature detection signal, the data input terminal of the first D flip-flop is coupled to the inverted output terminal of the first D flip-flop, the non-inverted output terminal of the first D flip-flop is coupled to the enable input terminal of the pulse counter and the low-level synchronous reset terminal of the pulse counter, and the inverted output terminal of the first D flip-flop is also coupled to the clock terminal CK of the rising edge data flip-flop.

[0054] The output of the pulse counter can be coupled to the data input of the rising edge data flip-flop;

[0055] The output of the rising-edge data flip-flop is coupled to the data input of the decoder;

[0056] The decoder can determine the current ambient temperature based on the output of the rising edge data trigger.

[0057] In practice, both the clock input terminal of the pulse counter and the clock input terminal of the decoder can be input with a high-frequency system clock.

[0058] In a practical implementation, the decoder may include a memory that stores the mapping relationship between the frequency of the temperature detection signal and the temperature. This mapping relationship can be presented in the form of a mapping table or a mapping function.

[0059] In practice, the memory in the decoder can be non-volatile memory.

[0060] In practical applications, the temperature values ​​at the frequencies corresponding to different temperature detection signals can be measured in advance, and then the above mapping relationship can be established. Alternatively, a mapping function can be fitted based on the temperature values ​​at the frequencies corresponding to different temperature detection signals.

[0061] It is understandable that the above mapping relationship is not limited to mapping tables and mapping functions.

[0062] In practice, when measuring the temperature value at the frequency corresponding to different temperature detection signals, the ambient temperature during the test can be strictly controlled to be 25℃. The temperature value at the same frequency is measured multiple times in a row. After removing the maximum and minimum values, the remaining values ​​are arithmetically averaged to obtain the final correspondence between frequency and temperature.

[0063] Continue to refer to Figure 1The first D flip-flop includes two inputs, two outputs, and an enable input. The two inputs are the data input (D) and the clock input (CK). The two outputs are the output (Q) and the inverted output (QN). The CK input of the first D flip-flop is the temperature detection signal. The D and QN inputs are connected to the DPG node, the Q input is connected to the PEN node, and the enable input (EN) is the enable signal (EN).

[0064] The pulse counter PC includes a first enable input PEN, a clock input CK, a low-level synchronous reset input SRN, and a second enable input EN. Its output is a pulse count output DOUT. The PEN and SRN terminals of the pulse counter PC are connected to the node output from EN via the delay unit Delay. The CK terminal of the pulse counter PC receives the high-frequency system clock SYCLK, and the DOUT terminal is coupled to the input DIN of the rising-edge data flip-flop. The second enable input EN of the pulse counter PC receives the enable signal EN.

[0065] The rising edge data trigger PEDDFF can be a rising edge data trigger. PEDDFF includes two inputs, one output, and one enable input. The two inputs are the control input CK and the data input DIN. The output is the output latch output TOUT, and the enable input EN receives the enable signal EN. The CK input of PEDDFF is connected to the DPG node, and the DIN input is connected to the pulse count output DOUT of the pulse counter PC. The data output TOUT of PEDDFF is connected to the data input TIN of the decoder.

[0066] The decoder TD includes three inputs, two outputs, and one enable input. The three inputs are: latch enable indicator GT, data input TIN, and clock input CK. The two outputs are: temperature resolution completion signal output TR and temperature indication signal output TP. The GT input of the decoder TD is connected to the DPG node, the TIN input is connected to the TOUT input of the rising edge data flip-flop PEDDFF, the clock input CK is input to the high-frequency system clock SYCLK, the TP input is the output TEMP, the TR input is connected to the output TEMP_TRIG, and the enable input is the enable signal EN.

[0067] In practice, the data processing unit can perform functions such as pulse counting, high-level enable rising edge data trigger, and temperature decoding.

[0068] The working principle of the temperature sensor provided in the above embodiments of the present invention will be explained below. The input terminal of the first inverting module is connected to the TA node, the output terminal of the first inverting module is connected to the TB node, and the output terminal of the second inverting module is connected to the TC node.

[0069] The temperature detection unit, through a temperature sensing module, a first inverting module, and a second inverting module, forms an oscillator that changes with temperature. The oscillator's operating waveform is as follows: Figure 4 As shown. (Refer to...) Figure 4 The present invention provides a waveform diagram of the working state of a temperature detection unit in an embodiment of the present invention.

[0070] The enable signal EN is at a high level during operation.

[0071] The first D flip-flop outputs the signal level from the D terminal to the Q terminal on the rising edge of the input signal (i.e., the temperature detection signal) at the CK terminal. The QN terminal of the first D flip-flop outputs a signal that is inverted compared to the Q terminal. When the PEN and SRN terminals are high, the pulse counter PC counts each rising edge pulse of the temperature detection signal and outputs the count value to the rising edge data flip-flop PEDDFF. When the PEN and SRN terminals are low, the pulse counter PC stops counting, and its output count value remains unchanged. On the next rising edge of CK, the count value of the pulse counter PC is reset to zero and counting restarts.

[0072] Since the TC signal and the system clock signal SYSCLK are asynchronous, a second D flip-flop DFF2 is added to ensure the correctness of timing and data. The function of DFF2 is to send the EN data to the SRN terminal of the PC module only on the first rising edge of SYSCLK after the EN signal level changes. This creates a delay between the falling edge of the SRN terminal and the rising edge of the DPG signal, ensuring that the SRN signal is high at the rising edge of the DPG signal, which will not cause a reset. This ensures that the correct data D can be correctly transmitted to the data T on the rising edge of the DPG signal, ultimately ensuring that the TD module receives the correct signal.

[0073] On the rising edge, the CK input of the rising edge data trigger PEDDFF latches the output DOUT of the pulse counter PC. The decoder TD begins decoding on the second rising edge of CK after the GT input is high, searching the ROM for the temperature value corresponding to the output of the rising edge data trigger PEDDFF. On the first rising edge of CK after decoding is complete, the TEMP_TRIG input is set high, and the TEMP input outputs the temperature value. On the next rising edge of CK, the TEMP_TRIG input is set low. The falling edge pulse of the TEMP_TRIG input indicates that temperature detection is complete. The current ambient temperature is then obtained by reading the value from the TEMP input. The duration of the high level at the TEMP_TRIG input can be set according to the actual application; this invention does not impose any limitations.

[0074] In the specific implementation, the first D flip-flop DFF1, the second D flip-flop DFF2, the rising edge data flip-flop PEDDFF, and the decoder TD have no reset input. After power-on, the first D flip-flop DFF1 outputs 0 at its Q input and 1 at its QN input. After power-on, the second D flip-flop DFF2 outputs 0 at its Q input. After power-on, the rising edge data flip-flop PEDDFF outputs 0 at its T input. After power-on, both the TEMP input and the TEMP_TRIG input of the decoder TD output 0.

[0075] The output of the rising-edge data flip-flop PEDDFF can be a 32-bit binary number, represented as T<31:0>; the input of the rising-edge data flip-flop PEDDFF can also be a 32-bit binary number, represented as D<31:0>. The output of the TEMP terminal can be an 8-bit binary number, represented as TEMP<7:0>. T<31:0> and D<31:0> can use unsigned binary encoding, while TEMP<7:0> can use two's complement encoding.

[0076] In practical applications, it is known that the chip's operating temperature range is -45℃ to 125℃. Therefore, -45 to 125 in TEMP<7:0> can be set as the normal value, and the other values ​​can be used to characterize whether the temperature sensing circuit is in a powered-on state or exceeds the temperature limit. For example, a power-on value of -128 in TEMP<7:0> does not mean that the actual temperature is -128℃, but indicates that it is in a powered-on state.

[0077] The decoder's ROM stores a mapping table with a total of 172 indices, each data occupies 4 bytes (32 bits). ROM[0] is the first data in the mapping table, and ROM

[171] is the 172nd data in the mapping table. ROM[0] stores the batch test average of T<31:0> at -45.5℃, ROM[1] stores the batch test average of T<31:0> at -44.5℃, and so on. ROM

[171] stores the batch test average of T<31:0> at 125.5℃.

[0078] The specific decoding process of the decoder, taking the binary search method as an example, is as follows (regl, regh, regmid, and regtemp are all internal registers of the decoder):

[0079] [1] The decoder TD starts decoding on the second rising edge of CK after the GT terminal is high.

[0080] [2] Set the left boundary register regl=0 and the right boundary register regh=171.

[0081] [3] Determine if the value of TIN<31:0> is less than ROM[0]. If yes, set regtemp<7:0> = -100 and jump to [9]. Otherwise, proceed to the next step.

[0082] 【4】Determine if the value of TIN<31:0> is greater than ROM

[171] . If yes, set regtemp<7:0> = -99 and jump to 【9】. Otherwise, proceed to the next step.

[0083] 【5】Calculate the bisection point regmid = (regl + regh) / 2 and round it down.

[0084] 【6】Determine if the value of TIN<31:0> is greater than or equal to ROM[regmid]. If yes, set regl = regmid; otherwise, set regh = regmid. Proceed to the next step.

[0085] [7] Determine if regh-regl=1 is true; otherwise, jump to [5]; otherwise, proceed to the next step.

[0086] 【8】Set regtemp<7:0> = regl-45. Proceed to the next step.

[0087] [9] On the next rising edge of CK, send the value of regtemp to TP<7:0> and set TR high.

[0088]

[10] On the next rising edge of CK, set TR low.

[0089] Specifically, the timing diagram of the data processing unit can be found in [reference needed]. Figure 5 . Reference Figure 5 A timing diagram of a data processing unit according to an embodiment of the present invention is provided. Figure 5 In the diagram, D is the connection line between the DOUT terminal of the pulse counter PC and the DIN terminal of the rising edge data trigger PEDDFF, and T is the connection line between the TOU terminal of the rising edge data trigger PEDDFF and the TIN terminal of the decoder TD.

[0090] In summary, the temperature detection unit forms an oscillation circuit, outputting a temperature detection signal with a frequency corresponding to the current ambient temperature. The data processing unit measures the frequency of the temperature detection signal to determine the current ambient temperature. The temperature sensing module in the temperature detection unit consists of N PMOS transistors, eliminating the need for dedicated thermistors. Therefore, the entire temperature sensing circuit can be composed of basic components such as MOS transistors and capacitors, resulting in a simple circuit structure and relatively simple manufacturing processes for the MOS transistors.

[0091] Furthermore, the temperature sensing circuit provided in this embodiment of the invention can operate at a relatively low voltage, for example, in a low-voltage power supply system of 0.9V. This is because both the first and second inverting modules are composed of MOSFETs, which can operate in the subthreshold region. Consequently, ultra-low power consumption can be achieved.

[0092] Furthermore, the data processing unit can also operate in low-voltage mode, depending on the power consumption of the data circuit and V. 2 The frequency is directly proportional to f, so it can effectively reduce power consumption even when operating in low voltage mode; in the above formula, V is the power supply and f is the frequency corresponding to the temperature detection signal.

[0093] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A temperature sensing circuit, characterized in that, include: Temperature detection unit and data processing unit, wherein: The temperature detection unit is coupled to the data processing unit and is adapted to generate and output a temperature detection signal with a frequency corresponding to the current ambient temperature. The temperature detection unit includes a temperature sensing module, which is composed of N PMOS transistors, and the gates and drains of the N PMOS transistors are interconnected; N≥2. The temperature detection unit further includes a first inverting module, a second inverting module, and a capacitor, wherein: the input terminal of the first inverting module is coupled to the second terminal of the capacitor, and its output terminal is coupled to the input terminal of the second inverting module; the output terminal of the second inverting module is coupled to the first terminal of the capacitor and the output terminal of the temperature detection unit; the temperature sensing module has its first terminal coupled to the output terminal of the first inverting module, and its second terminal coupled to the input terminal of the first inverting module; The data processing unit is adapted to receive the temperature detection signal and determine the temperature value of the current environment based on the frequency of the temperature detection signal.

2. The temperature sensing circuit as described in claim 1, characterized in that, The temperature sensing module includes a first PMOS transistor and a second PMOS transistor, wherein: The source of the first PMOS transistor is coupled to the output terminal of the first inverting module, and its gate is coupled to the gate and drain of the second PMOS transistor, and its drain is coupled to the drain of the second PMOS transistor. The source of the second PMOS transistor is coupled to the input terminal of the first inverting module.

3. The temperature sensing circuit as described in claim 2, characterized in that, The substrate of the first PMOS transistor is coupled to the output terminal of the first inverting module, and the substrate of the second PMOS transistor is coupled to the input terminal of the first inverting module.

4. The temperature sensing circuit as described in claim 1, characterized in that, The first inverting module includes: a third PMOS transistor and a first NMOS transistor, wherein: The third PMOS transistor has its source coupled to the power supply terminal of the first inverting module, its gate coupled to the input terminal of the first inverting module, and its drain coupled to the output terminal of the first inverting module. The first NMOS transistor has its gate coupled to the gate of the third PMOS transistor, its drain coupled to the drain of the third PMOS transistor, and its source coupled to the ground terminal of the first inverting module.

5. The temperature sensing circuit as described in claim 1, characterized in that, The second inverting module includes: a fourth PMOS transistor and a second NMOS transistor, wherein: The fourth PMOS transistor has its source coupled to the power supply terminal of the second inverting module, its gate coupled to the output terminal of the first inverting module, and its drain coupled to the output terminal of the second inverting module. The gate of the second NMOS transistor is coupled to the gate of the fourth PMOS transistor, the drain of the second NMOS transistor is coupled to the drain of the fourth PMOS transistor, and the source of the second inverting module is coupled to the ground terminal.

6. The temperature sensing circuit as described in claim 1, characterized in that, The capacitor is a MOM capacitor.

7. The temperature sensing circuit as described in claim 1, characterized in that, The data processing unit includes a first D flip-flop, a second D flip-flop, a pulse counter, a rising edge data flip-flop, and a decoder, wherein: The first D flip-flop has the temperature detection signal input at its clock input terminal, its data input terminal coupled to its inverted output terminal, its non-inverted output terminal coupled to the enable input terminal of the pulse counter and the data input terminal of the second D flip-flop, and its inverted output terminal coupled to the latch-on indicator terminal of the decoder and the control terminal of the rising edge data flip-flop. The second D flip-flop has its non-inverting output terminal coupled to the low-level synchronous reset terminal of the pulse counter; The pulse counter has its pulse counting output terminal coupled to the data input terminal of the rising edge data trigger; The output of the rising edge data trigger is coupled to the data input of the decoder; The decoder is adapted to determine the temperature value of the current environment based on the output of the rising edge data trigger.

Images