Display device

Abstract

A display device includes a display panel, a plurality of multiplexers, and a plurality of impedance circuits. The display panel has a plurality of sub-pixels arranged in an array, a plurality of data lines, and a plurality of gate lines. Each sub-pixel is electrically connected to a data line and a gate line. Each multiplexer is disposed between a set of data lines and a data terminal. Each multiplexer receives a sub-pixel voltage from the data terminal and provides the sub-pixel voltage to a first data line of the set of data lines during a sub-pixel charging period. Each impedance circuit is disposed between a data line and a ground terminal. Some of the plurality of impedance circuits receive a ground voltage from the ground terminal and provide the ground voltage to at least a second data line of the set of data lines during the sub-pixel charging period. The display device can reduce interference noise to improve wireless signal transmission performance.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Taiwan Patent Application No. 111147998, filed on December 14, 2022, which is incorporated herein by reference for all purposes as if fully set forth herein. Technical Field

[0003] The present invention relates to a display technology, and in particular to a display device. Background Art

[0004] Near-field communication (NFC) technology provides short-range wireless connections for two-way communication between electronic devices. Operating at a frequency of 13.56 MHz, this technology utilizes antenna coils for mutual induction. One set of coils acts as the induction coil for the NFC reader, while the other acts as the induction coil for the NFC tag. The NFC reader is the device that initiates communication, while the NFC tag (or card) responds to the initiator's request and accepts the communication request.

[0005] Because NFC uses high-frequency signals, it's susceptible to environmental influences. Specifically, when the antenna trace area overlaps the panel, the panel's numerous metal traces will couple the in-plane signal to the antenna. However, this signal appears as noise to the NFC reader. Furthermore, if the antenna is placed to the side of the panel or on the same plane, the metal traces on the panel will form a loop and transmit the signal back to the NFC reader through load modulation, causing NFC reader reception errors.

[0006] In view of this, how to effectively reduce noise in a display device with NFC functionality and alleviate abnormalities to improve communication capabilities will be an important issue for those skilled in the art. Summary of the Invention

[0007] The present invention provides a display device which can reduce interference noise to improve wireless signal transmission performance.

[0008] To achieve the aforementioned object of the invention, according to one embodiment of the present invention, a display device is proposed, comprising a display panel, a plurality of multiplexers, and a plurality of impedance circuits. The display panel has a plurality of sub-pixels, a plurality of data lines, and a plurality of gate lines arranged in an array, and each sub-pixel is electrically connected to a data line and a gate line. The plurality of multiplexers are each arranged between a group of data lines in the plurality of data lines and a data terminal, and each multiplexer receives a sub-pixel voltage from the data terminal and provides the sub-pixel voltage to a first data line in the group of data lines during sub-pixel charging. Each impedance circuit is arranged between a data line and a ground terminal, and some of the plurality of impedance circuits receive a ground voltage from the ground terminal and provide the ground voltage to at least a second data line in the group of data lines during sub-pixel charging.

[0009] The advantages of the present invention are:

[0010] In a display device according to an embodiment of the present invention, a multiplexer is disposed between a group of data lines and a data terminal, and an impedance circuit is disposed between each data line and a ground terminal. During sub-pixel charging, the multiplexer provides a sub-pixel voltage from the data terminal to one data line in the group, while the impedance circuit provides a ground voltage to the remaining data lines in the group. This allows the signals generated by each data line to the driver circuit to be substantially or nearly identical, thereby reducing interference noise and improving wireless signal transmission performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is a schematic diagram of a display device according to an embodiment of the present invention;

[0012] Figure 2 According to the present invention Figure 1 A schematic diagram of signal waveforms according to an embodiment.

[0013] in:

[0014] 100: display device;

[0015] 110: display panel;

[0016] 120: driving circuit;

[0017] 200: waveform;

[0018] CT1-CT3: sub-pixel charging period;

[0019] D1, D2, D3, D4, D5, D6: data lines;

[0020] DO1, DO2: data terminals during sub-pixel discharge;

[0021] G1, G2, G3: gate lines;

[0022] GND: ground terminal;

[0023] MUX3_1, MUX3_2: multiplexers;

[0024] P11, P12, P13, P14, P15, P16, P21, P22, P23, P24, P25, P26, P31, P32, P33, P34, P35, P36: sub-pixel;

[0025] PT: pre-charge period;

[0026] RC1, RC2, RC3, RC4, RC5, RC6: impedance circuit;

[0027] RE: impedance element;

[0028] SW, SW1, SW2, SW3: switching elements;

[0029] SWB, SWB', SWG, SWG', SWR, SWR': control signals. DETAILED DESCRIPTION

[0030] It should be understood that although the terms "first," "second," "third," etc. may be used herein to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or portion from another element, component, region, layer, or portion. Thus, the "first element," "first component," "first region," "first layer," or "first portion" discussed below could be referred to as the "second element," "second component," "second region," "second layer," or "second portion" or portions without departing from the teachings herein.

[0031] The terms used herein are for the purpose of describing specific embodiments only and are not intended to be limiting. As used herein, unless the content clearly indicates otherwise, the singular forms "a", "an" and "the" are intended to include plural forms, including "at least one". "Or" means "and / or". As used herein, the term "and / or" includes any and all combinations of one or more of the relevant listed items. It should also be understood that when used in this specification, the terms "include" and / or "including" specify the presence of the features, regions, wholes, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, regions, wholes, steps, operations, elements, parts and / or their combinations.

[0032] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the invention belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present invention, and will not be interpreted as idealized or overly formal unless explicitly defined as such herein.

[0033] Figure 1 is a schematic diagram of a display device according to an embodiment of the present invention. Figure 1 The display device 100 includes a display panel 110, multiple multiplexers (e.g., multiplexers MUX3_1 and MUX3_2), and multiple impedance circuits (e.g., impedance circuits RC1-RC6). The display panel 110 has multiple sub-pixels (e.g., sub-pixels P11-P16, P21-P26, P31-P36) arranged in an array, multiple data lines (e.g., data lines D1-D6), and multiple gate lines (e.g., gate lines G1-G3). Each sub-pixel (e.g., sub-pixels P11-P16, P21-P26, P31-P36) is electrically connected to a data line (e.g., data lines D1-D6) and a gate line (e.g., gate lines G1-G3), that is, is arranged at the intersection of multiple data lines and multiple gate lines. Furthermore, each sub-pixel can turn on a corresponding transistor (e.g., a thin film transistor) based on each gate drive signal.

[0034] In this embodiment, multiple multiplexers may be respectively disposed between a group of data lines and a corresponding data terminal. Each multiplexer receives a sub-pixel voltage from the data terminal and provides the sub-pixel voltage to a first data line in the group of data lines during a sub-pixel charging period. For example, multiplexer MUX3_1 is disposed between data lines D1, D3, and D5 and data terminal DO1. Multiplexer MUX3_1 receives a sub-pixel voltage from data terminal DO1 and provides the sub-pixel voltage to data line D1 (also referred to as the first data line).

[0035] In this embodiment, multiple impedance circuits may be respectively disposed between a data line and a ground terminal, and some of the impedance circuits receive a ground voltage from the ground terminal and provide the ground voltage to at least one second data line in the group of data lines during a sub-pixel charging period. For example, impedance circuits RC1, RC2, and RC3 are respectively disposed between data lines D1, D5, and D3 and the ground terminal GND, and some of the impedance circuits RC2 and RC3 receive a ground voltage from the ground terminal GND and provide the ground voltage to data lines D3 and D5 (also referred to as second data lines).

[0036] It should be noted that in this embodiment, the data line provided with the sub-pixel voltage is called the first data line, and the data line provided with the ground voltage is called the second data line. Those skilled in the art can deduce various situations based on the above examples.

[0037] In one embodiment, during a pre-charge period or a sub-pixel discharge period following a sub-pixel charging period, all impedance circuits in the plurality of impedance circuits receive a ground voltage from the ground terminal and provide the ground voltage to all data lines in a group of data lines. For example, all impedance circuits RC1, RC2, and RC3 receive a ground voltage from the ground terminal GND and provide the ground voltage to all data lines D1, D5, and D3.

[0038] In one embodiment, the display device 100 further includes a driver circuit 120. The driver circuit 120 is coupled to the multiplexers MUX3_1 and MUX3_2 and the impedance circuits RC1-RC6, and outputs control signals SWR, SWG, SWB, SWR', SWG', and SWB' to control the multiplexers MUX3_1 and MUX3_2 to provide sub-pixel voltages to the data lines D1 and D4 (or the data lines D5 and D2 or the data lines D3 and D6), and to control some of the impedance circuits to provide ground voltages to the data lines D5, D3, D2, and D6 (or the data lines D1, D3, D4, and D6 or the data lines D1, D5, D4, and D2).

[0039] Figure 1 In the embodiment of the present invention, a display device in which two multiplexers MUX3_1 and MUX3_2 correspond to six sub-pixels P11-P16, P21-P26, or P31-P36 (i.e., a 2:6 ratio) is used as an example. It is worth mentioning that each pixel in the display panel includes three sub-pixels, namely an R sub-pixel, a G sub-pixel, and a B sub-pixel. That is, in this embodiment of the present invention, sub-pixels P11, P14, P21, P24, P31, and P34 are R sub-pixels, sub-pixels P12, P15, P22, P25, P32, and P35 are G sub-pixels, and sub-pixels P13, P16, P23, P26, P33, and P36 are B sub-pixels.

[0040] The display device 100 is specifically configured as follows: a multiplexer MUX3_1 is disposed between a data terminal DO1 and data lines D1, D3, and D5 (also referred to as the first group of data lines), and a multiplexer MUX3_2 is disposed between a data terminal DO2 and data lines D2, D4, and D6 (also referred to as the second group of data lines). Specifically, during a subpixel charging period, multiplexer MUX3_1 receives a first subpixel voltage from data terminal DO1 and provides the first subpixel voltage to data line D1, D5, or D3 (also referred to as the first data line). Furthermore, multiplexer MUX3_2 receives a second subpixel voltage from data terminal DO2 and provides the second subpixel voltage to data line D4, D2, or D6 (also referred to as the first data line). It is noteworthy that the first group of data lines (i.e., data lines D1, D3, and D5) and the second group of data lines (i.e., data lines D2, D4, and D6) are arranged in a cross-connected arrangement.

[0041] In one embodiment, multiplexers MUX3_1 and MUX3_2 each include switch elements SW1-SW3. Switch element SW1 receives a control signal SWR and is turned on or off based on the control signal SWR. Switch element SW2 receives a control signal SWG and is turned on or off based on the control signal SWG. Switch element SW3 receives a control signal SWB and is turned on or off based on the control signal SWB.

[0042] In one embodiment, each impedance circuit RC1-RC6 includes a switch element SW and an impedance element RE. The switch element SW is disposed between one of the data lines D1-D6 and the impedance element RE, and the impedance element RE is disposed between the switch element SW and the ground terminal GND. The switch elements SW of impedance circuits RC1 and RC4 receive a control signal SWR' and are turned on or off based on the control signal SWR'. The switch elements SW of impedance circuits RC2 and RC5 receive a control signal SWG' and are turned on or off based on the control signal SWG'. The switch elements SW of impedance circuits RC3 and RC6 receive a control signal SWB' and are turned on or off based on the control signal SWB'. Furthermore, the impedance element RE comprises at least one of a diode, a resistor, and an inductor. In one embodiment, the resistance RZ of the impedance elements RE in impedance circuits RC1-RC6 is the same.

[0043] In one embodiment, the display device 100 further includes a near-field wireless communication reader (not shown). The near-field wireless communication reader is disposed below or on the side of the display device 100 .

[0044] Figure 2 According to the present invention Figure 1 Schematic diagram of the waveform of the signal of the embodiment. For details on the operation of the display device 100, please also refer to Figure 1 and Figure 2The waveform 200 shows that the display time interval can be divided into a pre-charge period PT, a plurality of sub-pixel charging periods CT1-CT3, and a plurality of sub-pixel discharging periods DT1-DT3. Figure 2 In the embodiment, the multiplexers MUX3_1 and MUX3_2 can make the switch elements SW1, SW2, and SW3 mutually conductive according to the control signals SWR, SWG, and SWB, and the switch elements SW of the impedance circuits RC1-RC6 can make the switch elements SW mutually conductive according to the control signals SWR', SWG', and SWB'.

[0045] Specifically, when the display device 100 is operating in a pre-charge period PT prior to the sub-pixel charge period CT1, the control signals SWR, SWG, and SWB may be set to a disabled state (e.g., a low voltage level), and the control signals SWR', SWG', and SWB' may be set to an enabled state (e.g., a high voltage level). This disconnects the switches SW1, SW2, and SW3 of the multiplexer MUX3_1 and turns on the switches SW of the impedance circuits RC1, RC2, and RC3. In this case, the resistance between the data lines D1, D3, and D5 and the driver circuit 120 is equal to the sum of the resistances RZ of the impedance elements RE in the impedance circuits RC1, RC2, and RC3 (i.e., 3RZ).

[0046] When the display device 100 operates in a sub-pixel charging period CT1, SWG, SWB, and SWR' may be set to a disabled state (e.g., a low voltage level), and control signals SWR, SWG', and SWB' may be set to an enabled state (e.g., a high voltage level). This disconnects the switch elements SW2 and SW3 of the multiplexer MUX3_1 and the switch element SW of the impedance circuit RC1, while turning on the switch element SW1 and the switch elements SW of the impedance circuits RC2 and RC3. In this case, the resistance between the data lines D1, D3, and D5 and the driver circuit 120 is equal to the sum of the resistance RZ of the impedance elements RE in the impedance circuits RC2 and RC3 plus the resistance RIC of the driver circuit 120 (i.e., 2RZ + RIC).

[0047] When the display device 100 operates during a sub-pixel discharge period DT1 following a sub-pixel charge period CT1, the control signals SWR, SWG, and SWB may be set to a disabled state (e.g., a low voltage level), and the control signals SWR', SWG', and SWB' may be set to an enabled state (e.g., a high voltage level). This causes the switches SW1, SW2, and SW3 of the multiplexer MUX3_1 to be turned off and the switches SW of the impedance circuits RC1, RC2, and RC3 to be turned on. In this case, the resistance between the data lines D1, D3, and D5 and the driver circuit 120 is equal to the sum of the resistances RZ of the impedance elements RE in the impedance circuits RC1, RC2, and RC3 (i.e., 3RZ).

[0048] When the display device 100 operates in the sub-pixel charging period CT2, the control signals SWR, SWB, and SWG' may be set to a disabled state (e.g., a low voltage level), and the control signals SWG, SWR', and SWB' may be set to an enabled state (e.g., a high voltage level). This causes the switch elements SW1 and SW3 of the multiplexer MUX3_1 and the switch element RE of the impedance circuit RC2 to be turned off, and the switch element SW2 and the switch elements RE of the impedance circuits RC1 and RC3 to be turned on. In this case, the resistance between the data lines D1, D3, and D5 and the driver circuit 120 is equal to the sum of the resistance RZ of the impedance elements RE in the impedance circuits RC1 and RC3 plus the resistance RIC of the driver circuit 120 (i.e., 2RZ + RIC).

[0049] When the display device 100 operates during a sub-pixel discharge period DT2 following a sub-pixel charge period CT2, the control signals SWR, SWG, and SWB may be set to a disabled state (e.g., a low voltage level), and the control signals SWR', SWG', and SWB' may be set to an enabled state (e.g., a high voltage level). This causes the switch elements SW1, SW2, and SW3 of the multiplexer MUX3_1 to be turned off and the switch elements SW of the impedance circuits RC1, RC2, and RC3 to be turned on. In this case, the resistance between the data lines D1, D3, and D5 and the driver circuit 120 is equal to the sum of the resistances RZ of the impedance elements RE in the impedance circuits RC1, RC2, and RC3 (i.e., 3RZ).

[0050] When the display device 100 operates in a sub-pixel charging period CT3, the control signals SWR, SWG, and SWB' may be set to a disabled state (e.g., a low voltage level), and the control signals SWB, SWR', and SWG' may be set to an enabled state (e.g., a high voltage level). This causes the switch elements SW1 and SW2 of the multiplexer MUX3_1 and the switch element RE of the impedance circuit RC3 to be turned off, while the switch element SW3 and the switch elements RE of the impedance circuits RC1 and RC2 to be turned on. In this case, the resistance between the data lines D1, D3, and D5 and the driver circuit 120 is equal to the sum of the resistance RZ of the impedance elements RE in the impedance circuits RC1 and RC2 plus the resistance RIC of the driver circuit 120 (i.e., 2RZ + RIC).

[0051] When the display device 100 operates during a sub-pixel discharge period DT3 following a sub-pixel charge period CT3, the control signals SWR, SWG, and SWB may be set to a disabled state (e.g., a low voltage level), and the control signals SWR', SWG', and SWB' may be set to an enabled state (e.g., a high voltage level). This causes the switches SW1, SW2, and SW3 of the multiplexer MUX3_1 to be turned off and the switches SW of the impedance circuits RC1, RC2, and RC3 to be turned on. In this case, the resistance between the data lines D1, D3, and D5 and the driver circuit 120 is equal to the sum of the resistances RZ of the impedance elements RE in the impedance circuits RC1, RC2, and RC3 (i.e., 3RZ).

[0052] In one embodiment, depending on the noise immunity of the driving circuit 120, the resistance RZ can be 80% to 120% of the resistance RIC, thereby improving communication performance. In one embodiment, the impedance element RE can be disposed within a printed circuit board (PCB), a flexible printed circuit (FPC), a glass substrate, or an integrated circuit (IC), as long as it is electrically connected to the data line.

[0053] exist Figure 2 In the embodiment of the present invention, the display device 100 continues to operate in the next display time interval, and the signal of the next display time interval is the same as that of the above display time interval, which will not be described in detail here. It should be noted that in Figure 2 In the embodiment, the operation relationship between the multiplexer MUX3_2 and the data lines D4, D2, D6 and the driving circuit 120 can be operated according to the above operation relationship between the multiplexer MUX3_1 and the data lines D1, D5, D3 and the driving circuit 120, which will not be repeated here.

[0054] According to the above Figure 2 As can be seen from the description, during the pre-charging period, the sub-pixel charging period, or the sub-pixel discharging period after the sub-pixel charging period, the driving circuit 120 of the display device 100 of the present invention can control each switching element to be turned on or off so that the signals generated from the data lines D1-D6 to the driving circuit 120 are substantially or almost the same. This can effectively reduce noise in the display device with NFC function and alleviate abnormal situations to improve communication capabilities.

[0055] In summary, the display device of the present invention embodiment includes a multiplexer between a group of data lines and a data terminal, and an impedance circuit between each data line and a ground terminal. During the sub-pixel charging period, the multiplexer provides a sub-pixel voltage from the data terminal to one data line in the group, while the impedance circuit provides a ground voltage to the remaining data lines in the group. This allows the signals generated by each data line to the driver circuit to be substantially or nearly identical, thereby reducing interference noise and improving wireless signal transmission performance.

[0056] Although the present invention has been disclosed above with reference to the embodiments, they are not intended to limit the present invention. Anyone with ordinary skill in the art may make slight changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope of the appended patent applications.

Claims

1. A display device, characterized in that: include: A display panel having a plurality of sub-pixels, a plurality of data lines, and a plurality of gate lines arranged in an array, wherein each of the sub-pixels is electrically connected to a data line and a gate line; a plurality of multiplexers, each disposed between a group of data lines among the plurality of data lines and a data terminal, each of the multiplexers receiving a sub-pixel voltage from the data terminal and providing the sub-pixel voltage to a first data line among the group of data lines during a sub-pixel charging period; as well as A plurality of impedance circuits are each arranged between one of the data lines and a ground terminal, and some of the impedance circuits receive a ground voltage from the ground terminal during the sub-pixel charging period and provide the ground voltage to at least a second data line in the group of data lines.

2. The display device according to claim 1, wherein During a pre-charging period or a sub-pixel discharging period after the sub-pixel charging period, all impedance circuits in the plurality of impedance circuits receive the ground voltage from the ground terminal and provide the ground voltage to all data lines in the group of data lines.

3. The display device according to claim 1, wherein Also includes: A driving circuit is coupled to the multiplexers and the impedance circuits, and is configured to output control signals to control the multiplexers to provide the sub-pixel voltage to the first data line and to control the impedance circuits to provide the ground voltage to the at least one second data line.

4. The display device according to claim 1, wherein The plurality of multiplexers include: a first multiplexer disposed between a first data terminal and a first group of data lines among the plurality of data lines, configured to receive a first sub-pixel voltage from the first data terminal and provide the first sub-pixel voltage to a first data line among the first group of data lines during a sub-pixel charging period; and The second multiplexer is disposed between the second data terminal and a second group of data lines in the plurality of data lines, for receiving a second sub-pixel voltage from the second data terminal and providing the second sub-pixel voltage to a first data line in the second group of data lines during the sub-pixel charging period.

5. The display device according to claim 4, wherein The first multiplexer and the second multiplexer each include a first switching element, a second switching element, and a third switching element; The first switch element receives a first control signal and is turned on or off according to the first control signal; The second switch element receives a second control signal and is turned on or off according to the second control signal; The third switch element receives a third control signal and is turned on or off according to the third control signal.

6. The display device according to claim 4, wherein The first group of data lines and the second group of data lines are arranged to cross each other.

7. The display device according to claim 1, wherein Each of the impedance circuits includes a switch element and an impedance element. The switch element is disposed between one of the data lines and the impedance element, and the impedance element is disposed between the switch element and the ground terminal. The switch element receives a control signal and is turned on or off according to the control signal.

8. The display device according to claim 7, wherein: The impedance element includes at least one of a diode, a resistor, and an inductor.

9. The display device according to claim 7, wherein: The resistance values ​​of the impedance elements in the plurality of impedance circuits are all the same.

10. The display device according to claim 1, wherein Also includes: A short-range wireless communication reader is arranged below or beside the display panel.

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