Scan signal generating circuit and display device including the same

Abstract

The disclosure provides a display device including a display panel and a scan signal generator configured to generate a first (1-1) scan signal and a first (1-2) scan signal supplied to a first horizontal line of the display panel and a second (2-1) scan signal and a second (2-2) scan signal supplied to a second horizontal line of the display panel, wherein the scan signal generator includes a switching circuit and an output circuit.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit of Korean Patent Application No. 10-2021-0194663, filed on December 31, 2021, which is incorporated herein by reference as if it were fully set forth herein. Technical Field

[0003] This disclosure relates to a scan signal generating circuit and a display device including the scan signal generating circuit. Background Technology

[0004] With the development of information technology, the market for display devices, which serve as a connection medium between users and information, is growing. Consequently, display devices such as light-emitting diode (LED) devices, quantum dot (QDD) devices, and liquid crystal display (LCD) devices are being used more and more.

[0005] The display device described above includes: a display panel including sub-pixels, a driver that outputs drive signals for driving the display panel, and a power supply that generates power to the display panel or the driver.

[0006] In the aforementioned display device, when a driving signal (e.g., a scan signal and a data signal) is supplied to a sub-pixel formed in the display panel, the selected sub-pixel transmits light or directly emits light, thereby displaying an image. Summary of the Invention

[0007] The objective of this disclosure is to reduce the circuit area of ​​the shift register used to output the scan signal by grouping and integrating a total of four scan signal generators included in two stages to construct an integrated scan signal generation circuit, and to reduce the size of the bezel of the display panel by reducing the circuit area of ​​the shift register.

[0008] To achieve these objects and other advantages and in accordance with the purpose of the disclosure, as embodied and broadly described herein, a display apparatus includes a display panel and a scan signal generator configured to generate a first (1-1) scan signal and a first (1-2) scan signal supplied to a first horizontal line of the display panel and a second (2-1) scan signal and a second (2-2) scan signal supplied to a second horizontal line of the display panel, wherein the scan signal generator includes a switching circuit including a common node charged with a low voltage applied by turn-on operations of first and second transistors, an inverting node operating in opposition to the common node, and first to fourth stabilization transistors having a first electrode connected to the common node and a gate electrode connected to a gate low voltage line, and the scan signal generator includes an output circuit including first and second (1-1) pull-up transistors outputting the first (1-1) scan signal and the first (1-2) scan signal in response to a voltage of a first node corresponding to a second electrode of the first stabilization transistor and a voltage of a second node corresponding to a second electrode of the second stabilization transistor, and first and second (2-1) pull-up transistors outputting the second (2-1) scan signal and the second (2-2) scan signal in response to a voltage of a third node corresponding to a second electrode of the third stabilization transistor and a voltage of a fourth node corresponding to a second electrode of the fourth stabilization transistor.

[0009] The first (1-1) pull-up transistor can have a gate electrode connected to the first node, a first electrode connected to a first (1-1) clock signal line, and a second electrode connected to a first (1-1) output terminal, the second (1-2) pull-up transistor can have a gate electrode connected to the second node, a first electrode connected to a second (1-2) clock signal line, and a second electrode connected to a second (1-2) output terminal, the second (2-1) pull-up transistor can have a gate electrode connected to the third node, a first electrode connected to a second (2-1) clock signal line, and a second electrode connected to a second (2-1) output terminal, and the second (2-2) pull-up transistor can have a gate electrode connected to the fourth node, a first electrode connected to a second (2-2) clock signal line, and a second electrode connected to a second (2-2) output terminal.

[0010] The output circuit can include a first (1-1) pull-down transistor having a gate electrode connected to the inverting node, a first electrode connected to the gate high voltage line, and a second electrode connected to a first (1-1) output terminal; a first (1-2) pull-down transistor having a gate electrode connected to the inverting node, a first electrode connected to the gate high voltage line, and a second electrode connected to a first (1-2) output terminal; a first (2-1) pull-down transistor having a gate electrode connected to the inverting node, a first electrode connected to the gate high voltage line, and a second electrode connected to a first (2-1) output terminal; and a first (2-2) pull-down transistor having a gate electrode connected to the inverting node, a first electrode connected to the gate high voltage line, and a second electrode connected to a first (2-2) output terminal.

[0011] The output circuit can include a first (1-1) capacitor having a first electrode connected to the gate electrode of the first (1-1) pull-up transistor, and a second electrode connected to the first (1-1) output terminal; a first (1-2) capacitor having a first electrode connected to the gate electrode of the first (1-2) pull-up transistor, and a second electrode connected to the first (1-2) output terminal; a first (2-1) capacitor having a first electrode connected to the gate electrode of the first (2-1) pull-up transistor, and a second electrode connected to the first (2-1) output terminal; and a first (2-2) capacitor having a first electrode connected to the gate electrode of the first (2-2) pull-up transistor, and a second electrode connected to the first (2-2) output terminal.

[0012] The first transistor can have a gate electrode connected to the start signal line and a first electrode connected to the gate low voltage line, and the second transistor can have a gate electrode connected to the common node clock signal line, a first electrode connected to the second electrode of the first transistor, and a second electrode connected to the common node.

[0013] The switch circuit can include a third transistor having a gate electrode connected to the inverting node, a first electrode connected to the gate high voltage line, and a second electrode connected to the common node; a fourth transistor having a gate electrode connected to the inverting node clock signal line, a first electrode connected to the gate low voltage line, and a second electrode connected to the inverting node; a fifth transistor having a gate electrode connected to the start signal line, a first electrode connected to the gate high voltage line, and a second electrode connected to the inverting node; an eighth transistor having a gate electrode connected to the common node, a first electrode connected to the gate high voltage line, and a second electrode connected to the common node; a ninth transistor having a gate electrode connected to the reset signal line, a first electrode connected to the gate high voltage line, and a second electrode connected to the common node; and a node capacitor having a first electrode connected to the gate high voltage line and a second electrode connected to the inverting node.

[0014] The period in which the (1-1)th scan signal maintains a low voltage and the period in which the (2-1)th scan signal maintains a low voltage can not overlap, and the period in which the (1-2)th scan signal maintains a low voltage and the period in which the (2-2)th scan signal maintains a low voltage can partially overlap.

[0015] In another aspect of the disclosure, the scan signal generation circuit includes a switching circuit including a common node charged with a low voltage applied by the turn-on operation of the first and second transistors, an inverting node operating in opposition to the common node, and first to fourth stabilization transistors having a first electrode connected to the common node and a gate electrode connected to the gate low voltage line, and the scan signal generation circuit includes an output circuit including (1-1)th and (1-2)th pull-up transistors outputting the (1-1)th and (1-2)th scan signals in response to a voltage of a first node corresponding to the second electrode of the first stabilization transistor and a voltage of a second node corresponding to the second electrode of the second stabilization transistor, and (2-1)th and (2-2)th pull-up transistors outputting the (2-1)th and (2-2)th scan signals in response to a voltage of a third node corresponding to the second electrode of the third stabilization transistor and a voltage of a fourth node corresponding to the second electrode of the fourth stabilization transistor.

[0016] The (1-1)th pull-up transistor can have a gate electrode connected to the first node, a first electrode connected to the (1-1)th clock signal line, and a second electrode connected to the (1-1)th output terminal, the (1-2)th pull-up transistor can have a gate electrode connected to the second node, a first electrode connected to the (1-2)th clock signal line, and a second electrode connected to the (1-2)th output terminal, the (2-1)th pull-up transistor can have a gate electrode connected to the third node, a first electrode connected to the (2-1)th clock signal line, and a second electrode connected to the (2-1)th output terminal, and the (2-2)th pull-up transistor can have a gate electrode connected to the fourth node, a first electrode connected to the (2-2)th clock signal line, and a second electrode connected to the (2-2)th output terminal.

[0017] The output circuit can include: a first (1-1) pull-down transistor having a gate electrode connected to the inverting node, a first electrode connected to the gate high voltage line, and a second electrode connected to a first (1-1) output terminal; a first (1-2) pull-down transistor having a gate electrode connected to the inverting node, a first electrode connected to the gate high voltage line, and a second electrode connected to a first (1-2) output terminal; a second (2-1) pull-down transistor having a gate electrode connected to the inverting node, a first electrode connected to the gate high voltage line, and a second electrode connected to a second (2-1) output terminal; a second (2-2) pull-down transistor having a gate electrode connected to the inverting node, a first electrode connected to the gate high voltage line, and a second electrode connected to a second (2-2) output terminal; a first (1-1) capacitor having a first electrode connected to the gate electrode of the first (1-1) pull-up transistor and a second electrode connected to the first (1-1) output terminal; a first (1-2) capacitor having a first electrode connected to the gate electrode of the first (1-2) pull-up transistor and a second electrode connected to the first (1-2) output terminal; a second (2-1) capacitor having a first electrode connected to the gate electrode of the second (2-1) pull-up transistor and a second electrode connected to the second (2-1) output terminal; and a second (2-2) capacitor having a first electrode connected to the gate electrode of the second (2-2) pull-up transistor and a second electrode connected to the second (2-2) output terminal. BRIEF DESCRIPTION OF DRAWINGS

[0018] Figure 1 is a block diagram schematically showing a light emitting display device, and Figure 2 is a configuration diagram schematically showing Figure 1 the sub-pixel shown in

[0019] Figure 3 and Figure 4 is a diagram illustrating a configuration of an on-panel gate type gate driver, and Figure 5 is a diagram illustrating an arrangement example of an on-panel gate type gate driver.

[0020] Figure 6 is a circuit configuration diagram of a sub-pixel suitable for an embodiment of the present disclosure, Figure 7 is Figure 6 is a drive waveform diagram of the sub-pixel shown in Figures 8 to 11 shows the operation state of the device for each period according to the drive waveform shown in Figure 7

[0021] Figure 12 is a block diagram of a first shift register according to an experimental example, and Figure 13 is a block diagram of a first shift register according to an embodiment.

[0022] Figure 14 ​is a circuit configuration diagram of a scan signal generator suitable for embodiments of the present disclosure, Figure 15 is Figure 14 is a driving waveform diagram of the scan signal generator shown in FIG. 1, and Figures 16 to 20 is shown Figure 15 is the operation state of the scan signal generator at each period in FIG. 1.

[0023] Figure 21 is a diagram showing the concept of an integrated block of a shift register according to an embodiment of the present disclosure, Figure 22 is Figure 21 is an internal circuit configuration diagram of the integrated scan signal generation circuit shown in FIG. 2, and Figure 23 is Figure 22 is a driving waveform diagram of the circuit shown in FIG. 2. DETAILED DESCRIPTION

[0024] A display device according to the present disclosure can be implemented as a television, a video player, a personal computer (PC), a home theater, a car electric device, a smartphone, etc., but is not limited thereto. The display device according to the present disclosure can be implemented as a light emitting display (LED) device, a quantum dot display (QDD) device, a liquid crystal display (LCD) device, etc. However, for convenience of description, an example of a light emitting display device based on direct light emission of inorganic light emitting diodes or organic light emitting diodes will be described.

[0025] Further, although a p-type thin film transistor will be described below, an n-type thin film transistor or a structure in which n-type and p-type thin film transistors coexist can be used. A thin film transistor is a three-electrode element including a gate, a source, and a drain. The source is an electrode that supplies a carrier to the transistor. In a thin film transistor, the carrier flows from the source. The drain is an electrode through which the carrier exits the thin film transistor. That is, in a thin film transistor, the carrier flows from the source to the drain.

[0026] In the case of a p-type thin film transistor, the carrier is a hole, and thus the source voltage is higher than the drain voltage so that the hole can flow from the source to the drain. In a p-type thin film transistor, since the hole flows from the source to the drain, current flows from the source to the drain. On the other hand, in the case of an n-type thin film transistor, because the carrier is an electron, the source voltage is lower than the drain voltage so that the electron can flow from the source to the drain. In an n-type thin film transistor, since the electron flows from the source to the drain, current flows from the drain to the source. However, the source and the drain of the thin film transistor can be changed according to an applied voltage. In this regard, in the following description, any one of the source and the drain is described as a first electrode, and the other of the source and the drain is described as a second electrode.

[0027] Figure 1 is a block diagram schematically showing a light emitting display device, andFigure 2 is schematically shown Figure 1 a configuration diagram of subpixels shown in FIG. 1.

[0028] As Figure 1 and Figure 2 The light emitting display apparatus includes an image provider 110, a timing controller 120, a gate driver 130, a data driver 140, a display panel 150, a power supply 180, etc., as shown.

[0029] The image provider (set or host system) 110 can output various driving signals along with an image data signal supplied from the outside or an image data signal stored in an internal memory. The image provider 110 can supply a data signal and various driving signals to the timing controller 120.

[0030] The timing controller 120 can output a gate timing control signal GDC for controlling an operation timing of the gate driver 130, a data timing control signal DDC for controlling an operation timing of the data driver 140, and various synchronization signals (a vertical synchronization signal Vsync and a horizontal synchronization signal Hsync). The timing controller 120 can supply the data signal DATA supplied from the image provider 110 along with the data timing control signal DDC to the data driver 140. The timing controller 120 can take the form of an integrated circuit (IC) and be mounted on a printed circuit board, but is not limited thereto.

[0031] The gate driver 130 can output a gate signal (or a gate voltage) in response to the gate timing control signal GDC supplied from the timing controller 120. The gate driver 130 can supply the gate signal to subpixels included in the display panel 150 through gate lines GL1 to GLm. The gate driver 130 can take the form of an IC, or can be directly formed on the display panel 150 in an in-panel gate structure, but is not limited thereto.

[0032] The data driver 140 can sample and latch the data signal DATA in response to the data timing control signal DDC supplied from the timing controller 120, convert a digital data signal into an analog data voltage based on a gamma reference voltage, and output the analog data voltage. The data driver 140 can supply the data voltage to subpixels included in the display panel 150 through data lines DL1 to DLn. The data driver 140 can take the form of an IC and be mounted on the display panel 150 or mounted on a printed circuit board, but is not limited thereto.

[0033] The power supply 180 can generate a high-level voltage and a low-level voltage based on an external input voltage supplied from the outside, and output the high-level voltage and the low-level voltage through a first power supply line EVDD and a second power supply line EVSS. The power supply 180 can generate and output a voltage necessary to drive the gate driver 130 (e.g., a gate voltage including a gate high voltage and a gate low voltage) and a voltage necessary to drive the data driver 140 (a drain voltage including a drain voltage and a half-drain voltage) as well as the high-level voltage and the low-level voltage.

[0034] The display panel 150 can display an image in response to a driving signal including a gate signal and a data voltage, a driving voltage including a high-level voltage and a low-level voltage, etc. The sub-pixel of the display panel 150 directly emits light. The display panel 150 can be manufactured based on a substrate having rigidity or flexibility such as glass, silicon, polyimide, etc. Further, the sub-pixel that emits light can include red, green, and blue pixels, or include red, green, blue, and white pixels.

[0035] For example, one sub-pixel SP can be connected to a first data line DL1, a first gate line GL1, a first power supply line EVDD, and a second power supply line EVSS, and can include a pixel circuit including a switching transistor, a driving transistor, a capacitor, an organic light emitting diode, etc. Since the sub-pixel SP used in the light emitting display apparatus directly emits light, the circuit configuration is complex. Further, there are various compensation circuits for compensating for deterioration of the driving transistor for supplying a driving current necessary to drive the organic light emitting diode that emits light and the organic light emitting diode. In this regard, it should be noted that the sub-pixel SP is simply illustrated in the form of a block.

[0036] Meanwhile, in the above description, the timing controller 120, the gate driver 130, the data driver 140, etc. are described as separate components. However, depending on the implementation method of the light emitting display apparatus, one or more of the timing controller 120, the gate driver 130, and the data driver 140 can be integrated into one IC.

[0037] Figure 3 and Figure 4 is a diagram illustrating a configuration of an in-panel gate type gate driver, and Figure 5 is a diagram illustrating an arrangement example of the in-panel gate type gate driver.

[0038] As Figure 3As shown, the in-panel gate type gate driver 130 can include a shift register 131 and a level shifter 135. The level shifter 135 can generate a clock signal Clks and a start signal Vst based on signals and voltages output from the timing controller 120 and the power supply 180. The clock signal Clks can be generated in the form of j different phases (j is an integer equal to or greater than 2).

[0039] As shown in Figure 3 and Figure 4 Unlike the shift register 131, the level shifter 135 can be independently configured as an IC, or can be included in the power supply 180. However, this is merely an example, and the present disclosure is not limited thereto.

[0040] As shown in Figure 5 The first and second shift registers 131a and 131b outputting gate signals in the in-panel gate type gate driver can be disposed in the non-display area NA of the display panel 150. The first and second shift registers 131a and 131b can be formed as thin films on the display panel 150 in the in-panel gate structure. Although an example in which the first and second shift registers 131a and 131b are disposed in the left and right non-display areas NA of the display panel 150 is illustrated, the present disclosure is not limited thereto.

[0041] Figure 6 is a circuit configuration diagram of a sub-pixel suitable for an embodiment of the present disclosure, Figure 7 is Figure 6 a driving waveform diagram of a sub-pixel shown in Figures 8 to 11 shows the operation state of the device for each period according to the driving waveform shown in Figure 7

[0042] As shown in Figure 6 and Figure 7 A sub-pixel suitable for an embodiment of the present disclosure can include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a driving transistor DT, a capacitor CST, and an organic light emitting diode OLED, as shown in

[0043] ​The first transistor T1 can have a gate electrode connected to the first scan signal line SCN1, a first electrode connected to the first data line DL1, and a second electrode connected to the first electrode of the capacitor CST. The first transistor T1 can be turned on during the second period P2 in response to the first scan signal Scan1[n] applied through the first scan signal line SCN1. When the first transistor T1 is turned on, a data voltage applied through the first data line DL1 can be transmitted to the first electrode of the capacitor CST.

[0044] The second transistor T2 can have a gate electrode connected to the second scan signal line SCN2, a first electrode connected to the gate electrode of the driving transistor DT and the second electrode of the capacitor CST, and a second electrode connected to the second electrode of the driving transistor DT and the first electrode of the fourth transistor T4. The second transistor T2 can be turned on during the first period P1 and the second period P2 in response to the second scan signal Scan2[n] applied through the second scan signal line SCN2. When the second transistor T2 is turned on, the gate electrode and the second electrode of the driving transistor DT are connected, and thus the threshold voltage of the driving transistor DT can be sampled (threshold voltage compensation). Although the second transistor T2 can be formed of two transistors (double-gate transistor) as illustrated, so as to minimize a leakage current, it is not limited thereto.

[0045] The third transistor T3 can have a gate electrode connected to the first emission signal line EM1, a first electrode connected to the reference voltage line VREF, and a second electrode connected to the second electrode of the first transistor T1 and the first electrode of the capacitor CST. The third transistor T3 can be turned on during the first period P1 and the fourth period P4 in response to the first emission signal Em1[n] applied through the first emission signal line Em1. When the third transistor T3 is turned on, a voltage (such as an initialization voltage) applied through the reference voltage line VREF can be transmitted to the first electrode of the capacitor CST.

[0046] The fourth transistor T4 can have a gate electrode connected to the first emission signal line EM1, a first electrode connected to the second electrode of the driving transistor DT, and a second electrode connected to the anode of the organic light emitting diode OLED. The fourth transistor T4 can be turned on during the first period P1 and the fourth period P4 in response to the first emission signal Em1[n] applied through the first emission signal line Em1. When the fourth transistor T4 is turned on, a driving current generated from the driving transistor DT can be delivered to the anode of the organic light emitting diode OLED.

[0047] The fifth transistor T5 can have a gate electrode connected to the second scan signal line SCN2, a first electrode connected to the reference voltage line VREF, and a second electrode connected to the second electrode of the fourth transistor T4 and the anode of the organic light emitting diode OLED. In response to the second scan signal Scan2[n] applied through the second scan signal line SCN2, the fifth transistor T5 can be turned on during the first period P1 and the second period P2. When the fifth transistor T5 is turned on, a voltage (such as an initialization voltage) applied through the reference voltage line VREF can be transmitted to the anode of the organic light emitting diode OLED.

[0048] The driving transistor DT can include a gate electrode connected to the second electrode of the capacitor CST, a first electrode connected to the first power supply line EVDD, and a second electrode connected to the second electrode of the second transistor T2 and the first electrode of the fourth transistor T4. In response to the data voltage stored in the capacitor CST, the driving transistor DT can generate a driving current during the fourth period P4.

[0049] The organic light emitting diode OLED includes an anode connected to the second electrode of the fourth transistor T4 and the second electrode of the fifth transistor T5, and a cathode connected to the second power supply line EVSS. In response to the driving current transmitted through the turned-on fourth transistor T4, the organic light emitting diode OLED can emit light during the fourth period P4.

[0050] Figure 8 The illustrated first period P1 can be defined as an initialization period. Figure 9 The illustrated second period P2 can be defined as a data write and sampling period. Figure 10 The illustrated third period P3 can be defined as a holding period. Figure 11 The illustrated fourth period P4 can be defined as an emission period. The overall flow in the sub-pixel according to the operation state of the apparatus in each period according to the driving waveform can be as illustrated in Figure 6 and Figure 7 but this is only one example.

[0051] Figure 12 is a block diagram of a first shift register according to an experimental example, and Figure 13 is a block diagram of a first shift register according to an embodiment.

[0052] As illustrated in Figure 12 , the first shift register 131a according to the experimental example can include first scan signal generators SCN1[1] to SCN1[m], second scan signal generators SCN2[1] to SCN2[m], and emission signal generators EM[1] to EM[m]. The first shift register according to the experimental example can generate as illustrated in Figure 7The gate signals GL1 to GLm shown include scan signals and light emission signals, used to drive... Figure 6 The sub-pixels shown.

[0053] The first scan signal generator SCN1[1] to SCN1[m] and the second scan signal generator SCN2[1] to SCN2[m] can operate based on signals and voltages applied through the first clock signal line GCLKS, the first start signal line GVST, the first gate high voltage line VGH, and the first gate low voltage line VGL. The clock signal applied through the first clock signal line GCLKS can have at least 10 phases.

[0054] The light-emitting signal generators EM[1] to EM[m] can operate based on signals and voltages applied via a second clock signal line ECLKS, a second start signal line EVST, a second gate high voltage line VEH, and a second gate low voltage line VEL. The clock signal applied via the second clock signal line ECLKS can have at least two phases.

[0055] like Figure 13 As shown, the first shift register 131a according to the embodiment may include first scan signal generators SCN1[1] to SCN1[m], second scan signal generators SCN2[1] to SCN2[m], and light emission signal generators EM[1] to EM[m]. The first shift register according to the embodiment can generate signals such as... Figure 7 The gate signals GL1 to GLm shown include scan signals and light emission signals, used to drive... Figure 6 The sub-pixels shown.

[0056] The first scan signal generator SCN1[1] to SCN1[m] and the second scan signal generator SCN2[1] to SCN2[m] can operate based on signals and voltages applied through the first clock signal line GCLKS, the first start signal line GVST, the first gate high voltage line VGH and the first gate low voltage line VGL.

[0057] The light-emitting signal generators EM[1] to EM[m] can operate based on signals and voltages applied through the second clock signal line ECLKS, the second start signal line EVST, the second gate high voltage line VEH, and the second gate low voltage line VEL.

[0058] like Figure 12 and Figure 13As shown, the first scan signal generator SCN1[1], the second scan signal generator SCN2[1], and the first emission signal generator EM[1] can be included in the first stage STG1. The first gate signals including the first scan signal, the second scan signal, and the first emission signal output from the first stage STG1 can be transmitted through the first scan signal line, the second scan signal line, and the first emission signal line included in the first gate line GL1 located on the first horizontal line 1st. This can be understood from Figure 6 and Figure 7 determined.

[0059] Hereinafter, the circuits included in the second to Mth stages STG2 to STGm can be configured in the same manner as the first stage STG1, except that they are respectively connected to and output signals to the second horizontal line 2nd to the Mth horizontal line mth.

[0060] In an embodiment, unlike the experimental example, a total of four scan signal generators included in two stages (e.g., STG1 and STG2), for example, adjacent first scan signal generators (e.g., SCN1[1] and SCN1[2]) and adjacent second scan signal generators (e.g., SCN2[1] and SCN2[2]) can be grouped and integrated to form a single integrated scan signal generation circuit.

[0061] The above-described method of grouping and integrating a total of four scan signal generators adjacent to each other in the vertical and horizontal directions to form a single integrated scan signal generation circuit can be equally applied to the stages (not shown) of the second shift register as well as the stages STG1 to STGm of the first shift register 131a, a description of which will be provided hereinafter.

[0062] Figure 14 is a circuit configuration diagram of a scan signal generator suitable for the embodiments of the disclosure, Figure 15 is Figure 14 a driving waveform diagram of the scan signal generator shown in Figures 16 to 20 illustrates Figure 15 the operation state of the scan signal generator at each period in

[0063] As Figure 14 shown, the scan signal generator suitable for the embodiments can be connected to a start signal line VST, a gate low voltage line VGL, a gate high voltage line VGH, a first clock signal line CLK1, a third clock signal line CLK3, a fourth clock signal line CLK4, and a reset signal line QST.

[0064] A scan signal generator applicable to the embodiment can include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a stabilization transistor TBV, a sixth transistor T6_1, a seventh transistor T7_1, an eighth transistor T8, a ninth transistor T9, an output capacitor CQ1, and a node capacitor CQB.

[0065] For example, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the stabilization transistor TBV, the sixth transistor T6_1, the seventh transistor T7_1, the eighth transistor T8, and the ninth transistor T9 can be p-type transistors.

[0066] Further, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the eighth transistor T8, and the ninth transistor T9 can be formed of two transistors (double-gate transistors) to minimize generation of a leakage current, but the present disclosure is not limited thereto.

[0067] The first transistor T1 can have a gate electrode connected to a start signal line VST and a first electrode connected to a gate low voltage line VGL. The second transistor T2 can have a gate electrode connected to a fourth clock signal line CLK4, a first electrode connected to a second electrode of the first transistor T1, and a second electrode connected to a QN node QN. The third transistor T3 can have a gate electrode connected to a QB node QBN (an inverted node operating in opposition to the QN node), a first electrode connected to a gate high voltage line VGH, and a second electrode connected to the QN node QN.

[0068] The fourth transistor T4 can have a gate electrode connected to a third clock signal line CLK3, a first electrode connected to the gate low voltage line VGL, and a second electrode connected to the QB node QBN. The fifth transistor T5 can have a gate electrode connected to the start signal line VST, a first electrode connected to the gate high voltage line VGH, and a second electrode connected to the QB node QBN. The stabilization transistor TBV can have a gate electrode connected to the gate low voltage line VGL, a first electrode connected to the QN node QN, and a second electrode connected to a gate electrode of the sixth transistor T6_1.

[0069] The sixth transistor T6_1 may have a gate electrode connected to the second electrode of the stabilizing transistor TBV, a first electrode connected to the first clock signal line CLK1, and a second electrode connected to the output terminal G1O. The seventh transistor T7_1 may have a gate electrode connected to the QB node QBN, a first electrode connected to the gate high voltage line VGH, and a second electrode connected to the output terminal G1O. The eighth transistor T8 may have a gate electrode connected to the QN node QN, a first electrode connected to the gate high voltage line VGH, and a second electrode connected to the QB node QBN.

[0070] The ninth transistor T9 may have a gate electrode connected to the reset signal line QRST, a first electrode connected to the gate high voltage line VGH, and a second electrode connected to the QN node QN. The output capacitor CQ1 may have a first electrode connected to the gate electrode of the sixth transistor T6_1 and the second electrode of the stabilizing transistor TBV, and a second electrode connected to the output terminal G1O. The node capacitor CQB may have a first electrode connected to the gate high voltage line VGH and a second electrode connected to the QB node QBN.

[0071] exist Figure 15 and Figure 16 In the first time period P1 shown, the first transistor T1 can be turned on in response to a start signal Vst at a low voltage applied through the start signal line VST. The fifth transistor T5 can be turned on in response to a start signal Vst at a low voltage applied through the start signal line VST. The second transistor T2 can be turned on in response to a fourth clock signal at a low voltage applied through the fourth clock signal line CLK4. The stabilizing transistor TBV can be turned on in response to a gate low voltage at a low voltage applied through the gate low voltage line VGL.

[0072] exist Figure 15 and Figure 17 During the first time period P1, the QN node QN can be charged with a low gate voltage based on the conduction of the first transistor T1 and the second transistor T2, and the sixth transistor T6_1 can be turned on by the low gate voltage transmitted through the stabilizing transistor TBV. The QB node QBN can be charged with a high gate voltage based on the conduction of the fifth transistor T5 and the eighth transistor T8, and the seventh transistor T7_1 can be turned off by the high gate voltage. During the first time period P1, the QN node QN can be charged with a voltage corresponding to the sum of the low gate voltage and the threshold voltage of the transistor.

[0073] exist Figure 15 and Figure 18In the second period P2, as the first transistor T1, the second transistor T2, and the fifth transistor T5 are turned on, the QN node QN can enter a floating state. However, when the first clock signal Clk1 applied through the first clock signal line CLK1 changes to a low voltage, a bootstrap caused by the output capacitor CQ1 can occur in the QN node QN. Accordingly, the voltage Qn of the QN node QN can be lowered to the level of the gate low voltage. In addition, the low voltage of the first clock signal Clk1 can be output through the output terminal G1O via the turned-on sixth transistor T6_1. In this case, the low voltage of the first clock signal Clk1 output through the output terminal G1O can be used as the first scan signal G1 capable of turning on the transistors included in the sub-pixel.

[0074] In Figure 15 and Figure 19 In the third period P3, the low voltage charged in the QN node QN can still turn on the sixth transistor T6_1. However, the first clock signal Clk1 applied through the first clock signal line CLK1 can be in a state of changing from the low voltage to the high voltage. Accordingly, the high voltage of the first clock signal Clk1 can be output through the output terminal G1O via the turned-on sixth transistor T6_1.

[0075] In Figure 15 and Figure 20 In the fourth period P4, the fourth transistor T4 can be turned on by the third clock signal Clk3 at a logic voltage applied through the third clock signal line CLK3. The gate low voltage transferred through the fourth transistor T4 can charge the QB node QBN with the gate low voltage. The gate low voltage charged in the QB node QBN can turn on the third transistor T3, and the QN node QN can be charged with the gate high voltage applied through the gate high voltage line VGH through the turned-on third transistor T3. Accordingly, the sixth transistor T6_1 can be turned off. In contrast, the gate low voltage charged in the QB node QBN can turn on the seventh transistor T7_1, and the gate high voltage applied through the gate high voltage line VGH can be output through the output terminal G1O via the turned-on seventh transistor T7_1.

[0076] Figure 21 FIG. 1 is a diagram illustrating a concept of an integrated block of a shift register according to an embodiment of the disclosure, Figure 22 is an internal circuit configuration diagram of the integrated scan signal generation circuit illustrated in Figure 21 , and Figure 23 is a driving waveform diagram of the circuit illustrated in Figure 22 .

[0077] As Figure 21As shown, in an embodiment of the disclosure, the first scan signal generators (e.g., SCN1[1] and SCN1[2]) and the second scan signal generators (e.g., SCN2[1] and SCN2[2]) that generate scan signals supplied to the first gate line GL1 located on the first horizontal line 1st and the second gate line GL2 located on the second horizontal line 2nd can be grouped and integrated to form a single integrated scan signal generation circuit SCN[G1].

[0078] As before the integration, the integrated scan signal generation circuit SCN[G1] can generate scan signals supplied to the first gate line GL1 located on the first line 1st and the second gate line GL2 located on the second line 2nd. However, since a total of four signal generators are integrated, the circuit configuration is divided into a switching circuit SWTR for controlling nodes and an output circuit OUTBF for output signals. This will be described below. Here, the following description is based on Figure 14 The scan signal generators shown are to help understanding the description.

[0079] As Figure 22 As shown, the integrated scan signal generation circuit SCN[G1] according to an embodiment can include a switching circuit SWTR for controlling nodes and an output circuit OUTBF for output signals.

[0080] The switching circuit SWTR can include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a first stabilizing transistor TBV1, a second stabilizing transistor TBV2, a third stabilizing transistor TBV3, a fourth stabilizing transistor TBV4, an eighth transistor T8, a ninth transistor T9, and a node capacitor CQB.

[0081] The third transistor T3, the fourth transistor T4, the fifth transistor T5, the eighth transistor T8, and the ninth transistor T9 can be composed of two transistors (double-gate transistors) to minimize generation of a leakage current, but the disclosure is not limited thereto.

[0082] The first transistor T1 can have a gate electrode connected to the start signal line VST and a first electrode connected to the gate low voltage line VGL. The second transistor T2 can have a gate electrode connected to the (2-6)th clock signal line G2CLK6, a first electrode connected to the second electrode of the first transistor T1, and a second electrode connected to the common QN node QCN. The third transistor T3 can have a gate electrode connected to the QB node QBN, a first electrode connected to the gate high voltage line VGH, and a second electrode connected to the common QN node QCN. The (2-6)th clock signal line G2CLK6 can be defined as a common node clock signal line because a clock signal for controlling the common QN node QCN is applied thereto.

[0083] The fourth transistor T4 can have a gate electrode connected to the (2-4)th clock signal line G2CLK4, a first electrode connected to the gate low voltage line VGL, and a second electrode connected to the QB node QBN. The fifth transistor T5 can have a gate electrode connected to the start signal line VST, a first electrode connected to the gate high voltage line VGH, and a second electrode connected to the QB node QBN. The (2-4)th clock signal line G2CLK4 can be defined as an inverted node clock signal line because a clock signal for controlling the QB node QBN is applied thereto.

[0084] The first stabilizing transistor TBV1 can have a gate electrode connected to the gate low voltage line VGL, a first electrode connected to the common QN node QCN, and a second electrode connected to the first QN node QN1. The second stabilizing transistor TBV2 can have a gate electrode connected to the gate low voltage line VGL, a first electrode connected to the common QN node QCN, and a second electrode connected to the second QN node QN2. The third stabilizing transistor TBV3 can have a gate electrode connected to the gate low voltage line VGL, a first electrode connected to the common QN node QCN, and a second electrode connected to the third QN node QN3. The fourth stabilizing transistor TBV4 can have a gate electrode connected to the gate low voltage line VGL, a first electrode connected to the common QN node QCN, and a second electrode connected to the fourth QN node QN4.

[0085] The eighth transistor T8 can have a gate electrode connected to the common QN node QCN, a first electrode connected to the gate high voltage line VGH, and a second electrode connected to the QB node QBN. The ninth transistor T9 can have a gate electrode connected to the second reset signal line G2QRST, a first electrode connected to the gate high voltage line VGH, and a second electrode connected to the common QN node QCN. The node capacitor CQB can have a first electrode connected to the gate high voltage line VGH and a second electrode connected to the QB node QBN.

[0086] The output circuit OUTBF can include a (6-1)th transistor T6_1, a (6-2)th transistor T6_2, a (6-3)th transistor T6_3, a (6-4)th transistor T6_4, a (7-1)th transistor T7_1, a (7-2)th transistor T7_2, a (7-3)th transistor T7_3, a (7-4)th transistor T7_4, a (1-1)st output capacitor CQ1, a (1-2)nd output capacitor CQ2, a (2-1)st output capacitor CQ3, and a (2-2)nd output capacitor CQ4. The (6-1)th transistor T6_1, the (6-2)th transistor T6_2, the (6-3)th transistor T6_3, and the (6-4)th transistor T6_4 can be defined as a (1-1)st pull-up transistor, a (1-2)nd pull-up transistor, a (2-1)st pull-up transistor, and a (2-2)nd pull-up transistor, respectively. In addition, the (7-1)th transistor T7_1, the (7-2)th transistor T7_2, the (7-3)th transistor T7_3, and the (7-4)th transistor T7_4 can be defined as a (1-1)st pull-down transistor, a (1-2)nd pull-down transistor, a (2-1)st pull-down transistor, and a (2-2)nd pull-down transistor, respectively.

[0087] The (6-1)th transistor T6_1 can have a gate electrode connected to the first QN node QN1 that is the second electrode of the first stabilizing transistor TBV1, a first electrode connected to the (1-1)st clock signal line G1CLK1, and a second electrode connected to the (1-1)st output terminal G1O(1st). The (7-1)th transistor T7_1 can have a gate electrode connected to the QB node QBN, a first electrode connected to the gate high voltage line VGH, and a second electrode connected to the (1-1)st output terminal G1O(1st). The first output capacitor CQ1 can have a first electrode connected to the gate electrode of the (6-1)th transistor T6_1 and the first QN node QN1 that is the second electrode of the first stabilizing transistor TBV1, and a second electrode connected to the (1-1)st output terminal G1O(1st).

[0088] The (6-2)th transistor T6_2 can have a gate electrode connected to the second QN node QN2 which is a second electrode of the second stable transistor TBV2, a first electrode connected to the (1-2)th clock signal line G2CLK1, and a second electrode connected to the (1-2)th output terminal G2O(1st). The (7-2)th transistor T7_2 can have a gate electrode connected to the QB node QBN, a first electrode connected to the gate high voltage line VGH, and a second electrode connected to the (1-2)th output terminal G2O(1st). The second output capacitor CQ2 can have a first electrode connected to the gate electrode of the (6-2)th transistor T6_2 and the second QN node QN2 which is a second electrode of the second stable transistor TBV2, and a second electrode connected to the (1-2)th output terminal G2O(1st).

[0089] The (6-3)th transistor T6_3 can have a gate electrode connected to the third QN node QN3 which is a second electrode of the third stable transistor TBV3, a first electrode connected to the (2-1)th clock signal line G1CLK2, and a second electrode connected to the (2-1)th output terminal G1O(2nd). The (7-3)th transistor T7_3 can have a gate electrode connected to the QB node QBN, a first electrode connected to the gate high voltage line VGH, and a second electrode connected to the (2-1)th output terminal G1O(2nd). The third output capacitor CQ3 can have a first electrode connected to the gate electrode of the (6-3)th transistor T6_3 and the third QN node QN3 which is a second electrode of the third stable transistor TBV3, and a second electrode connected to the (2-1)th output terminal G1O(2nd).

[0090] The (6-4)th transistor T6_4 can have a gate electrode connected to the fourth QN node QN4 which is a second electrode of the fourth stable transistor TBV4, a first electrode connected to the (2-2)th clock signal line G2CLK2, and a second electrode connected to the (2-2)th output terminal G2O(2nd). The (7-4)th transistor T7_4 can have a gate electrode connected to the QB node QBN, a first electrode connected to the gate high voltage line VGH, and a second electrode connected to the (2-2)th output terminal G2O(2nd). The fourth output capacitor CQ4 can have a first electrode connected to the gate electrode of the (6-4)th transistor T6_4 and the fourth QN node QN4 which is a second electrode of the fourth stable transistor TBV4, and a second electrode connected to the (2-2)th output terminal G2O(2nd).

[0091] As Figure 22 and Figure 23As shown, the integrated scan signal generation circuit SCN[G1] according to the embodiment can operate based on the (1-1)th clock signal G1 Clk1, the (2-1)th clock signal G1 Clk2, the (3-1)th clock signal G1 Clk3, the (4-1)th clock signal G1 Clk4, the (1-2)th clock signal G2 Clk1, the (2-2)th clock signal G2 Clk2, the (3-2)th clock signal G2 Clk3, the (4-2)th clock signal G2 Clk4, the (5-2)th clock signal G2 Clk5, and the (6-2)th clock signal G2 Clk6.

[0092] The relationship between the clock signals for driving the integrated scan signal generation circuit SCN[G1] according to the embodiment will be described as follows.

[0093] The (1-1)th clock signal G1 Clk1, the (2-1)th clock signal G1 Clk2, the (3-1)th clock signal G1 Clk3, and the (4-1)th clock signal G1 Clk4 can generate a low voltage in a time close to one horizontal period (1H). The (1-2)th clock signal G2 Clk1, the (2-2)th clock signal G2 Clk2, the (3-2)th clock signal G2 Clk3, the (4-2)th clock signal G2 Clk4, the (5-2)th clock signal G2 Clk5, and the (6-2)th clock signal G2 Clk6 can generate a low voltage in a time close to 2 horizontal periods (2H).

[0094] The (4-1)th clock signal G1 Clk4 can change from a high voltage to a low voltage after the (6-2)th clock signal G2 Clk6 changes from a high voltage to a low voltage. The (1-1)th clock signal G1 Clk1 can change from a high voltage to a low voltage after the (1-2)th clock signal G2 Clk1 changes from a high voltage to a low voltage. The (2-1)th clock signal G1 Clk2 can change from a high voltage to a low voltage after the (2-2)th clock signal G2 Clk2 changes from a high voltage to a low voltage. The (3-1)th clock signal G1 Clk3 can change from a high voltage to a low voltage after the (3-2)th clock signal G2 Clk3 changes from a high voltage to a low voltage.

[0095] The periods during which the (4-1)th clock signal G1 Clk4, the (1-1)th clock signal G1 Clk1, the (2-1)th clock signal G1 Clk2, and the (3-1)th clock signal G1 Clk3 hold a low voltage can not overlap. On the other hand, the periods during which the (6-2)th clock signal G2 Clk6 and the (1-2)th clock signal G2 Clk1 hold a low voltage can overlap, the periods during which the (1-2)th clock signal G2 Clk1 and the (2-2)th clock signal G2 Clk1 hold a low voltage can overlap, the periods during which the (2-2)th clock signal G2 Clk2 and the (3-2)th clock signal G2 Clk3 hold a low voltage can overlap, the periods during which the (3-2)th clock signal G2 Clk3 and the (4-2)th clock signal G2 Clk4 hold a low voltage can overlap, and the periods during which the (4-2)th clock signal G2 Clk4 and the (5-2)th clock signal G2 Clk5 hold a low voltage can overlap.

[0096] Based on the clock signals described above, a method of driving the integrated scan signal generation circuit SCN[G1] according to the embodiment will be described below. However, since the operation of the switching circuit SWTR has already been described with reference to Figures 16 to 20 Since the operation of the switching circuit SWTR has already been described with reference to

[0097] As Figure 22 and Figure 23 indicated, when the QB node QBN has been charged with a high voltage (refer to QBn in Figure 23 ), the common QN node QCN can be in a state in which it has been charged with a low voltage (period during which QCN is low). This can be confirmed by referring to the charging states of the first to fourth QN nodes QN1 to QN4 (Qn1 to Qn4 in Figure 23 ).

[0098] The (6-1)th transistor T6_1 can turn on in response to the voltage Qn1 charged in the first QN node QN1 serving as the second electrode of the first stable transistor TBV1. When the (1-1)th clock signal G1 Clk1 applied through the (1-1)th clock signal line G1CLK1 changes from a high voltage to a low voltage in a state in which the (6-1)th transistor T6_1 is turned on, bootstrap caused by the first output capacitor CQ1 can occur in the first QN node QN1.

[0099] Accordingly, the voltage Qn1 of the first QN node QN1 can be lowered to the level of the gate low voltage. Also, the low voltage of the (1-1)th clock signal G1 Clk1 can be output through the (1-1)th output terminal G1O(1st) via the turned-on (6-1)th transistor T6_1. Since the low voltage output through the (1-1)th output terminal G1O(1st) corresponds to the first scan signal Scan1[n] in the (1-1)th clock signal G1 Clk1, it can be used as the first scan signal G1(1st) applied to the first horizontal line 1st. Since the first scan signal G1(1st) applied to the first horizontal line 1st is output through the (1-1)th output terminal G1O(1st), it can be defined as the (1-1)th scan signal G1(1st). Figure 7

[0100] The (6-2)th transistor T6_2 can be turned on in response to the voltage Qn2 charged in the second QN node QN2 which is the second electrode of the second stable transistor TBV2. When the (1-2)th clock signal G2 Clk1 applied through the (1-2)th clock signal line G2CLK1 changes from a high voltage to a low voltage in a state where the (6-2)th transistor T6_2 is turned on, a bootstrap caused by the second output capacitor CQ2 can occur in the second QN node QN2.

[0101] Accordingly, the voltage Qn2 of the second QN node QN2 can be lowered to the level of the gate low voltage. Also, the low voltage of the (1-2)th clock signal G2 Clk1 can be output through the (1-2)th output terminal G2O(1st) via the turned-on (6-2)th transistor T6_2. Since the low voltage output through the (1-2)th output terminal G2O(1st) corresponds to the second scan signal Scan2[n] in the (1-2)th clock signal G2 Clk1, it can be used as the second scan signal G2(1st) applied to the first horizontal line 1st. Since the second scan signal G2(1st) applied to the first horizontal line 1st is output through the (1-2)th output terminal G2O(1st), it can be defined as the (1-2)th scan signal G2(1st). Figure 7

[0102] The (6-3)th transistor T6_3 can be turned on in response to the voltage Qn3 charged in the third QN node QN3 which is the second electrode of the third stable transistor TBV3. When the (2-1)th clock signal G1 Clk2 applied through the (2-1)th clock signal line G1CLK2 changes from a high voltage to a low voltage in a state where the (6-3)th transistor T6_3 is turned on, a bootstrap caused by the third output capacitor CQ3 can occur in the third QN node QN3.

[0103] ​​Accordingly, the voltage Qn3 of the third QN node QN3 can be lowered to the level of the gate low voltage. Also, the low voltage of the (2-1)th clock signal G1 Clk2 can be output through the (2-1)th output terminal G1O(2nd) via the turned-on (6-3)th transistor T6_3. Since the low voltage output through the (2-1)th output terminal G1O(2nd) is similar to the first scan signal Scan1[n] in the (2-1)th clock signal G1 Clk2, it can be used as the first scan signal G1(2nd) applied to the second horizontal line 2nd. Since the first scan signal G1(2nd) applied to the second horizontal line 2nd is output through the (2-1)th output terminal G1O(2nd), it can be defined as the (2-1)th scan signal G1(2nd). Figure 7

[0104] The (6-4)th transistor T6_4 can be turned on in response to the voltage Qn4 charged in the fourth QN node QN4 which is the second electrode of the fourth stable transistor TBV4. When the (2-2)th clock signal G2 Clk2 applied through the (2-2)th clock signal line G2CLK2 changes from a high voltage to a low voltage in a state in which the (6-4)th transistor T6_4 is turned on, bootstrap caused by the fourth output capacitor CQ4 can occur in the fourth QN node QN4.

[0105] Accordingly, the voltage Qn4 of the fourth QN node QN4 can be lowered to the level of the gate low voltage. Also, the low voltage of the (2-2)th clock signal G2 Clk2 can be output through the (2-2)th output terminal G2O(2nd) via the turned-on (6-4)th transistor T6_4. Since the low voltage output through the (2-2)th output terminal G2O(2nd) is similar to the second scan signal Scan2[n] in the (2-2)th clock signal G2 Clk2, it can be used as the second scan signal G2(2nd) applied to the second horizontal line 2nd. Since the second scan signal G2(2nd) applied to the second horizontal line 2nd is output through the (2-2)th output terminal G2O(2nd), it can be defined as the (2-2)th scan signal G2(2nd). Figure 7

[0106] The period in which the (1-1)th scan signal G1(1st) maintains a low voltage and the period in which the (2-1)th scan signal G1(2nd) maintains a low voltage can not overlap. On the other hand, the period in which the (1-2)th scan signal G2(1st) maintains a low voltage and the period in which the (2-2)th scan signal G2(2nd) maintains a low voltage can partially overlap.

[0107] ​​The common QN node QCN charged with the low voltage can be maintained until a period when the (2-4)th clock signal G2 Clk4 applied through the (2-4)th clock signal line G2CLK4 changes from the high voltage to the low voltage.

[0108] Thereafter, when the (2-4)th clock signal G2 Clk4 applied through the (2-4)th clock signal line G2CLK4 changes from the high voltage to the low voltage, the QB node QBN charged with the gate low voltage and the third transistor T3 can be turned on. When the third transistor T3 is turned on, the common QN node QCN can be charged with the gate high voltage and the (6-1)th to (6-4)th transistors T6_1 to T6_4 can be turned off. On the other hand, the (7-1)th to (7-4)th transistors T7_1 to T7_4 are turned on, and thus the gate high voltage can be output to the (1-1)st, (2-1)st, (1-2)nd, and (2-2)nd output terminals G1O(1st), G2O(1st), G1O(2nd), and G2O(2nd).

[0109] As described above, by grouping and integrating a total of four scan signal generators included in two stages to form a single integrated scan signal generation circuit, the present disclosure has an effect of reducing a circuit area of a shift register for outputting a scan signal. Further, based on the reduction of the circuit area of the shift register for outputting the scan signal, the present disclosure has an effect of reducing a size of a bezel of a display panel.

Claims

1. A display apparatus comprising: a display panel; and a scan signal generator configured to generate a 1-1 scan signal and a 1-2 scan signal supplied to a first horizontal line of the display panel and a 2-1 scan signal and a 2-2 scan signal supplied to a second horizontal line of the display panel, wherein the scan signal generator comprises: a switching circuit including a common node charged with a low voltage applied by a turn-on operation of first and second transistors, an inverting node operated in opposition to the common node, and first to fourth stable transistors having a first electrode connected to the common node and a gate electrode connected to a gate low voltage line; and an output circuit including 1-1 and 1-2 pull-up transistors outputting the 1-1 and 1-2 scan signals in response to a voltage of a first node corresponding to a second electrode of the first stable transistor and a voltage of a second node corresponding to a second electrode of the second stable transistor, and 2-1 and 2-2 pull-up transistors outputting the 2-1 and 2-2 scan signals in response to a voltage of a third node corresponding to a second electrode of the third stable transistor and a voltage of a fourth node corresponding to a second electrode of the fourth stable transistor. The 1-1 pull-up transistor includes a gate electrode connected to the first node, a first electrode connected to a 1-1 clock signal line, and a second electrode connected to a 1-1 output terminal, 2. The display device according to claim 1, wherein The 1-2 pull-up transistor includes a gate electrode connected to the second node, a first electrode connected to a 1-2 clock signal line, and a second electrode connected to a 1-2 output terminal, The 2-1 pull-up transistor includes a gate electrode connected to the third node, a first electrode connected to a 2-1 clock signal line, and a second electrode connected to a 2-1 output terminal, and The 2-2 pull-up transistor includes a gate electrode connected to the fourth node, a first electrode connected to a 2-2 clock signal line, and a second electrode connected to a 2-2 output terminal. The output circuit includes:

3. The display device of claim 2, wherein, a 1-1 pull-down transistor including a gate electrode connected to the inverting node, a first electrode connected to a gate high voltage line, and a second electrode connected to the 1-1 output terminal; a 1-2 pull-down transistor including a gate electrode connected to the inverting node, a first electrode connected to the gate high voltage line, and a second electrode connected to the 1-2 output terminal; a 2-1 pull-down transistor including a gate electrode connected to the inverting node, a first electrode connected to the gate high voltage line, and a second electrode connected to the 2-1 output terminal; and a 2-2 pull-down transistor including a gate electrode connected to the inverting node, a first electrode connected to the gate high voltage line, and a second electrode connected to the 2-2 output terminal. The output circuit includes:

4. The display device according to claim 3, wherein ​ a first 1-1 capacitor including a first electrode connected to the gate electrode of the first 1-1 pull-up transistor and a second electrode connected to the first 1-1 output terminal; a first 1-2 capacitor including a first electrode connected to the gate electrode of the first 1-2 pull-up transistor and a second electrode connected to the first 1-2 output terminal; a second 1-1 capacitor including a first electrode connected to the gate electrode of the second 1-1 pull-up transistor and a second electrode connected to the second 1-1 output terminal; and a second 1-2 capacitor including a first electrode connected to the gate electrode of the second 1-2 pull-up transistor and a second electrode connected to the second 1-2 output terminal.

5. The display device according to claim 1, wherein The first transistor includes a gate electrode connected to a start signal line and a first electrode connected to a gate low voltage line, and the second transistor includes a gate electrode connected to a common node clock signal line, a first electrode connected to a second electrode of the first transistor, and a second electrode connected to the common node.

6. The display device of claim 5, wherein, The switching circuit includes: a third transistor including a gate electrode connected to the inversion node, a first electrode connected to a gate high voltage line, and a second electrode connected to the common node; a fourth transistor including a gate electrode connected to an inversion node clock signal line, a first electrode connected to the gate low voltage line, and a second electrode connected to the inversion node; a fifth transistor including a gate electrode connected to the start signal line, a first electrode connected to the gate high voltage line, and a second electrode connected to the inversion node; an eighth transistor including a gate electrode connected to the common node, a first electrode connected to the gate high voltage line, and a second electrode connected to the inversion node; a ninth transistor including a gate electrode connected to a reset signal line, a first electrode connected to the gate high voltage line, and a second electrode connected to the common node; and a node capacitor including a first electrode connected to the gate high voltage line and a second electrode connected to the inversion node.

7. The display device according to claim 1, wherein The period in which the first 1-1 scan signal remains at a low voltage and the period in which the second 1-1 scan signal remains at a low voltage do not overlap, and the period in which the first 1-2 scan signal remains at a low voltage and the period in which the second 1-2 scan signal remains at a low voltage partially overlap.

8. A scan signal generation circuit, comprising: a switching circuit including a common node charged with a low voltage applied by on operations of first and second transistors, an inversion node operating in opposition to the common node, and first to fourth stabilization transistors including a gate electrode connected to the common node and a first electrode connected to a gate low voltage line; and a node capacitor including a first electrode connected to the gate high voltage line and a second electrode connected to the inversion node. an output circuit including first-1 and first-2 pull-up transistors outputting first-1 and first-2 scan signals in response to a voltage of a first node corresponding to a second electrode of the first stable transistor and a voltage of a second node corresponding to a second electrode of the second stable transistor, and second-1 and second-2 pull-up transistors outputting second-1 and second-2 scan signals in response to a voltage of a third node corresponding to a second electrode of the third stable transistor and a voltage of a fourth node corresponding to a second electrode of the fourth stable transistor.

9. The scan signal generation circuit of claim 8, wherein, The first-1 pull-up transistor includes a gate electrode connected to the first node, a first electrode connected to a first-1 clock signal line, and a second electrode connected to a first-1 output terminal, The first-2 pull-up transistor includes a gate electrode connected to the second node, a first electrode connected to a first-2 clock signal line, and a second electrode connected to a first-2 output terminal, The second-1 pull-up transistor includes a gate electrode connected to the third node, a first electrode connected to a second-1 clock signal line, and a second electrode connected to a second-1 output terminal, and The second-2 pull-up transistor includes a gate electrode connected to the fourth node, a first electrode connected to a second-2 clock signal line, and a second electrode connected to a second-2 output terminal.

10. The scan signal generation circuit of claim 9, wherein, The output circuit includes: a first-1 pull-down transistor including a gate electrode connected to the inversion node, a first electrode connected to a gate high voltage line, and a second electrode connected to the first-1 output terminal; a first-2 pull-down transistor including a gate electrode connected to the inversion node, a first electrode connected to the gate high voltage line, and a second electrode connected to the first-2 output terminal; a second-1 pull-down transistor including a gate electrode connected to the inversion node, a first electrode connected to the gate high voltage line, and a second electrode connected to the second-1 output terminal; a second-2 pull-down transistor including a gate electrode connected to the inversion node, a first electrode connected to the gate high voltage line, and a second electrode connected to the second-2 output terminal; a first-1 capacitor including a first electrode connected to the gate electrode of the first-1 pull-up transistor and a second electrode connected to the first-1 output terminal; a first-2 capacitor including a first electrode connected to the gate electrode of the first-2 pull-up transistor and a second electrode connected to the first-2 output terminal; a second-1 capacitor including a first electrode connected to the gate electrode of the second-1 pull-up transistor and a second electrode connected to the second-1 output terminal; and a second-2 capacitor including a first electrode connected to the gate electrode of the second-2 pull-up transistor and a second electrode connected to the second-2 output terminal.

Images