A SiC UMOSFET device with integrated HJD and its fabrication method

Abstract

The application relates to a SiC UMOSFET device integrated with an HJD and a preparation method thereof, which comprises a metalized drain, an N+ substrate region, an N-epitaxial region, an N-csl region, a P-base region, a P+ buried layer, two P+ injection regions, an N+ injection region, a P+ PolySi region, a gate dielectric layer, an N-PolySi gate and a metalized source. The depth of the N-PolySi gate is greater than that of the P-base region, the depth of the P+ buried layer and the second P+ injection region is the same and greater than the trench depth. The contact interface between the source and the first P+ injection region and the N+ injection region is ohmic contact, and the interface between the P+ PolySi region and the N-epitaxial region is heterojunction contact. The application integrates a heterojunction diode structure in the device, improves the utilization rate of the cell area, further reduces the opening voltage, reduces the switching loss of the device, and improves the withstand voltage capacity of the device through the P+ buried layer and the P+ injection region.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, specifically to a SiC UMOSFET device with integrated HJD and its fabrication method. Background Technology

[0002] Silicon carbide (SiC) has a wider bandgap, a larger critical breakdown electric field, and higher thermal conductivity than silicon, giving SiC devices better radiation resistance, lower on-resistance, and lower energy loss. In summary, SiC devices offer significant advantages in high-power, high-temperature, high-radiation environments, as well as energy efficiency and environmental friendliness.

[0003] Metal-oxide-semiconductor field-effect transistors (MOSFETs) are widely used in power electronic systems due to their high integration density, good thermal stability, and strong radiation resistance. SiC MOSFETs, as a new third-generation semiconductor device, are currently the most favored silicon carbide power semiconductor device in industry due to their low on-state resistance, fast switching speed, and simple drive circuitry. Meanwhile, U-trench metal-oxide-semiconductor field-effect transistors (UMOSFETs) offer advantages such as low on-resistance, high switching speed, high-temperature performance, high voltage withstand capability, and smaller size, making them promising for future applications.

[0004] In power electronic systems, SiC MOSFETs primarily function as electronic switches. When the MOSFET is in the off state, there is a reverse leakage current between the drain and source. Without an anti-parallel diode, this leakage current could damage other components in the circuit. Furthermore, when SiC MOSFETs are used for AC circuit rectification, since the MOSFET can only conduct under forward voltage, an anti-parallel diode is needed to provide a conduction path under reverse voltage, thereby achieving current rectification. Therefore, a diode is typically connected in anti-parallel externally or integrated internally within the SiC MOSFET to improve the performance of the SiC MOSFET's body diode, thus increasing the SiC MOSFET's operating efficiency.

[0005] Connecting a reverse-parallel diode outside the SiC MOSFET can significantly improve the performance of the SiC MOSFET body diode, but it increases the circuit footprint, raises the device packaging cost, and introduces parasitic capacitance and inductance, resulting in a slower response speed of the reverse diode. Therefore, existing technologies integrate Schottky barrier diodes (SBDs) and junction barrier Schottky diodes (JBSs) inside the SiC MOSFET. However, the internally integrated SBDs and JBSs still have a large turn-on voltage and have high design complexity and manufacturing cost, so further technological improvements are needed. Summary of the Invention

[0006] To address the aforementioned problems in the prior art, this invention provides a SiC UMOSFET device with integrated HJD and its fabrication method. The technical problem to be solved by this invention is achieved through the following technical solution:

[0007] A SiC UMOSFET device with integrated HJD, the SiC UMOSFET device comprising a metallized drain, an N+ substrate layer, an N-epipolar layer and an N-current extension region stacked sequentially from bottom to top, wherein the contact between the N+ substrate layer and the metallized drain is an ohmic contact;

[0008] The N-current extension region is provided with a trench, a gate dielectric layer is provided in the trench, and an N-polysilicon gate is provided in the groove of the gate dielectric layer.

[0009] A P+ buried layer is disposed within part of the N-epipolar layer and within the groove on the lower surface of the N-current extension region, and a P-base region, a first P+ injection region, and an N+ injection region are disposed within the N-current extension region.

[0010] The N-current extension region and the second P+ injection region are located on both sides of the gate dielectric layer, respectively. The second P+ injection region is partially disposed within the N-epitaxial layer and partially disposed within the N-current extension region, and the lower end of the second P+ injection region wraps around the lower corner of one side of the lower end of the gate dielectric layer.

[0011] The P+ buried layer is located below the N- current extension region, and the P+ buried layer wraps around the lower corner of the other side of the lower end of the gate dielectric layer;

[0012] The P-base region is located above the remaining N-current extension region, the first P+ injection region and the N+ injection region are located above the P-base region, and the N+ injection region is located between the gate dielectric layer and the first P+ injection region; a metallized source is provided on the first P+ injection region and the N+ injection region;

[0013] A P+ polysilicon region is provided at the bottom of the trench, and the gate dielectric layer is provided on both sides and above the P+ polysilicon region. The lower end of the P+ polysilicon region is in direct contact with the N- epitaxial layer to form a heterojunction contact, and is connected to the metallization source through a via.

[0014] The contact between the metallized source and the P+ polysilicon region, the first P+ implantation region, and the N+ implantation region is an ohmic contact.

[0015] In one embodiment of the present invention, the depth of the N-current extension region is greater than the thickness of the N-polysilicon gate.

[0016] In one embodiment of the present invention, the depth of the P-base region is less than the depth of the N-current extension region, and the width of the P-base region is equal to the width of the N-current extension region.

[0017] In one embodiment of the present invention, the depth of the first P+ injection region is less than the depth of the P- base region, and the depth of the second P+ injection region is greater than the thickness of the gate dielectric layer.

[0018] In one embodiment of the present invention, the depth of the N+ injection region is equal to the depth of the first P+ injection region, and the sum of the widths of the N+ injection region and the first P+ injection region is equal to the width of the N-current extension region.

[0019] In one embodiment of the present invention, the depth of the trench is equal to the depth of the N-current extension region, and the depth of the trench is less than the depth of the second P+ injection region, and the width of the trench is greater than the shortest distance between the P+ buried layer and the second P+ injection region.

[0020] In one embodiment of the present invention, the width of the metallized source is less than the sum of the widths of the first P+ injection region and the N+ injection region.

[0021] In one embodiment of the present invention, the doping concentration of the N-current extension region is greater than the doping concentration of the N-epitaxial layer.

[0022] In one embodiment of the present invention, the doping concentrations of the first P+ implantation region and the second P+ implantation region are the same.

[0023] A method for fabricating a SiC UMOSFET device with integrated HJD, used to fabricate the SiC UMOSFET device described in any of the above embodiments, the fabrication method comprising:

[0024] Step 1: Select an N+ substrate layer;

[0025] Step 2: An N- epitaxial layer is formed on the N+ substrate layer using an epitaxial growth method;

[0026] Step 3: Ion implantation is performed on the surface of the N- epitaxial layer to form a P+ buried layer;

[0027] Step 4: Etch the N-epitaxial layer.

[0028] Step 5: Continue epitaxial growth on the surface of the N-epitaxial layer to form an N-current extension region;

[0029] Step 6: Perform ion implantation on the surface of the N-current extension region to form a second P+ implantation region on one side of the N-current extension region;

[0030] Step 7: Grooves are formed on the surfaces of the N-current extension region and the second P+ injection region to form trenches, and P+ polysilicon regions are deposited at the bottom of the trenches;

[0031] Step 8: Perform ion implantation on the surface of the N-current extension region to form a P-base region, and then perform ion implantation on the surface of the P-base region to form a first P+ implantation region;

[0032] Step 9: Perform ion implantation on the surface of the first P+ implantation region to form an N+ implantation region, then form a gate dielectric layer in the trench, and form an N-polysilicon gate in the groove of the gate dielectric layer.

[0033] Step 10: Form a metallized drain on the lower surface of the N+ substrate layer, and form a metallized source on the first P+ implantation region and the N+ implantation region.

[0034] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0035] The contact between the P+ polysilicon region and the N- epitaxial layer in this invention is a heterojunction contact, that is, an HJD structure is integrated inside the SiC UMOSFET device. This replaces the SBD or JBS structure integrated inside a typical SiC UMOSFET device. Because there is a smaller potential barrier difference between the P+ polysilicon region and the N- epitaxial layer, the HJD structure of this invention has a lower turn-on voltage (1.45V). As the HJD operates as a unipolar device, it further reduces switching losses, improves the energy conversion efficiency of the device, effectively suppresses minority carrier injection into the drift region, thereby suppressing bipolar degradation and optimizing reverse recovery characteristics.

[0036] The P+ buried layer and the second P+ implantation region in the N-epitaxial layer of the present invention have a combined shielding effect, which can protect the heterojunction interface and the U-shaped trench gate from the influence of high electric field and improve the withstand voltage capability of the device.

[0037] The first P+ injection region of the present invention can suppress the turn-on of the parasitic transistor composed of the N+ injection region, the P-base region and the N-csl region, thereby further improving the device performance.

[0038] The N-csl region of this invention can effectively reduce the JFET resistance, improve the conductivity of the device, and enhance the reliability of the device.

[0039] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0040] Figure 1 This is a schematic diagram of the structure of a SiC UMOSFET device with integrated HJD provided in an embodiment of the present invention;

[0041] Figures 2a-2i This is a schematic diagram illustrating the process of fabricating a SiC UMOSFET device with integrated HJD provided in an embodiment of the present invention.

[0042] Explanation of reference numerals in the attached figures:

[0043] 1-N+ substrate layer; 2-N-epitaxial layer; 3-P+ buried layer; 4-N-CSL region (N-current spread region); 5-Second P+ implantation region; 6-Trench; 7-P+PolySi region (P+ polysilicon region); 8-P-base region (P-base region); 9-First P+ implantation region; 10-N+ implantation region; 11-Gate dielectric layer; 12-N-PolySi gate (N-polysilicon gate); 13-Metalized drain; 14-Metalized source. Detailed Implementation

[0044] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0045] Example 1

[0046] Please see Figure 1 , Figure 1 This is a schematic diagram of a SiC UMOSFET device with integrated HJD provided in an embodiment of the present invention. The present invention provides a SiC UMOSFET device with integrated HJD, which includes a metallized drain 13, an N+ substrate layer 1, an N- epitaxial layer 2, and an N- current extension region 4 stacked sequentially from bottom to top. The contact between the N+ substrate layer 1 and the metallized drain 13 is an ohmic contact.

[0047] The N-current extension region 4 has a trench, a gate dielectric layer 11 is disposed in the trench, and an N-polysilicon gate 12 is disposed in the groove of the gate dielectric layer 11. The trench extends to the surface of the N-epitaxial layer 2.

[0048] A P+ buried layer 3 is disposed within a portion of the N-epitaxial layer 2 and within a groove on the lower surface of the N-current extension region 4. Specifically, a portion of the P+ buried layer 3 is located within the N-epitaxial layer, and a portion of the P+ buried layer 3 is located within a groove on the lower surface of the N-current extension region 4. Furthermore, the N-current extension region 4 contains a P-base region 8, a first P+ implantation region 9, and an N+ implantation region 10.

[0049] The N-current extension region 4 and the second P+ injection region 5 are located on both sides of the gate dielectric layer 11, respectively. The second P+ injection region 5 is partially disposed in the N-epitaxy layer 2 and partially disposed in the N-current extension region 4. The lower end of the second P+ injection region 5 wraps around the lower corner of one side of the lower end of the gate dielectric layer 11, and the lower corner is a corner at the lower end.

[0050] The P+ buried layer 3 is located below the N- current extension region 4, and the P+ buried layer 3 wraps around the lower corner of the other side of the gate dielectric layer 11.

[0051] The P-base region 8 is located above the remaining N-current extension region 4. The first P+ implantation region 9 and the N+ implantation region 10 are located above the P-base region 8, and the N+ implantation region 10 is located between the gate dielectric layer 11 and the first P+ implantation region 9. The remaining N-current extension region 4 is the N-current extension region that is retained after the formation of the N-current extension region 4 without ion implantation.

[0052] Metallization source 14 is provided on the first P+ injection region 9 and N+ injection region 10;

[0053] A P+ polysilicon region 7 is provided at the bottom of the trench, and gate dielectric layers 11 are provided on both sides and above the P+ polysilicon region 7. The lower end of the P+ polysilicon region 7 is in direct contact with the N- epitaxial layer 2 to form a heterojunction contact, and is connected to the metallized source 14 through a via.

[0054] The contact between the metallized source 14 and the P+ polysilicon region 7, the first P+ implantation region 9, and the N+ implantation region 10 is an ohmic contact.

[0055] Specifically, such as Figure 1 As shown, the N-current extension region is located on the far left of the N-epitaxial layer 2, and the depth of the N-current extension region is greater than the thickness of the N-polysilicon gate; the P-base region 8 is located in the middle of the N-current extension region 4, the first P+ implantation region 9 is located in the upper left corner of the N-current extension region 4, the second P+ implantation region 5 is located inside the N-current extension region 4, the N+ implantation region 10 is located in the upper right corner of the N-current extension region 4, and the P+ buried layer 3 is located in the lower left of the bottom of the trench, floating inside the N-epitaxial layer 2 and wrapping the lower left corner of the gate dielectric layer 11; the N-polysilicon gate 12 is located in the N-current extension region 4. Within the trench 6 between the expansion region 4 and the second P+ injection region 5, a gate dielectric layer 11 surrounds the N-polysilicon gate 12, isolating the N-polysilicon gate 12 from the N+ injection region 10, the P-base region 8, the N-current extension region 4, the P+ buried layer 3, the N-epitaxial layer 2, and the second P+ injection region 5. The P+ polysilicon region 7 is located within the trench, and its lower end is in direct contact with the N-epitaxial layer 2 to form a heterojunction contact, and is connected to the metallization source 14 through a via. The metallization source 14 is located at the upper left end of the first P+ injection region 9 and the N+ injection region 10.

[0056] In this invention, the N+ substrate layer 1, the N- epitaxial layer 2, and the N- current extension region 4 are all made of SiC material. Therefore, the P+ polysilicon region at the bottom of the trench directly contacts the N- epitaxial layer 2 of the SiC material, forming a heterojunction contact. Since there is a smaller potential barrier difference between the P+ polysilicon region and the N- epitaxial layer of the SiC material, the HJD (hetero-junction diode) structure formed by this invention has a lower turn-on voltage. As the HJD operates as a unipolar device, it can further reduce switching losses, improve the energy conversion efficiency of the device, effectively suppress minority carrier injection into the drift region, thereby suppressing bipolar degradation and optimizing reverse recovery characteristics.

[0057] The N-epitaxial layer of this invention includes a P+ buried layer and a second P+ implantation region. The depletion layer formed by the P+ buried layer, the second P+ implantation region, and the N-epitaxial layer can shield against high electric fields. The P+ buried layer and the second P+ implantation region enclose the gate dielectric layer. The lower left and lower right corners of the P+ buried layer and the second P+ implantation region are located below the gate dielectric layer and are surrounded by it. Therefore, the HJD is made inside the gate dielectric layer. Thus, the P+ buried layer and the second P+ implantation region also protect the HJD. Therefore, the P+ buried layer and the second P+ implantation region in the N-epitaxial layer of this invention have a combined shielding effect, which can protect the heterojunction interface and the U-shaped trench gate from the influence of high electric fields and improve the withstand voltage capability of the device.

[0058] In this invention, the first P+ injection region forms an ohmic contact with the metallization source. The short circuit between the first P+ injection region and the metallization source suppresses the turn-on of the parasitic transistor composed of the N+ injection region, the P-base region, and the N-current extension region, thereby further improving the device performance.

[0059] Optionally, the depth of the N-current extension region 4 is greater than the thickness of the N-polysilicon gate 12, meaning the lower surface of the N-current extension region 4 is located below the N-polysilicon gate 12. This is because the N-current extension region 4 is below the channel, and the gate only needs to cover the channel in the P-base region, so the depth of the N-current extension region 4 will be greater than that of the N-polysilicon gate 12.

[0060] Optionally, the depth of the P-base region 8 is less than the depth of the N-current extension region 4, and the width of the P-base region 8 is equal to the width of the N-current extension region 4.

[0061] Optionally, the depth of the first P+ implantation region 9 is less than the depth of the P- base region 8, the depth of the second P+ implantation region 5 is greater than the thickness of the gate dielectric layer 11, and the lower end of the second P+ implantation region 5 wraps around the lower right corner of the gate dielectric layer 11 and part of the P+ polysilicon region.

[0062] Optionally, the depth of the N+ injection region 10 is equal to the depth of the first P+ injection region 9, and the sum of the widths of the N+ injection region 10 and the first P+ injection region 9 is equal to the width of the N- current extension region 4.

[0063] Optionally, the depth of the trench is equal to the depth of the N-current extension region 4, and the depth of the trench is less than the depth of the second P+ injection region 5, so that the depth of the trench cannot be too deep. If it exceeds the P+ buried layer, the P+ buried layer will not be able to play a protective role. The width of the trench is greater than the shortest distance between the P+ buried layer 3 and the second P+ injection region 5. The lower end of the P+ buried layer 3 wraps the lower left corner of the gate dielectric layer 11 and part of the P+ polysilicon region.

[0064] Optionally, the width of the metallized source 14 is less than the sum of the widths of the first P+ injection region 9 and the N+ injection region 10, that is, a portion of the metallized source 14 covers the upper surface of the first P+ injection region 9 and a portion of the metallized source 14 is disposed on a portion of the N+ injection region 10.

[0065] Optionally, the doping concentration of the N-current extension region 4 is greater than the doping concentration of the N-epitaxy layer 2.

[0066] The doping concentration of the N-current extension region 4 in this invention is greater than that of the N-epitaxy layer 2, so the on-resistance is smaller. Therefore, it can effectively reduce the JFET resistance, improve the conductivity of the device, and improve the reliability of the device.

[0067] Optionally, the doping concentration of the N+ substrate layer 1 is greater than the doping concentration of the N- epitaxial layer 2.

[0068] Optionally, the doping concentration in the N-current extension region is lower than the doping concentration in the P-base region.

[0069] Optionally, the doping concentration of the P+ buried layer 3 is equal to the doping concentration of the second P+ implantation region 5 and is greater than the doping concentration of the N-current extension region. The doping concentration of the P+ polysilicon region is greater than the doping concentration of the P+ buried layer 3, and the doping concentration of the P+ polysilicon region is equal to the doping concentration of the N-polysilicon gate.

[0070] Optionally, the first P+ implantation region 9 and the second P+ implantation region 5 have the same doping concentration.

[0071] Optionally, the thickness of the N+ substrate layer 1 is 1–100 μm.

[0072] In this embodiment, the thickness of the N+ substrate layer 1 is 3 μm, and the doping concentration is 5 × 10⁻⁶. 18 cm -3 .

[0073] Optionally, the thickness of the N-epitaxial layer 2 is 10–500 μm.

[0074] In this embodiment, the thickness of the N-epitaxy layer 2 is 25 μm, and the doping concentration is 8 × 10⁻⁶. 15 cm -3 .

[0075] Optionally, the thickness of the N-current extension region 4 is 1–10 μm.

[0076] In this embodiment, the N-current extension region 4 has a thickness of 1 μm, a width of 1.5 μm, and a doping concentration of 2 × 10⁻⁶. 16 cm -3 .

[0077] Optionally, the thickness of the P-base region 8 is 0.5–5 μm.

[0078] In this embodiment, the P-base region 8 has a thickness of 0.5 μm, a width of 1.5 μm, and a doping concentration of 3 × 10⁻⁶. 17 cm -3 .

[0079] Optionally, the thickness of the N+ implantation region 10 is 0.1–2 μm.

[0080] In this embodiment, the N+ implantation region 10 has a thickness of 0.8 μm, a width of 1 μm, and a doping concentration of 1 × 10⁻⁶. 19 cm -3 .

[0081] Optionally, the thickness of the P+ buried layer 3 is 0.1–2 μm.

[0082] In this embodiment, the P+ buried layer 3 has a thickness of 0.5 μm, a width of 0.8 μm, and a doping concentration of 1 × 10⁻⁶. 19 cm -3 .

[0083] Optionally, the thickness of the P+ injection region is 1 to 10 μm, and the number of P+ injection regions can be two or more.

[0084] In this embodiment, the first P+ implantation region 9 has a thickness of 0.8 μm, a width of 0.5 μm, and a doping concentration of 1 × 10⁻⁶. 19 cm -3 The second P+ implantation region 5 has a thickness of 2.5 μm, a width of 1.5 μm, and a doping concentration of 1 × 10⁻⁶. 19 cm -3 .

[0085] Optionally, the thickness of the P+ polysilicon region 7 is 0.1–5 μm.

[0086] In this embodiment, the P+ polysilicon region 7 has a thickness of 0.2 μm, a width of 1.6 μm, and a doping concentration of 1 × 10⁻⁶. 20 cm -3 .

[0087] Optionally, the thickness of the N-polysilicon gate 12 is 0.8–5 μm.

[0088] In this embodiment, the N-polysilicon gate 12 has a thickness of 1.5 μm, a width of 1.8 μm, and a doping concentration of 1 × 10⁻⁶. 20 cm -3 .

[0089] Optionally, the thickness of the gate dielectric layer surrounding the N-polysilicon gate 12 is 0.1 to 2 μm.

[0090] Optionally, the gate dielectric layer 11 surrounding the N-polysilicon gate 12 is a SiO2 layer with a thickness of 0.1 μm.

[0091] Optionally, the metal materials for the metallized drain 13 and the metallized source 14 are titanium, nickel, molybdenum or tungsten.

[0092] The contact between the P+ polysilicon region and the N- epitaxial layer in this invention is a heterojunction contact, that is, an HJD structure is integrated inside the SiC UMOSFET device. This replaces the SBD or JBS structure integrated inside a typical SiC UMOSFET device. Because there is a smaller potential barrier difference between the P+ polysilicon region and the N- epitaxial layer, the HJD structure of this invention has a lower turn-on voltage (1.45V). As the HJD operates as a unipolar device, it further reduces switching losses, improves the energy conversion efficiency of the device, effectively suppresses minority carrier injection into the drift region, thereby suppressing bipolar degradation and optimizing reverse recovery characteristics.

[0093] The P+ buried layer and the second P+ implantation region in the N-epitaxial layer of the present invention have a combined shielding effect, which can protect the heterojunction interface and the U-shaped trench gate from the influence of high electric field and improve the withstand voltage capability of the device.

[0094] The first P+ injection region of the present invention can suppress the turn-on of the parasitic transistor composed of the N+ injection region, the P-base region and the N-csl region, thereby further improving the device performance.

[0095] The N-csl region of this invention can effectively reduce the JFET resistance, improve the conductivity of the device, and enhance the reliability of the device.

[0096] Example 2

[0097] Please see Figures 2a-2i , Figures 2a-2i This is a schematic diagram illustrating the fabrication process of a SiC UMOSFET device with integrated HJD provided in an embodiment of the present invention. The present invention provides a method for fabricating a SiC UMOSFET device with integrated HJD, which is used to fabricate the SiC UMOSFET device described in Embodiment 1. The fabrication method includes:

[0098] Step 1: Select N+ substrate layer 1.

[0099] Step 2, please refer to Figure 2a An N- epitaxial layer 2 is formed on an N+ substrate layer 1 by epitaxial growth.

[0100] Specifically, first, a thickness of 3 μm and a doping concentration of 5 × 10⁻⁶ were tested. 18 cm -3The SiC substrate was subjected to RCA standard cleaning, and then an epitaxial growth with a thickness of 25 μm and a doping concentration of 8 × 10⁻⁶ was performed on the SiC substrate. 15 cm -3 2. N-epipolar layer.

[0101] Step 3, please refer to Figure 2b Ion implantation was performed on the surface of the N-epipolar layer 2 to form a P+ buried layer.

[0102] Specifically, a SiO2 layer is deposited on the surface of N-epitaxial layer 2, and photoresist is coated on it. A 0.8 μm long mask is placed on N-epitaxial layer 2 at a distance of 1.1 μm from the left and 3.1 μm from the right. After exposure, development, etching and photoresist removal, aluminum ions are implanted into N-epitaxial layer 2 to a depth of 0.4 μm and a doping concentration of 1 × 10⁻⁶. 19 cm -3 After implantation, annealing is performed, followed by removal of the first SiO2 layer, ultimately forming a P+ buried layer 3 in the middle of the N-epitaxy layer 2.

[0103] Step 4, please refer to Figure 2c Etching of part of the N-epipolar layer 2.

[0104] Specifically, a SiO2 layer is deposited on the surface of the N-epitaxial layer 2, and photoresist is coated on it. A mask with a length of 0.8 μm is placed on the N-epitaxial layer 2 at a distance of 1.1 μm from the left and 3.1 μm from the right. After exposure, development, etching and photoresist removal, the N-epitaxial layer 2 is etched downwards by 0.2 μm, and then annealed to remove the second SiO2 layer.

[0105] Step 5, please refer to Figure 2d Epitaxial growth continues on the surface of the N-epitaxial layer 2 to form the N-current extension region 4.

[0106] Specifically, an N-current extension region 4 with a doping concentration slightly higher than that of the N-epitaxial layer 2 is grown on the surface of the N-epitaxial layer 2, with a doping concentration of 2 × 10⁻⁶. 16 cm -3 The epitaxial height is 1.8 μm.

[0107] Step 6, please refer to Figure 2e Ion implantation is performed on the surface of the N-current extension region 4 to form a second P+ implantation region 5 on one side of the N-current extension region 4.

[0108] Specifically, a SiO2 layer is deposited on the surface of the N-current extension region 4, and photoresist is coated on it. A 1.9 μm long mask is placed on the rightmost side of the N-current extension region 4. After exposure, development, etching and photoresist removal, aluminum ion implantation is performed on the N-current extension region 4 to a depth of 2 μm and a doping concentration of 1 × 10⁻⁶.19 cm -3 After implantation, annealing is performed, followed by removal of the third SiO2 layer, ultimately forming a second P+ implantation region 5 that extends into the N-epitaxial layer 2 on the right side of the N-current extension region 4.

[0109] Step 7, please refer to Figure 2f Grooves are etched on the surfaces of the N-current extension region 4 and the second P+ injection region 5 to form a trench 6, and a P+ polysilicon region 7 is deposited at the bottom of the trench 6.

[0110] Specifically, a SiO2 layer is deposited on the upper surface of the N-current extension region 4 and the second P+ implantation region 5, and photoresist is coated on it. A mask with a length of 2μm is placed between the N-current extension region 4 and the second P+ implantation region 5. After exposure, development, etching and photoresist removal, the fourth SiO2 layer is removed, and finally a trench 6 is formed between the N-current extension region 4 and the second P+ implantation region 5.

[0111] A SiO2 layer was deposited on the upper surface of trench 6, and photoresist was coated on it. A 1.6 μm long mask was placed in the middle of trench 6. After exposure, development, etching and removal of the photoresist, P+ polysilicon with a thickness of 0.2 μm and a doping concentration of 1×10⁻⁶ was deposited. 19 cm -3 After removing the fifth SiO2 layer, P+ polysilicon 7 is finally formed in the middle of the trench 6. The P+ polysilicon 7 is located above the P+ buried layer 3, the N- epitaxial layer 2 and the second P+ implantation region 5 at the bottom of the trench 6.

[0112] Step 8, please refer to Figure 2g Ion implantation is performed on the surface of the N-current extension region 4 to form the P-base region 8, and then ion implantation is performed on the surface of the P-base region 8 to form the first P+ implantation region 9.

[0113] Specifically, a SiO2 layer is deposited on the surface of the N-current extension region 4, and photoresist is coated on it. A 1.5 μm long mask is placed on the leftmost side of the N-current extension region 4. After exposure, development, etching, and photoresist removal, aluminum ions are implanted into the N-current extension region 4 to a depth of 1.3 μm and a doping concentration of 3 × 10⁻⁶. 17 cm -3 Then, aluminum ions are implanted into the N-current extension region 4 to a depth of 0.8 μm. After implantation, annealing is performed, and then the sixth SiO2 layer is removed. Finally, the P-base region 8 and the first P+ implantation region 9 are formed directly above the N-current extension region 4.

[0114] Step 9, please refer to Figure 2hIon implantation is performed on the surface of the first P+ implantation region 9 to form an N+ implantation region 10. Then, a gate dielectric layer 11 is formed in the trench 6, and an N-polysilicon gate 12 is formed in the groove of the gate dielectric layer 11.

[0115] Specifically, a SiO2 layer is deposited on the upper surface of the first P+ implantation region 9, and photoresist is coated on it. A 1 μm long mask is placed on the upper right side of the first P+ implantation region 9. After exposure, development, etching and removal of the photoresist, phosphorus ion implantation is performed to a depth of 0.8 μm and a doping concentration of 1 × 10⁻⁶. 19 cm -3 After implantation, annealing is performed, and then the seventh SiO2 layer is removed, finally forming the N+ implantation region 10 to the right of the first P+ implantation region 9;

[0116] A SiO2 layer is deposited on the surface of the first P+ implantation region 9, N+ implantation region 10, trench 6, and second P+ implantation region 5. Photoresist is then applied, and a gap is left on the surface of trench 6 in the mask. After exposure, development, etching, and removal of the photoresist, an N-polysilicon layer is first deposited on the device surface, followed by a SiO2 layer. Photoresist is then applied, and a gap is left on trench 6 in the mask. After exposure, development, etching, and removal of the photoresist, the eighth SiO2 layer is removed. Finally, a gate dielectric layer 11 and an N-polysilicon gate 12 are formed on the surface of trench 6.

[0117] Step 10, please refer to Figure 2i A metallized drain 13 is formed on the lower surface of the N+ substrate layer 1, and a metallized source 14 is formed on the first P+ implantation region 9 and the N+ implantation region 10. The P+ polysilicon region 7 is shorted to the metallized source 14 through a back via.

[0118] Specifically, a metallized drain 13 is formed by depositing titanium metal at the bottom of the device, and titanium metal is deposited on the upper surface of the N+ implantation region 10 and the first P+ implantation region 9. After high-temperature annealing, a metallized source 14 is formed. A via is formed by etching on the back of the P+ polysilicon region 7. The via is interconnected with the metallized source by sputtering titanium metal. The contact between the metallized drain 13 and the N+ substrate layer 1 is an ohmic contact, and the contact between the metallized source 14 and the N+ implantation region 10 and the first P+ implantation region 9 is an ohmic contact. Finally, surface planarization is performed to complete the process design and fabricate the SiC UMOSFET device.

[0119] In the description of this invention, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0120] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0121] Although the invention has been described herein in conjunction with various embodiments, those skilled in the art will understand and implement other variations of the disclosed embodiments by reviewing the accompanying drawings, disclosure, and appended claims in carrying out the claimed invention. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality. A single processor or other unit can implement several functions listed in the claims. While different dependent claims may recite certain measures, this does not mean that these measures cannot be combined to produce good results.

[0122] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, any modifications made without departing from the inventive concept should be considered within the scope of protection of the present invention.

Claims

1. A SiC UMOSFET device with integrated HJD, characterized in that, The SiC UMOSFET device includes a metallized drain (13), an N+ substrate layer (1), an N- epitaxial layer (2), and an N- current extension region (4) stacked sequentially from bottom to top. The contact between the N+ substrate layer (1) and the metallized drain (13) is an ohmic contact. The N-current extension region (4) is provided with a trench, and a gate dielectric layer (11) is provided in the trench. An N-polysilicon gate (12) is provided in the groove of the gate dielectric layer (11). A P+ buried layer (3) is provided in the groove on the lower surface of the N-epilayer (2) and the N-current extension region (4), and a P-base region (8), a first P+ injection region (9) and an N+ injection region (10) are provided in the N-current extension region (4), wherein, The N-current extension region (4) and the second P+ injection region (5) are located on both sides of the gate dielectric layer (11). The second P+ injection region (5) is partially disposed in the N-epitaxy layer (2) and partially disposed in the N-current extension region (4). The lower end of the second P+ injection region (5) wraps around the lower corner of one side of the lower end of the gate dielectric layer (11). The P+ buried layer (3) is located below the N- current extension region (4), and the P+ buried layer (3) wraps the lower corner of the other side of the lower end of the gate dielectric layer (11); The P-base region (8) is located above the remaining N-current extension region (4), the first P+ injection region (9) and the N+ injection region (10) are located above the P-base region (8), and the N+ injection region (10) is located between the gate dielectric layer (11) and the first P+ injection region (9); a metallized source (14) is provided on the first P+ injection region (9) and the N+ injection region (10); A P+ polysilicon region (7) is provided at the bottom of the trench, and the gate dielectric layer (11) is provided on both sides and above the P+ polysilicon region (7). The lower end of the P+ polysilicon region (7) is in direct contact with the N- epitaxial layer (2) to form a heterojunction contact, and is connected to the metallized source electrode (14) through a via. The contact between the metallized source (14) and the P+ polysilicon region (7), the first P+ implantation region (9), and the N+ implantation region (10) is an ohmic contact.

2. The SiC UMOSFET device with integrated HJD according to claim 1, characterized in that, The depth of the N-current extension region (4) is greater than the thickness of the N-polysilicon gate (12).

3. The SiC UMOSFET device with integrated HJD according to claim 1, characterized in that, The depth of the P-base region (8) is less than the depth of the N-current extension region (4), and the width of the P-base region (8) is equal to the width of the N-current extension region (4).

4. The SiC UMOSFET device with integrated HJD according to claim 1, characterized in that, The depth of the first P+ injection region (9) is less than the depth of the P- base region (8), and the depth of the second P+ injection region (5) is greater than the thickness of the gate dielectric layer (11).

5. The SiC UMOSFET device with integrated HJD according to claim 1, characterized in that, The depth of the N+ injection region (10) is equal to the depth of the first P+ injection region (9), and the sum of the widths of the N+ injection region (10) and the first P+ injection region (9) is equal to the width of the N-current extension region (4).

6. The SiC UMOSFET device with integrated HJD according to claim 1, characterized in that, The depth of the trench is equal to the depth of the N-current extension region (4), and the depth of the trench is less than the depth of the second P+ injection region (5). The width of the trench is greater than the shortest distance between the P+ buried layer (3) and the second P+ injection region (5).

7. The SiC UMOSFET device with integrated HJD according to claim 1, characterized in that, The width of the metallized source (14) is less than the sum of the widths of the first P+ injection region (9) and the N+ injection region (10).

8. The SiC UMOSFET device with integrated HJD according to claim 1, characterized in that, The doping concentration of the N-current extension region (4) is greater than the doping concentration of the N-epipolar layer (2).

9. The SiC UMOSFET device with integrated HJD according to claim 1, characterized in that, The first P+ implantation region (9) and the second P+ implantation region (5) have the same doping concentration.

10. A method for fabricating a SiC UMOSFET device with integrated HJD, characterized in that, The method for fabricating the SiC UMOSFET device according to any one of claims 1 to 9 comprises: Step 1: Select an N+ substrate layer (1); Step 2: An N- epitaxial layer (2) is formed on the N+ substrate layer (1) by epitaxial growth; Step 3: Ion implantation is performed on the surface of the N-epipolar layer (2) to form a P+ buried layer; Step 4: Etch the N-epitaxial layer (2); Step 5: Continue epitaxial growth on the surface of the N-epi-epitaxy layer (2) to form an N-current extension region (4); Step 6: Ion implantation is performed on the surface of the N-current extension region (4) to form a second P+ implantation region (5) on one side of the N-current extension region (4); Step 7: Grooves are made on the surfaces of the N-current extension region (4) and the second P+ injection region (5) to form trenches (6), and P+ polysilicon regions (7) are deposited at the bottom of the trenches (6); Step 8: Ion implantation is performed on the surface of the N-current extension region (4) to form a P-base region (8), and then ion implantation is performed on the surface of the P-base region (8) to form a first P+ implantation region (9); Step 9: Ion implantation is performed on the surface of the first P+ implantation region (9) to form an N+ implantation region (10), and a gate dielectric layer (11) is formed in the trench (6), and an N-polysilicon gate (12) is formed in the groove of the gate dielectric layer (11). Step 10: Form a metallized drain (13) on the lower surface of the N+ substrate (1), and form a metallized source (14) on the first P+ implantation region (9) and the N+ implantation region (10).

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