Multi-core heterogeneous chip inter-core communication method, system, chip and storage medium

Abstract

The present invention provides a method, system, chip and storage medium for inter-core communication of a multi-core heterogeneous chip. The method includes: allocating a fixed address space for each processor; setting a first protection mechanism and a second protection mechanism for each address space; when communication occurs between processors, the sending end adds verification data to the communication data and stores the communication data in its own address space; the first protection mechanism performs error checking and correction on the current communication data; the receiving end obtains the communication data from the sending end address space that meets the second protection mechanism, and when the parsing of the verification data is successful, the communication data is successfully obtained; otherwise, the acquisition fails, thereby achieving secure communication between the cores of a multi-core heterogeneous chip. The present invention adopts an internal inter-process communication method to reduce the load of CPU operation, not only meeting the functional safety ASIL D level requirements, but also ensuring that the communication between the processors does not interfere with each other.

Description

Technical Field

[0001] The present invention relates to the field of autonomous driving domain control, and in particular to a method, system, chip and storage medium for inter-core communication in multi-core heterogeneous chips. Background Art

[0002] In autonomous driving domain control products, the autonomous driving domain controller is responsible for the data processing power required for autonomous driving, including but not limited to data processing from millimeter-wave radar, cameras, lidar, GPS, inertial navigation, and other devices. It also ensures the security of underlying core data and network data under autonomous driving. As a hub, the autonomous driving domain controller connects the upper and lower levels, effectively serving the intelligentization of the vehicle. The system architecture design of traditional technical solutions uses an MCU and a SoC. The MCU and SoC communicate using SPI, UART, or Ethernet. The traditional domain controller MCU + SoC technical solution has the following technical problems:

[0003] 1. Does not meet the functional safety ASIL D level requirements. For the communication bus module, the software and hardware design needs to meet the following nine failure modes: communication node loss; message corruption; unacceptable message delay; message loss; unexpected message duplication; message sequence error; message insertion; message spoofing; message addressing error;

[0004] 2. There is interference between processors, and the CPU is running under heavy load. Summary of the Invention

[0005] In view of this, the purpose of the present invention is to provide a multi-core heterogeneous chip inter-core communication method, system, chip and storage medium, which adopts an internal inter-process communication method to reduce the load of CPU operation, not only meeting the functional safety ASIL D level requirements, but also ensuring that the communication between each processor does not interfere with each other.

[0006] The present invention provides a multi-core heterogeneous chip inter-core communication method, the method comprising:

[0007] Allocate a fixed address space for each processor;

[0008] Setting a first protection mechanism and a second protection mechanism for each of the address spaces;

[0009] When communication occurs between processors, the sending end adds verification data to the communication data and stores the communication data in its own address space;

[0010] The first protection mechanism performs error checking and correction on the current communication data;

[0011] The receiving end obtains the communication data from the sending end address space that satisfies the second protection mechanism. When the parsing of the verification data is successful, the communication data is obtained successfully; otherwise, the acquisition fails.

[0012] Preferably, said dividing a fixed address space for each processor specifically includes: dividing the same number of address spaces as the number of processors in the shared memory, and each processor corresponds to an independent address space.

[0013] Preferably, the verification data specifically includes:

[0014] First verification data, used to verify duplication, loss, insertion, incorrect sequence and blocking of the communication data;

[0015] Second verification data, used to verify loss, delay and blocking of the communication data;

[0016] third verification data, used to verify disguise, incorrect addressing, and insertion of the communication data;

[0017] The fourth verification data is used to verify damage and asymmetry of the communication data.

[0018] Preferably, the first protection mechanism performs error checking and correction on the current communication data, specifically including: checking the communication data to determine whether a 2-bit error occurs in the communication data, and if so, reporting the current error and ending the process; otherwise, determining whether a 1-bit error occurs in the communication data, and if so, correcting the current 1-bit error, otherwise, the communication data is correct, and the communication data is stored in its own address space.

[0019] Preferably, the second protection mechanism specifically includes: controlling each processor to only be able to perform read and write access operations on its own address space, and each processor to only be able to perform read operations on address spaces other than its own, and not to perform write operations, otherwise, the system will be reset and restarted.

[0020] As another preferred embodiment, the present invention further provides a multi-core heterogeneous chip inter-core secure communication system, the system comprising at least:

[0021] The controller includes several processors.

[0022] The memory is used to divide a fixed address space for each processor; the memory is provided with a first protection module and a second protection module.

[0023] The communication module is used for data interaction between the processors.

[0024] Preferably, the first protection module is used to check the communication data stored in the address space. When a 1-bit error occurs in the data, the current 1-bit error is corrected; when a 2-bit error occurs in the data, the current error is reported.

[0025] The second protection module is used to control each processor to only perform read and write access operations on its own address space; and to control each processor to only perform read operations on address spaces other than its own, and not to perform write operations, otherwise the system will be reset and restarted.

[0026] Preferably, a verification module is provided in the communication module for adding verification data to the communication data or parsing the verification data.

[0027] As another preferred embodiment, the present invention further provides a chip, comprising: a processor for calling and running a computer program from a local storage unit, so that a device equipped with the chip executes the multi-core heterogeneous chip inter-core communication method as described above.

[0028] As another preferred embodiment, a storage medium is located in any control unit, wherein the storage medium includes a computer program executable by a processor, and the computer program is used to execute the multi-core heterogeneous chip inter-core communication method as described above.

[0029] Compared with the prior art, the present invention has the following beneficial effects:

[0030] The present invention adds verification data to the communication data of the multi-core heterogeneous chip of the autonomous driving domain control product, which can meet the functional safety design requirements of the communication module. A first protection mechanism is set for each address space, which can perform error checking and correction on the current communication data to avoid data damage. A second protection mechanism is set for each address space, which can avoid mutual interference and illegal tampering of communication data between cores, thereby meeting the functional safety ASIL D level design requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 The present invention is a flowchart of a multi-core heterogeneous chip inter-core communication method according to a preferred embodiment of the present invention.

[0032] Figure 2 Schematic diagram of a multi-core heterogeneous chip inter-core secure communication system in a preferred embodiment of the present invention.

[0033] Figure 3 Schematic diagram of address space protected by the second protection mechanism in a preferred embodiment of the present invention. DETAILED DESCRIPTION

[0034] To facilitate understanding of the present invention, the present invention will be described more fully below with reference to the accompanying drawings. The accompanying drawings illustrate preferred embodiments of the present invention. However, the present invention may be implemented in many different forms and is not limited to the embodiments described herein.

[0035] Please refer to Figure 1 In a preferred embodiment, a multi-core heterogeneous chip inter-core communication method includes:

[0036] Allocate a fixed address space for each processor;

[0037] Setting a first protection mechanism and a second protection mechanism for each of the address spaces;

[0038] When communication occurs between processors, the sending end adds verification data to the communication data and stores the communication data in its own address space;

[0039] The first protection mechanism performs error checking and correction on the current communication data;

[0040] The receiving end obtains the communication data from the sending end address space that satisfies the second protection mechanism. When the parsing of the verification data is successful, the communication data is obtained successfully; otherwise, the acquisition fails.

[0041] During the specific implementation process, a fixed address space is divided for each processor through the peripheral storage device Double Data Rate Synchronous Dynamic Random Access Memory DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory) for the exchange of read and write data between cores; by adding verification data to the communication data, the software security mechanism protection is increased; by setting a first protection mechanism in the address space, it is used to protect the correctness of the communication data; by setting a second protection mechanism in the address space, it is used to prevent accidental tampering of data between cores.

[0042] Among them, the processors use inter-process communication (IPC) to deliver data; preferably, the verification data can be verified by adding an E2E (End-to-End) end-to-end mechanism to the IPC communication protocol.

[0043] Preferably, said dividing a fixed address space for each processor specifically includes: dividing the same number of address spaces as the number of processors in the shared memory, and each processor corresponds to an independent address space.

[0044] In this embodiment, the verification data specifically includes:

[0045] First verification data, used to verify duplication, loss, insertion, incorrect sequence and blocking of the communication data;

[0046] Second verification data, used to verify loss, delay and blocking of the communication data;

[0047] third verification data, used to verify disguise, incorrect addressing, and insertion of the communication data;

[0048] The fourth verification data is used to verify damage and asymmetry of the communication data.

[0049] In the specific implementation process, the verification data is an E2E end-to-end protection mechanism.

[0050] The first check data can be the frame count Counter, the second check data can be the frame timeout Timeout, the third check data can be the data frame ID, and the fourth check data can be the CRC check. Please refer to the following table:

[0051] E2E protection mechanism Detection failure modes Remark Frame Counter Duplication, loss, insertion, incorrect sequence, and blocking of information Count each frame, increment in loop Frame timeout Information loss, delay, and obstruction Frame timeout judgment Data frame IDDataID Disguise, incorrect addressing, insertion of information A unique ID for each message CRC check Information damage, asymmetry Cyclic Redundancy Check CRC-16

[0052] In the above technical solution, by adding an E2E protection mechanism, the nine failure modes that occur in the existing technology can be solved, and the end-to-end protection of the software security mechanism can be increased.

[0053] To further understand IPC communication, the technical solution for IPC communication is as follows: multi-core tasks can read data from the same channel, with zero copying to further improve performance; data is retained within the valid window period, and error handling is performed if it exceeds the window period; the release of available space is controlled to control the dispatch cycle; when processor data arrives, it is immediately written to shared memory through virtual IO; and the current latest data in shared memory is read when the algorithm begins calculation. Among them, virtual IO is an abstraction layer above the device in the paravirtualized hypervisor. It is an I / O paravirtualization solution, a set of programs for virtualizing general I / O devices, and an abstraction of a group of general I / O devices in the paravirtualized hypervisor.

[0054] In a preferred embodiment, the method of allocating a fixed address space for each processor specifically includes:

[0055] The address spaces having the same number as the processors are divided in the shared memory, and each processor corresponds to an independent address space.

[0056] For easier understanding, please refer to Figure 2,Schematic diagram of the secure communication system between cores of a multi-core heterogeneous chip.,For example, the chip consists of SoC A Core, MCU1, MCU2_0, MCU2_1, and MCU3_0, a total of 5 cores.,In the DDR memory space, a fixed address space IPC1_0, IPC2_0, IPC2_1, IPC3_0 and IPC_A are allocated to each core for,inter-core IPC communication and exchange of read and write data.

[0057] Preferably, the first protection mechanism performs error checking and correction on the current communication data, specifically including: checking the communication data to determine whether a 2-bit error occurs in the communication data, and if so, reporting the current error and ending the process; otherwise, determining whether a 1-bit error occurs in the communication data, and if so, correcting the current 1-bit error, otherwise, the communication data is correct, and the communication data is stored in its own address space.

[0058] During the specific implementation process, the first protection mechanism is an error checking and correction protection mechanism, which specifically includes: when a 1-bit error occurs in the communication data, the current 1-bit error is corrected; when a 2-bit error occurs in the communication data, the current error is reported.

[0059] Exemplarily, the communication address space is protected by ECC, i.e., error checking and correction protection. When a 1-bit error occurs in the data, it can be corrected; when a 2-bit error occurs in the data, an error can be detected; and the correctness of the communication data is protected by ECC checking.

[0060] In this embodiment, the second protection mechanism is a firewall protection mechanism, which specifically includes: controlling each processor to only be able to perform read and write access operations on its own address space, and each processor can only perform read operations on address spaces other than its own, and cannot perform write operations, otherwise the system will be reset and restarted.

[0061] Please refer to Figure 3 For example, the firewall function is enabled to protect the address spaces IPC1_0, IPC2_0, IPC2_1, IPC3_0, and IPC_A, preventing accidental tampering of data between cores. Figure 3 R stands for read and W stands for write.

[0062] For example, the firewall protects the IPC1_0 address space of the MCU1 core. MCU1 can perform read and write operations on it, while other cores MCU2_0, MCU2_1, MCU3_0 and A Core core can only perform read operations and cannot perform write operations, otherwise the system will reset and restart;

[0063] For example, the firewall protects the IPC2_0 address space of the MCU2_0 core. MCU2_0 can perform read and write operations on it, while other cores MCU1, MCU2_1, MCU3_0 and A Core core can only perform read operations and cannot perform write operations, otherwise the system will reset and restart.

[0064] For example, the firewall protects the IPC2_1 address space of the MCU2_1 core. MCU2_1 can perform read and write operations on it, while other cores MCU1, MCU2_0, MCU3_0 and A Core core can only perform read operations and cannot perform write operations. Otherwise, the system will reset and restart.

[0065] For example, the firewall protects the IPC3_0 address space of the MCU3_0 core. MCU3_0 can perform read and write operations on it, while other cores MCU1, MCU2_0, MCU2_1, and A Core core can only perform read operations and cannot perform write operations. Otherwise, the system will reset and restart.

[0066] For example, the firewall protects the IPC_A address space of Core A, and Core A can perform read and write operations on it. The other cores MCU1, MCU2_0, MCU2_1, and MCU3_0 can only perform read operations, but not write operations, otherwise the system will reset and restart.

[0067] In this embodiment, when communication occurs between processors, the sending end adds verification data to the communication data and stores the communication data in its own address space, specifically including:

[0068] Step 1: When communication occurs between processors, the sender adds check data to the communication data and stores it in its own address space.

[0069] Step 2: Check the communication data to determine whether there is a 2-bit error in the communication data. If so, report the current error and end the process; otherwise, enter S303.

[0070] Step 3: Determine whether a single-bit error occurs in the communication data. If so, correct the current single-bit error. Otherwise, the communication data is correct and the communication data is stored in its own address space.

[0071] In summary, the present invention implements an E2E check protection mechanism for the inter-core communication protocol of multi-core heterogeneous chips of autonomous driving domain control products, adds a data frame ID, a frame count, a frame timeout, and a CRC check to the communication data, meets the functional safety design requirements of the communication module, implements an ECC protection mechanism for the DDR storage address space of IPC communication, and when a 1-bit error occurs in the data, the 1-bit error can be corrected, and a 2-bit error can be detected to avoid data damage. The IPC address space of the storage space DDR for inter-core communication of multi-core heterogeneous cores is protected by a firewall. Each core can perform read and write access operations on the address space of its own core, and can only perform read access operations on the address space of other cores, but not write access operations, thereby avoiding mutual interference and illegal tampering of communication data between cores, thereby meeting the functional safety ASIL D level design requirements.

[0072] As another preferred embodiment, the present invention further provides a multi-core heterogeneous chip inter-core secure communication system, the system comprising at least:

[0073] The controller includes several processors.

[0074] The memory is used to divide a fixed address space for each processor; the memory is provided with a first protection module and a second protection module.

[0075] A communication module is used for data communication between the processors; wherein the communication module is provided with a verification module for adding verification data to the communication data or parsing the verification data.

[0076] In this embodiment, the first protection module is used to check the communication data stored in the address space. When a single-bit error occurs in the data, the current single-bit error is corrected; when a double-bit error occurs in the data, the current error is reported.

[0077] The second protection module is used to control each processor to only perform read and write access operations on its own address space; and to control each processor to only perform read operations on address spaces other than its own, and not to perform write operations, otherwise the system will be reset and restarted.

[0078] Please refer to Figures 2 to 3, where Domain is the controller, which consists of 5 processors including SoC A Core, MCU1, MCU2_0, MCU2_1, and MCU3_0. DDR is the memory, which is divided into five address spaces: IPC1_0, IPC2_0, IPC2_1, IPC3_0, and IPC_A. The communication module is the IPC communication module. ECC is the first protection module, which performs ECC protection on the communication address space, that is, error checking and correction protection. When a 1-bit error occurs in the data, it can be corrected; when a 2-bit error occurs in the data, an error can be detected; the correctness of the communication data is protected by ECC check. Firewall is the second protection module, that is, the firewall module. The firewall protects the address spaces IPC1_0, IPC2_0, IPC2_1, IPC3_0, and IPC_A to prevent accidental data tampering between cores.

[0079] As another preferred embodiment, the present invention further provides a chip, comprising: a processor for calling and running a computer program from a local storage unit, so that a device equipped with the chip executes the multi-core heterogeneous chip inter-core communication method as described above.

[0080] As another preferred embodiment, a storage medium is located in any control unit, wherein the storage medium includes a computer program executable by a processor, and the computer program is used to execute the multi-core heterogeneous chip inter-core communication method as described above.

[0081] Although example embodiments have been described herein with reference to the accompanying drawings, it should be understood that the above example embodiments are merely illustrative and are not intended to limit the scope of the present invention. Various changes and modifications may be made therein by those skilled in the art without departing from the scope and spirit of the present invention. All such changes and modifications are intended to be included within the scope of the present invention as claimed in the appended claims.

[0082] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present invention.

[0083] The various system and method embodiments of the present invention can be implemented in hardware, or in software modules running on one or more processors, or in a combination thereof. It will be appreciated by those skilled in the art that a microprocessor or digital signal processor (DSP) can be used in practice to implement some or all of the functions of some modules according to embodiments of the present invention. The present invention can also be implemented as a system program (e.g., a computer program and a computer program product) for performing part or all of the methods described herein. Such a program implementing the present invention can be stored on a computer-readable medium, or can have the form of one or more signals. Such a signal can be downloaded from an Internet website, or provided on a carrier signal, or provided in any other form.

[0084] In the several embodiments provided in this application, it should be understood that the disclosed systems and methods can be implemented in other ways. For example, the system embodiments described above are merely illustrative. For example, the functional division described is merely a logical functional division. In actual implementation, other division methods may be used, such as combining or integrating multiple tools or components into another system, or ignoring or not implementing certain features.

[0085] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature identified as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, "plurality" means two or more, unless otherwise specifically defined.

[0086] Although the present invention is described in conjunction with the above specific embodiments, it is obvious that those skilled in the art can make many substitutions, modifications and variations based on the above content. Therefore, all such substitutions, improvements and variations are included in the spirit and scope of the appended claims.

Claims

1. A multi-core heterogeneous chip inter-core communication method, characterized in that: The method comprises: Allocate a fixed address space for each processor; Setting a first protection mechanism and a second protection mechanism for each of the address spaces; When communication occurs between processors, the sending end adds verification data to the communication data and stores the communication data in its own address space; The first protection mechanism performs error checking and correction on the current communication data; The receiving end obtains the communication data from the sending end address space that satisfies the second protection mechanism, and when parsing the verification data is successful, the communication data is obtained successfully; otherwise, the acquisition fails; Among them, the second protection mechanism specifically includes: controlling each processor to only perform read and write access operations on its own address space, and each processor can only perform read operations on address spaces other than its own, and cannot perform write operations, otherwise the system will be reset and restarted.

2. The multi-core heterogeneous chip inter-core communication method according to claim 1, characterized in that: The method of dividing a fixed address space for each processor specifically includes: dividing the same number of address spaces as the number of processors in the shared memory, and each processor corresponds to an independent address space.

3. The multi-core heterogeneous chip inter-core communication method according to claim 2, characterized in that: The verification data at least includes: First verification data, used to verify duplication, loss, insertion, incorrect sequence and blocking of the communication data; Second verification data, used to verify loss, delay and blocking of the communication data; third verification data, used to verify disguise, incorrect addressing, and insertion of the communication data; The fourth verification data is used to verify damage and asymmetry of the communication data.

4. The multi-core heterogeneous chip inter-core communication method according to claim 3, characterized in that: The first protection mechanism performs error checking and correction on the current communication data, specifically including: The communication data is checked to determine whether a 2-bit error occurs in the communication data. If so, the current error is reported and the process ends. Otherwise, it is determined whether a 1-bit error occurs in the communication data. If so, the current 1-bit error is corrected. Otherwise, the communication data is correct and the communication data is stored in its own address space.

5. A system using the multi-core heterogeneous chip inter-core communication method according to any one of claims 1 to 4, characterized in that: The system comprises at least: A controller, including several processors; A memory, configured to divide a fixed address space for each processor; the memory being provided with a first protection module and a second protection module; The communication module is used for data interaction between the processors.

6. The system according to claim 5, characterized in that The first protection module is used to check the communication data stored in the address space, and when a single-bit error occurs in the data, correct the current single-bit error; When there are 2 bits of error in the data, the current error will be reported; The second protection module is used to control each processor to only perform read and write access operations on its own address space; And control each processor to only read the address space other than its own, and not to write to it. Otherwise, the system will be reset and restarted.

7. The system according to claim 6, characterized in that The communication module is provided with a verification module for adding verification data to the communication data or parsing the verification data.

8. A chip, characterized in that: The chip is a multi-core heterogeneous chip, used to implement the multi-core heterogeneous chip inter-core communication method as described in any one of claims 1-4.

9. A storage medium, characterized in that: Located in any control unit, the storage medium includes a computer program executable by a processor, and the computer program is used to execute the multi-core heterogeneous chip inter-core communication method as described in any one of claims 1-4.

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