A multi-structure attractor chaotic circuit based on a memristive Hopfield neural network

Abstract

The present invention discloses a multi-structure attractor chaotic circuit based on a memristive Hopfield neural network, comprising: a Hopfield neural network circuit N1 for generating a basic chaotic signal, and a memristor circuit N2 for generating a structure number control signal; the Hopfield neural network circuit N1 is provided with an x signal input terminal, an x1 signal output terminal, and a negative f(x1) signal output terminal, and the x1 signal output terminal is used for outputting a chaotic signal in the vertical direction; the memristor circuit N2 is provided with a #imgabs0# signal output terminal and an x signal output terminal, and its input terminal is connected to the negative f(x1) signal output terminal of the Hopfield neural network circuit N1, the x signal output terminal is connected to the signal input terminal of the Hopfield neural network circuit N1, and the #imgabs1# signal output terminal is used for outputting a chaotic signal in the horizontal direction; the circuit of the present invention can generate multi-structure chaotic attractors with any number (odd and even), the chaotic signal has large randomness, high encryption strength and strong anti-cracking ability. The invention can be used in the field of secure communication.

Description

Technical Field

[0001] The present invention relates to the technical field of chaotic secure communication, and particularly relates to a multi-structure attractor chaotic circuit based on a memristive Hopfield neural network. Background Art

[0002] Chaos is a major discovery in natural science in the 20th century by mankind. It reveals the inherent randomness of the motion of nonlinear systems, reflects the unity of determinism and randomness in human society and nature, and is regarded as the third revolution in basic science after the theory of relativity and quantum theory. Chaotic systems have characteristics such as ergodicity, pseudo-randomness, and strong sensitivity to system parameters and initial values, and have extremely broad application prospects in aspects such as image encryption, information processing, and communication security.

[0003] Generally, the more complex the topological trajectory of a chaotic attractor is, the more complex the dynamics of the chaotic system is, the higher the randomness of the obtained chaotic sequence is, and the more secure the communication is. In recent years, chaotic systems with multi-scroll attractors have received extensive attention in the field of secure communication due to the adjustable number of scrolls and the complexity of scroll trajectories. Many patents have proposed multi-scroll chaotic circuit generators. For example, Chinese Patent Authorization Publication No. CN111431694A discloses a multi-scroll chaotic circuit based on sawtooth wave control, which can generate multiple grid multi-scroll chaotic attractors; another example is Chinese Patent Authorization Publication No. CN112311526B, which discloses a modular multi-scroll chaotic circuit based on an S-function generator, which can generate multi-scroll chaotic attractors with adjustable amplitude and frequency. However, these circuits all achieve the control of the number of unit scroll attractors by adopting different control methods, without changing the dynamic complexity of the unit attractor.

[0004] The Hopfield neural network is an artificial neural network model with complex nonlinear dynamics. The memristor discovered in 2008 is the fourth basic circuit element after resistance, capacitance, and inductance. The memristor has synaptic-like bionic characteristics such as nonlinearity, non-volatility, plasticity, and nanoscale size, and has been widely used in constructing memristive Hopfield neural networks. A large number of research results show that memristive Hopfield neural networks can generate non-scroll structure attractors that are more complex than scroll attractor trajectories. However, multi-structure chaotic attractors with multiple non-scroll unit structures have rarely been studied. The trajectory of a multi-structure chaotic attractor is more complex than that of a multi-scroll chaotic attractor and has great application value in image encryption and secure communication. Therefore, it is of great research significance to implement a chaotic circuit that generates multi-structure chaotic attractors. Summary of the Invention

[0005] In view of the above-mentioned defects or deficiencies, the purpose of the present invention is to provide a multi-structural attractor chaotic circuit based on a memristive Hopfield neural network.

[0006] The solution of the present invention to solve its technical problems is: a multi-structural attractor chaotic circuit based on a memristive Hopfield neural network, including:

[0007] A Hopfield neural network circuit N1 for generating a basic chaotic signal, provided with an x signal input terminal, an x1 signal output terminal, and a negative f(x1) signal output terminal;

[0008] A memristor circuit N2 for generating a structure number control signal, provided with A signal output terminal and an x signal output terminal, the input terminal of which is connected to the negative f(x1) signal output terminal of the Hopfield neural network circuit N1 for generating a basic chaotic signal, and the x signal output terminal of which is connected to the signal input terminal of the Hopfield neural network circuit N1 for generating a basic chaotic signal.

[0009] Further, the Hopfield neural network circuit N1 for generating a basic chaotic signal includes: neuron activation function circuits T1 to T3, operational amplifiers OP 21 to OP 23 , resistors R 21 to R 27 , resistors R 31 to R 33 , and capacitors C1 to C3;

[0010] The output terminal of the operational amplifier OP 21 is respectively connected to the right end of the resistor R 31 , the right end of the capacitor C1, and the input terminal of the neuron activation function circuit T1. The negative input terminal of the operational amplifier OP 21 is respectively connected to the right end of the resistor R 21 , the right end of the resistor R 22 , the right end of the resistor R 23 , the left end of the resistor R 31 , and the left end of the capacitor C1. The left end of the resistor R 21 is connected to the negative output terminal of the neuron activation function circuit T1. The left end of the resistor R 22 is connected to the negative output terminal of the neuron activation function circuit T2. The left end of the resistor R 23 is connected to the negative output terminal of the neuron activation function circuit T3;

[0011] The output terminal of the operational amplifier OP 22 is respectively connected to the right end of the resistor R 32 , the right end of the capacitor C2, and the input terminal of the neuron activation function circuit T2. The negative input terminal of the operational amplifier OP 22The negative input terminals are respectively connected to the right end of resistor R 24 the right end of resistor R 25 the right end of resistor R 32 the left end, the left end of capacitor C2. The left end of resistor R 24 is connected to the positive output terminal of the neuron activation function circuit T1. The left end of resistor R 25 is connected to the negative output terminal of the neuron activation function circuit T2;

[0012] The output terminals of operational amplifier OP 23 are respectively connected to the right end of resistor R 33 the right end, the right end of capacitor C3, and the input terminal of the neuron activation function circuit T3. The negative input terminals of operational amplifier OP 23 are respectively connected to the right end of resistor R 26 the right end of resistor R 27 the right end of resistor R 33 the left end, the left end of capacitor C3, and the x signal output terminal of the memristor circuit N2 that generates the structure number control signal. The left end of resistor R 26 is connected to the positive output terminal of the neuron activation function circuit T2. The left end of resistor R 27 is connected to the negative output terminal of the neuron activation function circuit T3;

[0013] The positive input terminals of operational amplifiers OP 21 OP 22 OP 23 are all connected to the ground.

[0014] Furthermore, the neuron activation function circuit T1 is provided with an x1 signal input terminal, a positive f(x1) signal output terminal, and a negative f(x1) signal output terminal. The neuron activation function circuit T1 includes: operational amplifiers OP 31 to OP 33 resistors R 41 to R 46 diodes D1 to D2;

[0015] The output terminal of operational amplifier OP 31 is respectively connected to the right end of resistor R 42 the right end, the left end of resistor R 43 the positive electrode of diode D1 and the negative electrode of diode D2. The negative input terminals of operational amplifier OP 31 are respectively connected to the right end of resistor R 41 the right end, the left end of resistor R 42 the negative electrode of diode D1 and the positive electrode of diode D2. The left end of resistor R 41 is connected to the x1 signal output terminal of the Hopfield neural network circuit N1 that generates the basic chaotic signal;

[0016] Operational amplifier OP 32 's output terminal is respectively connected to the right end of resistor R 44 and the left end of resistor R 45 ; the negative input terminal of operational amplifier OP 32 is respectively connected to the right end of resistor R 43 and the left end of resistor R 44 ;

[0017] The output terminal of operational amplifier OP 33 is connected to the right end of resistor R 46 ; the negative input terminal of operational amplifier OP 33 is respectively connected to the right end of resistor R 45 and the left end of resistor R 46 ;

[0018] The neuron activation function circuit T2 is provided with an x2 signal input terminal, a positive f(x2) signal output terminal, and a negative f(x2) signal output terminal. The neuron activation function circuit T2 includes: operational amplifiers OP 41 to OP 43 , resistors R 51 to R 56 , and diodes D3 to D4;

[0019] The output terminal of operational amplifier OP 41 is respectively connected to the right end of resistor R 52 , the left end of resistor R 53 , the positive electrode of diode D3, and the negative electrode of diode D4. The negative input terminal of operational amplifier OP 41 is respectively connected to the right end of resistor R 51 , the left end of resistor R 52 , the negative electrode of diode D3, and the positive electrode of diode D4. The left end of resistor R 51 is connected to the x2 signal output terminal of the Hopfield neural network circuit N1 that generates the basic chaotic signal;

[0020] The output terminal of operational amplifier OP 42 is respectively connected to the right end of resistor R 54 , the left end of resistor R 55 . The negative input terminal of operational amplifier OP 42 is respectively connected to the right end of resistor R 53 and the left end of resistor R 54 ;

[0021] The output terminal of operational amplifier OP 43 is connected to the right end of resistor R 56 . The negative input terminal of operational amplifier OP 43 is respectively connected to the right end of resistor R 55 and the left end of resistor R56 is connected to the left end;

[0022] The neuron activation function circuit T3 is provided with an x3 signal input terminal, a positive f(x3) signal output terminal, and a negative f(x3) signal output terminal. The neuron activation function circuit T3 includes: an operational amplifier OP 51 to OP 53 , a resistor R 61 to R 66 , and diodes D5 to D6;

[0023] The output terminal of the operational amplifier OP 51 is respectively connected to the right end of the resistor R 62 , the left end of the resistor R 63 , the positive electrode of the diode D5, and the negative electrode of the diode D6. The negative input terminal of the operational amplifier OP 51 is respectively connected to the right end of the resistor R 61 , the left end of the resistor R 62 , the negative electrode of the diode D5, and the positive electrode of the diode D6. The left end of the resistor R 61 is connected to the x3 signal output terminal of the Hopfield neural network circuit N1 that generates a basic chaotic signal;

[0024] The output terminal of the operational amplifier OP 52 is respectively connected to the right end of the resistor R 64 , the left end of the resistor R 65 . The negative input terminal of the operational amplifier OP 52 is respectively connected to the right end of the resistor R 63 and the left end of the resistor R 64 ;

[0025] The output terminal of the operational amplifier OP 53 is connected to the right end of the resistor R 66 . The negative input terminal of the operational amplifier OP 53 is respectively connected to the right end of the resistor R 65 and the left end of the resistor R 66 ;

[0026] The positive input terminals of the operational amplifiers OP 31 to OP 33 , OP 41 to OP 43 , OP 51 to OP 53 are all connected to the ground.

[0027] Furthermore, the memristor circuit N2 that generates a structure number control signal includes: operational amplifiers OP 00 to OP 0(2n) , resistors R 00 to R0(2n) 、Control switches S0 to S n 、Control voltages positive and negative e1 to positive and negative e n 、Operational amplifiers OP 11 to OP 15 、Resistors R 11 to R 18 、Resistor R F 、Resistor R a 、Resistor R b 、Resistor R c 、Capacitor C4 and analog multiplier M, where the proportionality coefficient of the analog multiplier M is 0.1;

[0028] The output terminal of operational amplifier OP 00 is connected to the left end of resistor R 00 The negative input terminal of operational amplifier OP 00 is respectively connected to the negative input terminals of operational amplifiers OP 01 to OP 0(2n) the negative input terminal of operational amplifier OP 14 output terminal, the left end of capacitor C4, the left end of resistor R 13 the left end of, and the left input terminal of analog multiplier M. The right end of resistor R 00 is connected to the left end of control switch S0;

[0029] The output terminal of operational amplifier OP 01 is connected to the left end of resistor R 01 The negative input terminal of operational amplifier OP 01 is respectively connected to the negative input terminals of operational amplifiers OP 00 、OP 02 to OP 0(2n) the negative input terminal of operational amplifier OP 14 output terminal, the left end of capacitor C4, the left end of resistor R 13 the left end of, and the left input terminal of analog multiplier M. The positive input terminal of operational amplifier OP 01 is connected to control voltage positive e1. The right end of resistor R 01 is respectively connected to the right end of resistor R 02 the right end of and the left end of control switch S1;

[0030] The output terminal of operational amplifier OP 02 is connected to the left end of resistor R 02 The negative input terminal of operational amplifier OP 02 is respectively connected to the negative input terminals of operational amplifiers OP 00 to OP 01 、OP 03 to OP 0(2n) the negative input terminal of operational amplifier OP 14 output terminal, the left end of capacitor C4, resistor R13 is connected to the left end of 02 and the left input terminal of the analog multiplier M. The positive input terminal of the operational amplifier OP 02 is connected to the negative control voltage e1. The right end of the resistor R 01 is respectively connected to the right end of the resistor R

[0031] and the left end of the control switch S1; 03 The output terminal of the operational amplifier OP is connected to the left end of the resistor R 03 . The negative input terminal of the operational amplifier OP 03 is respectively connected to the negative input terminals of the operational amplifiers OP 00 to OP 02 , OP 04 to OP 0(2n) , the negative input terminal of the operational amplifier OP 14 output terminal, the left end of the capacitor C4, the left end of the resistor R 13 and the left input terminal of the analog multiplier M. The positive input terminal of the operational amplifier OP 03 is connected to the positive control voltage e2. The right end of the resistor R 03 is respectively connected to the right end of the resistor R 04 and the left end of the control switch S2;

[0032] The output terminal of the operational amplifier OP 04 is connected to the left end of the resistor R 04 . The negative input terminal of the operational amplifier OP 04 is respectively connected to the negative input terminals of the operational amplifiers OP 00 to OP 03 , OP 05 to OP 0(2n) , the negative input terminal of the operational amplifier OP 14 output terminal, the left end of the capacitor C4, the left end of the resistor R 13 and the left input terminal of the analog multiplier M. The positive input terminal of the operational amplifier OP 04 is connected to the negative control voltage e2. The right end of the resistor R 04 is respectively connected to the right end of the resistor R 03 and the left end of the control switch S2;

[0033] The output terminal of the operational amplifier OP 0(2n-1) is connected to the left end of the resistor R 0(2n-1) . The negative input terminal of the operational amplifier OP 0(2n-1) is respectively connected to the negative input terminals of the operational amplifiers OP 00 to OP 0(2n-2) , OP 0(2n) , the negative input terminal of the operational amplifier OP 14 output terminal, the left end of the capacitor C4, the left end of the resistor R 13is connected to the left end and the left input terminal of the analog multiplier M. The positive input terminal of the operational amplifier OP 0(2n-1) is connected to the positive control voltage e n The right end of the resistor R 0(2n-1) is respectively connected to the right end of the resistor R 0(2n) and the left end of the control switch S n ;

[0034] The output terminal of the operational amplifier OP 0(2n) is connected to the left end of the resistor R 0(2n) The negative input terminal of the operational amplifier OP 0(2n) is respectively connected to the negative input terminals of the operational amplifiers OP 00 to OP 0(2n-1) the negative input terminal of the operational amplifier OP 14 the output terminal, the left end of the capacitor C4, the left end of the resistor R 13 and the left input terminal of the analog multiplier M. The positive input terminal of the operational amplifier OP 0(2n) is connected to the negative control voltage e n The right end of the resistor R 0(2n) is respectively connected to the right end of the resistor R 0(2n-1) and the left end of the control switch S n ;

[0035] The output terminal of the operational amplifier OP 11 is respectively connected to the left end of the resistor R 11 and the right end of the resistor R F The negative input terminal of the operational amplifier OP 11 is respectively connected to the left end of the resistor R F and the right ends of the control switches S0 to S n ;

[0036] The output terminal of the operational amplifier OP 12 is respectively connected to the right end of the resistor R 12 and the upper end of the resistor R 15 The negative input terminal of the operational amplifier OP 12 is respectively connected to the right end of the resistor R 11 and the left end of the resistor R 12 The positive input terminal of the operational amplifier OP 12 is respectively connected to the right end of R 13 and the upper end of R 14 ;

[0037] The output terminal of the operational amplifier OP 13 is respectively connected to the lower end of the resistor R 16 and the upper end of the resistor R c The negative input terminal of the operational amplifier OP 13 is respectively connected to the right end of the resistor R 15The lower end of and resistor R 16 is connected to the upper end of;

[0038] The operational amplifier OP 14 The output terminals of are respectively connected to the operational amplifier OP 00 to OP 0(2n) The negative input terminal, the left end of the capacitor C4, the left input terminal of the analog multiplier M, and the resistor R 13 The left end of, the operational amplifier OP 14 The negative input terminal of is respectively connected to the right end of the capacitor C1 and the resistor R 18 The left end of;

[0039] The operational amplifier OP 15 The output terminals of are respectively connected to the resistor R 17 The left end of and the resistor R 18 The right end of, the operational amplifier OP 15 The negative input terminal of is respectively connected to the resistor R 17 The right end of, the resistor R c The lower end of and the resistor R b The left end of;

[0040] The left input terminal of the analog multiplier M is respectively connected to the operational amplifier OP 00 to OP 0(2n) The negative input terminal of, the output terminal of the operational amplifier OP 14 The left end of the capacitor C4, and the resistor R 13 The left end of, the upper input terminal of the analog multiplier M is respectively connected to the resistor R b The right end of and the negative f(x1) signal output terminal of the Hopfield neural network circuit N1 that generates the basic chaotic signal, the output terminal of the analog multiplier M is connected to the resistor R a The left end of, the resistor R a The right end of is connected to the x signal input terminal of the Hopfield neural network circuit N1 that generates the basic chaotic signal;

[0041] The operational amplifier OP 00 OP 11 OP 13 to OP 15 The positive input terminals of and the resistor R 14 The lower end of are all connected to the ground.

[0042] Furthermore, the dimensionless mathematical model of the memristor circuit N2 that generates the structure number control signal is as follows:

[0043]

[0044] Wherein,

[0045]

[0046] Among them, is the internal state variable of the memristor, is the internal state variable function of the memristor, a, b, and c are the system parameters of the memristor, and N and M are the control parameters of the memristor.

[0047] Furthermore, the resistor used in the Hopfield neural network circuit N1 that generates the basic chaotic signal is a precision adjustable resistor or a precision adjustable potentiometer.

[0048] Furthermore, the resistors used in the neuron activation function circuits T1, T2, and T3 are precision adjustable resistors or precision adjustable potentiometers.

[0049] Furthermore, the resistor used in the memristor circuit N2 that generates the structure number control signal is a precision adjustable resistor or a precision adjustable potentiometer.

[0050] The beneficial effects of the present invention are as follows: The present invention designs a multi-structure attractor chaotic circuit based on a memristive Hopfield neural network, filling the blank in this aspect without research. This circuit can generate multi-structure chaotic attractors with any number by adjusting the control switch and control voltage of the memristor circuit N2 that generates the structure number control signal, having complex attractor trajectories and rich dynamic characteristics, capable of providing highly random chaotic sequences, and effectively improving the security of image encryption and secure communication. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] Figure 1 is a schematic circuit connection structure diagram of the Hopfield neural network circuit N1 that generates the basic chaotic signal.

[0052] Figure 2 is a schematic circuit connection structure diagram of the neuron activation function circuit T1.

[0053] Figure 3 is a schematic circuit connection structure diagram of the neuron activation function circuit T2.

[0054] Figure 4 is a schematic circuit connection structure diagram of the neuron activation function circuit T3.

[0055] Figure 5 is a schematic circuit connection structure diagram of the memristor circuit N2 that generates the structure number control signal.

[0056] Figure 6 is a 5-structure chaotic attractor diagram (N = 2).

[0057] Figure 7 is a 6-structure chaotic attractor diagram (M = 2).

[0058] Figure 8 It is a 7-structure chaotic attractor graph (N = 3).

[0059] Figure 9 It is an 8-structure chaotic attractor graph (M = 3). Detailed implementation manners

[0060] The present invention will be described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0061] In the description of the present invention, the orientation descriptions such as up, down, left, right, etc. indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. It is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the referred elements must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation to the present invention.

[0062] Reference Figures 1 to 5 , a multi-structure attractor chaotic circuit based on a memristive Hopfield neural network, includes:

[0063] A Hopfield neural network circuit N1 for generating a basic chaotic signal and a memristor circuit N2 for generating a structure number control signal. The Hopfield neural network circuit N1 for generating a basic chaotic signal is provided with an x signal input terminal, x1, x2, x3 signal output terminals, and a negative f(x1) signal output terminal; the neuron activation function circuit T1 is provided with a positive f(x1) signal output terminal and a negative f(x1) signal output terminal, and its input terminal is connected to the x1 signal output terminal of the Hopfield neural network circuit N1 for generating a basic chaotic signal; the neuron activation function circuit T2 is provided with a positive f(x2) signal output terminal and a negative f(x2) signal output terminal, and its input terminal is connected to the x2 signal output terminal of the Hopfield neural network circuit N1 for generating a basic chaotic signal; the neuron activation function circuit T3 is provided with a positive f(x3) signal output terminal and a negative f(x3) signal output terminal, and its input terminal is connected to the x3 signal output terminal of the Hopfield neural network circuit N1 for generating a basic chaotic signal; the memristor circuit N2 for generating a structure number control signal is provided with a signal output terminal and an x signal output terminal, its input terminal is connected to the negative f(x1) signal output terminal of the Hopfield neural network circuit N1 for generating a basic chaotic signal, and its x signal output terminal is connected to the signal input terminal of the Hopfield neural network circuit N1 for generating a basic chaotic signal.

[0064] The Hopfield neural network circuit N1 for generating a basic chaotic signal includes: neuron activation function circuits T1 to T3, operational amplifiers OP 21 to OP 23 and resistors R 21 to R 27 and resistors R 31 to R 33 as well as capacitors C1 to C3;

[0065] The output terminals of the operational amplifiers OP 21 are respectively connected to the right ends of the resistors R 31 , the right end of the capacitor C1, and the input terminal of the neuron activation function circuit T1. The negative input terminals of the operational amplifiers OP 21 are respectively connected to the right ends of the resistors R 21 , the right ends of the resistors R 22 , the right ends of the resistors R 23 , the left end of the resistor R 31 , and the left end of the capacitor C1. The left end of the resistor R 21 is connected to the negative output terminal of the neuron activation function circuit T1. The left end of the resistor R 22 is connected to the negative output terminal of the neuron activation function circuit T2. The left end of the resistor R 23 is connected to the negative output terminal of the neuron activation function circuit T3;

[0066] The output terminals of the operational amplifiers OP 22 are respectively connected to the right ends of the resistors R 32 , the right end of the capacitor C2, and the input terminal of the neuron activation function circuit T2. The negative input terminals of the operational amplifiers OP 22 are respectively connected to the right ends of the resistors R 24 , the right ends of the resistors R 25 , the left end of the resistor R 32 , and the left end of the capacitor C2. The left end of the resistor R 24 is connected to the positive output terminal of the neuron activation function circuit T1. The left end of the resistor R 25 is connected to the negative output terminal of the neuron activation function circuit T2;

[0067] The output terminals of the operational amplifiers OP 23 are respectively connected to the right ends of the resistors R 33 , the right end of the capacitor C3, and the input terminal of the neuron activation function circuit T3. The negative input terminals of the operational amplifiers OP 23 are respectively connected to the right ends of the resistors R 26 , the right ends of the resistors R 27 , the left end of the resistor R 33 , the left end of the capacitor C3, and the x signal output terminal of the memristor circuit N2 for generating a structure number control signal. The resistor R26 The left end is connected to the positive output terminal of the neuron activation function circuit T2, and the resistor R 27 The left end is connected to the negative output terminal of the neuron activation function circuit T3;

[0068] The operational amplifier OP 21 、OP 22 、OP 23 The positive input terminals are all connected to the ground.

[0069] The Hopfield neural network circuit N1 that generates the basic chaotic signal generates a Hopfield neural network model:

[0070]

[0071] The neuron activation function circuit T1 is provided with an x1 signal input terminal, a positive f(x1) signal output terminal, and a negative f(x1) signal output terminal. The neuron activation function circuit T1 includes: operational amplifiers OP 31 to OP 33 、resistors R 41 to R 46 、diodes D1 to D2;

[0072] The output terminal of the operational amplifier OP 31 is respectively connected to the right end of the resistor R 42 、the left end of the resistor R 43 、the positive electrode of the diode D1 and the negative electrode of the diode D2. The negative input terminal of the operational amplifier OP 31 is respectively connected to the right end of the resistor R 41 、the left end of the resistor R 42 、the negative electrode of the diode D1 and the positive electrode of the diode D2. The left end of the resistor R 41 is connected to the x1 signal output terminal of the Hopfield neural network circuit N1 that generates the basic chaotic signal;

[0073] The output terminal of the operational amplifier OP 32 is respectively connected to the right end of the resistor R 44 、the left end of the resistor R 45 The negative input terminal of the operational amplifier OP 32 is respectively connected to the right end of the resistor R 43 and the left end of the resistor R 44 ;

[0074] The output terminal of the operational amplifier OP 33 is connected to the right end of the resistor R 46 The negative input terminal of the operational amplifier OP 33 is respectively connected to the right end of the resistor R 45 and the left end of the resistor R 46is connected to the left end;

[0075] The neuron activation function circuit T2 is provided with an x2 signal input terminal, a positive f(x2) signal output terminal, and a negative f(x2) signal output terminal. The neuron activation function circuit T2 includes: operational amplifiers OP 41 to OP 43 resistors R 51 to R 56 and diodes D3 to D4;

[0076] The output terminals of operational amplifier OP 41 are respectively connected to the right end of resistor R 52 , the left end of resistor R 53 , the positive electrode of diode D3, and the negative electrode of diode D4. The negative input terminal of operational amplifier OP 41 is respectively connected to the right end of resistor R 51 , the left end of resistor R 52 , the negative electrode of diode D3, and the positive electrode of diode D4. The left end of resistor R 51 is connected to the x2 signal output terminal of the Hopfield neural network circuit N1 that generates the basic chaotic signal;

[0077] The output terminals of operational amplifier OP 42 are respectively connected to the right end of resistor R 54 , the left end of resistor R 55 . The negative input terminals of operational amplifier OP 42 are respectively connected to the right end of resistor R 53 and the left end of resistor R 54 ;

[0078] The output terminal of operational amplifier OP 43 is connected to the right end of resistor R 56 . The negative input terminals of operational amplifier OP 43 are respectively connected to the right end of resistor R 55 and the left end of resistor R 56 ;

[0079] The neuron activation function circuit T3 is provided with an x3 signal input terminal, a positive f(x3) signal output terminal, and a negative f(x3) signal output terminal. The neuron activation function circuit T3 includes: operational amplifiers OP 51 to OP 53 resistors R 61 to R 66 and diodes D5 to D6;

[0080] The output terminals of operational amplifier OP 51 are respectively connected to the right end of resistor R 62 , the left end of resistor R 63The left end, the positive electrode of diode D5, and the negative electrode of diode D6 are connected, and the inverting input terminal of operational amplifier OP 51 is respectively connected to resistor R 61 at its right end, resistor R 62 at its left end, the negative electrode of diode D5, and the positive electrode of diode D6. The left end of resistor R 61 is connected to the x3 signal output terminal of the Hopfield neural network circuit N1 that generates the basic chaotic signal;

[0081] The output terminal of operational amplifier OP 52 is respectively connected to resistor R 64 at its right end and resistor R 65 at its left end. The inverting input terminal of operational amplifier OP 52 is respectively connected to resistor R 63 at its right end and resistor R 64 at its left end;

[0082] The output terminal of operational amplifier OP 53 is connected to resistor R 66 at its right end. The inverting input terminal of operational amplifier OP 53 is respectively connected to resistor R 65 at its right end and resistor R 66 at its left end;

[0083] The positive input terminals of operational amplifiers OP 31 to OP 33 , OP 41 to OP 43 , OP 51 to OP 53 are all connected to the ground.

[0084] The neuron activation function circuits T1, T2, and T3 are respectively used to generate activation functions ±f(x1), ±f(x2), ±f(x3):

[0085] ±f(x1) = ±tanh(x1);

[0086] ±f(x2) = ±tanh(x2);

[0087] ±f(x3) = ±tanh(x3);

[0088] The memristor circuit N2 that generates the structure number control signal includes: operational amplifiers OP 00 to OP 0(2n) , resistors R 00 to R 0(2n) , control switches S0 to S n , control voltages positive and negative e1 to positive and negative e n , operational amplifier OP 11To OP 15 , resistor R 11 to R 18 , resistor R F , resistor R a , resistor R b , resistor R c , capacitor C4 and analog multiplier M, the proportionality coefficient of the analog multiplier M is 0.1;

[0089] Operational amplifier OP 00 's output terminal is connected to the left end of resistor R 00 , the negative input terminal of operational amplifier OP 00 is respectively connected to the negative input terminals of operational amplifiers OP 01 to OP 0(2n) , the negative input terminal of operational amplifier OP 14 's output terminal, the left end of capacitor C4, the left end of resistor R 13 , and the left input terminal of analog multiplier M. The right end of resistor R 00 is connected to the left end of control switch S0;

[0090] Operational amplifier OP 01 's output terminal is connected to the left end of resistor R 01 , the negative input terminal of operational amplifier OP 01 is respectively connected to operational amplifiers OP 00 , OP 02 to OP 0(2n) , the negative input terminal of operational amplifier OP 14 's output terminal, the left end of capacitor C4, the left end of resistor R 13 , and the left input terminal of analog multiplier M. The positive input terminal of operational amplifier OP 01 is connected to control voltage positive e1. The right end of resistor R 01 is respectively connected to the right end of resistor R 02 and the left end of control switch S1;

[0091] Operational amplifier OP 02 's output terminal is connected to the left end of resistor R 02 , the negative input terminal of operational amplifier OP 02 is respectively connected to operational amplifiers OP 00 to OP 01 , OP 03 to OP 0(2n) , the negative input terminal of operational amplifier OP 14 's output terminal, the left end of capacitor C4, the left end of resistor R 13 , and the left input terminal of analog multiplier M. The positive input terminal of operational amplifier OP 02 is connected to control voltage negative e1. The right end of resistor R 02The right ends are respectively connected to resistor R 01 The right end and the left end of control switch S1;

[0092] Operational amplifier OP 03 The output terminal is connected to the left end of resistor R 03 The negative input terminal of operational amplifier OP 03 Is respectively connected to the negative input terminals of operational amplifiers OP 00 To OP 02 、OP 04 To OP 0(2n) The negative input terminal, the output terminal of operational amplifier OP 14 The left end of capacitor C4, the left end of resistor R 13 The left end, the left input terminal of analog multiplier M; the positive input terminal of operational amplifier OP 03 Is connected to control voltage positive e2; the right end of resistor R 03 Is respectively connected to the right end of resistor R 04 The right end and the left end of control switch S2;

[0093] Operational amplifier OP 04 The output terminal is connected to the left end of resistor R 04 The negative input terminal of operational amplifier OP 04 Is respectively connected to the negative input terminals of operational amplifiers OP 00 To OP 03 、OP 05 To OP 0(2n) The negative input terminal, the output terminal of operational amplifier OP 14 The left end of capacitor C4, the left end of resistor R 13 The left end, the left input terminal of analog multiplier M; the positive input terminal of operational amplifier OP 04 Is connected to control voltage negative e2; the right end of resistor R 04 Is respectively connected to the right end of resistor R 03 The right end and the left end of control switch S2;

[0094] Operational amplifier OP 0(2n-1) The output terminal is connected to the left end of resistor R 0(2n-1) The negative input terminal of operational amplifier OP 0(2n-1) Is respectively connected to the negative input terminals of operational amplifiers OP 00 To OP 0(2n-2) 、OP 0(2n) The negative input terminal, the output terminal of operational amplifier OP 14 The left end of capacitor C4, the left end of resistor R 13 The left end, the left input terminal of analog multiplier M; the positive input terminal of operational amplifier OP 0(2n-1) Is connected to control voltage positive e n Connected; the right end of resistor R 0(2n-1) The right end is respectively connected to resistor R0(2n) The right end of n is connected to the left end of the control switch S;

[0095] The output terminal of the operational amplifier OP 0(2n) is connected to the left end of the resistor R 0(2n) The negative input terminals of the operational amplifier OP 0(2n) are respectively connected to the negative input terminals of the operational amplifier OP 00 to OP 0(2n-1) The negative input terminal of the operational amplifier OP 14 The output terminal, the left end of the capacitor C4, the left end of the resistor R 13 The left end of the analog multiplier M is connected. The positive input terminal of the operational amplifier OP 0(2n) is connected to the negative control voltage e n The right end of the resistor R 0(2n) is respectively connected to the right end of the resistor R 0(2n-1) The right end of the control switch S n The left end is connected;

[0096] The output terminal of the operational amplifier OP 11 is respectively connected to the left end of the resistor R 11 and the right end of the resistor R F The negative input terminals of the operational amplifier OP 11 are respectively connected to the left end of the resistor R F and the right ends of the control switches S0 to S n The left end is connected;

[0097] The output terminal of the operational amplifier OP 12 is respectively connected to the right end of the resistor R 12 and the upper end of the resistor R 15 The negative input terminals of the operational amplifier OP 12 are respectively connected to the right end of the resistor R 11 and the left end of the resistor R 12 The positive input terminals of the operational amplifier OP 12 are respectively connected to the right end of R 13 and the upper end of R 14 The upper end is connected;

[0098] The output terminal of the operational amplifier OP 13 is respectively connected to the lower end of the resistor R 16 and the upper end of the resistor R c The negative input terminals of the operational amplifier OP 13 are respectively connected to the lower end of the resistor R 15 and the upper end of the resistor R 16 The upper end is connected;

[0099] The output terminal of the operational amplifier OP 14 is respectively connected to the operational amplifier OP 00To OP 0(2n) The negative input terminal of, the left end of capacitor C4, the left input terminal of analog multiplier M, and resistor R 13 The left ends are connected. The operational amplifier OP 14 The negative input terminal of is respectively connected to the right end of capacitor C1 and the left end of resistor R 18 The left ends are connected;

[0100] The operational amplifier OP 15 The output terminal of is respectively connected to the left end of resistor R 17 The left end and the right end of resistor R 18 The right ends are connected. The operational amplifier OP 15 The negative input terminal of is respectively connected to the right end of resistor R 17 The right end, the lower end of resistor R c The lower end and the left end of resistor R b The left ends are connected;

[0101] The left input terminal of analog multiplier M is respectively connected to the operational amplifier OP 00 To OP 0(2n) The negative input terminal of, the output terminal of operational amplifier OP 14 The left end of capacitor C4, and the left end of resistor R 13 The left ends are connected. The upper input terminal of analog multiplier M is respectively connected to the right end of resistor R b The right end and the negative f(x1) signal output terminal of the Hopfield neural network circuit N1 that generates the basic chaotic signal. The output terminal of analog multiplier M is connected to the left end of resistor R a The left end of resistor R a The right end is connected to the x signal input terminal of the Hopfield neural network circuit N1 that generates the basic chaotic signal;

[0102] The operational amplifier OP 00 、OP 11 、OP 13 To OP 15 The positive input terminals of and resistor R 14 The lower ends are all grounded.

[0103] The memristor circuit N2 for generating the structure number control signal is used to implement the memristor model:

[0104]

[0105] Wherein, g is the proportionality coefficient 0.1 of analog multiplier M;

[0106] According to Figures 1 to 5 Connecting the circuit, the state equation of the multi-structure attractor chaotic signal generated by the circuit of the present invention can be obtained as:

[0107]

[0108] Among them, when the internal state function of the memristor circuit N2 that generates the structure number control signal The mathematical expression is:

[0109]

[0110] When, the number of structure attractors generated by the circuit of the present invention is 2N + 1 (N ≥ 0) (odd);

[0111] When the internal state function of the memristor circuit N2 that generates the structure number control signal The mathematical expression is:

[0112]

[0113] When, the number of structure attractors generated by the circuit of the present invention is 2M + 2 (M ≥ 0) (even), where N and M are natural numbers in the text.

[0114] Selection of circuit elements and power supply voltage of the present invention: Figures 1 to 5 For all operational amplifiers in, the model is TL082CP, the power supply voltage is ±E = ±15V, and the output voltage saturation value of each operational amplifier is Vsat = ±13.5V. Figure 1 For the analog multiplier in, the model is AD633, and the power supply voltage is ±E = ±15V. Figures 2 to 4 For all diodes in, the model is 1N4007. To ensure the accuracy of the resistance value, Figures 1 to 5 All resistors in are precision adjustable resistors or precision adjustable potentiometers.

[0115] The parameters of each component of the present invention are as follows:

[0116] Table 1 (unit: kΩ)

[0117]

[0118] Table 1 is the parameter table of the resistors, with the unit of kΩ.

[0119] Table 2 (unit: nF)

[0120] Capacitor Value Capacitor Value Capacitor Value Capacitor Value <![CDATA[C1]]> 1 <![CDATA[C2]]> 1 <![CDATA[C3]]> 1 <![CDATA[C4]]> 1

[0121] Table 2 is the parameter table of each capacitor, with the unit of nF.

[0122] According to the parameters given in Table 1 and Table 2, the state equation of the multi-structure attractor chaotic signal based on the memristive Hopfield neural network can be obtained as:

[0123]

[0124] The present invention is tested according to the parameters in Table 1 and Table 2, in combination with the switch states of control switches S0 - S n and the parameter values of control voltages e1 - e n to obtain a correspondence table of the number of unit structures of the generated chaotic signal, as shown in Table 3 and Table 4:

[0125] Table 3

[0126] N <![CDATA[S0]]> <![CDATA[S1(e1 = 1V)]]> <![CDATA[S2 (e2 = 3V)]]> <![CDATA[S3(e3 = 5V)]]> … <![CDATA[S n (e n = 2n - 1V)]]> Number of structures 0 Disconnect Disconnect Disconnect Disconnect … Disconnect 1 1 Disconnect Connect Disconnect Disconnect … Disconnect 3 2 Disconnect Connect Connect Disconnect … Disconnect 5 3 Disconnect Connect Connect Connect … Disconnect 7 … … … … … … … … N Disconnect Connect Connect Connect … Connect 2N+1

[0127] Table 3 shows the correspondence between the control parameter N, the control switch state, the control voltage parameter, and the number of unit structures (odd numbers).

[0128] Table 4

[0129] M <![CDATA[S0]]> <![CDATA[S1(e1 = 2V)]]> <![CDATA[S2 (e2 = 4V)]]> <![CDATA[S3(e3 = 6V)]]> … <![CDATA[S n (e n =2n V)]]> Number of structures 0 Connect Disconnect Disconnect Disconnect … Disconnect 2 1 Connect Connect Disconnect Disconnect … Disconnect 4 2 Connect Connect Connect Disconnect … Disconnect 6 3 Connect Connect Connect Connect … Disconnect 8 … … … … … … … … M Connect Connect Connect Connect … Connect 2M+2

[0130] Table 4 shows the correspondence between the control parameter M, the control switch state, the control voltage parameter, and the number of unit structures (even numbers).

[0131] The present invention is tested according to the correspondences in Table 3 and Table 4, Figure 6 , Figure 7 , Figure 8 , Figure 9 respectively giving the phase diagrams of the 5 - structure chaotic attractor, 6 - structure chaotic attractor, 7 - structure chaotic attractor, and 8 - structure chaotic attractor generated by a multi - structure attractor chaotic circuit based on a memristive Hopfield neural network of the present invention.

[0132] As can be seen from Table 3 and Table 4, the circuit of the present invention can generate multi - structure chaotic attractors with any number (odd and even), can provide chaotic sequences with high randomness, and ensure the communication security of secure communication.

Claims

1. A multi-structure attractor chaotic circuit based on a memristive Hopfield neural network, characterized in that, Including: A Hopfield neural network circuit N1 that generates a basic chaotic signal, having an x signal input terminal, an x1 signal output terminal, and a negative f(x1) signal output terminal; The memristor circuit N2 that generates the structure number control signal is provided with a signal output terminal and an x signal output terminal. Its input terminal is connected to the negative f(x1) signal output terminal of the Hopfield neural network circuit N1 that generates the basic chaotic signal, and its x signal output terminal is connected to the signal input terminal of the Hopfield neural network circuit N1 that generates the basic chaotic signal; The Hopfield neural network circuit N1 that generates the basic chaotic signal is further provided with an x2 signal output terminal and an x3 signal output terminal. The Hopfield neural network circuit N1 that generates the basic chaotic signal includes: neuron activation function circuits T1 to T3, operational amplifiers OP 21 to OP 23 , resistors R 21 to R 27 , resistors R 31 to R 33 , and capacitors C1 to C3; Operational amplifier OP 21 The output terminals of are respectively connected to the right end of resistor R 31 , the right end of capacitor C1, and the input terminal of neuron activation function circuit T1. The negative input terminal of operational amplifier OP 21 is respectively connected to the right end of resistor R 21 , the right end of resistor R 22 , the right end of resistor R 23 , the right end of resistor R 31 , the left end of resistor R 21 , and the left end of capacitor C1. The left end of resistor R 22 is connected to the negative output terminal of neuron activation function circuit T1. The left end of resistor R 23 is connected to the negative output terminal of neuron activation function circuit T2. The left end of resistor R is connected to the negative output terminal of neuron activation function circuit T3; Operational amplifier OP 22 The output terminals of are respectively connected to the right end of resistor R 32 , the right end of capacitor C2, and the input terminal of neuron activation function circuit T2. The negative input terminal of operational amplifier OP 22 is respectively connected to the right end of resistor R 24 , the right end of resistor R 25 , the right end of resistor R 32 , the left end of capacitor C2. The left end of resistor R 24 is connected to the positive output terminal of neuron activation function circuit T1, and the left end of resistor R 25 is connected to the negative output terminal of neuron activation function circuit T2; Operational amplifier OP 23 The output terminals of which are respectively connected to the right end of resistor R 33 , the right end of capacitor C3, and the input terminal of neuron activation function circuit T3. The negative input terminal of operational amplifier OP 23 is respectively connected to the right end of resistor R 26 , the right end of resistor R 27 , the right end of resistor R 33 , the left end of capacitor C3, and the x-signal output terminal of memristor circuit N2 that generates the structure number control signal. The left end of resistor R 26 is connected to the positive output terminal of neuron activation function circuit T2, and the left end of resistor R 27 is connected to the negative output terminal of neuron activation function circuit T3; Operational amplifier OP 21 、OP 22 、OP 23 The positive input terminals of all are connected to the ground; The memristor circuit N2 that generates the structure number control signal includes: operational amplifier OP 00 to OP 0(2n) resistor R 00 to R 0(2n) control switches S0 to S n control voltages positive and negative e1 to positive and negative e n operational amplifier OP 11 to OP 15 resistor R 11 to R 18 resistor R F resistor R a resistor R b resistor R c capacitor C4 and analog multiplier M, and the proportionality coefficient of the analog multiplier M is 0.1; Operational amplifier OP 00 's output terminal is connected to the left end of resistor R 00 ; the negative input terminal of operational amplifier OP 00 is respectively connected to the negative input terminals of operational amplifiers OP 01 to OP 0(2n) , the output terminal of operational amplifier OP 14 , the left end of capacitor C4, the left end of resistor R 13 , and the left input terminal of analog multiplier M; the right end of resistor R 00 is connected to the left end of control switch S0; Operational amplifier OP 01 's output terminal is connected to the left end of resistor R 01 , and the negative input terminal of operational amplifier OP 01 is respectively connected to the negative input terminals of operational amplifiers OP 00 , OP 02 to OP 0(2n) , the output terminal of operational amplifier OP 14 , the left end of capacitor C4, the left end of resistor R 13 , and the left input terminal of analog multiplier M. The positive input terminal of operational amplifier OP 01 is connected to control voltage positive e1. The right end of resistor R 01 is respectively connected to the right end of resistor R 02 and the left end of control switch S1; Operational amplifier OP 02 The output terminal of is connected to resistor R 02 at its left end. The negative input terminal of operational amplifier OP 02 is respectively connected to the negative input terminals of operational amplifiers OP 00 to OP 01 、OP 03 to OP 0(2n) at their negative input terminals, the output terminal of operational amplifier OP 14 the left end of capacitor C4, the left end of resistor R 13 at its left end, and the left input terminal of analog multiplier M. The positive input terminal of operational amplifier OP 02 is connected to control voltage negative e1. The right end of resistor R 02 is respectively connected to the right end of resistor R 01 at its right end and the left end of control switch S1; Operational amplifier OP 03 's output terminal is connected to the left end of resistor R 03 The negative input terminal of operational amplifier OP 03 is respectively connected to the negative input terminals of operational amplifiers OP 00 to OP 02 、OP 04 to OP 0(2n) 's negative input terminal, the output terminal of operational amplifier OP 14 , the left end of capacitor C4, the left end of resistor R 13 , and the left input terminal of analog multiplier M. The positive input terminal of operational amplifier OP 03 is connected to control voltage positive e2. The right end of resistor R 03 is respectively connected to the right end of resistor R 04 and the left end of control switch S2; Operational amplifier OP 04 's output terminal is connected to the left end of resistor R 04 , and the negative input terminal of operational amplifier OP 04 is respectively connected to the negative input terminals of operational amplifiers OP 00 to OP 03 , OP 05 to OP 0(2n) , the negative input terminal of operational amplifier OP 14 's output terminal, the left end of capacitor C4, the left end of resistor R 13 , and the left input terminal of analog multiplier M. The positive input terminal of operational amplifier OP 04 is connected to control voltage negative e2. The right end of resistor R 04 is respectively connected to the right end of resistor R 03 and the left end of control switch S2; Operational amplifier OP 0(2n-1) 's output terminal is connected to the left end of resistor R 0(2n-1) ; the negative input terminal of operational amplifier OP 0(2n-1) is respectively connected to the negative input terminals of operational amplifiers OP 00 to OP 0(2n-2) , OP 0(2n) , the negative input terminal of operational amplifier OP 14 's output terminal, the left end of capacitor C4, the left end of resistor R 13 ; the positive input terminal of operational amplifier OP 0(2n-1) is connected to the positive control voltage e n ; the right end of resistor R 0(2n-1) is respectively connected to the right end of resistor R 0(2n) and the left end of control switch S n ; Operational amplifier OP 0(2n) 's output terminal is connected to the left end of resistor R 0(2n) ; the negative input terminal of operational amplifier OP 0(2n) is respectively connected to the negative input terminals of operational amplifiers OP 00 to OP 0(2n-1) , the output terminal of operational amplifier OP 14 , the left end of capacitor C4, the left end of resistor R 13 , and the left input terminal of analog multiplier M; the positive input terminal of operational amplifier OP 0(2n) is connected to the negative control voltage e n ; the right end of resistor R 0(2n) is respectively connected to the right end of resistor R 0(2n-1) and the left end of control switch S n ; Operational amplifier OP 11 The output terminals of are respectively connected to the left end of resistor R 11 and the right end of resistor R F ; the negative input terminal of operational amplifier OP 11 is respectively connected to the left end of resistor R F and the right end of control switches S0 to S n ; Operational amplifier OP 12 The output terminals of which are respectively connected to the right end of resistor R 12 and the upper end of resistor R 15 ; the negative input terminals of operational amplifier OP 12 are respectively connected to the right end of resistor R 11 and the left end of resistor R 12 ; the positive input terminals of operational amplifier OP 12 are respectively connected to the right end of R 13 and the upper end of R 14 ; Operational amplifier OP 13 The output terminals of 16 are respectively connected to the lower end of resistor R c and the upper end of resistor R 13 The negative input terminals of operational amplifier OP 15 are respectively connected to the lower end of resistor R 16 and the upper end of resistor R; Operational amplifier OP 14 The output terminals of 00 are respectively connected to the negative input terminals of operational amplifiers OP 0(2n) to OP 13 , the left end of capacitor C4, the left input terminal of analog multiplier M, and the left end of resistor R 14 . The negative input terminal of operational amplifier OP 18 is respectively connected to the right end of capacitor C1 and the left end of resistor R Operational amplifier OP 15 The output terminals of 17 are respectively connected to the left end of resistor R 18 and the right end of resistor R 15 The negative input terminals of operational amplifier OP 17 are respectively connected to the right end of resistor R c the lower end of resistor R b and the left end of resistor R; The left input terminal of the analog multiplier M is respectively connected to the negative input terminals of operational amplifiers OP 00 to OP 0(2n) , the output terminal of operational amplifier OP 14 , the left end of capacitor C4, and the left end of resistor R 13 . The upper input terminal of the analog multiplier M is respectively connected to the right end of resistor R b and the negative f(x1) signal output terminal of the Hopfield neural network circuit N1 that generates the basic chaotic signal. The output terminal of the analog multiplier M is connected to the left end of resistor R a . The right end of resistor R a is connected to the x signal input terminal of the Hopfield neural network circuit N1 that generates the basic chaotic signal; Operational amplifier OP 00 、OP 11 、OP 13 to OP 15 's positive input terminal and the lower end of resistor R 14 are both connected to ground.

2. The multi-structure attractor chaotic circuit based on a memristive Hopfield neural network according to claim 1, characterized in that: The neuron activation function circuit T1 is provided with an x1 signal input terminal, a positive f(x1) signal output terminal, and a negative f(x1) signal output terminal. The neuron activation function circuit T1 includes operational amplifiers OP 31 to OP 33 , resistors R 41 to R 46 , and diodes D1 to D2; Operational amplifier OP 31 The output terminals of 42 are respectively connected to the right end of resistor R 43 , the left end of resistor R 31 , the positive electrode of diode D1 and the negative electrode of diode D2. The negative input terminal of operational amplifier OP 41 is respectively connected to the right end of resistor R 42 , the left end of resistor R 41 , the negative electrode of diode D1 and the positive electrode of diode D2. The left end of resistor R 41 is connected to the x1 signal output terminal of the Hopfield neural network circuit N1 that generates the basic chaotic signal; Operational amplifier OP 32 The output terminals of 44 are respectively connected to the right end of resistor R 45 and the left end of resistor R 32 The negative input terminals of operational amplifier OP 43 are respectively connected to the right end of resistor R 44 and the left end of resistor R; Operational amplifier OP 33 's output terminal is connected to the right end of resistor R 46 ; the negative input terminal of operational amplifier OP 33 is respectively connected to the right end of resistor R 45 and the left end of resistor R 46 ; The neuron activation function circuit T2 is provided with an x2 signal input terminal, a positive f(x2) signal output terminal, and a negative f(x2) signal output terminal. The neuron activation function circuit T2 includes: operational amplifiers OP 41 to OP 43 , resistors R 51 to R 56 , and diodes D3 to D4; Operational amplifier OP 41 The output terminals of are respectively connected to the right end of resistor R 52 , the left end of resistor R 53 , the positive electrode of diode D3 and the negative electrode of diode D4. The negative input terminal of operational amplifier OP 41 is respectively connected to the right end of resistor R 51 , the left end of resistor R 52 , the negative electrode of diode D3 and the positive electrode of diode D4. The left end of resistor R 51 is connected to the x2 signal output terminal of the Hopfield neural network circuit N1 that generates the basic chaotic signal; Operational amplifier OP 42 The output terminals of 54 are respectively connected to the right end of resistor R 55 and the left end of resistor R 42 The negative input terminals of operational amplifier OP 53 are respectively connected to the right end of resistor R 54 and the left end of resistor R; Operational amplifier OP 43 The output terminal of is connected to the right end of resistor R 56 The negative input terminal of operational amplifier OP 43 is respectively connected to the right end of resistor R 55 and the left end of resistor R 56 ; The neuron activation function circuit T3 is provided with an x3 signal input terminal, a positive f(x3) signal output terminal, and a negative f(x3) signal output terminal. The neuron activation function circuit T3 includes operational amplifiers OP 51 to OP 53 , resistors R 61 to R 66 , and diodes D5 to D6; Operational amplifier OP 51 's output terminal is respectively connected to the right end of resistor R 62 , the left end of resistor R 63 , the positive electrode of diode D5 and the negative electrode of diode D6. The negative input terminal of operational amplifier OP 51 is respectively connected to the right end of resistor R 61 , the left end of resistor R 62 , the negative electrode of diode D5 and the positive electrode of diode D6. The left end of resistor R 61 is connected to the x3 signal output terminal of the Hopfield neural network circuit N1 that generates the basic chaotic signal; Operational amplifier OP 52 The output terminals of 64 are respectively connected to the right end of resistor R 65 and the left end of resistor R 52 The negative input terminals of operational amplifier OP 63 are respectively connected to the right end of resistor R 64 and the left end of resistor R; Operational amplifier OP 53 The output terminal of which is connected to the right end of resistor R 66 The negative input terminal of operational amplifier OP 53 Is respectively connected to the right end of resistor R 65 And the left end of resistor R 66 ; Operational amplifier OP 31 to OP 33 、OP 41 to OP 43 、OP 51 to OP 53 The positive input terminals of all are connected to the ground.

3. A multi-structure attractor chaotic circuit based on a memristive Hopfield neural network according to claim 1, characterized in that: The dimensionless mathematical model of the memristor circuit N2 that generates a structure number control signal is as follows: Wherein, Among them, is the internal state variable of the memristor, is the internal state variable function of the memristor, a, b, and c are the system parameters of the memristor, and N and M are the control parameters of the memristor.

4. A multi-structure attractor chaotic circuit based on a memristive Hopfield neural network according to claim 1, characterized in that: The resistors used in the Hopfield neural network circuit N1 that generates a basic chaotic signal are precision adjustable resistors or precision adjustable potentiometers.

5. A multi-structure attractor chaotic circuit based on a memristive Hopfield neural network according to claim 2, characterized in that: The resistors used in the neuron activation function circuits T1, T2, and T3 are precision adjustable resistors or precision adjustable potentiometers.

6. A multi-structure attractor chaotic circuit based on a memristive Hopfield neural network according to claim 1, characterized in that: The resistors used in the memristor circuit N2 that generates a structure number control signal are precision adjustable resistors or precision adjustable potentiometers.

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